CN114005880A - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN114005880A
CN114005880A CN202111278894.7A CN202111278894A CN114005880A CN 114005880 A CN114005880 A CN 114005880A CN 202111278894 A CN202111278894 A CN 202111278894A CN 114005880 A CN114005880 A CN 114005880A
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type
conductive
region
groove
conductivity
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CN114005880B (en
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朱袁正
叶鹏
周锦程
杨卓
刘晶晶
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Wuxi NCE Power Co Ltd
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Wuxi NCE Power Co Ltd
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Priority to PCT/CN2021/128397 priority patent/WO2023070703A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a power semiconductor device, which comprises: a first conductive type epitaxial layer is arranged on the first conductive type substrate; a first conductive type well region is arranged in the first conductive type epitaxial layer, is distributed below the second type through holes and covers the side part and the bottom of the first type groove, and the concentration of impurities in the first conductive type well region is higher than that in the first conductive type epitaxial layer; or, the concentration of the impurity in the first conductivity type well region is lower than that in the first conductivity type epitaxial layer, and the concentration of the impurity in the first conductivity type well region is lower than that in the first conductivity type epitaxial layer. The invention also discloses a manufacturing method of the power semiconductor device. The power semiconductor device provided by the invention can improve the reliability of short-circuit operation of the device.

Description

Power semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method of the power semiconductor device.
Background
Under the short-circuit working mode, a large amount of current flows through the shielding grid groove power device, when the device is turned off at the moment when the short-circuit working mode is ended, parasitic inductance in the circuit enables the current to forcedly break down the device in an avalanche mode, and the device can experience a high-voltage and ultra-high-current state in a very short time. The device has breakdown weak points at the terminal and the transition region, so that current is concentrated and generates heat, and the heat cannot be smoothly transferred to the active region due to extremely short time, so that the device is burnt at the terminal or the transition region.
Therefore, how to eliminate the breakdown weakness of the termination and the transition region to improve the reliability of the power semiconductor device in the short-circuit operation mode is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a power semiconductor device and a manufacturing method thereof, and solves the problem of low reliability in a short circuit working mode in the related technology.
As a first aspect of the present invention, there is provided a power semiconductor device, comprising:
the structure comprises a first conductive type substrate, wherein a first conductive type epitaxial layer is arranged on the first conductive type substrate, at least one second type groove and a plurality of first type grooves extending towards the inside of the first conductive type epitaxial layer are arranged on the upper surface of the first conductive type epitaxial layer, the first type grooves are parallel to each other and are arranged at intervals, and the second type grooves are arranged around the periphery of the first type grooves;
the inner part of a partial groove section of each first-class groove is completely filled with first-class conductive polycrystalline silicon, a field oxide layer formed by insulating media is arranged between the first-class conductive polycrystalline silicon and the first conductive type epitaxial layer, a second-class insulating medium layer is arranged above the first-class grooves, source metal is arranged above the second-class insulating medium layer, and the source metal is in ohmic contact with the first-class conductive polycrystalline silicon in the first-class grooves through first-class through holes in the second-class insulating medium layer;
filling first-class conductive polysilicon in part of groove sections of each first-class groove, filling second-class conductive polysilicon above the first-class conductive polysilicon, filling first-class insulating medium layers between the second-class conductive polysilicon and the first-class conductive polysilicon, arranging a gate oxide layer between the second-class conductive polysilicon and the first-conductivity type epitaxial layer, arranging a second-conductivity-type body region on the upper surface of the first-class conductive epitaxial layer between every two adjacent first-class grooves, arranging a first-conductivity-type source region on the upper surface of part of the second-conductivity-type body region, arranging second-class insulating medium layers above the first-class grooves and the first-conductivity-type source region, arranging source metal above part of the second-class insulating medium layers, and enabling the source metal to be in ohmic contact with the first-conductivity-type source region and the second-conductivity-type body region through second-class through holes in the second-class insulating medium layers Contacting;
a first conductive type well region is arranged in the first conductive type epitaxial layer, the distribution region of the first conductive type well region comprises a side region and a bottom region which are below the second type through holes and wrap the first type groove, and the concentration of first conductive type impurities in the first conductive type well region is higher than that in the first conductive type epitaxial layer; alternatively, the first and second electrodes may be,
a first conductive type well region is arranged in the first conductive type epitaxial layer, the distribution region of the first conductive type well region comprises, in a direction parallel to the first type of groove, a side region and a bottom region of the first type of groove between the second type of through hole and the second type of groove, a side region and a bottom region of the first type of groove between adjacent second type of through holes, and a side region and a bottom region of the second type of groove, and the concentration of first conductive type impurities in the first conductive type well region is lower than that in the first conductive type epitaxial layer.
Further, a first conductivity type well region is arranged in the first conductivity type epitaxial layer, and the distribution region of the first conductivity type well region comprises a bottom region and a side region which are below the second type through holes and wrap the first type groove;
the first conductive type well region is located below the second type through hole along the boundary in the direction parallel to the first type groove, and the first conductive type well region is not distributed in the side region and the bottom region of at least one first type groove in the first conductive type epitaxial layer, which is close to the second type groove section parallel to the first type groove;
the concentration of the first conductivity type impurity in the first conductivity type well region is 1.01 times to 5 times that in the first conductivity type epitaxial layer.
Further, the first conductivity type well region distribution region includes, in a direction parallel to the first type trench, a side region and a bottom region of the first type trench between the second type via and the second type trench, a side region and a bottom region of the first type trench between adjacent second type vias, and a side region and a bottom region of the second type trench;
the first conduction type well region extends to a partial region below the second type through hole along a boundary in a direction parallel to the first type groove, and a side region and a bottom region of at least one first type groove, close to a second type groove section parallel to the first type groove, in the first conduction type epitaxial layer are coated by the first conduction type well region;
the concentration of the first conductivity-type impurity in the first conductivity-type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity-type impurity in the first conductivity-type well region.
Furthermore, first-class conductive polysilicon is filled in the second-class groove, a field oxide layer is arranged between the first-class conductive polysilicon and the first conductive epitaxial layer, a second-class insulating medium layer is arranged above the second-class groove, source metal is arranged above the second-class insulating medium layer, and the first-class conductive polysilicon in the second-class groove is in ohmic contact with the source metal through a first-class through hole in the second-class insulating medium layer.
Further, a second conductive type body region is arranged on the surface of the first conductive type epitaxial layer between a second type groove section parallel to the first type groove and the adjacent first type groove, a second type insulating medium layer is arranged above the second conductive type body region, source metal is arranged above the second type insulating medium layer, and the source metal is in ohmic contact with the second conductive type body region through a second type through hole in the second type insulating medium layer.
Furthermore, a second insulating medium layer is arranged above each first groove, a gate metal is arranged above part of the second insulating medium layer, and the gate metal is in ohmic contact with the second conductive polysilicon through a third through hole in the second insulating medium layer.
Further, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
As another aspect of the present invention, there is provided a method for manufacturing the power semiconductor device, which includes:
providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
forming a thick oxide layer on the surface of the first conductive type epitaxial layer, and selectively etching the thick oxide layer and the first conductive type epitaxial layer to form a first type groove and a second type groove;
selectively reserving part of photoresist after coating the photoresist, and injecting first conductive type impurities or second conductive type impurities into the side region and the bottom region of the first type groove at a first angle to form a first conductive type well region;
after removing the photoresist and the thick oxide layer, forming field oxide layers on the surface of the first conduction type epitaxial layer, the bottom area and the side area of the first type of groove and the bottom area and the side area of the second type of groove;
forming first conductive polycrystalline silicon in the first type groove and the second type groove respectively;
after selectively etching part of the conductive polysilicon in the first type of groove, forming a first type of insulating medium layer in the etched area;
forming a gate oxide layer in the first-class groove, and forming second-class conductive polycrystalline silicon on the first-class insulating medium layer in the first-class groove;
sequentially forming a second conductive type body region and a first conductive type source region;
depositing an insulating medium to form a second type insulating medium layer;
selectively etching the second type insulating medium layer, the first conductive type source region, the second conductive type body region, the first type conductive polycrystalline silicon and the second type conductive polycrystalline silicon to form a first type through hole, a second type through hole and a third type through hole;
and forming a source metal and a gate metal.
Further, the selectively retaining a portion of the photoresist after coating the photoresist, and implanting a first conductive type impurity or a second conductive type impurity into both the side region and the bottom region of the first type trench at a first angle to form a first conductive type well region includes:
selectively retaining part of photoresist after coating the photoresist, and injecting first conductive type impurities into the side region and the bottom region of the first-type groove at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises the side region and the bottom region which are below the second-type through holes and wrap the first-type groove, and the concentration of the first conductive type impurities in the first conductive type well region is higher than that of the first conductive type impurities in the first conductive type epitaxial layer; alternatively, the first and second electrodes may be,
and after coating the photoresist, selectively retaining part of the photoresist, and injecting second conductive type impurities into the side regions and the bottom regions of the first type trenches at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises, in a direction parallel to the first type trenches, the side regions and the bottom regions of the first type trenches between the second type through holes and the second type trenches, the side regions and the bottom regions of the first type trenches between adjacent second type through holes, and the side regions and the bottom regions of the second type trenches, and the concentration of the first conductive type impurities in the first conductive type well region is lower than that in the first conductive type epitaxial layer.
Further, the first angle ranges from 0 degrees to 60 degrees.
According to the power semiconductor device, the first conductive type well region is arranged, so that the phenomenon that the device is provided with large current at the terminal and the transition region is avoided, the terminal and the transition region are not damaged, the reliability of the device in a short-circuit working mode is improved, and the short-circuit capacity of the device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic top view of a metal and a trench of a device according to the present invention.
FIG. 2 is a cross-sectional view taken along the dashed line AA' in FIG. 1 according to an exemplary embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along the dashed line BB' in FIG. 1 according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along the dashed line CC' in FIG. 1 according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along the dotted line DD' in FIG. 1 according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view illustrating a first conductive epitaxial layer grown on a first conductive substrate according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view illustrating the formation of a first type trench and a second type trench in an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view illustrating the formation of a first conductivity type well region according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view illustrating the removal of the photoresist and the thick oxide layer according to the embodiment of the present invention.
FIG. 10 is a cross-sectional view of a field oxide layer formed in an embodiment of the invention.
Fig. 11 is a schematic cross-sectional view illustrating the formation of the first type of conductive polysilicon according to the embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view illustrating selective etching of the upper portion of the conductive polysilicon in the first-type trench according to the embodiment of the present invention.
FIG. 13 is a cross-sectional view of an embodiment of the present invention in which an insulating dielectric layer is deposited to fill the upper portion of the first type of trench.
Fig. 14 is a schematic cross-sectional view illustrating the removal of the insulating dielectric layer over the epitaxial layer of the first conductivity type in accordance with an embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view illustrating the formation of a first type of insulating dielectric in an embodiment of the invention.
Fig. 16 is a schematic cross-sectional view illustrating the formation of a gate oxide layer in an embodiment of the invention.
Fig. 17 is a schematic cross-sectional view illustrating the formation of a second type of conductive polysilicon according to an embodiment of the present invention.
Fig. 18 is a schematic cross-sectional view illustrating the formation of a second-conductivity-type body region and a first-conductivity-type source region in an embodiment of the present invention.
FIG. 19 is a cross-sectional view of a second type of insulating dielectric formed in accordance with an embodiment of the present invention.
Fig. 20 is a schematic cross-sectional view illustrating the formation of the first type of via, the second type of via, and the third type of via in the embodiment of the present invention.
FIG. 21 is a cross-sectional view taken along the dashed line AA' in FIG. 1 according to another embodiment of the present invention.
Fig. 22 is a schematic cross-sectional view taken along the dashed line BB' in fig. 1 according to another embodiment of the present invention.
Fig. 23 is a schematic cross-sectional view taken along the dashed line CC' in fig. 1 according to another embodiment of the present invention.
Fig. 24 is a schematic cross-sectional view taken along the dotted line DD' in fig. 1 according to another embodiment of the present invention.
FIG. 25 is a cross-sectional view of a cell with a well of a first conductivity type according to an embodiment of the present invention.
Fig. 26 is a cross-sectional view of a cell without a first conductivity type well according to an embodiment of the present invention.
FIG. 27 is a graph showing the electric field distribution along dashed lines FF 'and EE' when the cell structure of FIGS. 25 and 26 breaks down, respectively.
Fig. 28 is a flowchart of a method for manufacturing a power semiconductor device according to the present invention.
Fig. 29 is a schematic diagram of a positional relationship between a first type of trench and a second type of trench provided in the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the present embodiment, a power semiconductor device is provided, fig. 1 is a top view of the power semiconductor device provided according to the embodiment of the present invention, fig. 2 to 5 are cross-sectional views taken along a dotted line AA ', a dotted line BB', a dotted line CC ', and a dotted line DD' in fig. 1, respectively, and fig. 21 to 24 are cross-sectional views taken along a dotted line AA ', a dotted line BB', a dotted line CC ', and a dotted line DD' in fig. 1, respectively, including:
the structure comprises a first conduction type substrate 1, wherein a first conduction type epitaxial layer 2 is arranged on the first conduction type substrate 1, at least one second type groove 16 and a plurality of first type grooves 3 extending towards the inside of the first conduction type epitaxial layer 2 are arranged on the upper surface of the first conduction type epitaxial layer 2, the plurality of first type grooves 3 are arranged in parallel at intervals, and the second type grooves 16 are arranged around the first type grooves 3.
It should be understood here that the first-type grooves 3 are all disposed in parallel with each other, and the second-type grooves 16 surround and encircle a plurality of first-type grooves 3, for example, the direction shown in fig. 1 is taken as an example, the first-type grooves 3 are all disposed in parallel along the horizontal direction, the second-type grooves 16 are disposed in a ring shape, and all the first-type grooves 3 are disposed in a ring-shaped area of the second-type grooves 13, specifically, as shown in fig. 29, the positional relationship between the first-type grooves 3 and the second-type grooves 16 is schematically illustrated, the structure shown in fig. 29 is only illustrated by taking one second-type groove 16 as an example, and two or more second-type grooves 16 may also be disposed, and a plurality of second-type grooves 16 are all disposed in a ring shape.
As shown in fig. 3 or fig. 22, a first type of conductive polysilicon 5 is completely filled in a partial groove section of each first type of trench 3, a field oxide layer 6 formed by an insulating medium is disposed between the first type of conductive polysilicon 5 and the first conductive type epitaxial layer 2, a second type of insulating medium layer 12 is disposed above the first type of trench 3, a source metal 13 is disposed above the second type of insulating medium layer 12, and the source metal 13 is in ohmic contact with the first type of conductive polysilicon 5 located in the first type of trench 3 through a first type of via hole 15 located in the second type of insulating medium layer 12.
It should be understood that this structure can be understood with reference to fig. 3 and 5, since BB 'is located at the center of the device, where the first type of through-hole 15 is located, and along both sides of the dashed line BB' the second type of through-hole 14 is located. In addition, it can be seen in fig. 5 that the interior of the trench segments of the first-type trenches 3 located below the first-type vias 15 is completely filled with the first-type conductive polysilicon 5.
As shown in fig. 2 or fig. 21, the inside of a part of the trench section of each first-type trench 3 is partially filled with first-type conductive polysilicon 5, second-type conductive polysilicon 8 is filled above the first-type conductive polysilicon 5, a first-type insulating medium layer 7 is filled between the second-type conductive polysilicon 8 and the first-type conductive polysilicon 5, a gate oxide layer 9 is arranged between the second-type conductive polysilicon 8 and the first-type conductive epitaxial layer 2, a second-type conductive body region 10 is arranged on the upper surface of the first-type conductive epitaxial layer 2 between every two adjacent first-type trenches 3, a first-type conductive source region 11 is arranged on the upper surface of a part of the second-type conductive body region 10, a second-type insulating medium layer 12 is arranged above the first-type trenches 3 and the first-type conductive source region 11, and a source metal 13 is arranged above a part of the second-type insulating medium layer 12, the source metal 13 is in ohmic contact with the first conductive type source region 11 and the second conductive type body region 10 through a second type via hole 14 located in the second type insulating dielectric layer 12.
It should be understood that, as shown in fig. 5, the first type of conductive polysilicon 5 is filled in the first type of trench 3 except for the part of the trench segment previously described, and the first type of conductive polysilicon 5 is filled in part in other part of the trench segment, and then the second type of conductive polysilicon 8 is filled above the first type of conductive polysilicon 5.
As shown in fig. 2 to 5, a first conductivity type well region 4 is disposed in the first conductivity type epitaxial layer 2, a distribution region of the first conductivity type well region 4 includes a side region and a bottom region below the second type via hole 14 and covering the first type trench 3, and a concentration of a first conductivity type impurity in the first conductivity type well region 4 is higher than a concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2; alternatively, the first and second electrodes may be,
as shown in fig. 21 to 24, a first conductivity-type well region 4 is disposed in the first conductivity-type epitaxial layer 2, and a distribution region of the first conductivity-type well region 4 includes, in a direction parallel to the first-type trenches 3, side regions and bottom regions of the first-type trenches 3 between the second-type vias 14 and the second-type trenches 16, side regions and bottom regions of the first-type trenches 3 between adjacent second-type vias 14, and side regions and bottom regions of the second-type trenches 16, and a concentration of the first conductivity-type impurity in the first conductivity-type well region 4 is lower than a concentration of the first conductivity-type impurity in the first conductivity-type epitaxial layer 2.
It should be understood that the PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2 and the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4 have different breakdown characteristics, and by the arrangement of the first conductivity type well region structure as shown in fig. 2 to 5, since the concentration of the first conductivity type impurity in the first conductivity type well region 4 is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 in this manner, the peak electric field intensity at the PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2 is significantly lower than the peak electric field intensity at the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4 during avalanche breakdown, as shown in fig. 25 is a schematic cross-sectional structure of a unit cell provided with the first conductivity type well region 4, fig. 26 is a schematic cross-sectional structure view of a cell without a first conductivity type well region, fig. 27 is a schematic electric field distribution diagram of the cell structure in fig. 25 and 26 along a dashed line FF 'and a dashed line EE' respectively during breakdown, and an electric field at a PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4 in fig. 25 is much higher than a PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2, so that most of a current flows through the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4 during large current avalanche breakdown of the device, thereby protecting a transition region and a terminal region.
In addition, the PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2 and the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4 have different breakdown characteristics, and through the arrangement of the first conductivity type well region structure shown in fig. 21 to 24, since the concentration of the first conductivity type impurity in the first conductivity type well region 4 is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 in this manner, during avalanche breakdown, the peak electric field intensity at the PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2 is significantly higher than the peak electric field intensity at the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4, so that most of the current flows through the PN junction formed by the second conductivity type body region 10 and the first conductivity type epitaxial layer 2 during large current avalanche breakdown of the device, thereby protecting the transition and termination regions.
In summary, the power semiconductor device provided by the embodiment of the invention avoids the aggregation of large currents at the terminal and the transition region of the device by arranging the first conductivity type well region, so that the terminal and the transition region are not damaged, thereby improving the reliability of the device in the short-circuit working mode and improving the short-circuit capability of the device.
As a specific implementation manner, as shown in fig. 2 to 5, a first conductivity type well region 4 is disposed in the first conductivity type epitaxial layer 2, and a distribution region of the first conductivity type well region 4 includes a bottom region and a side region below the second type via 14 and covering the first type trench 3;
the boundaries of the first conductivity type well region 4 in the direction parallel to the first-type trenches 3 are all located below the second-type through holes 14, and the first conductivity type well region 4 is not distributed in the side region and the bottom region of at least one first-type trench 3 in the first conductivity type epitaxial layer 2, which is close to the second-type trench segment parallel to the first-type trenches 3;
the concentration of the first conductivity-type impurity in the first conductivity-type well region 4 is 1.01 times to 5 times the concentration of the first conductivity-type impurity in the first conductivity-type epitaxial layer.
In this embodiment, the distribution of the first conductivity type well regions 4 may be understood as that they are distributed mainly under the second-type vias 14 and wrap the sides and bottom of the first-type trenches 3 in a direction parallel to the first-type trenches 3, as can be seen from fig. 2 and 4. In addition, the boundaries of the first conductivity type well region 4 in this direction do not exceed both ends of the second-type via hole 14, i.e., the boundaries are below the second-type via hole 14. In a direction perpendicular to said first-type trenches 3, the distribution of first conductivity-type well regions 4 is mainly at the bottom and sides of the first-type trenches 3, and no first conductivity-type well regions are provided at the sides and bottom of at least one first-type trench 3 near the trench segments of the second-type trenches 16 (which should be parallel to the first-type trenches 3, i.e. the lateral trench segment portions as shown in fig. 29).
As another specific implementation, as shown in fig. 1 and fig. 21 to fig. 24, the first conductivity type well region 4 distribution region includes, in a direction parallel to the first type trenches 3, side regions and bottom regions of the first type trenches 3 between the second type vias 14 and the second type trenches 16, side regions and bottom regions of the first type trenches 3 between adjacent second type vias 14, and side regions and bottom regions of the second type trenches 16;
the first conductive type well 4 region extends to a partial region below the second type through hole 14 along the boundary in the direction parallel to the first type groove 3, and the side region and the bottom region of at least one first type groove 3 in the first conductive type epitaxial layer 2, which is close to the second type groove section parallel to the first type groove 3, are coated by the first conductive type well region 4;
the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 is 1.01 times to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region 4.
In this embodiment, the distribution of the first conductivity type well regions 4 may be understood as that, in a direction parallel to the first-type trenches 3, except for the first-type trenches below the second-type vias 14, the first conductivity type well regions 4 are disposed at the bottom and the side portions of the first-type trenches 3 below other regions, and in this direction, the boundary positions of the first conductivity type well regions 4 may extend to below the second-type vias 14. The first conductivity type well regions 4 are arranged at the bottom and sides of the second type trenches 16, and at the sides and bottom of at least one first type trench 3 adjacent to the second type trenches 16, in a direction perpendicular to said first type trenches 3.
On the basis of the foregoing embodiment, as shown in fig. 3 and 4, and fig. 22 and 23, the inside of the second-type trench 16 is filled with the first-type conductive polysilicon 5, a field oxide layer 6 is disposed between the first-type conductive polysilicon 5 and the first conductive epitaxial layer 2, the second-type insulating dielectric layer 12 is disposed above the second-type trench 16, the source metal 13 is disposed above the second-type insulating dielectric layer 12, and the first-type conductive polysilicon 5 in the second-type trench 16 is in ohmic contact with the source metal 13 through the first-type through hole 15 located in the second-type insulating dielectric layer 12.
As shown in fig. 2 and fig. 21, a second conductive type body region 10 is disposed on the surface of the first conductive type epitaxial layer 2 between the groove section of the second type of trench 16 parallel to the first type of trench 3 and the adjacent first type of trench 3, a second insulating dielectric layer 12 is disposed above the second conductive type body region 10, a source metal 13 is disposed above the second insulating dielectric layer 12, and the source metal 13 is in ohmic contact with the second conductive type body region 10 through a second type of via hole 14 located in the second insulating dielectric layer 12.
As shown in fig. 4 and 5, and fig. 23 and 24, a second type insulating medium layer 12 is disposed above each first type trench 3, a gate metal 17 is disposed above the second type insulating medium layer 12, and the gate metal 17 is in ohmic contact with the second type conductive polysilicon 8 through a third type via 18 located in the second type insulating medium layer 12.
It should be understood that the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, and when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.
In the embodiments of the present invention, a power semiconductor device is taken as an example of the N-type power semiconductor device, and at this time, the first conductivity type is N-type, and the second conductivity type is P-type.
As a specific embodiment of the present invention, as shown in fig. 1 to 5, the present invention includes an N-type substrate 1, an N-type epitaxial layer 2 is disposed above the N-type substrate 1, as shown in fig. 1, which is a schematic top view of a device, a strip-shaped first-type trench 3 is disposed on a surface of the N-type epitaxial layer 2, the first-type trench is parallel to and uniformly distributed in the surface, and a second-type trench 16 surrounds the first-type trench 3.
As shown in fig. 3, which is a schematic cross-sectional structure view taken along a dashed line BB' in fig. 1, at a middle position of the first-type trench 3, the first-type trench 3 is filled with first-type conductive polysilicon 5, the first-type conductive polysilicon 5 in the first-type trench 3 is insulated from the N-type epitaxial layer 2 by the field oxide layer 6, a second-type insulating dielectric layer 12 is disposed above the N-type epitaxial layer 2 and the first-type trench 3 between adjacent first-type trenches 3, a source metal 13 is disposed above the second-type insulating dielectric layer 12, and the source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the first-type trench 3 through a first-type via 15 in the second-type insulating dielectric layer 12; the second type of trenches 16 are filled with the first type of conductive polysilicon 5, and the first type of conductive polysilicon 5 in the second type of trenches 16 is insulated from the N-type epitaxial layer 2 by the field oxide layer 6. From the overlooking angle of the device, a second insulating medium layer 12 is arranged above a groove section of a second groove 16 parallel to the first groove 3, a source metal 13 is arranged above the second insulating medium layer 12, and the source metal 13 is in ohmic contact with the first conductive polycrystalline silicon 5 in the second groove 16 through a first through hole 15.
As shown in fig. 2, which is a schematic cross-sectional structure view taken along a dashed line AA' in fig. 1, a first type conductive polysilicon 5 is disposed in a lower half section of a first type trench 3, a second type conductive polysilicon 8 is disposed in an upper half section of the first type trench 3, the first type conductive polysilicon 5 and the second type conductive polysilicon 8 are insulated by a first type insulating medium layer 7, the first type conductive polysilicon 5 is insulated from an N type epitaxial layer 2 by a field oxide layer 6, the second type conductive polysilicon 8 is insulated from the N type epitaxial layer 2 by a gate oxide layer 9, a P type body region 10 is disposed on a surface of the N type epitaxial layer 2 between adjacent first type trenches 3, an N type source region 11 is disposed on a surface of the P type body region 10, a second type insulating medium layer 12 is disposed above the first type trench 3 and the N type source region 11, a source metal 13 is disposed above the second type insulating medium layer 12, and the source metal 13 is respectively connected to the N type source region 11 and the P type body region 10 through a second type ohmic via a second type through hole 14 in the second type insulating medium layer 12 Contacting; a P-type body region 10 is arranged on the surface of the N-type epitaxial layer 2 between the groove section of the second type groove 16 parallel to the first type groove 3 and the adjacent first type groove 3, a second type insulating medium layer 12 is arranged above the P-type body region 10, a source metal 13 is arranged above the second type insulating medium layer 12, and the source metal 13 is in ohmic contact with the P-type body region 10 through a second type through hole 14.
As shown in fig. 5, which is a schematic cross-sectional structure view taken along a dashed line DD' in fig. 1, a second type insulating medium layer 12 is disposed at the ends of the two ends of the first type trench 3 and above the first type trench 3, a gate metal 17 is disposed above the second type insulating medium layer 12, and the gate metal 17 is in ohmic contact with the second type conductive polysilicon 8 through a third type via 18 in the second type insulating medium layer 12.
As shown in fig. 4, which is a schematic cross-sectional structure view taken along a dashed line CC' in fig. 1, in a direction parallel to the first-type trench 3, an N-type well region 4 is disposed in the N-type epitaxial layer 2 near the sidewall and the bottom of the first-type trench 3, the N-type well region 4 is disposed only under the second-type via holes 14, an edge of the N-type well region 4 does not cross a dead end of the second-type via holes 14, and an edge of the N-type well region 4 is about 5 μm away from a dead end of the second-type via holes 14; the concentration of the N-type impurities in the N-type well region 4 is higher than that in the N-type epitaxial layer 2.
As shown in fig. 2, in the direction perpendicular to the first-type trenches 3, the N-type epitaxial layer 2 near the sidewall and the bottom of the first-type trench 3 near the second-type trench 16 is not provided with the N-type well region 4.
The reason why the N-type well region 4 is arranged in this way is that the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2 and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics, because the doping concentration of the N-type well region 4 in this embodiment is greater than that of the epitaxial layer 2, the peak electric field intensity at the PN junction formed by the P-type body region 10 and the epitaxial layer 2 is significantly lower than that at the PN junction formed by the P-type body region 10 and the N-type well region 4 during avalanche breakdown, as shown in fig. 25, the cross-sectional structure diagram of the cell provided with the first conductivity type well region in this embodiment is shown in fig. 26, the cross-sectional structure diagram of the cell not provided with the first conductivity type well region in this embodiment is shown in fig. 26, as shown in fig. 27, electric field distribution diagrams cut along the broken lines FF 'and EE' during breakdown of the cell structures in fig. 25 and 26, respectively, and the electric field distribution diagram at the PN junction formed by the P-type body region 10 and the N-type well region 4 in fig. 25 is much higher than that formed by the P-type body region 10 and the PN junction formed by the epitaxial layer 2 When the device is subjected to large-current avalanche breakdown, most of current flows through a PN junction formed by the P-type body region 10 and the N-type well region 4, so that the transition region and the terminal region are protected.
As another specific embodiment of the present invention, as shown in fig. 1, 21 to 24, the present invention includes an N-type substrate 1, an N-type epitaxial layer 2 is disposed above the N-type substrate 1, as shown in fig. 1, a schematic top view of the device provided by the present invention is shown, a strip-shaped first-type trench 3 is disposed on a surface of the N-type epitaxial layer 2, the first-type trench 3 is parallel to each other and is uniformly distributed, and a second-type trench 16 surrounds a periphery of the first-type trench 3;
as shown in fig. 22, which is a schematic cross-sectional structure view taken along a dashed line BB' in fig. 1, at a middle position of the first-type trenches 3, the first-type trenches 3 are filled with first-type conductive polysilicon 5, the first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxide layer 6, a second-type insulating dielectric layer 12 is disposed above the N-type epitaxial layer 2 and the first-type trenches 3 between adjacent first-type trenches 3, a source metal 13 is disposed above the second-type insulating dielectric layer 12, and the source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the first-type trenches 3 through the first-type through holes 15 in the second-type insulating dielectric layer 12; the second-class grooves 16 are filled with first-class conductive polysilicon 5, the first-class conductive polysilicon 5 in the second-class grooves 16 is insulated from the N-type epitaxial layer 2 through the field oxide layer 6, as seen from the top view of the device, a second-class insulating medium layer 12 is arranged above the groove sections of the second-class grooves 16 parallel to the first-class grooves 3, source metal 13 is arranged above the second-class insulating medium layer 12, and the source metal 13 is in ohmic contact with the first-class conductive polysilicon 5 in the second-class grooves 16 through first-class through holes 15.
As shown in fig. 21, which is a schematic cross-sectional structure view taken along a dashed line AA' in fig. 1, a first type conductive polysilicon 5 is disposed in a lower half section of the first type trench 3, a second type conductive polysilicon 8 is disposed in an upper half section of the first type trench 3, the first type conductive polysilicon 5 and the second type conductive polysilicon 8 are insulated by a first type insulating dielectric layer 7, the first type conductive polysilicon 5 is insulated from the N type epitaxial layer 2 by a field oxide layer 6, the second type conductive polysilicon 8 is insulated from the N type epitaxial layer 2 by a gate oxide layer 9, a P type body region 10 is disposed on a surface of the N type epitaxial layer 2 between adjacent first type trenches 3, an N type source region 11 is disposed on a surface of the P type body region 10, a second type insulating dielectric layer 12 is disposed above the first type trench 3 and the N type source region 11, a source metal 13 is disposed above the second type insulating dielectric layer 12, and the source metal 13 is respectively connected to the N type source region 11 and the P type body region 10 through a second type ohmic via a second type through hole 14 in the second type insulating dielectric layer 12 Contacting; a P-type body region 10 is arranged on the surface of the N-type epitaxial layer 2 between the groove section of the second type groove 16 parallel to the first type groove 3 and the adjacent first type groove 3, a second type insulating medium layer 12 is arranged above the P-type body region 10, a source metal 13 is arranged above the second type insulating medium layer 12, and the source metal 13 is in ohmic contact with the P-type body region 10 through a second type through hole 14.
As shown in fig. 24, which is a schematic cross-sectional structure view taken along a dashed line DD' in fig. 1, at the ends of two ends of the first-type trench 3, a second-type insulating dielectric layer 12 is disposed above the first-type trench 3, a gate metal 17 is disposed above the second-type insulating dielectric layer 12, and the gate metal 17 is in ohmic contact with the second-type conductive polysilicon 8 through a third-type via 18 in the second-type insulating dielectric layer 12.
As shown in fig. 23, which is a schematic cross-sectional structure view taken along a dashed line CC' in fig. 1, in a direction parallel to the first-type trench 3, except for below the second-type via hole 14, an N-type well region 4 is disposed in the N-type epitaxial layer 2 near the sidewall and the bottom of the first-type trench 3, an edge of the N-type well region 4 crosses a dead end of the second-type via hole 14, and a portion of the edge enters below the second-type via hole 14, and an N-type well region 4 is disposed in the N-type epitaxial layer 2 near the sidewall and the bottom of the second-type trench 16; the concentration of the N-type impurities in the N-type well region 4 is lower than that in the N-type epitaxial layer 2.
As shown in fig. 21, in the direction perpendicular to the first-type trenches 3, from the top view of the device, the N-type epitaxial layer 2 near the sidewall and the bottom of the first-type trench 3 near the second-type trench 16 is provided with an N-type well region 4.
The reason why the N-type well region 4 is arranged is that the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2 and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics, and since the doping concentration of the N-type well region 4 is smaller than that of the N-type epitaxial layer 2 in this embodiment, the peak electric field intensity on the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2 is significantly higher than that on the PN junction formed by the P-type body region 10 and the N-type well region 4 during avalanche breakdown, so that most current flows through the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2 during large current avalanche breakdown of the device, thereby protecting the transition region and the terminal region.
As another embodiment of the present invention, there is provided a method for manufacturing a power semiconductor device as described above, wherein as shown in fig. 28, the method includes:
s110, providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
it should be noted that the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, and when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is an N-type, and the second conductivity type is a P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is a P-type, and the second conductivity type is an N-type.
In the embodiments of the present invention, a power semiconductor device is taken as an example of the N-type power semiconductor device, and at this time, the first conductivity type is N-type, and the second conductivity type is P-type.
In this step, as shown in fig. 6, an N-type substrate 1 is provided, and an N-type epitaxial layer 2 is grown on the N-type substrate 1.
S120, forming a thick oxidation layer on the surface of the first conduction type epitaxial layer, and forming a first type groove and a second type groove after selectively etching the thick oxidation layer and the first conduction type epitaxial layer;
in this step, as shown in fig. 7, a thick oxide layer 19 is formed on the surface of the N-type epitaxial layer 2, and the thick oxide layer 19 and the N-type epitaxial layer 2 are selectively etched to form the first-type trenches 3 and the second-type trenches 16.
S130, selectively retaining part of the photoresist after coating the photoresist, and injecting first conductive type impurities or second conductive type impurities into the side area and the bottom area of the first type groove at a first angle to form a first conductive type well region;
in this step, as shown in fig. 8, after the photoresist is coated, a portion of the photoresist 20 is selectively remained, and then N-type impurities are implanted at the sidewall and the bottom of the first-type trench 3 at an angle of a first angle a (in this embodiment, the first angle a shown in fig. 8 may be specifically 17 °), so as to form an N-type well region 4.
Specifically, the selectively retaining a portion of the photoresist after coating the photoresist, and implanting a first conductive type impurity or a second conductive type impurity into both a side region and a bottom region of the first type trench at a first angle to form a first conductive type well region includes:
selectively retaining part of photoresist after coating the photoresist, and injecting first conductive type impurities into the side region and the bottom region of the first-type groove at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises the side region and the bottom region which are below the second-type through holes and wrap the first-type groove, and the concentration of the first conductive type impurities in the first conductive type well region is higher than that of the first conductive type impurities in the first conductive type epitaxial layer; alternatively, the first and second electrodes may be,
and after coating the photoresist, selectively retaining part of the photoresist, and injecting second conductive type impurities into the side regions and the bottom regions of the first type trenches at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises, in a direction parallel to the first type trenches, the side regions and the bottom regions of the first type trenches between the second type through holes and the second type trenches, the side regions and the bottom regions of the first type trenches between adjacent second type through holes, and the side regions and the bottom regions of the second type trenches, and the concentration of the first conductive type impurities in the first conductive type well region is lower than that in the first conductive type epitaxial layer.
It should be understood that, in order to form the structure shown in fig. 2 to 5, N-type impurities are implanted into both the side regions and the bottom region of the first-type trench 3 at a first angle a, so as to form N-type well regions 4, the N-type well regions 4 are distributed below the second-type via holes 14 and cover the side regions and the bottom region of the first-type trench 3, and the concentration of the N-type impurities in the N-type well regions 4 is higher than that in the N-type epitaxial layer 2. Preferably, the concentration of the N-type impurity in the N-type well region 4 is 1.01 times to 5 times the concentration of the N-type impurity in the N-type epitaxial layer 2.
In order to form the structure shown in fig. 21 to 24, P-type impurities are implanted at a first angle a into both side regions and a bottom region of the first-type trench 3 (it should be understood here that the concentration of the N-type impurities is reduced by implanting the P-type impurities to neutralize the N-type impurities), an N-type well region 4 is formed, the N-type well region 4 is distributed below the first-type via 15 and covers the side regions and the bottom region of the first-type trench 3, and is distributed around the second-type trench 16 and covers the side regions and the bottom region of the second-type trench 16, and the concentration of the N-type impurities in the N-type well region 4 is lower than the concentration of the first conductive-type impurities in the N-type epitaxial layer 2. Preferably, the concentration of the first conductivity type impurity in the N type epitaxial layer 2 is 1.01 times to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region 4.
Preferably, the first angle a ranges from 0 ° to 60 °.
S140, after removing the photoresist and the thick oxide layer, forming field oxide layers on the surface of the first conduction type epitaxial layer, the bottom area and the side area of the first type of groove and the bottom area and the side area of the second type of groove;
in this step, as shown in fig. 9, the photoresist 20 and the thick oxide layer 19 are removed; as shown in fig. 10, a field oxide layer 6 is formed on the surface of the N-type epitaxial layer 2, the bottom and the sidewall of the first-type trenches 3 and the second-type trenches 16.
S150, forming first-class conductive polycrystalline silicon in the first-class grooves and the second-class grooves respectively;
in this step, as shown in fig. 11, conductive polysilicon is deposited to fill the first-type trenches 3 and the second-type trenches 16, and then the conductive polysilicon is etched to form the first-type conductive polysilicon 5 in the first-type trenches 3 and the second-type trenches 16.
S160, after selectively etching part of the conductive polycrystalline silicon in the first-class groove, forming a first-class insulating medium layer in the etched area;
in this step, as shown in fig. 12, the upper half portion of the conductive polysilicon in the first type trench 3 is selectively etched; as shown in fig. 13, an insulating dielectric layer is deposited to fill the upper half part of the first-type trenches 3; as shown in fig. 14, the insulating medium layer above the N-type epitaxial layer 2 is removed; as shown in fig. 15, a portion of the insulating dielectric layer in the first-type trenches 3 is selectively etched to form first-type insulating dielectrics 7.
S170, forming a gate oxide layer in the first-class groove, and forming second-class conductive polycrystalline silicon on the first-class insulating medium layer in the first-class groove;
in this step, as shown in fig. 16, the gate oxide layer 9 is formed within the first-type trenches 3; as shown in fig. 17, conductive polysilicon is deposited to fill the upper half of the first-type trenches 3, and then the conductive polysilicon is etched to form second-type conductive polysilicon 8 in the upper half of the first-type trenches 3.
S180, sequentially forming a second conduction type body region and a first conduction type source region;
in this step, as shown in fig. 18, P-type impurities are implanted into the surface of the device and then annealed to form P-type body regions 10, and then N-type impurities are selectively implanted to form N-type source regions 11 after activation.
S190, depositing an insulating medium to form a second insulating medium layer;
in this step, as shown in fig. 19, an insulating dielectric is deposited to form a second type of insulating dielectric 12 on the device surface.
S200, selectively etching the second type insulating medium layer, the first conduction type source region, the second conduction type body region, the first type conduction polycrystalline silicon and the second type conduction polycrystalline silicon to form a first type through hole, a second type through hole and a third type through hole;
in this step, as shown in fig. 20, the second type insulating medium 12, the N type epitaxial layer 2, the first type conductive polysilicon 5 and the second type conductive polysilicon 8 are selectively etched to form the first type via 15, the second type via 14 and the third type via 18.
S210, forming a source metal and a gate metal.
In this step, as shown in fig. 2, 5, 21 and 24, after depositing metal on the device surface, the metal is selectively etched to form a source metal 13 and a gate metal 17.
In summary, the method for manufacturing a power semiconductor device according to the embodiment of the present invention avoids the aggregation of large currents at the terminal and the transition region of the device by forming the first conductive type well region, so that the terminal and the transition region are not damaged, thereby improving the reliability of the device in the short circuit mode and improving the short circuit capability of the device. In addition, the manufacturing method provided by the embodiment of the invention also has the advantages of simple process, low cost and compatibility with the existing process.
For the principle of the method for manufacturing the power semiconductor device according to the embodiment of the present invention, reference may be made to the foregoing description of the power semiconductor device, and details are not described herein.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A power semiconductor device, comprising:
the structure comprises a first conductive type substrate, wherein a first conductive type epitaxial layer is arranged on the first conductive type substrate, at least one second type groove and a plurality of first type grooves which extend towards the inside of the first conductive type epitaxial layer are arranged on the upper surface of the first conductive type epitaxial layer, the first type grooves are parallel to each other and are arranged at intervals, and the second type grooves are arranged around the first type grooves;
the inner part of a partial groove section of each first-class groove is completely filled with first-class conductive polycrystalline silicon, a field oxide layer formed by insulating media is arranged between the first-class conductive polycrystalline silicon and the first conductive type epitaxial layer, a second-class insulating medium layer is arranged above the first-class grooves, source metal is arranged above the second-class insulating medium layer, and the source metal is in ohmic contact with the first-class conductive polycrystalline silicon in the first-class grooves through first-class through holes in the second-class insulating medium layer;
filling first-class conductive polysilicon in part of groove sections of each first-class groove, filling second-class conductive polysilicon above the first-class conductive polysilicon, filling first-class insulating medium layers between the second-class conductive polysilicon and the first-class conductive polysilicon, arranging a gate oxide layer between the second-class conductive polysilicon and the first-conductivity type epitaxial layer, arranging a second-conductivity-type body region on the upper surface of the first-class conductive epitaxial layer between every two adjacent first-class grooves, arranging a first-conductivity-type source region on the upper surface of part of the second-conductivity-type body region, arranging second-class insulating medium layers above the first-class grooves and the first-conductivity-type source region, arranging source metal above part of the second-class insulating medium layers, and enabling the source metal to be in ohmic contact with the first-conductivity-type source region and the second-conductivity-type body region through second-class through holes in the second-class insulating medium layers Contacting;
a first conductive type well region is arranged in the first conductive type epitaxial layer, the distribution region of the first conductive type well region comprises a side region and a bottom region which are below the second type through holes and wrap the first type groove, and the concentration of first conductive type impurities in the first conductive type well region is higher than that in the first conductive type epitaxial layer; alternatively, the first and second electrodes may be,
a first conductive type well region is arranged in the first conductive type epitaxial layer, the distribution region of the first conductive type well region comprises, in a direction parallel to the first type of groove, a side region and a bottom region of the first type of groove between the second type of through hole and the second type of groove, a side region and a bottom region of the first type of groove between adjacent second type of through holes, and a side region and a bottom region of the second type of groove, and the concentration of first conductive type impurities in the first conductive type well region is lower than that in the first conductive type epitaxial layer.
2. The power semiconductor device according to claim 1, wherein a first conductivity type well region is disposed in the first conductivity type epitaxial layer, and the first conductivity type well region distribution region includes a bottom region and a side region which are under the second type via holes and which cover the first type trench;
the first conductive type well region is located below the second type through hole along the boundary in the direction parallel to the first type groove, and the first conductive type well region is not distributed in the side region and the bottom region of at least one first type groove in the first conductive type epitaxial layer, which is close to the second type groove section parallel to the first type groove;
the concentration of the first conductivity type impurity in the first conductivity type well region is 1.01 times to 5 times that in the first conductivity type epitaxial layer.
3. The power semiconductor device according to claim 1, wherein the first conductivity type well region distribution region includes, in a direction parallel to the first type of trench, side regions and bottom regions of the first type of trench between the second type of via and the second type of trench, side regions and bottom regions of the first type of trench between adjacent second type of vias, and side regions and bottom regions of the second type of trench;
the first conduction type well region extends to a partial region below the second type through hole along a boundary in a direction parallel to the first type groove, and a side region and a bottom region of at least one first type groove, close to a second type groove section parallel to the first type groove, in the first conduction type epitaxial layer are coated by the first conduction type well region;
the concentration of the first conductivity-type impurity in the first conductivity-type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity-type impurity in the first conductivity-type well region.
4. The power semiconductor device according to any one of claims 1 to 3,
the first type of conductive polysilicon is filled in the second type of groove, a field oxide layer is arranged between the first type of conductive polysilicon and the first conductive epitaxial layer, the second type of insulating medium layer is arranged above the second type of groove, source metal is arranged above the second type of insulating medium layer, and the first type of conductive polysilicon in the second type of groove is in ohmic contact with the source metal through the first type of through hole in the second type of insulating medium layer.
5. The power semiconductor device according to any one of claims 1 to 3, wherein a second conductivity type body region is arranged on the surface of the first conductivity type epitaxial layer between the second type trench groove section parallel to the first type trench and the adjacent first type trench, a second type insulating medium layer is arranged above the second conductivity type body region, a source metal is arranged above the second type insulating medium layer, and the source metal is in ohmic contact with the second conductivity type body region through a second type through hole in the second type insulating medium layer.
6. The power semiconductor device according to any one of claims 1 to 3, wherein a second type insulating dielectric layer is disposed above each first type trench, and a gate metal is disposed above a portion of the second type insulating dielectric layer, and the gate metal is in ohmic contact with the second type conductive polysilicon through a third type via hole disposed in the second type insulating dielectric layer.
7. The power semiconductor device according to any one of claims 1 to 3, wherein the power semiconductor device comprises an N-type power semiconductor device and a P-type power semiconductor device, and when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.
8. A method for manufacturing a power semiconductor device according to any one of claims 1 to 7, comprising:
providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
forming a thick oxide layer on the surface of the first conductive type epitaxial layer, and selectively etching the thick oxide layer and the first conductive type epitaxial layer to form a first type groove and a second type groove;
selectively reserving part of photoresist after coating the photoresist, and injecting first conductive type impurities or second conductive type impurities into the side region and the bottom region of the first type groove at a first angle to form a first conductive type well region;
after removing the photoresist and the thick oxide layer, forming field oxide layers on the surface of the first conduction type epitaxial layer, the bottom area and the side area of the first type of groove and the bottom area and the side area of the second type of groove;
forming first conductive polycrystalline silicon in the first type groove and the second type groove respectively;
after selectively etching part of the conductive polysilicon in the first type of groove, forming a first type of insulating medium layer in the etched area;
forming a gate oxide layer in the first-class groove, and forming second-class conductive polycrystalline silicon on the first-class insulating medium layer in the first-class groove;
sequentially forming a second conductive type body region and a first conductive type source region;
depositing an insulating medium to form a second type insulating medium layer;
selectively etching the second type insulating medium layer, the first conductive type source region, the second conductive type body region, the first type conductive polycrystalline silicon and the second type conductive polycrystalline silicon to form a first type through hole, a second type through hole and a third type through hole;
and forming a source metal and a gate metal.
9. The method according to claim 8, wherein the step of selectively retaining a portion of the photoresist after coating the photoresist and implanting first conductivity type impurities or second conductivity type impurities at a first angle into the side regions and the bottom regions of the first type trenches to form first conductivity type well regions comprises:
selectively retaining part of photoresist after coating the photoresist, and injecting first conductive type impurities into the side region and the bottom region of the first-type groove at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises the side region and the bottom region which are below the second-type through holes and wrap the first-type groove, and the concentration of the first conductive type impurities in the first conductive type well region is higher than that of the first conductive type impurities in the first conductive type epitaxial layer; alternatively, the first and second electrodes may be,
and after coating the photoresist, selectively retaining part of the photoresist, and injecting second conductive type impurities into the side regions and the bottom regions of the first type trenches at a first angle to form a first conductive type well region, wherein the first conductive type well region distribution region comprises, in a direction parallel to the first type trenches, the side regions and the bottom regions of the first type trenches between the second type through holes and the second type trenches, the side regions and the bottom regions of the first type trenches between adjacent second type through holes, and the side regions and the bottom regions of the second type trenches, and the concentration of the first conductive type impurities in the first conductive type well region is lower than that in the first conductive type epitaxial layer.
10. The method of manufacturing of claim 8 or 9, wherein the first angle is in a range of 0 ° to 60 °.
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