CN113690293B - IGBT device and preparation method thereof - Google Patents
IGBT device and preparation method thereof Download PDFInfo
- Publication number
- CN113690293B CN113690293B CN202010418476.2A CN202010418476A CN113690293B CN 113690293 B CN113690293 B CN 113690293B CN 202010418476 A CN202010418476 A CN 202010418476A CN 113690293 B CN113690293 B CN 113690293B
- Authority
- CN
- China
- Prior art keywords
- region
- conductive structure
- groove
- doped region
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 210000000746 body region Anatomy 0.000 claims abstract description 66
- 238000000605 extraction Methods 0.000 claims abstract description 35
- 238000011049 filling Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 82
- 239000011229 interlayer Substances 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000872 buffer Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 230000005684 electric field Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
The application relates to an IGBT device and a preparation method thereof, wherein the device comprises: a drift region; a body region formed within the drift region; a first doped region and a second doped region formed in the body region; the groove penetrates through the first doping region and the body region in sequence and extends into the drift region; the filling structure comprises an oxide layer formed on the inner wall of the groove, and a first conductive structure and a second conductive structure which are filled in the groove and isolated from each other, wherein the bottom depth of the first conductive structure is greater than that of the second conductive structure; the extension region is formed in the drift region below the groove and surrounds the bottom of the groove; the emitter extraction structure is contacted with the first doping region and the second doping region; and a gate extraction structure contacting the second conductive structure, wherein the drift region, the first doped region, the body region, the second doped region, and the extension region have a first conductivity type. By forming the extension region surrounding the bottom of the trench, the switching speed of the IGBT device can be improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to an IGBT device and a manufacturing method thereof.
Background
IGBT (Insulated Gate Bipolar Transistor ) device is used as bipolar device, which integrates the working mechanism of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal Oxide semiconductor field effect transistor) and bipolar transistor, and has the advantages of reduced on-voltage, high-voltage resistance and low power consumption. However, the switching speed of the IGBT device is slow due to the surplus carriers in the drift region when on.
Disclosure of Invention
Based on the above, it is necessary to provide a new IGBT device and a method for manufacturing the same, aiming at the technical problem that the switching speed of the current IGBT device is slow.
An IGBT device comprising:
a drift region having a first conductivity type;
a body region formed within the drift region, having a second conductivity type;
a first doped region formed in the body region and having a first conductivity type;
the second doped region is formed in the body region and has a second conductive type, and the doping concentration of the second doped region is larger than that of the body region;
the grooves sequentially penetrate through the first doping region and the body region and extend into the drift region, and the second doping region is arranged at intervals with the grooves;
the filling structure comprises an oxide layer formed on the inner wall of the groove, and a first conductive structure and a second conductive structure which are filled in the groove and isolated from each other, wherein the bottom depth of the first conductive structure is greater than that of the second conductive structure;
an extension region formed in the drift region below the trench and surrounding the bottom of the trench, the extension region having the second conductivity type, the extension region being isolated from the first conductive structure by the oxide layer;
an emitter extraction structure in contact with the first doped region and the second doped region; and
and the grid electrode leading-out structure is contacted with the second conductive structure.
In one embodiment, the second doped region is located in a body region at the bottom of the first doped region, and the emitter extraction structure penetrates through the first doped region and extends into the second doped region.
In one embodiment, the second doped region surrounds the bottom of the emitter extraction structure.
In one embodiment, the method further comprises:
and the interlayer dielectric layer covers the first doped region and the groove, the emitter extraction structure also penetrates through the interlayer dielectric layer and is in contact with an emitter on the interlayer dielectric layer, and the grid extraction structure also penetrates through the interlayer dielectric layer and is in contact with a grid on the interlayer dielectric layer.
In one embodiment, the first conductive structure and the second conductive structure are respectively formed at the bottom and the top of the trench, and an isolation structure for isolating the first conductive structure and the second conductive structure is formed between the first conductive structure and the second conductive structure.
In one embodiment, the doping concentration of the drift region above the extension region is higher than the doping concentration of the drift region below the extension region.
In one embodiment, the first conductive structure is an uncharged floating structure.
In one embodiment, the first conductive structure is led out from an end of the trench and electrically connected to the emitter lead-out structure.
A preparation method of an IGBT device comprises the following steps:
forming a drift region on a semiconductor substrate, forming a groove on the drift region, forming an oxide layer on the inner wall of the groove, and forming a first conductive type drift region;
forming an extension region within the drift region under the trench, the extension region having the second conductivity type and surrounding a bottom of the trench;
filling a first conductive structure and a second conductive structure which are isolated from each other in the groove, wherein the bottom depth of the first conductive structure is greater than that of the second conductive structure;
doping the drift region with the second conductivity type to form a body region, wherein the body region is in contact with the inner wall of the groove, and the depth of the body region is smaller than that of the groove;
and doping the body region respectively by a first conductive type and a second conductive type, correspondingly forming a first doped region and a second doped region, wherein the first doped region is contacted with the groove, the doping concentration of the second doped region is larger than that of the body region, forming an emitter extraction structure contacted with the first doped region and the second doped region, and forming a grid extraction structure contacted with the second conductive structure.
In one embodiment, before doping the drift region with the second conductivity type to form a body region, the method further comprises:
and doping the drift region with the first conductivity type, and improving the concentration of the drift region above the extension region.
According to the IGBT device and the preparation method thereof, the groove is formed in the drift region, the expansion region surrounding the bottom of the groove is formed, the conductivity types of the expansion region and the drift region are opposite, and the expansion region and the filling structure in the groove act together, so that the switching speed of the IGBT device can be improved, meanwhile, the switching capacitance and the conduction voltage drop of the IGBT device are reduced, and the problem of electric field concentration at the bottom of the groove is solved.
Drawings
Fig. 1a is a partial cross-sectional side view of an IGBT device in an embodiment of the present application in a cellular region;
fig. 1b is a partial cross-sectional side view of an IGBT device outside a cellular region according to another embodiment of the present application;
fig. 2 is a flowchart illustrating steps of a method for fabricating an IGBT device according to an embodiment of the present application;
fig. 3a to 3h are cross-sectional views of structures corresponding to relevant steps of a method for manufacturing an IGBT device according to an embodiment of the present application.
Description of the reference numerals
A 100 drift region; 110 body regions; 111 a first doped region; 112 a second doped region; 121 oxide layer; 122 a first conductive structure; 123 a second conductive structure; 124 isolation structures; 130 extension; 140 buffers; a 150 collector region; 200 interlayer dielectric layers; 310 emitter extraction structures; 320 emitter connection structure.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in connection with fig. 1a, the IGBT device comprises a drift region 100 of the first conductivity type, the drift region 100 being formed on a semiconductor substrate, the drift region 100 being in particular formed by epitaxial growth of the semiconductor substrate. The upper surface layer of the drift region 100 is formed with a body region 110 of the second conductivity type. The body region 110 has a first doped region 111 and a second doped region 112 formed therein, wherein the first doped region 111 has a first conductivity type, the second doped region 112 has a second conductivity type, and the doping concentration of the second doped region 112 is greater than that of the body region 110, and the first doped region 111 and the second doped region 112 are in contact with each other.
The first doped region 111 is provided with a trench penetrating the first doped region 111 and the body region 110 and extending into the drift region 100, i.e. the bottom end of the trench is located in the drift region 100, and the trench is spaced apart from the second doped region 112. The trench is filled with a filling structure comprising an oxide layer 121 formed on the inner wall of the trench, a first conductive structure 122 and a second conductive structure 123 isolated from each other. Within the same trench, the extension depth of the first conductive structure 122 is greater than the extension depth of the second conductive structure 123, i.e., the distance of the first conductive structure 122 from the bottom of the trench is smaller than the distance of the second conductive structure 123 from the bottom of the trench. Specifically, the oxide layer 121 is divided into an isolation oxide layer 121a and a gate oxide layer 121b, wherein the oxide layer between the first conductive structure 122 and the inner wall of the trench is the isolation oxide layer 121a, and the oxide layer between the second conductive structure 123 and the inner wall of the trench is the gate oxide layer 121b. Specifically, the first conductive structure 122 and the second conductive structure 123 may be polysilicon. An extension region 130 is also formed in the drift region 100, the extension region 130 being located below the trench and surrounding the bottom of the trench, and the extension region 130 being of the second conductivity type, the extension region 130 being isolated from the first conductive structure 122 by the oxide layer 121.
The IGBT device further comprises an emitter extraction structure 310 and a gate extraction structure (not shown in the figures), which emitter extraction structure 310 and gate extraction structure may be metal pillars, in particular tungsten metal. The emitter extraction structure 310 is in contact with the first doped region 111 and the second doped region 112, and the gate extraction structure is in contact with the second conductive structure 123 in the trench.
Wherein the first conductivity type is N type, and the second conductivity type is P type; alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
It will be appreciated that the front side of the IGBT device should also have an emitter metal layer and a gate metal layer isolated from each other, the emitter extraction structures 310 are each connected to the emitter metal layer, and the gate extraction structures are each connected to the gate metal layer. It will be appreciated that the IGBT device further includes a buffer region 140 isolated from the body region and a collector region 150 in contact with the buffer region 140.
In the above IGBT device, the oxide layer between the second conductive structure 123 and the sidewall of the trench is the gate oxide layer 121b, the gate oxide layer 121b inside the trench and the second conductive structure 123 form a trench gate structure, and when a voltage is applied to the gate, a conducting channel is formed in the body region 110 at two sides of the trench, so as to provide a drift region current for the drift region 100, and make the IGBT conduct. Meanwhile, the bottom of the trench is also provided with a first conductive structure 122, and the first conductive structure 122 and the isolation oxide layer 121a in the drift region 100 form an inner field plate, so that the electric field distribution in the drift region 100 can be adjusted, a depletion region is formed in the drift region contacted with the inner field plate, and the withstand voltage level of the device is improved. Meanwhile, the first conductive structure 122 is formed at the bottom of the trench, so that the switching capacitance of the IGBT device can be reduced, and the conduction voltage drop of the device can be reduced. Since the extension region 130 is further formed in the drift region 100, the extension region 130 surrounds the bottom of the trench and has a conductivity type opposite to that of the drift region 100, and when the IGBT device is turned from the on state to the off state, the extension region 130 is combined with the remaining carriers of the drift region 100 to increase the switching speed. In addition, the problem of electric field concentration at the bottom of the trench can be solved by forming the extension region 130, and the breakdown position can be transferred from the trench to the interface between the extension region 130 and the drift region 100 when the device is reverse-voltage-resistant.
The first conductive structure 122 may be a floating structure, or may be electrically connected to an emitter to obtain an emitter potential. In one embodiment, as shown in fig. 1b, the first conductive structure 122 is led out from the trench end outside the cellular region, i.e. at the trench end, the first conductive structure 122 extends to the trench top and contacts the emitter connection structure 320, thereby obtaining an emitter potential, and thus enhancing the adjustment capability of the inner field plate and the extension region 130 to the electric field. In another embodiment, the first conductive structure 122 is a floating structure, the first conductive structure 122 is led out from the end of the trench, the first conductive structure 122 is not in contact with the emitter connecting structure 320, and an interlayer dielectric layer 200 with a certain thickness is further provided between the first conductive structure 122 and the emitter connecting structure, but the first conductive structure 122 can obtain the induced potential of the emitter, so that the first conductive structure 122 is electrified, and the electric connection with the emitter is realized in an induction manner, so that the leakage path of the emitter and the first conductive structure can be cut off, and the emitter leakage is avoided. In another embodiment, the first conductive structure 122 is a floating structure and is not electrically connected to the emitter, and cannot acquire the potential of the emitter, and therefore, the first conductive structure 122 is not charged.
In one embodiment, as shown in fig. 1a, the second doped region 112 is located in the body region 110 at the bottom of the first doped region 111, and the second doped region 112 may be in contact with the first doped region 111. On this structure, the emitter extraction structure 310 may extend from the top of the structure through the first doped region 111 and into the second doped region 112 to electrically connect the emitter with the first doped region 111 and the second doped region 112. Further, the width of the second doped region 112 is greater than the width of the emitter extraction structure 310, the emitter extraction structure 310 extends into the second doped region 112, and the bottom of the emitter extraction structure 310 is surrounded by the second doped region 112, so as to reduce the contact resistance between the emitter extraction structure 310 and the body region 110.
In one embodiment, as shown in fig. 1a, an interlayer dielectric layer 200 is further formed on the first doped region 111 and the trench, and the interlayer dielectric layer 200 may be silicon oxide. The emitter extraction structure 310 penetrates the interlayer dielectric layer 200 and the first doped region 111 on the one hand and extends into the second doped region 112 to be in contact with the first doped region 111 and the second doped region, and also penetrates the interlayer dielectric layer 200 and is in contact with the first conductive structure 122 in the trench on the other hand. The gate lead-out structure is formed directly above the trench, penetrating the interlayer dielectric layer 200 and contacting the second conductive structure 123 within the trench. Further, the grid electrode lead-out structure and the emitter electrode lead-out structure are staggered so as to be connected with the grid electrode metal layer and the emitter electrode metal layer respectively.
In particular, the distribution of the first conductive structures 122 and the second conductive structures 123 within the trench has a variety of designs.
In an embodiment, as shown in fig. 1a, in the trench, the first conductive structure 122 is distributed at the bottom of the trench, the second conductive structure 123 is distributed at the top of the trench, and the first conductive structure 122 and the second conductive structure 123 are isolated by the isolation structure 124, wherein the oxide layer 121 is formed between the first conductive structure 122 and the inner wall of the trench and between the second conductive structure 123 and the inner wall of the trench. Specifically, the oxide layer between the first conductive structure 122 and the inner wall of the trench is an isolation oxide layer 121a, and the oxide layer between the second conductive structure 123 and the inner wall of the trench is a gate oxide layer 121b. Specifically, the isolation structure 124 is silicon oxide. In this embodiment, the first conductive structure 122 at the bottom of the trench can regulate the electric field of the drift region, enhance the depletion of the drift region, weaken the switching capacitance, and improve the device performance. Further, as shown in fig. 1a, in the trench, the top surface of the first conductive structure 122 and the bottom surface of the second conductive structure 123 are approximately flat surfaces. In another embodiment, in the trench, the middle of the top surface of the first conductive structure 122 is protruded outwards, and the middle of the bottom surface of the second conductive structure 123 is recessed inwards to fit the protrusion of the first conductive structure 122.
In another embodiment, in the trench, the first conductive structure 122 extends from the top of the trench to the bottom of the trench, and an oxide layer 121 is formed between the first conductive structure 122 and the inner wall of the trench, the second conductive structure 123 is formed in the oxide layer 121 on both sides of the first conductive structure 122, the first conductive structure 122 is isolated from the second conductive structure 123 by the oxide layer 121, and the depth of the first conductive structure 122 extending toward the bottom of the trench is greater than the depth of the second conductive structure 123 extending toward the bottom of the trench. In this embodiment, the second conductive structure 123 is provided in the oxide layer 121, so that the thickness of the oxide layer 121 can be increased, thereby enhancing the device withstand voltage.
In an embodiment, as shown in fig. 1a, the buffer region 140 of the IGBT device is formed on a side of the drift region 100 away from the body region 110, the collector region 150 is formed on a side of the buffer region 140 away from the drift region 140, the buffer region 140 has a first conductivity type and the doping concentration of the buffer region 140 is greater than that of the drift region 100, and the collector region has a second conductivity type, thereby forming a vertical channel IGBT device, and increasing the on-current.
Since the extension region 130 and the body region 110 have the second conductivity type, the drift region 100 has the first conductivity type, and the extension region 130, the body region 110, and the drift region 100 interposed therebetween form a junction field effect transistor, the presence of which limits the channel current. Thus, in one embodiment, increasing the doping concentration of the drift region above the extension region 130 may reduce the impact of the junction field effect transistor and increase the channel current.
According to the IGBT device, the groove is formed, the first conductive structure and the second conductive structure are filled in the groove, and meanwhile, the expansion area surrounding the bottom of the groove is formed at the bottom of the groove, so that the switching capacitance of the IGBT device can be reduced, the conduction voltage drop of the device can be reduced, the problem of electric field concentration at the bottom of the groove can be solved, and the reliability of the device can be improved.
The application also relates to a preparation method of the IGBT device, as shown in fig. 2, which comprises the following steps:
step S210: forming a drift region on a semiconductor substrate, forming a groove on the drift region, forming an oxide layer on the inner wall of the groove, and forming the drift region with a first conductivity type.
As shown in fig. 3a, the drift region 100 of the first conductivity type is formed on a semiconductor substrate, and specifically, the drift region 100 may be formed by growing an epitaxial layer on the semiconductor substrate and doping the epitaxial layer with the first conductivity type. After forming the drift region 100, a hard mask is formed on the drift region 100, an etching window is defined through the hard mask, the drift region 100 is etched, and a trench is formed on the drift region 100. An oxide layer 121 is formed on the inner wall of the trench, and specifically, the oxide layer 121 may be formed on the inner wall of the trench by a thermal oxidation process, and at this time, the oxide layer 121 covers the inner wall and the bottom of the trench.
Step S220: an extension region is formed within the drift region under the trench, the extension region having the second conductivity type and surrounding a bottom of the trench.
As shown in fig. 3b, with the hard mask as a blocking layer, the drift region 100 under the trench is subjected to ion implantation of the second conductivity type through the trench, and an extension region 130 is formed in the drift region 100 under the trench, the extension region 130 surrounding the bottom of the trench.
Step S230: and filling the first conductive structure and the second conductive structure which are isolated from each other in the groove, wherein the bottom depth of the first conductive structure is larger than that of the second conductive structure.
In one embodiment, step S330 specifically includes:
step S231: and filling the first conductive structure into the groove, etching the first conductive structure and the oxide layer which are positioned at the top of the groove, and reserving the first conductive structure and the oxide layer at the bottom of the groove.
As shown in fig. 3c, the first conductive structure is filled into the trench through a deposition process, the first conductive structure and the oxide layer at the top of the trench are removed through etching by an etching back process, and the first conductive structure 122 and the oxide layer 121 at the bottom of the trench are exposed.
Step S232: and forming an isolation structure in the groove, wherein the isolation structure covers the first conductive structure at the bottom of the groove and does not fill the groove.
Specifically, as shown in fig. 3d, an isolation structure 124 is formed in the trench, specifically, the isolation structure may be filled in the trench by a deposition process, and then a portion of the isolation structure at the top of the trench is etched back, so as to retain the isolation structure 124 at the bottom. In one embodiment, the isolation structure may be silicon oxide, and the hard mask may be silicon oxide or silicon nitride, and the hard mask is removed during etching of the isolation structure.
Step S233: and forming an oxide layer on the inner wall of the groove above the isolation structure and filling the second conductive structure into the groove.
As shown in fig. 3e, an oxide layer is continuously formed on the inner wall of the trench above the isolation structure 124 and the second conductive structure 123 is filled in the trench, at this time, the oxide layer between the first conductive structure 122 and the inner wall of the trench is the isolation oxide layer 121a, and the oxide layer between the second conductive structure 123 and the inner wall of the trench is the gate oxide layer 121b.
Through steps S331 to S333, a filling structure is formed in the trench. Since the extension region 130 is isolated from the first conductive structure 122, the leakage path from the first conductive structure 122 to the extension region 130 is cut off, and thus leakage can be reduced.
Step S240: and doping the drift region with the second conductivity type to form a body region, wherein the body region is in contact with the groove, and the depth of the body region is smaller than that of the groove.
As shown in fig. 3f, the body region 110 is formed by doping the upper surface layer of the drift region 100 with the second conductivity type, the body region 100 and the trench structure are formed, and the depth of the body region 110 is smaller than the depth of the trench. A pass channel may be formed in the body region 110 on both sides of the trench by the trench gate.
In an embodiment, the process of forming the body region 110 is a high-temperature push-well process, wherein the temperature and time of the high-temperature push-well can be adjusted according to the doping depth and doping concentration of the body region, specifically, the temperature range of the high-temperature push-well can be controlled between 900 ℃ and 1200 ℃, and the time range of the high-temperature push-well can be controlled between 10min and 180 min. At the same time of high temperature push-trap, the dopant ions of the extension region 130 are diffused outward, so that the extension region 130 is expanded outward, thereby increasing the volume of the extension region 130.
In an embodiment, after step S330 and before step S340, the method further includes doping the drift region with the first conductivity type, and increasing the doping concentration of the drift region 100 to increase the on-current of the IGBT device.
Step S250: and doping the body region respectively by a first conductive type and a second conductive type, correspondingly forming a first doped region and a second doped region, wherein the first doped region is contacted with the groove, the doping concentration of the second doped region is larger than that of the body region, forming an emitter extraction structure contacted with the first doped region and the second doped region, and forming a grid extraction structure contacted with the second conductive structure.
In a specific embodiment, step S250 specifically includes:
step S251: and doping the upper surface layer of the body region with the first conduction type to form a first doped region.
As shown in fig. 3f, the upper surface layer of the body region 110 is doped with the first conductivity type, and a first doped region 111 is formed in the upper surface layer of the body region 110.
Step S252: forming an interlayer dielectric layer covering the first doped region and the groove on the first doped region, forming an emitter contact hole penetrating through the interlayer dielectric layer and the first doped region in sequence and extending into the body region, and forming a gate contact hole penetrating through the interlayer dielectric layer.
As shown in fig. 3g, an interlayer dielectric layer 200 covering the first doped region 111 and the trench is continuously formed on the first doped region 111. The interlayer dielectric layer 200, the first doped region 111 and a part of the body region 110 are sequentially etched to form an emitter contact hole which sequentially penetrates through the interlayer dielectric layer 200, the first doped region 111 and extends into the body region 110, and the body region 110 can be exposed through the emitter contact hole. It will be appreciated that, along with forming the emitter contact hole, a gate contact hole (not shown) is also formed, which penetrates the interlayer dielectric layer 200 and exposes the second conductive structure 123.
Step S253: and doping the body region through the emitter contact hole in a second conduction type to form a second doped region.
After forming the emitter contact hole, the body region 110 may be exposed through the emitter contact hole, doped through the emitter contact hole, and the second doped region 112 may be formed in the body region at the bottom of the emitter contact hole.
Step S254: and filling conductive materials into the emitter contact holes to form emitter lead-out structures, and filling conductive materials into the grid contact holes to form grid lead-out structures.
With continued reference to fig. 3g, the emitter contact hole is filled with a conductive material, forming an emitter extraction structure 310 in contact with the first and second doped regions 111, 112. It will be appreciated that the emitter contact hole is filled with a conductive material and the gate contact hole is also filled with a conductive material to form a gate lead-out structure (not shown).
It will be appreciated that the IGBT device also includes a buffer region and a collector region, and therefore, should include a step of forming the buffer region and the collector region in addition to the above steps.
In one embodiment, after step S250, the method further includes:
step S260: and forming a first conductive type buffer region on one side of the substrate, which is away from the body region, and forming a second conductive type collector region on one side of the buffer region, which is away from the body region.
As shown in fig. 3h, a buffer region 140 of the first conductivity type is formed on a side of the drift region facing away from the body region 110, and a collector region of the second conductivity type is formed on a side of the buffer region 140 facing away from the body region 110, thereby forming a vertical channel IGBT device.
It will be appreciated that the IGBT device further comprises an emitter metal layer and a gate metal layer on the top layer and a collector metal layer on the bottom surface, as shown in fig. 3 h.
According to the IGBT device manufacturing method, the trench gate structure is formed, and the extension region 130 surrounding the bottom of the trench is formed in the drift region 100, so that the switching speed can be improved, meanwhile, the switching capacitance of the IGBT device can be reduced, the conduction voltage drop of the device can be reduced, the problem of electric field concentration at the bottom of the trench can be solved, and the reliability of the device can be improved.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (7)
1. An IGBT device, comprising:
a drift region having a first conductivity type;
a body region formed within the drift region, having a second conductivity type;
a first doped region formed in the body region and having a first conductivity type;
the second doped region is formed in the body region and has a second conductive type, and the doping concentration of the second doped region is larger than that of the body region;
the grooves sequentially penetrate through the first doping region and the body region and extend into the drift region, and the second doping region is arranged at intervals with the grooves;
the filling structure comprises an oxide layer formed on the inner wall of the groove, and a first conductive structure and a second conductive structure which are filled in the groove and isolated from each other, wherein the bottom depth of the first conductive structure is greater than that of the second conductive structure;
an extension region formed in the drift region below the trench and surrounding the bottom of the trench, the extension region having the second conductivity type, the extension region being isolated from the first conductive structure by the oxide layer;
an emitter extraction structure in contact with the first doped region and the second doped region; and
a gate lead-out structure in contact with the second conductive structure;
the second doped region is positioned in the body region at the bottom of the first doped region, and the emitter extraction structure penetrates through the first doped region and extends into the second doped region; the depth of the top of the expansion region in the IGBT device is shallower than that of the bottom of the first conductive structure, the first conductive structure is led out from the end part of the groove and is electrically connected with the emitter leading-out structure outside the cellular region, and the bottom of the first conductive structure is in direct contact with the expansion region at the end part of the groove.
2. The IGBT device of claim 1 wherein the second doped region surrounds the bottom of the emitter extraction structure.
3. The IGBT device of claim 1, further comprising:
and the interlayer dielectric layer covers the first doped region and the groove, the emitter extraction structure also penetrates through the interlayer dielectric layer and is in contact with an emitter on the interlayer dielectric layer, and the grid extraction structure also penetrates through the interlayer dielectric layer and is in contact with a grid on the interlayer dielectric layer.
4. The IGBT device of claim 1 wherein the first and second conductive structures are formed at the bottom and top of the trench, respectively, with an isolation structure formed between the first and second conductive structures that isolates the first and second conductive structures.
5. The IGBT device of claim 1 wherein the doping concentration of the drift region above the extension region is higher than the doping concentration of the drift region below the extension region.
6. The preparation method of the IGBT device is characterized by comprising the following steps of:
forming a drift region on a semiconductor substrate, forming a groove on the drift region, forming an oxide layer on the inner wall of the groove, and forming a first conductive type drift region;
forming an extension region in the drift region below the trench with the oxide layer formed on the inner wall, wherein the extension region has a second conductivity type and surrounds the bottom of the trench;
filling a first conductive structure and a second conductive structure which are isolated from each other in the groove, wherein the bottom depth of the first conductive structure is greater than that of the second conductive structure;
doping the drift region with the second conductivity type to form a body region, wherein the body region is in contact with the groove, and the depth of the body region is smaller than that of the groove;
doping the body region respectively with a first conductive type and a second conductive type, correspondingly forming a first doped region and a second doped region, wherein the first doped region is in contact with the groove, the doping concentration of the second doped region is larger than that of the body region, an emitter extraction structure in contact with the first doped region and the second doped region is formed, and a grid extraction structure in contact with the second conductive structure is formed;
the second doped region is positioned in the body region at the bottom of the first doped region, and the emitter extraction structure penetrates through the first doped region and extends into the second doped region; the depth of the top of the expansion region in the IGBT device is shallower than that of the bottom of the first conductive structure, the first conductive structure is led out from the end part of the groove and is electrically connected with the emitter leading-out structure outside the cellular region, and the bottom of the first conductive structure is in direct contact with the expansion region at the end part of the groove.
7. The method of manufacturing of claim 6, further comprising, prior to doping the drift region with the second conductivity type to form a body region:
and doping the drift region with the first conductivity type, and improving the concentration of the drift region above the extension region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010418476.2A CN113690293B (en) | 2020-05-18 | 2020-05-18 | IGBT device and preparation method thereof |
| PCT/CN2020/140131 WO2021232801A1 (en) | 2020-05-18 | 2020-12-28 | Igbt device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010418476.2A CN113690293B (en) | 2020-05-18 | 2020-05-18 | IGBT device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113690293A CN113690293A (en) | 2021-11-23 |
| CN113690293B true CN113690293B (en) | 2024-04-12 |
Family
ID=78575409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010418476.2A Active CN113690293B (en) | 2020-05-18 | 2020-05-18 | IGBT device and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113690293B (en) |
| WO (1) | WO2021232801A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116525435A (en) * | 2022-09-05 | 2023-08-01 | 苏州华太电子技术股份有限公司 | IGBT device manufacturing method and IGBT device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129973A (en) * | 2008-12-01 | 2010-06-10 | Toyota Motor Corp | Semiconductor device |
| CN204011433U (en) * | 2014-06-09 | 2014-12-10 | 英飞凌科技股份有限公司 | Power semiconductor |
| CN107731899A (en) * | 2017-10-20 | 2018-02-23 | 电子科技大学 | A kind of trench gate electric charge memory type IGBT device and its manufacture method with Pliers bit architectures |
| CN110459604A (en) * | 2018-05-08 | 2019-11-15 | 艾鲍尔半导体 | Protected type trench device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016025177A (en) * | 2014-07-18 | 2016-02-08 | トヨタ自動車株式会社 | Switching element |
| JP2016181618A (en) * | 2015-03-24 | 2016-10-13 | 株式会社デンソー | Semiconductor device |
| JP6625938B2 (en) * | 2016-07-22 | 2019-12-25 | 株式会社東芝 | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator |
| CN108346692B (en) * | 2017-01-25 | 2023-11-21 | 杭州士兰集成电路有限公司 | Power semiconductor device and method of manufacturing the same |
| CN108321196B (en) * | 2018-02-05 | 2020-05-01 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| US20210320202A1 (en) * | 2020-04-10 | 2021-10-14 | Nami MOS CO., LTD. | Super Shielded Gate Trench MOSFET Having Superjunction Structure |
-
2020
- 2020-05-18 CN CN202010418476.2A patent/CN113690293B/en active Active
- 2020-12-28 WO PCT/CN2020/140131 patent/WO2021232801A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129973A (en) * | 2008-12-01 | 2010-06-10 | Toyota Motor Corp | Semiconductor device |
| CN204011433U (en) * | 2014-06-09 | 2014-12-10 | 英飞凌科技股份有限公司 | Power semiconductor |
| CN107731899A (en) * | 2017-10-20 | 2018-02-23 | 电子科技大学 | A kind of trench gate electric charge memory type IGBT device and its manufacture method with Pliers bit architectures |
| CN110459604A (en) * | 2018-05-08 | 2019-11-15 | 艾鲍尔半导体 | Protected type trench device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021232801A1 (en) | 2021-11-25 |
| CN113690293A (en) | 2021-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101404906B1 (en) | Lateral power devices with self-biasing electrodes | |
| US9105680B2 (en) | Insulated gate bipolar transistor | |
| US9153676B2 (en) | Insulated gate bipolar transistor | |
| CN109920854B (en) | MOSFET device | |
| US5349224A (en) | Integrable MOS and IGBT devices having trench gate structure | |
| US20220320295A1 (en) | Sic mosfet structures with asymmetric trench oxide | |
| CN110914997A (en) | Semiconductor device with LOCOS trench | |
| US20210217845A1 (en) | Semiconductor device | |
| CN112201690A (en) | MOSFET transistor | |
| KR20010102255A (en) | Self-aligned silicon carbide lmosfet | |
| WO2021232807A1 (en) | Semiconductor device and preparation method therefor | |
| WO2021232806A1 (en) | Trench gate metal oxide semiconductor field effect transistor and manufacturing method therefor | |
| US11264475B2 (en) | Semiconductor device having a gate electrode formed in a trench structure | |
| CN113690293B (en) | IGBT device and preparation method thereof | |
| KR20150061201A (en) | Power semiconductor device and method of fabricating the same | |
| CN113889523A (en) | Semiconductor device based on three-dimensional grid field plate structure and manufacturing method thereof | |
| WO2021232802A1 (en) | Igbt device and preparation method therefor | |
| WO2021232813A1 (en) | Trench gate metal oxide semiconductor field effect transistor, and manufacturing method thereof | |
| CN113097297A (en) | Power device structure and manufacturing method | |
| JPH09260648A (en) | Semiconductor device and manufacture thereof | |
| CN113690301B (en) | Semiconductor device and method for manufacturing the same | |
| US11862676B2 (en) | Semiconductor device and preparation method thereof | |
| CN213459746U (en) | MOSFET transistor | |
| KR20230114167A (en) | The semiconductor devices having a side channel and horizontal channel of a trench, and fabricating methods of the same | |
| JP2024074426A (en) | Semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |