WO2023010555A1 - 芯片封装结构及电子设备 - Google Patents
芯片封装结构及电子设备 Download PDFInfo
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- WO2023010555A1 WO2023010555A1 PCT/CN2021/111275 CN2021111275W WO2023010555A1 WO 2023010555 A1 WO2023010555 A1 WO 2023010555A1 CN 2021111275 W CN2021111275 W CN 2021111275W WO 2023010555 A1 WO2023010555 A1 WO 2023010555A1
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- WIPO (PCT)
- Prior art keywords
- chip
- substrate
- metal
- circuit device
- elevated
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000004806 packaging method and process Methods 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 5
- 230000001939 inductive effect Effects 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 230000003028 elevating effect Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000011800 void material Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
Definitions
- the present application relates to the technical field of packaging, in particular to a chip packaging structure and electronic equipment.
- capacitors or inductors are commonly used devices.
- the size of the capacitors and inductors to be used can vary widely for different needs. Some capacitors and inductors are small in size and can be formed inside the chip, while some capacitors and inductors are large in size and can only be set outside the chip.
- FIG. 1 shows a typical IC packaging structure.
- the package structure includes a package substrate 10 , a chip 11 and an inductor 12 .
- the packaging substrate 10 is used to carry the chip 11 and the inductor 12 .
- the inside of the package substrate 10 is provided with signal lines, and the bottom of the package substrate 10 is provided with solder balls.
- the signal flowing into the chip 11 must first pass through the inductor 12 . Therefore, to flow into the chip 11 , the signal needs to pass through the packaging substrate 10 , the inductor 12 , and the packaging substrate 10 in sequence, and then enter the chip 11 .
- the signal enters the package substrate 10 twice, which increases the complexity of wiring on the package substrate.
- more and more electronic devices will be carried on the top surface of the packaging substrate. Not only the signal lines in the packaging substrate will become denser, but also the space on the top surface of the packaging substrate will become increasingly tight.
- Embodiments of the present application provide a chip packaging structure and electronic equipment, which can solve the problem that more electronic devices cannot be carried due to the limited area of the packaging substrate.
- the present application provides a chip packaging structure, which includes a substrate, a chip, a first circuit device, and an elevated board.
- the substrate includes an upper surface (first surface) and a lower surface (second surface), and metal circuits are arranged on the substrate.
- the chip is arranged on the upper surface of the substrate.
- the top of the first circuit device is fixed on the lower surface of the substrate, and is electrically connected to the chip through metal lines.
- the top of the elevated board is fixed on the lower surface of the substrate, and a metal via hole connecting the top and bottom of the elevated board is provided in the elevated board, and the metal via hole is electrically connected to the metal line; the first circuit device
- the surface of the bottom is flush with the surface of the bottom of the raised plate.
- the first circuit device is arranged on the lower surface of the substrate, which no longer occupies the space on the upper surface of the substrate, and can make the upper surface of the substrate more capable of carrying more devices; at the same time, it can make the printed circuit board (Printed circuit board (PCB) signals can directly flow into the chip after passing through the first circuit device and the substrate; in this case, more metal lines in the substrate can be distributed in the direction vertical to the substrate, simplifying the wiring complexity of the substrate degree, so that the interaction path between the first circuit device and the chip in the vertical direction is shortened.
- PCB printed circuit board
- Planar pins (lead-out pins) are electrically connected to the PCB, thereby improving the processability and stability of the chip packaging structure when it is placed on the board (that is, on the board), and ensuring a reliable connection between the chip packaging structure and the PCB.
- the elevated plate is a ring structure, and the first circuit device is surrounded by the elevated plate.
- the first circuit device is a chip, an electron tube, a capacitive device, a resistive device or an inductive device.
- the chip, the first circuit device and the raised board are wrapped by molding; that is, the chip, the first circuit device and the raised board are integrally molded in the chip packaging structure.
- the first circuit device includes a first pin and a second pin; the first pin is located on the top of the first circuit device and is fixed on the lower surface of the substrate for electrically connecting with the metal line. sexual connection; the second pin is located at the bottom of the first circuit device.
- the first circuit device can be electrically connected to the metal lines in the substrate through the first pins on the top, and can be electrically connected to the PCB through the second pins on the bottom.
- the top and the bottom of the elevated board are respectively provided with welding pads connected to two ends of the metal via hole.
- the elevated board can be electrically connected to the metal lines in the substrate through the solder pads on the top, and electrically connected to the PCB through the solder pads on the bottom.
- metal side walls are formed on the sides of the elevated board; the metal side walls extend along the sides of the elevated board to the top and bottom of the elevated board, and are exposed at the top and bottom of the elevated board.
- the metal via hole and the metal sidewall can transmit signals at the same time, which is equivalent to having two flow paths, thereby increasing the flow path, thereby improving the flow capability of the chip package structure in the vertical direction.
- the metal vias are filled with resin to improve the reliability of the metal vias.
- the present application also provides an electronic device, including a printed circuit board and a chip package structure as provided in any of the aforementioned possible implementation modes;
- the board is electrically connected.
- the bottom of the first circuit device in the chip package structure is fixed on the printed circuit board and is electrically connected to the printed circuit board.
- FIG. 1 is a schematic diagram of a chip packaging structure provided by the related art of the present application.
- FIG. 2 is a schematic diagram of a chip package structure provided by an embodiment of the present application.
- Fig. 3 is a schematic plan view of an elevated board provided by an embodiment of the present application.
- Fig. 4 is the schematic cross-sectional view of the elevated plate in Fig. 3 along the OO' position;
- FIG. 5 is a schematic cross-sectional view of an elevated plate provided in an embodiment of the present application.
- Fig. 6 is a schematic cross-sectional view of an elevated board provided by an embodiment of the present application.
- Some embodiments of the present application provide an electronic device, and the electronic device may be applied in fields such as a network center and a base station, and the present application does not make any special limitations on this.
- the electronic device includes a printed circuit board (printed circuit board, PCB) 02, and at least one chip package structure 01 connected to the PCB 02.
- PCB printed circuit board
- FIG. 2 it is only schematically illustrated by taking a chip package structure 01 as an example, but the application is not limited thereto. In other possible implementation modes, two or more than two can also be set on the PCB 02 chip package structure 01.
- the chip package structure 01 may be a 3D (dimension) chip package structure, a 2.5D chip package structure, a SiP (system in package, system-in-package) structure, and the like.
- the chip packaging structure 01 can be applied to power management chip packaging structures, radio frequency front-end chip packaging structures, and the like.
- the chip packaging structure 01 is provided with a substrate 1 , at least one chip 2 (die), and at least one first circuit device 3 .
- the substrate 1 has an upper surface a1 (that is, the first surface) and a lower surface a2 (that is, the second surface) that are oppositely disposed, and metal circuits are disposed in the substrate 1 .
- the upper surface a1 and the lower surface a2 of the substrate 1 are usually provided with connection structures electrically connected to the internal metal lines, such as pads (or pads, pads), micro bumps ( ⁇ bump), etc.;
- the connection structure, pins, etc. are similar to this and will not be repeated here.
- the chip 2 is disposed on the upper surface a1 of the substrate 1 and is electrically connected to the metal circuit in the substrate 1 .
- the chip 2 can be connected to the connection structure (such as pad) on the upper surface of the substrate 1 through pins (such as pads) provided on the bottom surface thereof.
- the first circuit device 3 is arranged on the lower surface a2 of the substrate 1, the top of the first circuit device 3 is fixed on the lower surface a2 of the substrate 1, and the first circuit device 3 is electrically connected to the chip 2 through the metal circuit provided in the substrate 1 .
- the first circuit device 3 can be connected to the connection structure (such as a pad) provided on the lower surface of the substrate 1 through the pins provided on the top (ie, the first pins).
- the bottom of the first circuit device 3 can also be provided with pins (i.e. the second pin), the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed on the PCB 02, and the bottom of the first circuit device 3 can be fixed.
- Pin is electrically connected with PCB 02.
- the present application does not limit the specific arrangement form of the above-mentioned first circuit device 3 .
- the first circuit device 3 can be an active device, such as a chip (integrated circuit), an electron tube, etc.; it can also be a passive device, such as an inductance device, a capacitor device, a resistance device, etc.
- the first circuit device 3 may be a large inductive device.
- the chip packaging structure 01 may be provided with one first circuit device 3 , or may be provided with two or more first circuit devices 3 . In practice, the first circuit device 3 can be set as required.
- the first circuit device 3 is arranged on the lower surface a2 of the substrate 1 in this application.
- the substrate 1 is no longer occupied.
- the space on the upper surface of the substrate can make the upper surface of the substrate 1 more capable of carrying more devices;
- the signal through the PCB 02 can directly flow into the chip 2 after passing through the first circuit device 3 and the substrate 1; in this case Therefore, more metal circuits in the substrate 1 can be distributed in the direction perpendicular to the substrate 1 , which simplifies the wiring complexity of the substrate and shortens the interaction path between the first circuit device 3 and the chip 2 in the vertical direction.
- the first circuit device 3 since the first circuit device 3 itself has a certain thickness, there is a certain height difference ⁇ h between the bottom of the first circuit device 3 and the lower surface a2 of the substrate 1 .
- the lower surface a2 of the substrate 1 can be Located in the area outside the first circuit device 3, a frame board 4 (frame board, FB) is set, and the electrical connection between the substrate 1 and the PCB 02 is realized through the frame board 4, that is, the PCB 02 is connected to the substrate 1 through the frame board 4.
- Fig. 3 is a schematic plan view of the elevated plate 4 in Fig. 2, and Fig. 4 is a sectional view of Fig. 3 along OO' position.
- the top of the elevated plate 4 is fixed on the lower surface a2 of the base plate 1, and a metal via hole 40 connecting the top and the bottom is provided inside the elevated plate 4, and on the frame
- the top of the elevated plate 4 is electrically connected to the metal line in the substrate 1 through the metal via 40; in this case, the bottom of the elevated plate 4 can be fixed on the PCB 02 and electrically connected to the PCB 02 through the metal via 40 . That is to say, by setting the elevating plate 4 in the area outside the first circuit device 3 on the lower surface a2 of the substrate 1, the electrical connection between the PCB 02 and the substrate 02 is realized through the elevating plate 4.
- solder pads P connected to both ends of the metal via hole 40 are respectively provided on the top and bottom of the elevated board 4 .
- the elevated board 4 can be electrically connected to the metal lines in the substrate 1 through the solder pads P located on the top, and electrically connected to the PCB 02 through the solder pads P located at the bottom.
- the top and bottom of the elevated board 4 are respectively provided with soldering pads P connected to both ends of the metal via hole 40 as an example for schematic illustration.
- the gap between the bottom of the first circuit device 3 and the lower surface a2 of the substrate 1 can be filled by the elevated plate 4.
- the height difference ⁇ h in this case, the bottom of the elevating board 4 and the bottom of the first circuit device 3 can be electrically connected to the PCB 02 through the pin (that is, the lead-out pin) on the same plane, thereby improving the chip package structure 02.
- the manufacturability and stability of the board ensure the reliable connection of the chip package structure 01 and the PCB 02.
- the bottom surface of the elevated board 4 is flush with the bottom surface of the first circuit device 3, and the bottom surface of the elevated board 4 and the bottom of the first circuit device 3 are electrically connected to the PCB 02 as An example is illustrated.
- the above description about the bottom surface of the elevated board 4 being “flat” with the bottom surface of the first circuit device 3 does not refer to absolute coplanarity, and those skilled in the art should understand that at least Ensure that the bottom surface of the elevated board 4 and the bottom surface of the first circuit device 3 can be connected to the PCB 02 to achieve normal connection, that is, the bottom surface of the elevated board 3 and the bottom of the first circuit device 3 There may be a certain height difference on the surface, but the height difference can be regarded as "flat” within the error range allowed by the connection process.
- the welding plane can allow an error within 30 ⁇ m, then the height difference between the bottom surface of the elevated plate 4 and the bottom surface of the first circuit device 3 can be regarded as a flat surface within 30 ⁇ m. together.
- the elevated board 4 and the first circuit device 3 can be packaged as a whole, that is, the chip 2, the first circuit device 3 and the elevated board 4 are integrally packaged. Wrapped in plastic wrap. In other possible implementation manners, the elevated board 4 and the first circuit device 3 may also be fixed on the lower surface of the substrate 1 by means of underfill. This application does not limit this, and it can be set according to actual needs.
- the elevating plate 4 arranged in the chip packaging structure 01 there is no limitation on the shape and quantity of the elevating plate 4 arranged in the chip packaging structure 01 , which can be arranged according to actual needs.
- a ring-shaped elevated plate 4 may be provided in the chip package structure 01 , and the first circuit device 3 is surrounded by the ring-shaped elevated plate.
- the elevated board 4 can be in the shape of a strip or a block; in this case, multiple elevated boards 4 can be set in the chip packaging structure 01, such as a plurality of elevated boards 4 can be distributed along the circumference of the chip package structure 01.
- the central part of the metal via 40 is a hole V. Therefore, in order to improve the reliability of the metal via 40, in some possible implementation methods, The void V of the metal via 40 is filled.
- the filling material in the void V of the metal via 40 there is no limitation on the filling material in the void V of the metal via 40 .
- the filling material can be a conductive material, such as copper, copper alloy, aluminum, etc.; for another example, the filling material can also be an insulating material, such as a resin material. It can be understood that filling the void V of the metal via hole 40 with a conductive material (such as copper) can improve the flow capacity of the chip package structure in the vertical direction.
- the void V of the metal via hole 40 may be filled with copper material by pouring copper paste.
- resin may be used to fill the void V of the metal via hole 40 .
- the flow capacity of the chip package structure 01 in the vertical direction is limited to a certain extent.
- the metal side wall S extends along the side of the elevated plate 4 to the top and bottom of the elevated plate 4 , and is connected to the metal via hole 40 through the solder pad P.
- the metal via 40 and the metal sidewall S can transmit signals at the same time, which is equivalent to having two flow paths, thereby increasing the flow path, thereby improving the flow capacity of the chip package structure in the vertical direction .
- the two metal sidewalls S extend along the side of the raised board 4 to the top and bottom of the raised board 4 , and are connected to the metal via hole 40 through the welding pad P.
- the two metal sidewalls S and the metal via 40 can transmit signals at the same time, which is equivalent to having three flow paths, which further increases the flow path and improves the vertical stability of the chip package structure. flow capacity.
- a group (multiple) of metal vias 40 can be electrically connected to one metal sidewall S, or can be electrically connected to multiple independently provided metal sidewalls S. This is not limited, and can be set according to actual needs.
- a group of metal vias 40 are connected to a plurality of independently arranged metal sidewalls S. In this case, the same electrical signal can be transmitted through the plurality of metal sidewalls S respectively, so as to meet the needs of the chip.
- Requirements for the package structure for example, multiple metal sidewalls S can be used to meet the requirements of multiple power supplies and multiple signals for the chip package structure.
- the manufacturing process of the elevated plate 4 will be schematically described below.
- the elevated board 4 can be made of organic resin material, and the metal parts (such as metal vias 40, metal side walls S, soldering pads P, etc.) provided in the elevated board 4 can be made of copper, but not Not limited to this.
- the elevated board 4 can be manufactured using low-cost PCB preparation technology.
- a plate of resin material can be used first, and the through hole through the top and bottom of the plate and the overall outline (such as ring shape, strip shape, etc.) can be engraved through the milling cutter operation to make the main structure of the elevated plate 4 . Then, electroplating or electroless plating can be used to perform metallization on the inside of the through hole and part of the side of the main structure to form metal vias, metal side walls, etc.; then use a milling cutter to mill off the excess to obtain the required elevated board 4.
- the elevated plate 4 provided in this application adopts the method of the metal via 40 , based on the current manufacturing process of the metal via 40 (such as electroplating process), the height of the metal via 40 can reach more than 2 mm. That is to say, the use of the elevated plate 4 provided by the embodiment of the present application can solve the problem that the height difference of the lower surface of the substrate exceeds 2mm and the pins, so as to meet the needs of a wider range of chip packaging structures. For example, a chip packaging structure that can meet the extremely large height difference brought about by ultra-large height circuit devices.
- the height of the metal via hole 40 in the elevated plate 4 may be 2mm-3mm; for example, it may be 2mm, 2.5mm, 3mm and so on.
- the height difference between the substrate 1 and the first circuit device 4 is filled by adding an elevated plate 4 in the chip package structure 01, so that the size of the chip package structure 01 will hardly be enlarged, that is, The size of the chip package structure 01 is almost unchanged. If there is no need to change the size and position of the original pads in the chip package structure, the board-level application restrictions are small.
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Abstract
本申请提供了一种芯片封装结构及电子设备,涉及封装技术领域,能够解决因封装基板面积有限而无法承载更多电子器件的问题。该芯片封装结构包括基板、芯片、第一电路器件、架高板。其中,基板包括上表面(第一表面)和下表面(第二表面),且基板中设有金属线路。芯片设置在基板的上表面。第一电路器件的顶部被固定在基板的下表面上,并通过金属线路与芯片电连接。架高板的顶部被固定在基板的下表面上,并且架高板内设有连通架高板的顶部和底部的金属过孔,且金属过孔与金属线路电性连接;第一电路器件的底部的表面与架高板的底部的表面平齐。
Description
本申请涉及封装技术领域,尤其涉及一种芯片封装结构及电子设备。
在电子电路中,电容或电感是常用器件。针对不同的需求,要使用的电容和电感的尺寸会差异很大。有些电容和电感,体积较小,能够形成在芯片内部,而有的电容电感体积较大,只能设置在芯片外部。
图1所示是一种典型的集成电路封装结构。该封装结构包括封装基板10、芯片11以及电感12。其中,封装基板10用于承载芯片11和电感12。封装基板10的内部设置有信号线路,并且封装基板10的底部设置有焊球。在某些场景下,流入芯片11的信号要先经过电感12。因此,信号要流入芯片11,需要依次通过封装基板10、电感12、封装基板10,然后才能进入芯片11。在这个过程中,信号进入了封装基板10两次,这增加了封装基板上的布线复杂度。而且,随着工业需求的提升,封装基板顶部表面承载的电子器件会越来越多,不仅封装基板内的信号线路越来越密集,封装基板的顶部表面的空间也愈发紧张。
发明内容
本申请实施例提供一种芯片封装结构及电子设备,能够解决因封装基板面积有限而无法承载更多电子器件的问题。
本申请提供一种芯片封装结构,该芯片封装结构包括基板、芯片、第一电路器件、架高板。其中,基板包括上表面(第一表面)和下表面(第二表面),且基板上设有金属线路。芯片设置在基板的上表面。第一电路器件的顶部被固定在基板的下表面上,并通过金属线路与芯片电连接。架高板的顶部被固定在基板的下表面上,并且架高板内设有连通架高板的顶部和底部的金属过孔,且金属过孔与金属线路电性连接;第一电路器件的底部的表面与架高板的底部的表面平齐。
一方面,本申请中将第一电路器件设置在基板的下表面,不再占用基板的上表面的空间,能够使得基板的上表面更够承载更多的器件;同时能够使得经印刷线路板(printed circuit board,PCB)的信号可以直接通过第一电路器件和基板后流入芯片;在此情况下,能够使得基板中的金属线路更多的分布在垂直基板的方向上,简化了基板的布线复杂度,使得第一电路器件与芯片在垂直方向的交互路径缩短。另一方面,通过在基板的下表面位于第一电路器件以外区域设置架高板,并且架高板内部设置连通顶部和底部的金属过孔;通过设置架高板的底部的表面与第一电路器件的底部的表面平齐,通过第一电路器件填补第一电路器件的底部与基板的下表面之间的高度差,并通过架高板实现基板的下表面与第一电路器件的底部的同一平面出pin(引出引脚),与PCB进行电连接,从而提升芯片封装结构在上板(也即上)时的可加工性和稳定性,保证芯片封装结构与PCB的可靠连接。
在一些可能实现的方式中,架高板为环形结构,第一电路器件被架高板环绕。
在一些可能实现的方式中,第一电路器件为芯片、电子管、电容器件、电阻器件或电感器件。
在一些可能实现的方式中,芯片、第一电路器件以及架高板被塑封材料(molding)包裹;也即在芯片封装结构中芯片、第一电路器件以及架高板整体被塑封。
在一些可能实现的方式中,第一电路器件包括第一引脚和第二引脚;第一引脚位于第一电路器件的顶部,被固定在基板的下表面上,用于与金属线路电性连接;第二引脚位于第一电路器件的底部。在此情况下,第一电路器件可以通过顶部设置的第一引脚与基板中的金属线路实现电连接,通过底部设置的第二引脚实现与PCB的电连接。
在一些可能实现的方式中,架高板的顶部和底部上分别设置有与金属过孔的两端连接的焊垫。在此情况下,架高板可以通过位于顶部的焊垫与基板中的金属线路电连接,通过位于底部的焊垫与PCB电连接。在一些可能实现的方式中,架高板的侧面形成有金属侧壁;金属侧壁沿着架高板的侧面延伸至架高板的顶部和底部,并在架高板的顶部和底部与暴露于架高板的顶部和底部的金属过孔连接。在此情况下,金属过孔和金属侧壁能够同时进行信号传输,相当于具有两条通流路径,从而增加了通流路径,进而提高了芯片封装结构在垂直方向上的通流能力。
在一些可能实现的方式中,金属过孔中填充有树脂,以提高金属过孔的可靠性。
本申请还提供一种电子设备,包括印刷线路板以及如前述任一种可能实现的方式中提供的芯片封装结构;架高板的底部固定在印刷线路板上,并通过金属过孔与印刷线路板电性连接。
在一些可能实现的方式中,芯片封装结构中的第一电路器件的底部固定在印刷线路板上,并与印刷线路板电性连接。
图1为本申请相关技术提供的一种芯片封装结构示意图;
图2为本申请实施例提供的一种芯片封装结构示意图;
图3为本申请实施例提供的一种架高板的平面示意图;
图4为图3中的架高板沿OO’位置的剖面示意图;
图5为本申请实施例提供的一种架高板的剖面示意图;
图6为本申请实施例提供的一种架高板的剖面示意图。
为使本申请的目的、技术方案和优点更加清楚,下面将结合本申请中的附图,对本申请中的技术方案进行清楚地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的,而不能理解为指示或暗示相对重要性,也不能理解为指示或暗示顺序。“连接”、“相连”等类似的词语,用于表达不同组件之间的互通或互相作用,可以包括直接相连或通 过其他组件间接相连。“至少一个(项)”是指一个或者多个,“多个”是指两个或两个以上。“和/或”,用于描述关联对象的关联关系,表示可以存在三种关系,例如,“A和/或B”可以表示:只存在A,只存在B以及同时存在A和B三种情况,其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含,例如,包含了一系列步骤或单元。方法、***、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于相对于附图中的部件的方位而言的,这些方向性术语是相对的概念,它们用于相对于的描述和澄清,其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请一些实施例提供一种电子设备,该电子设备可以应用于网络中心、基站等领域,本申请对此不作不做特殊限制。
参考图2所示,上述电子设备中包括印制线路板(printed circuit board,PCB)02,以及与PCB 02连接至少一个芯片封装结构01。图2中仅是示意的以一个芯片封装结构01为例进行示意说明的,但本申请并不限制于此,在另一些可能实现的方式中,PCB 02上也可以设置两个或两个以上的芯片封装结构01。
本申请对于上述芯片封装结构01的类型、应用等均不作限制。示意的,该芯片封装结构01可以是3D(dimension)芯片封装结构、2.5D芯片封装结构、SiP(system in package,***级封装)结构等。该芯片封装结构01可以应用至电源管理类芯片封装结构、射频前端类芯片封装结构等。
以下对本申请实施例提供的芯片封装结构01的具体设置进行示意的说明。
参考图2所示,上述芯片封装结构01中设置有基板1、至少一个芯片2(die)、至少一个第一电路器件3。
基板1具有相对设置的上表面a1(也即第一表面)和下表面a2(也即第二表面),并且在基板1中设置有金属线路。示意的,基板1的上表面a1和下表面a2通常设置有与内部的金属线路电连接的连接结构,如焊垫(或者说焊盘、pad)、微凸点(μbump)等;下文所涉及的连接结构、引脚等,均于此类似,不再赘述。
芯片2设置在基板1的上表面a1,并与基板1中的金属线路电性连接。示意的,芯片2可以通过设置在其下表面的引脚(如pad)与基板1的上表面的连接结构(如pad)连接。
第一电路器件3设置在基板1的下表面a2,第一电路器件3的顶部被固定在基板1的下表面a2,并且第一电路器件3通过基板1中设置的金属线路与芯片2电连接。
示意的,第一电路器件3可以通过顶部设置的引脚(即第一引脚)与基板1的下表面设置的连接结构(如pad)连接。当然,在一些可能实现的方式中,第一电路器件3的底部也可以设置引脚(即第二引脚),该第一电路器件3底部可以固定在PCB 02上,并通过底部设置的引脚与PCB 02电连接。
本申请对于上述第一电路器件3的具体设置形式不作限制。第一电路器件3可以是有源器件,如芯片(集成电路)、电子管等;也可以是无源器件,如电感器件、电容器件、电阻器件等。例如,在一些实施例中,第一电路器件3可以是大型电感器件。该芯片封装结构01中可以设置有一个第一电路器件3,也可以设置有两个或两个以上的第一电路器 件3。实际中可以根据需要设置第一电路器件3。
此处可以理解的是,相比于将电路器件放置在基板1的上表面a1而言,本申请中将第一电路器件3设置在基板1的下表面a2,一方面,不再占用基板1的上表面的空间,能够使得基板1的上表面更够承载更多的器件;另一方面,经PCB 02的信号可以直接通过第一电路器件3和基板1后流入芯片2;在此情况下,能够使得基板1中的金属线路更多的分布在垂直基板1的方向上,简化了基板的布线复杂度,使得第一电路器件3与芯片2在垂直方向的交互路径缩短。
在此基础上,参考图2所示,由于第一电路器件3本身具有一定的厚度,从而使得第一电路器件3的底部与基板1的下表面a2之间存在一定的高度差Δh。基于此,为了保证基板1的下表面a2正常出pin(引出引脚),与PCB 02进行正常的电连接,在本申请实施例提供的芯片封装结构01中,可以在基板1的下表面a2中位于第一电路器件3以外区域,设置架高板4(frame board,FB),通过架高板4实现基板1与PCB 02的电连接,也即PCB 02通过架高板4与基板1中的金属线路实现电连接。
图3为图2中架高板4的平面示意图,图4为图3沿OO’位置的剖面图。结合图2、图3和图4所示,上述架高板4的顶部被固定在基板1的下表面a2,并且架高板4内部设置有连通顶部和底部的金属过孔40,并且在架高板4的顶部通过金属过孔40与基板1中的金属线路电连接;在此情况下,架高板4的底部可以固定在PCB 02上,并通过金属过孔40与PCB 02实现电连接。也就是说,通过在基板1的下表面a2位于第一电路器件3以外区域设置架高板4,通过该架高板4实现PCB 02与基板02之间的电连接。
在一些可能实现的方式中,参考图4所示,架高板4的顶部和底部上分别设置有与金属过孔40的两端连接的焊垫P。在此情况下,架高板4可以通过位于顶部的焊垫P与基板1中的金属线路电连接,通过位于底部的焊垫P与PCB 02电连接。以下实施例均是架高板4的顶部和底部上分别设置有与金属过孔40的两端连接焊垫P为例进行示意说明的。
可以理解的是,为了保证通过架高板4实现PCB 02与基板02的电连接,应保证架高板4的底部的表面凸出于第一电路器件3的底部的表面,或者,架高板4的底部的表面与第一电路器件3的底部的表面平齐。考虑到整个芯片封装结构01的厚度,避免造成芯片封装结构01厚度的增加,通常可以设置架高板4的底部的表面与第一电路器件3的底部的表面平齐。
在设置架高板4的底部的表面与第一电路器件3的底部的表面平齐的情况下,通过架高板4能够填补第一电路器件3的底部与基板1的下表面a2之间的高度差Δh,在此情况下,可以在架高板4的底部与第一电路器件3的底部进行同一平面出pin(即引出引脚)与PCB 02进行电连接,从而提升芯片封装结构02在上板(也即上PCB)时的可加工性和稳定性,保证芯片封装结构01与PCB 02的可靠连接。以下实施例均是架高板4的底部的表面与第一电路器件3的底部的表面平齐,并且架高板4的底部的表面与第一电路器件3的底部均与PCB 02电连接为例进行示意说明的。
需要说明的是,上述关于架高板4的底部的表面与第一电路器件3的底部的表面“平齐”的描述,并不指绝对的共平面,本领域的技术人员应当理解到,至少保证架高板4的底部的表面与第一电路器件3的底部的表面能够进行出pin与PCB 02实现正常连接即可,也即架高板3的底部的表面与第一电路器件3的底部的表面可能存在的一定的高度差,但 该高度差在连接工艺允许的误差范围内均可视为“平齐”。例如,以焊接工艺为例,焊接平面可以允许存在30μm以内的误差,那么架高板4的底部的表面与第一电路器件3的底部的表面之间的高度差在30μm以内即可以视为平齐。
还需要说明的是,在本申请实施例提供的芯片封装结构01中,可以将架高板4和第一电路器件3进行整体封装,即芯片2、第一电路器件3以及架高板4整体被塑封材料包裹。在另一些可能实现的方式中,也可以将架高板4和第一电路器件3可以通过点胶(underfill)的方式固定在基板1的下表面。本申请对此不作限制,实际中可以根据需要进行设置。
另外,本申请中对于设置在芯片封装结构01中的架高板4的形状、数量等不作限制,实际中可以根据需要进行设置。例如,在一些可能实现的方式中,参考图2和图3所示,芯片封装结构01中可以设置一个环形结构的架高板4,第一电路器件3被环形结构的架高板环绕。又例如,在一些可能实现的方式中,架高板4可以为条状、块状等结构;在此情况下,芯片封装结构01中可以设置多个架高板4,如多个架高板4可以沿芯片封装结构01的一周分散设置。
此外,参考图4所示,考虑到金属过孔40的实际制作工艺,金属过孔40的中心部分为孔隙V,因此为了提高金属过孔40的可靠性,在一些可能实现的方式中,可以对金属过孔40的孔隙V进行填充。
本申请中对于金属过孔40的孔隙V中的填充材料不作限制。例如,该填充材料可以是导电材料,如铜、铜合金、铝等;又例如,该填充材料还可以是绝缘材料,如树脂类材料。可以理解的是,采用导电材料(如铜)对金属过孔40的孔隙V进行填充,能够提高芯片封装结构在垂直方向的通流能力。
示意的,在一些可能实现的方式中,可以采用灌注铜浆的方式对金属过孔40的孔隙V进行铜材料的填充。
示意的,在一些可能实现的方式中,可以采用树脂对金属过孔40的孔隙V进行填充。
另外,由于金属过孔40的粗度以及密度等受制作工艺条件的限制,从而会使得芯片封装结构01在垂直方向的通流能力受到一定的限制。基于此,为了满足芯片封装结构01对垂直方向的大通流能力的要求,参考图5所示,在一些可能实现的方式中,可以在架高板4的一个侧面设置金属侧壁S,并且该金属侧壁S沿着架高板4的侧面延伸至架高板4的顶部和底部,通过焊垫P与金属过孔40连接。在此情况下,金属过孔40和金属侧壁S能够同时进行信号传输,相当于具有两条通流路径,从而增加了通流路径,进而提高了芯片封装结构在垂直方向上的通流能力。
在此基础上,为了进一步的增加芯片封装结构01在垂直方向上的通流能力,参考图6所示,在一些可能实现的方式中,可以在架高板4相对的两个侧壁分别设置金属侧壁S,两个金属侧壁S沿着架高板4的侧面延伸至架高板4的顶部和底部,通过焊垫P与金属过孔40连接。在此情况下,两个金属侧壁S与金属过孔40能够同时进行信号传输,相当于具有三条通流路径,也即进一步的增加了通流路径,提高了芯片封装结构在垂直方向上的通流能力。
在本申请实施例提供的芯片封装结构中,一组(多个)金属过孔40可以与一个金属侧壁S电连接,也可以与多个独立设置的金属侧壁S电连接,本申请对此不作限制,实际 中可以根据需求进行设置。示意的,在一些实施例中,一组金属过孔40与多个独立设置的金属侧壁S连接,在此情况下,可以通过多个金属侧壁S分别传输相同的电信号,以满足芯片封装结构的需求;例如,可以通过多个金属侧壁S满足芯片封装结构多电源、多信号的需求。
以下对架高板4的制作过程进行示意的说明。
示意的,架高板4可以采用有机树脂材料制成,架高板4中设置的金属部件(如金属过孔40、金属侧壁S、焊垫P等)可以采用铜材质制成,但并不限制于此。
在一些可能实现的方式中,可以采用低成本的PCB制备技术来制作架高板4。
示意的,可以先采用树脂材料的板材,通过铣刀作业可以镂刻出贯通板材顶部和底部的通孔以及整体轮廓(如环状、条状等)制作出架高板4的主体结构。然后可以采用电镀或者化学镀的方式,在通孔的内侧以及主体结构的部分侧面做金属化处理形成金属过孔、金属侧壁等;再以铣刀铣去多余部分,得到需要的架高板4。
可以理解的是,相比于相关技术中采用植球、铜柱等对具有高度差的基板进行出pin而言,一般仅能满足1mm以内的高度差。本申请提供的架高板4中采用金属过孔40的方式,基于目前对金属过孔40的制作工艺(如电镀工艺),金属过孔40的高度能够达到2mm以上。也就是说,采用本申请实施例提供的架高板4能够解决基板的下表面在2mm以上的高度差出pin的问题,从而也就能够满足更大范围芯片封装结构的需求。例如,可以满足超大高度电路器件所带来的极大高度差的芯片封装结构。
示意的,在一些可能实现的方式中,架高板4中的金属过孔40的高度可以为2mm~3mm;例如,可以是2mm、2.5mm、3mm等。
另外,还可以理解的是,本申请中通过在芯片封装结构01中添加架高板4来填补基板1与第一电路器件4的高度差,几乎不会扩大芯片封装结构01的尺寸,也即芯片封装结构01的尺寸几乎不变,如不需要额外改动芯片封装结构中原有的焊垫大小、位置等,板级应用限制小。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
Claims (10)
- 一种芯片封装结构,其特征在于,包括:基板,所述基板包括第一表面和第二表面,所述基板上设有金属线路;芯片,设置在所述第一表面上;第一电路器件,所述第一电路器件的顶部被固定在所述第二表面上,并通过所述金属线路与所述芯片电连接;以及架高板,所述架高板的顶部被固定在所述第二表面上,所述架高板内设有连通所述架高板的顶部和底部的金属过孔,且所述金属过孔与所述金属线路电性连接;所述第一电路器件的底部的表面与所述架高板的底部的表面平齐。
- 如权利要求1所述的芯片封装结构,其特征在于,所述架高板为环形结构,所述第一电路器件被所述架高板环绕。
- 如权利要求1或2所述的芯片封装结构,其特征在于,所述第一电路器件为芯片、电子管、电容器件、电阻器件或电感器件。
- 如权利要求1-3任一项所述的芯片封装结构,其特征在于,所述芯片、所述第一电路器件以及所述架高板被塑封材料包裹。
- 如权利要求1-4任一项所述的芯片封装结构,其特征在于,所述第一电路器件包括第一引脚和第二引脚;所述第一引脚位于所述第一电路器件的顶部,被固定在所述第二表面上,用于与所述金属线路电性连接;所述第二引脚位于所述第一电路器件的底部。
- 如权利要求1-5任一项所述的芯片封装结构,其特征在于,所述架高板的顶部和底部上分别设置有与所述金属过孔的两端连接的焊垫。
- 如权利要求1-6任一项所述的芯片封装结构,其特征在于,所述架高板的侧面形成有金属侧壁;所述金属侧壁沿着所述架高板的侧面延伸至所述架高板的顶部和底部,并在所述架高板的顶部和底部与暴露于所述架高板的顶部和底部的金属过孔连接。
- 如权利要求1-7任一项所述的芯片封装结构,其特征在于,所述金属过孔中填充有树脂。
- 一种电子设备,其特征在于,包括印刷线路板以及如权利要求1-8任一项所述的芯片封装结构;所述架高板的底部固定在所述印刷线路板上,并通过所述金属过孔与所述印刷线路板电性连接。
- 如权利要求9所述的电子设备,其特征在于,所述芯片封装结构中的第一电路器件的底部固定在所述印刷线路板上,并与所述印刷线路板电性连接。
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TW200414835A (en) * | 2003-01-30 | 2004-08-01 | Phoenix Prec Technology Corp | Integrated storage plate with embedded passive components and method for fabricating electronic device with the plate |
CN101661920A (zh) * | 2008-08-26 | 2010-03-03 | 欣兴电子股份有限公司 | 芯片封装载板及其制造方法 |
CN204516757U (zh) * | 2015-02-12 | 2015-07-29 | 江苏长电科技股份有限公司 | 蓝宝石开槽的指纹传感器封装结构 |
CN106558573A (zh) * | 2015-09-23 | 2017-04-05 | 联发科技股份有限公司 | 半导体封装结构及形成该半导体封装结构的方法 |
CN108987371A (zh) * | 2017-06-02 | 2018-12-11 | 旭德科技股份有限公司 | 元件内埋式封装载板及其制作方法 |
CN113133198A (zh) * | 2019-12-30 | 2021-07-16 | 华为技术有限公司 | 电路板组件和电子设备 |
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TW200414835A (en) * | 2003-01-30 | 2004-08-01 | Phoenix Prec Technology Corp | Integrated storage plate with embedded passive components and method for fabricating electronic device with the plate |
CN101661920A (zh) * | 2008-08-26 | 2010-03-03 | 欣兴电子股份有限公司 | 芯片封装载板及其制造方法 |
CN204516757U (zh) * | 2015-02-12 | 2015-07-29 | 江苏长电科技股份有限公司 | 蓝宝石开槽的指纹传感器封装结构 |
CN106558573A (zh) * | 2015-09-23 | 2017-04-05 | 联发科技股份有限公司 | 半导体封装结构及形成该半导体封装结构的方法 |
CN108987371A (zh) * | 2017-06-02 | 2018-12-11 | 旭德科技股份有限公司 | 元件内埋式封装载板及其制作方法 |
CN113133198A (zh) * | 2019-12-30 | 2021-07-16 | 华为技术有限公司 | 电路板组件和电子设备 |
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