CN103579169A - 半导体封装及半导体封装基座的制造方法 - Google Patents

半导体封装及半导体封装基座的制造方法 Download PDF

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CN103579169A
CN103579169A CN201310286640.9A CN201310286640A CN103579169A CN 103579169 A CN103579169 A CN 103579169A CN 201310286640 A CN201310286640 A CN 201310286640A CN 103579169 A CN103579169 A CN 103579169A
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pedestal
wire
semiconductor
semiconductor packages
layer
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CN103579169B (zh
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林子闳
许文松
于达人
张垂弘
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MediaTek Inc
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MediaTek Inc
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Priority to CN201610206320.1A priority Critical patent/CN105789174B/zh
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Abstract

本发明提供一种半导体封装及半导体封装基座的制造方法。上述半导体封装包括导线，内嵌于基座中；半导体装置，通过导电结构安置于上述导线上。本发明所提出的半导体封装及半导体封装基座的制造方法，可改善产品的可靠度和质量。

Description

半导体封装及半导体封装基座的制造方法
技术领域
本发明是有关于一种半导体封装及半导体封装基座（base）的制造方法，特别是有关于一种高密度（high density）半导体封装的基座的制造方法以及半导体封装。
背景技术
为了确保电子产品或通信设备的小型化和多功能性，通常要求半导体封装具有小尺寸，以支持多针（multi-pin）连接、高速和高功能。输入/输出(I/O)引脚数的增加再加上对高性能集成电路(IC)的需求增加，导致了覆晶封装体（flipchip packages）的发展。
覆晶技术使用芯片上的凸块以与封装基板（substrate）互连。正面朝下的覆晶经过最短的路径接合至封装基板。这些技术可以不仅适用于单一芯片封装技术，也可以适用于更高层数或集成层数的封装技术，在更高层数或集成层数的封装技术中的封装体更大，且这些技术可以适用于容纳数个芯片的更复杂的基板，以形成较大的功能单元。使用区域数组（area array）的上述覆晶技术可实现与装置的更高的密度连接和非常低的电感的封装体连接。然而，上述覆晶技术要求印刷电路板(PCB)制造商缩小线宽和线距或发展芯片直接接触(direct chipattach,DCA)半导体。因此，增加输入/输出(I/O)连接数量的多功能芯片封装会导致热电特性问题，举例来说，散热问题、串音(crosstalk)、信号传输延迟(PropagationDelay)或射频(RF)电路的电磁干扰等问题。上述热电特性问题会影响产品的可靠度和质量。
因此，需要高密度的覆晶封装和用于高密度的覆晶封装的印刷电路板(PCB)，以改善上述缺点。
发明内容
有鉴于此，本发明提供一种半导体封装及半导体封装基座的制造方法。
依据本发明一实施方式，提供一种半导体封装。该半导体封装包括导线，内嵌于基座中；以及半导体装置，通过导电结构安置于该导线上。
依据本发明另一实施方式，提供一种半导体封装。该半导体封装包括导线，该导线的顶面和侧壁的至少一个部分连接至基座；以及半导体装置，通过导电结构安置于该导线上。
依据本发明又一实施方式，提供一种半导体封装基座的制造方法。该半导体封装基座的制造方法包括提供载板，该载板的顶面和底面上具有多个导电种晶层；分别于该多个导电种晶层上形成多个第一导线；将第一基座材料层和第二基座材料层分别堆叠于该多个导电种晶层上，且覆盖该多个第一导线；分别于该第一基座材料层的第一表面和该第二基座材料层的第一表面上形成多个第二导线，其中该第一基座材料层的该第一表面和该第二基座材料层的该第一表面分别远离该载板的该顶面和该底面；以及将带有该多个第一导线和该多个第二导线的该第一基座材料层以及将带有该多个第一导线和该多个第二导线的该第二基座材料层分别从该载板的该顶面和该底面分离，以形成第一基座和第二基座。
依据本发明又一实施方式，提供一种半导体封装基座的制造方法。该半导体封装基座的制造方法包括提供载板；在该载板上形成至少一个导线；在该载板上形成额外绝缘材料；以及在该额外绝缘材料上定义图案，其中该图案形成于至少一个导线上。
本发明所提出的半导体封装及半导体封装基座的制造方法，可改善产品的可靠度和质量。
附图说明
图1-4为根据本发明实施方式的半导体封装的剖面图。
图5a-5e为根据本发明实施方式的半导体封装的基座的制造方法的剖面图。
图6a-6e为根据本发明另一实施方式的半导体封装的制造方法的剖面图。
具体实施方式
为了让本发明的目的、特征、及优点能更明显易懂，下文特举较佳的实施方式并配合所附附图做详细的说明。本发明说明书提供不同的实施方式来说明本发明不同实施方式的技术特征。其中，实施方式中的各装置的配置仅用于解释本发明的目的，并非用以限制本发明。为了简化说明，附图中的标号部分重复，然而这种标号部分的重复并不能说明不同实施方式之间的关联性。
图1-4为根据本发明实施方式的半导体封装的剖面图。在此实施方式中，上述半导体封装可为覆晶封装体(flip chip package)，该覆晶封装体使用导电结构（例如铜柱状凸块(copper pillar bump)）以将半导体装置连接至基座，其中该导电结构接触该导线。在本发明的另一个实施方式中，上述半导体封装可为使用接合线技术的封装，以将半导体装置连接至基座。举例来说，该半导体装置可通过导电结构安置（mounted）于导线上。图1显示本发明实施方式的半导体封装500a的剖面示意图。请参考图1，上述半导体封装500a可包括基座200，上述基座200具有装置贴附面(device attach surface)214。在本发明的实施方式中，基座200，例如为印刷电路板(print circuit board，PCB)，可由聚丙烯(polypropylene，PP)来形成。请注意基座200可为单一层（single layer）结构或多层（multilayer）结构。多个导线202a，内嵌于基座200中。在本发明的实施方式中，导线202a可包括信号线部分（segment）或接地线部分，上述信号线或接地线可用于半导体装置300的输入/输出(input/output，I/O)连接，其中半导体装置300直接安置(mounted)于基座200之上。因此，每一个导线202a具有作为基座200的垫区的部分。在此实施方式中，导线202a的宽度W1设计为大于5μm。然而，应注意导线的宽度W1并无限制。对于不同的设计，如果有需要的话，导线的宽度W1可以小于5μm。
半导体装置300可通过接合工艺用面向基座200的主动表面(active surface)安置于基座200的装置贴附面214上。在本发明的一个实施方式中，半导体装置300可包括芯片(die)、被动组件(passive component)、封装(package)或晶圆级封装(wafer level package)。在此实施方式中，半导体装置300可为覆晶封装体(flipchip package)。半导体装置300的电路设置于上述主动表面上，且金属焊垫304设置于上述电路的顶部上。上述半导体装置300的上述电路通过设置于半导体装置300的主动表面上的多个导电结构222互连至基座200的电路。然而，应注意，如图1所示的导电结构222仅为实施方式，而并非用以限定本发明。
如图1所示，半导体装置300可包括半导体主体301，位于上述半导体主体301上(overlying)的金属焊垫304，以及覆盖金属焊垫304的绝缘层302。在此实施方式中，半导体主体301可包括但不限于半导体基板、形成于上述半导体基板的主要表面（main surface）上的电路装置、层间介电层(inter-layer dielectriclayers,ILD layers)和互连结构。在本发明的一个实施方式中，上述互连结构可包括多个金属层、与金属层交错堆叠（laminate）的多个介电层，以及穿过位于半导体基板上的该多个介电层的多个通孔插塞（via）。上述金属焊垫304可包括上述互连结构的上述金属层的最上层金属层。在本发明的一个实施方式中，绝缘层302可以为单一层结构或多层结构，以及绝缘层302可包括但不限于氮化硅、氧化硅、氮氧化硅、聚酰亚胺(polyimide)或上述任意组合。并且，绝缘层302可具有应力缓冲和绝缘的功能。在本发明的一个实施方式中，金属焊垫304可包括但不限于铝、铜或上述合金。可于绝缘层302中形成多个开口。每一个开口暴露出金属焊垫304的至少一个部分。
如图1所示，导电结构222可包括导电凸块结构（例如铜凸块结构或焊锡凸块结构）、导线结构，或导电性糊剂结构(conductive paste structure)。在此实施方式中，导电结构222可为由金属堆叠（stack）构成的铜凸块结构，上述金属堆叠包括凸块下金属层(under bump metallurgy(UBM)layer)306、铜层216（例如电镀铜层）和焊锡盖层(solder cap)220。上述金属堆叠可进一步包括导电缓冲层218，其中导电缓冲层218位于铜层216和焊锡盖层220之间。在本发明的一个实施方式中，可利用例如溅镀（sputtering）法或电镀（plating）法的沉积工艺以及后续的各向异性蚀刻工艺（anisotropic etching process），在开口中暴露出来的金属焊垫304上形成凸块下金属层(UBM layer)306。上述各向异性蚀刻工艺于形成导电柱状物之后进行。凸块下金属层306也可延伸于绝缘层302的顶面上。在此实施方式中，凸块下金属层306可包括钛、铜或上述组合。铜层216（例如电镀铜层），可形成于凸块下金属层306上。开口可利用铜层216和凸块下金属层306填充，且位于开口内的铜层216和凸块下金属层306可形成导电结构222的集成插塞(integral plug)。铜层216的形成位置(图未显示)可利用干膜抗蚀剂（dry film photoresist）图型（pattern）或液体光刻胶（liquid photoresist）图型来定义。
可通过电镀焊锡和图案化光刻胶层或通过网印（screen printing）工艺和后续的回焊工艺于铜层216上形成焊锡盖层220。可利用电镀法于铜层216和焊锡盖层220之间形成由镍形成的导电缓冲层218。上述导电缓冲层218可作为形成于其上的焊锡盖层220的种晶层(seed layer)、黏着层(adhesion layer)以及障碍层(barrier layer)。在本发明的一个实施方式中，导电结构222（例如为导电柱状结构）可作为金属焊垫304的焊点(solder joint)，而金属焊垫304用于传输形成于其上的半导体装置300的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。因此，导电结构222的铜层216可帮助增加凸块结构的机械强度。在本发明的一个实施方式中，可以在半导体装置300和基座200之间的间隙中导入底胶填充材料或底胶230。在本发明的一个实施方式中，底胶填充材料或底胶230可包括毛细填充胶(capillary underfill，CUF)、成型底部填充胶(moldedunderfill，MUF)、非导电性绝缘胶(nonconductive paste，NCP)、非导电性绝缘膜(nonconductive film，NCF)或上述任意组合。
在本发明的一个实施方式中，导线具有顶面，上述顶面可位于上述基座的表面的上方、下方或对齐上述基座的表面，以改善高密度半导体封装的绕线能力。如图1所示，导线202a的顶面212a设置于上述基座200的装置贴附面214的下方。即导线202a的底面206a和导线202a的至少一个部分侧壁204a设计连接至基座200。在此实施方式中，导电结构222连接基座200的至少一个部分。举例来说，导电结构222的焊锡盖层220设置为与基座200的一部分接触。进一步地，导电结构222可仅连接至导线202a的一顶面212a。由于导线的顶面凹陷于基座200的装置贴附面214内，所以会增加凸块接合至导线的空间(bump-to-trace space)，且有效地避免凸块接合至导线的桥接问题(the problem ofbump-to-trace bridging)。
图2显示本发明另一实施方式的半导体封装500b的剖面示意图。上述图式中的各装置如有与图1所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在此实施方式中，内嵌于基座200中的半导体封装500b的导线202b可具有顶面212b，上述顶面212b设计为对齐于基座200的装置贴附面214，以改善用于高密度半导体封装的绕线能力。即导线202b的底面206b和侧壁204b设计为完全连接至基座200。因此，导电结构222的焊锡盖层220设置于基座200的装置贴附面214上，且仅接触至导线202b的顶面212b。
图3显示本发明又一实施方式的半导体封装500c的剖面示意图。上述图式中的各装置如有与图1和图2所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在此实施方式中，内嵌于基座200中的半导体封装500c的导线202c可具有顶面212c，上述顶面212c设计为位于基座200的装置贴附面214的上方，以改善用于高密度半导体封装的绕线能力。即导线202c的底面206c和导线202c的仅一部分侧壁204c设计连接至基座200。在此实施方式中，导电结构222的焊锡盖层220设置于基座200的装置贴附面214上，且包裹导线202c的顶面212c和仅包裹导线202c一部分侧壁204c。
图4显示本发明又另一实施方式的半导体封装500d的剖面示意图。上述图式中的各装置如有与图1-3所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在本发明的一个实施方式中，上述基座可包括如图1-3所示的单一层结构。在本发明的另一个实施方式中，上述基座可包括多层结构。在此实施方式中，内嵌于基座部分200a中的半导体封装500d的导线202d可具有顶面212d，上述顶面212d设计对齐于基座部分200a的装置贴附面214，以改善用于高密度半导体封装的绕线能力。即导线202d的底面206d和侧壁204d设计为连接至基座部分200a。并且具有开口210的绝缘层208设置于基座部分200a上。上述绝缘层208设置于基座部分200a的装置贴附面214的上方。在此实施方式中，基座部分200a和绝缘层208可一起作为多层基座。如图4所示，导线202d从开口210中暴露出来。因此，导电结构222的焊锡盖层220是穿过绝缘层208的一部分而形成的，且仅接触至导线202d的顶面212d。应注意，绝缘层208不需对齐于导线202d的侧壁204d。绝缘层208可以位于如图4所示的导线202d的侧壁204d的外侧或内侧。
图5a-5e为根据本发明实施方式的半导体封装的基座（即第一基座200c和第二基座200d）的制造方法的剖面图。在此实施方式中，半导体封装的基座的制造方法也可称为双侧基座制造工艺(double-sided base fabricating process)。实施方式中的各装置如有与图1-4所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。如图5a所示，提供一载板400，上述载板400的顶面401和底面403上具有导电种晶层（conductive seed layer）402a和导电种晶层402b。在本发明的一个实施方式中，载板400可包括FR4环氧玻璃(FR4glass epoxy)或不锈钢(stainless steel)。并且，导电种晶层402a和导电种晶层402b做为种晶层以用于后续形成的位于上述载板400的顶面401和底面403上的基座的互连导线。在本发明的一个实施方式中，导电种晶层402a和导电种晶层402b可包括铜。
接着，如图5b所示，分别于载板400的顶面401和底面403上形成第一导线404a和第一导线404b，即分别于导电种晶层402a和导电种晶层402b上形成第一导线404a和第一导线404b。第一导线404a和第一导线404b的底部连接至导电种晶层402a和导电种晶层402b的顶部。在本发明的一个实施方式中，可利用电镀工艺（plating process）和各向异性蚀刻工艺形成第一导线404a和第一导线404b。上述电镀工艺和各向异性蚀刻工艺同时于上述载板400的顶面401和底面403进行。在本发明的一个实施方式中，电镀工艺可包括有电电镀工艺(electrical plating process)。在本发明的一个实施方式中，第一导线404a和第一导线404b可包括铜。在本发明的一个实施方式中，第一导线404a和第一导线404b的宽度可设计大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在此实施方式中，上述各向异性蚀刻工艺可精确地控制第一导线404a和404b的宽度。
接着，如图5c所示，进行堆叠工艺，将第一基座材料层406a和第二基座材料层406b分别堆叠于载板400的顶面401和底面403上，即将第一基座材料层406a和第二基座材料层406b分别堆叠于导电种晶层402a和导电种晶层402b上，其中第一基座材料层406a和第二基座材料层406b分别覆盖第一导线404a和第一导线404b。在此实施方式中，同时于上述载板400的顶面401和底面403上进行第一基座材料层406a和第二基座材料层406b的堆叠工艺。在本发明的一个实施方式中，第一基座材料层406a和第二基座材料层406b可包括聚丙烯(polypropylene，PP)。
接着，请再参考图5c，进行钻孔工艺，以形成穿过第一基座材料层406a和第二基座材料层406b的开口(图未显示)，以定义后续形成的通孔插塞408a和通孔插塞408b的位置。在本发明的一个实施方式中，上述钻孔工艺包括激光钻孔工艺、蚀刻钻孔工艺或机械钻孔工艺。接着，进行电镀工艺，将导电材料填入上述开口中，以形成通孔插塞408a和通孔插塞408b，其中上述通孔插塞408a和通孔插塞408b将第一导线404a和第一导线404b互连至后续形成的第二导线410a和第二导线410b。在此实施方式中，上述钻孔工艺和电镀工艺同时且分别于上述第一基座材料层406a和第二基座材料层406b上进行。
接着，请再参考图5c，分别于上述第一基座材料层406a的第一表面412上和第二基座材料层406b的第一表面414上形成多个第二导线410a～410b。如图5c所示，上述第一基座材料层406a的第一表面412和第二基座材料层406b的第一表面414分别远离上述载板400的顶面401和底面403。可利用电镀工艺和各向异性蚀刻工艺形成第二导线410a和第二导线410b。上述电镀工艺和各向异性蚀刻工艺同时于上述第一基座材料层406a的第一表面412上和第二基座材料层406b的第一表面414上进行。在本发明的一个实施方式中，电镀工艺可包括有电电镀工艺。在本发明的一个实施方式中，第二导线410a和第二导线410b可包括铜。在本发明的一个实施方式中，第二导线410a和第二导线410b的宽度可设计为大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在此实施方式中，上述各向异性蚀刻工艺可精确地控制第二导线410a和第二导线410b的宽度。
接着，如图5d和图5e所示，将带有第一导线404a和第二导线410a的第一基座材料层406a以及带有该第一导线404b和该第二导线410b的第二基座材料层406b分别从如图5c所示的上述载板400的顶面401和底面403分离，以形成彼此分离的第一基座200c和第二基座200d。接着，请再参考第5d和5e图，分别从第一基座200c的第二表面416和第二基座200d的第二表面418上移除导电种晶层402a和导电种晶层402b。
如图5d和图5e所示，第一导线404a和第一导线404b对齐于第一基座200c的第二表面416和第二基座200d的第二表面418，其中第二表面416和第二表面418分别相对于第一表面412和第一表面414。在此实施方式中，利用双侧基座制造工艺(double-sided base fabricating process)，同时于相对表面上制造第一基座200c和第二基座200d。
在本发明的另一个实施方式中，分离如图5d和图5e所示的第一基座200c和第二基座200d之后，可选择性分别于第一基座200c的第二表面416上和第二基座200d的第二表面418上形成具有开口的两个保护层（passivation layer）或绝缘层（图未示）。在此实施方式中，第一基座200c和第二基座200d的第一导线404a和第一导线404b从开口中暴露出来。具有开口的绝缘层以及如图5d/图5e所示的第一导线404a/第一导线404b可类似于如图4所示的具有开口的绝缘层208以及导线202d。并且，在此实施方式中，第一基座200c/第二基座200d和其上的绝缘层可一起作为多层基座(multilayer base)。
图6a-6e为根据本发明另一实施方式的半导体封装的制造方法的剖面图。并且，图6e显示本发明另一实施方式的半导体封装500e的剖面图。上述图式中的各装置如有与图1-4、图5a-5e所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在本发明的另一个实施方式中，上述基座可具有多层结构。如图6a所示，提供具有顶面451的基座450。接着，如图6b所示，在上述基座450的顶面451上形成至少一个导线454。在本发明的一个实施方式中，可利用电镀工艺和各向异性蚀刻工艺形成导线454。在本发明的一个实施方式中，电镀工艺可包括有电电镀工艺。在本发明的一个实施方式中，导线454可包括铜。在本发明的一个实施方式中，导线454的宽度可设计大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在此实施方式中，上述各向异性蚀刻工艺可精确地控制导线454的宽度。
接着，如图6c所示，进行堆叠工艺，在上述基座450的顶面451上设置额外绝缘材料456。并且，上述额外绝缘材料456覆盖导线454的顶面460和侧壁462。
接着，请参考图6d，进行钻孔工艺，以形成穿过上述额外绝缘材料456的至少一个开口458，以定义后续形成的导电结构的位置，上述导电结构例如可为铜凸块结构或焊锡凸块结构。在本发明的一个实施方式中，上述钻孔工艺包括激光钻孔工艺、蚀刻钻孔工艺或机械钻孔工艺。在此实施方式中，导线454的顶面460会从上述额外绝缘材料456的开口458中暴露出来。
接着，请参考图6e，进行接合工艺，将半导体装置300通过导电结构222安置于基座450。上述图式中的半导体装置300和导电结构222的装置如有与图1-4所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。进行接合工艺之后，导电结构222设置穿过上述额外绝缘材料456的开口458，且仅接触至导线454的顶面460。接着，可于半导体装置300和上述额外绝缘材料456之间的间隙中导入底胶填充材料或底胶230。在本发明的一个实施方式中，底胶填充材料或底胶230可包括毛细底胶填充材料(capillary underfill，CUF)、成型底胶填充材料(molded underfill，MUF)，非导电性绝缘胶(nonconductive paste，NCP)、非导电性绝缘膜(nonconductive film，NCF)或上述任意组合。最后，上述基座450、上述额外绝缘材料456、上述半导体装置300、上述导线454和上述导电结构222一起形成半导体封装500e。
本发明实施方式提供一种半导体封装。上述半导体封装设计包括内嵌于基座（例如为印刷电路板(PCB)）中的导线。上述导线具有顶面，上述顶面可位于上述基座的表面的上方、下方或对齐上述基座的表面，以改善用于高密度半导体封装的绕线能力。并且，上述导线的宽度可设计大于5μm。再者，上述基座可包括单一层结构或多层结构。本发明实施方式也提供一种用于半导体封装的基座的制造方法。在本发明的一个实施方式中，上述方法可同时于载板的两侧制造两个基座。并且，导线内嵌于上述基座中。再者，可利用电镀工艺和各向异性蚀刻工艺形成导线，且上述各向异性蚀刻工艺可精确地控制上述导线的宽度。在本发明的另一个实施方式中，上述方法可制造包括单一层结构或多层结构的基座，以增加设计选择。在本发明的另一个实施方式中，上述方法包括提供载板；在载板上形成至少一个导线；在载板上形成额外绝缘材料；以及于额外绝缘材料上定义图案，其中该图案形成于该至少一个导线上。
虽然本发明以较佳实施方式揭露如上，然而此较佳实施方式并非用以限定本发明，本领域技术人员不脱离本发明的精神和范围内，凡依本发明申请专利范围所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (26)

1.一种半导体封装，其特征在于，包括：
导线，内嵌于基座中；以及
半导体装置，通过导电结构安置于该导线上。
2.根据权利要求1项所述的半导体封装，其特征在于，该导线的宽度大于5μm。
3.根据权利要求1项所述的半导体封装，其特征在于，该导线具有顶面，该顶面位于该基座的表面的上方、下方或对齐该基座的该表面。
4.根据权利要求1项所述的半导体封装，其特征在于，进一步包括：
底胶填充材料，位于该基座和该半导体装置之间。
5.根据权利要求4项所述的半导体封装，其特征在于，该底胶填充材料包括毛细底胶填充材料、成型底胶填充材料、非导电性绝缘胶、非导电性绝缘膜或上述组合。
6.根据权利要求1项所述的半导体封装，其特征在于，进一步包括：
绝缘层，具有开口，该绝缘层设置于该基座上且位于该基座的装置贴附面的上方，其中该导线从该开口中暴露出来。
7.根据权利要求1项所述的半导体封装，其特征在于，该导电结构接触该导线。
8.根据权利要求1项所述的半导体封装，其特征在于，该导电结构仅接触该导线的顶面。
9.根据权利要求1项所述的半导体封装，其特征在于，该导电结构包裹该导线的顶面和侧壁的一部分。
10.根据权利要求1项所述的半导体封装，其特征在于，该导电结构连接该基座的至少一个部分。
11.根据权利要求1项所述的半导体封装，其特征在于，该导电结构包括导电凸块结构、导线结构或导电性糊剂结构。
12.根据权利要求11项所述的半导体封装，其特征在于，该导电凸块结构包括铜凸块结构或焊锡凸块结构。
13.根据权利要求1项所述的半导体封装，其特征在于，该导电结构由金属堆叠构成，该金属堆叠包括凸块下金属层、铜层和焊锡盖层。
14.根据权利要求13项所述的半导体封装，其特征在于，该导电结构进一步包括导电缓冲层，位于该铜层和该焊锡盖层之间。
15.根据权利要求1项所述的半导体封装，其特征在于，该半导体装置包括芯片、被动组件、封装或晶圆级封装。
16.如申请专利范围第1项所述的半导体封装，其特征在于，该基座包括单一层结构或多层结构。
17.一种半导体封装，其特征在于，包括：
导线，该导线的顶面和侧壁的至少一个部分连接至基座；以及
半导体装置，通过导电结构安置于该导线上。
18.一种半导体封装基座的制造方法，其特征在于，包括：
提供载板，该载板的顶面和底面上具有多个导电种晶层；
分别于该多个导电种晶层上形成多个第一导线；
将第一基座材料层和第二基座材料层分别堆叠于该多个导电种晶层上，且覆盖该多个第一导线；
分别于该第一基座材料层的第一表面和该第二基座材料层的第一表面上形成多个第二导线，其中该第一基座材料层的该第一表面和该第二基座材料层的该第一表面分别远离该载板的该顶面和该底面；以及
将带有该多个第一导线和该多个第二导线的该第一基座材料层以及将带有该多个第一导线和该多个第二导线的该第二基座材料层分别从该载板的该顶面和该底面分离，以形成第一基座和第二基座。
19.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，进一步包括：
进行钻孔工艺，以形成穿过该第一基座材料层和该第二基座材料层的开口；以及
在形成该多个第二导线之前，进行电镀工艺，将导电材料填入该开口中形成通孔插塞以用于将该多个第一导线互连至该多个第二导线。
20.根据权利要求19项所述的半导体封装基座的制造方法，其特征在于，该钻孔工艺包括激光钻孔工艺、蚀刻钻孔工艺或机械钻孔工艺，该电镀工艺包括有电电镀工艺。
21.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，利用电镀工艺和各向异性蚀刻工艺形成该多个第一导线和该多个第二导线。
22.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，该制造方法进一步包括：
从该第一基座的第二表面和该第二基座的第二表面上移除该多个导电种晶层。
23.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，进一步包括：
分别于该第一基座和该第二基座上形成具有开口的绝缘层，其中该第一基座和该第二基座的该多个第一导线从该多个开口中暴露出来。
24.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，该第一基座和该第二基座的该多个第一导线对齐该第一基座的第二表面和该第二基座的第二表面，以及该第一基座的该第二表面和该第二基座的该第二表面分别相对于该第一基座的该第一表面和该第二基座的该第一表面。
25.根据权利要求18项所述的半导体封装基座的制造方法，其特征在于，该多个第一导线的宽度大于5μm。
26.一种半导体封装基座的制造方法，其特征在于，包括：
提供载板；
在该载板上形成至少一个导线；
在该载板上形成额外绝缘材料；以及
在该额外绝缘材料上定义图案，其中该图案形成于该至少一个导线上。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206500A (zh) * 2014-11-07 2016-12-07 联发科技股份有限公司 半导体封装
CN106910732A (zh) * 2015-09-16 2017-06-30 联发科技股份有限公司 半导体封装
CN107424971A (zh) * 2016-04-29 2017-12-01 英飞凌科技股份有限公司 芯片载体上基于腔体的特征
CN107768337A (zh) * 2016-08-19 2018-03-06 联发科技股份有限公司 预先凸起的重分布层结构及半导体封装
US10573616B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6282454B2 (ja) * 2013-12-10 2018-02-21 新光電気工業株式会社 半導体パッケージの製造方法
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9275967B2 (en) * 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
CN106463427B (zh) * 2014-06-27 2020-03-13 索尼公司 半导体装置及其制造方法
JP6660687B2 (ja) * 2015-07-30 2020-03-11 シチズン電子株式会社 半導体素子および発光装置
US10643965B2 (en) * 2016-05-25 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of forming a joint assembly
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
US20200051925A1 (en) * 2018-08-13 2020-02-13 Mediatek Inc. Semiconductor device with an em-integrated damper
US11127705B2 (en) * 2019-01-16 2021-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR102633142B1 (ko) 2019-08-26 2024-02-02 삼성전자주식회사 반도체 패키지
KR20210092073A (ko) * 2020-01-15 2021-07-23 해성디에스 주식회사 회로기판의 제조 방법
TWI726685B (zh) * 2020-04-16 2021-05-01 錼創顯示科技股份有限公司 微型發光元件顯示裝置
KR20230168460A (ko) * 2022-06-07 2023-12-14 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US20030193094A1 (en) * 2002-04-12 2003-10-16 Nec Electronics Corporation Semiconductor device and method for fabricating the same
TW200915452A (en) * 2007-06-11 2009-04-01 Texas Instruments Inc Stable gold bump solder connections
CN101958289A (zh) * 2005-07-29 2011-01-26 米辑电子股份有限公司 半导体组件
US20110101526A1 (en) * 2009-10-29 2011-05-05 Ching-Wen Hsiao Copper Bump Joint Structures with Improved Crack Resistance
US20110169164A1 (en) * 2010-01-13 2011-07-14 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor package

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925297A (en) * 1972-10-17 1975-12-09 Westinghouse Electric Corp Filled composition and article containing perfluorinated surfactant
JP2715793B2 (ja) 1992-03-19 1998-02-18 日本電気株式会社 半導体装置及びその製造方法
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
WO2002058443A1 (en) 2001-01-16 2002-07-25 Delaware Capital Formation, Inc. Contact pads and circuit boards incorporating same
US20020105789A1 (en) 2001-02-02 2002-08-08 Siliconware Precision Industries Co., Ltd. Semiconductor package for multi-chip stacks
US6510976B2 (en) 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
JP2003163459A (ja) 2001-11-26 2003-06-06 Sony Corp 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。
EP1455392A4 (en) 2001-12-07 2008-05-07 Fujitsu Ltd SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
US6960828B2 (en) * 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
US6929981B2 (en) 2002-09-06 2005-08-16 Advanpack Solutions Pte, Ltd. Package design and method of manufacture for chip grid array
US6734039B2 (en) 2002-09-06 2004-05-11 Advanpack Solutions Pte Ltd. Semiconductor chip grid array package design and method of manufacture
US6750082B2 (en) 2002-09-13 2004-06-15 Advanpack Solutions Pte. Ltd. Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip
US20040108580A1 (en) 2002-12-09 2004-06-10 Advanpack Solutions Pte. Ltd. Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture
US7320173B2 (en) 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US20050087883A1 (en) 2003-10-22 2005-04-28 Advanpack Solutions Pte. Ltd. Flip chip package using no-flow underfill and method of fabrication
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US20060060937A1 (en) 2004-09-23 2006-03-23 Advanpack Solutions Pte Ltd Embedded passive component
US20060103016A1 (en) 2004-11-12 2006-05-18 Advanpack Solutions Pte Ltd Heat sinking structure
KR100674319B1 (ko) 2004-12-02 2007-01-24 삼성전기주식회사 얇은 코어층을 갖는 인쇄회로기판 제조방법
TWI268130B (en) 2004-12-23 2006-12-01 Phoenix Prec Technology Corp Method for fabricating a multi-layer packaging substrate
JP4768994B2 (ja) 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
US20060180888A1 (en) 2005-02-14 2006-08-17 Advanpack Solutions Pte Ltd Optical sensor package and method of manufacture
JP4185499B2 (ja) 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20070196979A1 (en) 2006-02-21 2007-08-23 Advanpack Solutions Pte Ltd Flip chip in package using flexible and removable leadframe
US20070284420A1 (en) 2006-06-13 2007-12-13 Advanpack Solutions Pte Ltd Integrated circuit chip formed on substrate
US7589398B1 (en) 2006-10-04 2009-09-15 Amkor Technology, Inc. Embedded metal features structure
TWI378540B (en) 2006-10-14 2012-12-01 Advanpack Solutions Pte Ltd Chip and manufacturing method thereof
DE102007034402B4 (de) 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
TW200828477A (en) 2006-12-22 2008-07-01 Advanpack Solutions Pte Ltd Device and method for testing semiconductor element, and manufacturing method thereof
US20080248610A1 (en) 2007-04-03 2008-10-09 Advanpack Solutions Pte Ltd Thermal bonding process for chip packaging
JP4800253B2 (ja) 2007-04-04 2011-10-26 新光電気工業株式会社 配線基板の製造方法
US20080246147A1 (en) 2007-04-09 2008-10-09 Chao-Yuan Su Novel substrate design for semiconductor device
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
TWI357137B (en) 2007-10-19 2012-01-21 Advanced Semiconductor Eng Flip chip package structure and carrier thereof
TWI368303B (en) 2007-12-21 2012-07-11 Packaging substrate structure
US7880297B2 (en) 2007-12-31 2011-02-01 Mediatek Inc. Semiconductor chip having conductive member for reducing localized voltage drop
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US20100073894A1 (en) 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
JP2010109032A (ja) * 2008-10-29 2010-05-13 Fujitsu Microelectronics Ltd 半導体装置の製造方法
JP5221315B2 (ja) 2008-12-17 2013-06-26 新光電気工業株式会社 配線基板及びその製造方法
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
JP5339928B2 (ja) 2009-01-15 2013-11-13 新光電気工業株式会社 配線基板及びその製造方法
JP5107959B2 (ja) 2009-04-09 2012-12-26 ルネサスエレクトロニクス株式会社 基板
EP2421848A1 (en) 2009-04-22 2012-02-29 Janssen Pharmaceutica N.V. Azetidinyl diamides as monoacylglycerol lipase inhibitors
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
TW201133745A (en) 2009-08-27 2011-10-01 Advanpack Solutions Private Ltd Stacked bump interconnection structure and semiconductor package formed using the same
TWI416636B (zh) 2009-10-22 2013-11-21 Unimicron Technology Corp 封裝結構之製法
TWI388018B (zh) 2009-10-22 2013-03-01 Unimicron Technology Corp 封裝結構之製法
KR101290045B1 (ko) 2009-10-29 2013-07-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 플립칩 본딩을 위한 강건 접속 구조
JP5590869B2 (ja) * 2009-12-07 2014-09-17 新光電気工業株式会社 配線基板及びその製造方法並びに半導体パッケージ
US8917521B2 (en) 2010-04-28 2014-12-23 Advanpack Solutions Pte Ltd. Etch-back type semiconductor package, substrate and manufacturing method thereof
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
TWI432794B (zh) 2010-07-05 2014-04-01 Univ Nat Yunlin Sci & Tech Anti - glare film with different internal and external haze and its making method
US8227334B2 (en) 2010-07-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Doping minor elements into metal bumps
US9048135B2 (en) 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
CN103824836B (zh) 2010-08-31 2017-03-01 先进封装技术私人有限公司 半导体承载元件及半导体封装件
KR101780423B1 (ko) 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20120267779A1 (en) 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
US8288871B1 (en) 2011-04-27 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Reduced-stress bump-on-trace (BOT) structures
US20120326299A1 (en) * 2011-06-24 2012-12-27 Topacio Roden R Semiconductor chip with dual polymer film interconnect structures
US10109503B2 (en) 2011-07-22 2018-10-23 Advanpack Solutions Pte Ltd. Method of manufacturing semiconductor package device
US9053989B2 (en) 2011-09-08 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure in semiconductor device
US9099340B2 (en) 2011-10-07 2015-08-04 Volterra Semiconductor Corporation Power management applications of interconnect substrates
US9536818B2 (en) 2011-10-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
CN202948918U (zh) 2011-10-20 2013-05-22 先进封装技术私人有限公司 封装基板及半导体元件的封装结构
US9301391B2 (en) 2011-11-29 2016-03-29 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of substrate structure
CN103165566B (zh) 2011-12-19 2016-02-24 先进封装技术私人有限公司 基板结构、半导体封装件及半导体封装件的制造方法
JP5893387B2 (ja) 2011-12-22 2016-03-23 新光電気工業株式会社 電子装置及びその製造方法
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9159670B2 (en) 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
KR102134019B1 (ko) 2013-11-25 2020-07-14 에스케이하이닉스 주식회사 볼 랜드를 포함하는 기판 및 반도체 패키지와, 그 제조방법
US10037941B2 (en) 2014-12-12 2018-07-31 Qualcomm Incorporated Integrated device package comprising photo sensitive fill between a substrate and a die

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US20030193094A1 (en) * 2002-04-12 2003-10-16 Nec Electronics Corporation Semiconductor device and method for fabricating the same
CN101958289A (zh) * 2005-07-29 2011-01-26 米辑电子股份有限公司 半导体组件
TW200915452A (en) * 2007-06-11 2009-04-01 Texas Instruments Inc Stable gold bump solder connections
US20110101526A1 (en) * 2009-10-29 2011-05-05 Ching-Wen Hsiao Copper Bump Joint Structures with Improved Crack Resistance
CN102054811A (zh) * 2009-10-29 2011-05-11 台湾积体电路制造股份有限公司 集成电路结构
US20110169164A1 (en) * 2010-01-13 2011-07-14 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor package

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573616B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10573615B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10580747B2 (en) 2012-07-31 2020-03-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US11469201B2 (en) 2012-07-31 2022-10-11 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
CN106206500A (zh) * 2014-11-07 2016-12-07 联发科技股份有限公司 半导体封装
US10312210B2 (en) 2014-11-07 2019-06-04 Mediatek Inc. Semiconductor package
CN106910732A (zh) * 2015-09-16 2017-06-30 联发科技股份有限公司 半导体封装
CN107424971A (zh) * 2016-04-29 2017-12-01 英飞凌科技股份有限公司 芯片载体上基于腔体的特征
CN107424971B (zh) * 2016-04-29 2021-06-08 英飞凌科技股份有限公司 芯片载体上基于腔体的特征
CN107768337A (zh) * 2016-08-19 2018-03-06 联发科技股份有限公司 预先凸起的重分布层结构及半导体封装

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US20200176408A1 (en) 2020-06-04
US20160307861A1 (en) 2016-10-20
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