WO2023005203A1 - 垂直结构led芯片及其制造方法 - Google Patents

垂直结构led芯片及其制造方法 Download PDF

Info

Publication number
WO2023005203A1
WO2023005203A1 PCT/CN2022/078633 CN2022078633W WO2023005203A1 WO 2023005203 A1 WO2023005203 A1 WO 2023005203A1 CN 2022078633 W CN2022078633 W CN 2022078633W WO 2023005203 A1 WO2023005203 A1 WO 2023005203A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
electrode
metal
led chip
Prior art date
Application number
PCT/CN2022/078633
Other languages
English (en)
French (fr)
Inventor
范伟宏
毕京锋
郭茂峰
李士涛
赵进超
金全鑫
Original Assignee
厦门士兰明镓化合物半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门士兰明镓化合物半导体有限公司 filed Critical 厦门士兰明镓化合物半导体有限公司
Publication of WO2023005203A1 publication Critical patent/WO2023005203A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the invention belongs to the technical field of semiconductor devices, and more specifically relates to a vertical structure LED chip and a manufacturing method thereof.
  • the vertical structure LED chip has the advantage of high brightness compared with the horizontal structure LED chip.
  • the vertical structure LED chip transfers the epitaxial layer from the sapphire substrate with poor insulation and heat dissipation to the bonding substrate with excellent electrical and thermal conductivity, which can withstand higher operating current and obtain higher brightness.
  • the vertical structure LED chip is easier to micro-nano process the light-emitting surface, thereby reducing the total reflection of the epitaxial layer and the air interface to increase the light extraction efficiency.
  • vertical structure LED chips mainly include vertical reverse polarity (N electrode upward) structure and vertical positive polarity (P electrode upward) structure.
  • LED chips with a vertical reverse polarity structure generally use comb electrodes combined with n-GaN layers to achieve the purpose of current expansion, but this solution will cause more serious current congestion at higher current densities, and current blocking layers are generally used However, both the current blocking layer and the N electrode will block and absorb part of the light emission, which will eventually lead to a decrease in the light extraction efficiency of the LED chip with a vertical reverse polarity structure.
  • LED chips with a vertical positive polarity structure need to use the same-side metal layer scheme, which requires the design and preparation of a complex metal-dielectric-metal stacked layer scheme, and because there must be stress between the metal and the dielectric, during the manufacturing process Especially in the process of bonding and substrate transfer, the stress regulation will face greater technical challenges, that is, the manufacturing process of LED chips with a vertical positive polarity structure is complicated.
  • the object of the present invention is to provide a vertical structure LED chip and a manufacturing method thereof, wherein the vertical structure LED chip is an LED chip with a vertical reverse polarity structure that has good current expansion and uniform injection effects, and better light extraction effects; Moreover, the manufacturing method of the vertical structure LED chip is simple, and the process complexity is reduced compared with the manufacturing scheme of the vertical positive polarity structure; The thermal resistance of the vertical structure LED chip is effectively reduced, and the process yield and device reliability of the vertical structure LED chip are effectively improved.
  • the application provides a vertical structure LED chip, comprising: a first substrate;
  • a transparent conductive layer and a metal nanowire layer located on the surface of the intrinsic semiconductor layer and the sidewall and bottom of the through hole.
  • the diameter of the through hole is 100 nanometers to 10 micrometers.
  • the pitch between adjacent through holes is 5 microns to 50 microns.
  • the plurality of through holes are arranged in an array, and the shape of the array is one of hexagonal, triangular, quadrilateral or circular arrays.
  • the hole spacing between at least some of the through holes is evenly distributed or gradually reduced along the center of the vertical structure LED chip to the edge area.
  • the material of the transparent conductive layer is one or more combinations of indium tin oxide, zinc aluminum oxide or graphene, and the transmittance of the transparent conductive layer is greater than 90%.
  • the material of the metal nanowire layer is one of silver nanowire layer, aluminum nanowire layer, gold nanowire layer and copper nanowire layer, and the transmittance of the metal nanowire layer is greater than 90%.
  • the first electrode is located on the surface of the first semiconductor layer, and further includes the intrinsic semiconductor layer, the transparent conductive layer and the metal nanowire layer between the first electrode and the first semiconductor layer, And the first electrode covers part of the surface of the metal nanowire layer;
  • the second electrode is located on the second surface of the first substrate.
  • a first electrode located on the surface of the first semiconductor layer
  • a current blocking layer located between the first ohmic contact layer and the second semiconductor layer, located below the first electrode and covered by the second semiconductor layer,
  • the transparent conductive layer and the metal nanowire layer are further included between the first electrode and the first semiconductor layer, and the first electrode covers part of the surface of the metal nanowire layer.
  • the first electrode is an N electrode
  • the second electrode is a P electrode
  • the passivation layer is located on the surface of the metal nanowire layer and exposes the first electrode, and the passivation layer forms a graded refractive index structure with the transparent conductive layer and the epitaxial layer.
  • the electron blocking layer is located between the light emitting layer and the second semiconductor layer.
  • the first step located around the vertical structure LED chip, penetrates through the intrinsic semiconductor layer, the first semiconductor layer, the light emitting layer, and the second semiconductor layer and exposes the first ohmic contact layer
  • a first included angle is formed between the side wall and the bottom of the first step, and the first included angle is 30°-60°, wherein the passivation layer also covers the bottom and the bottom of the first step side wall.
  • the first electrode is a composite metal layer, including a first metal layer, a second metal layer and a third metal layer sequentially located on the surface of the metal nanowire layer, and the thickness of the first metal layer is 1 Nanometer to 100 nanometers, the thickness of the second metal layer and the third metal layer are both 100 nanometers to 1 micron.
  • the first metal layer is one of chromium layer, titanium layer, vanadium layer, and hafnium layer
  • the second metal layer is one or more combinations of aluminum, titanium, platinum, and gold materials
  • a material layer, the third metal layer is a gold layer.
  • the surface of the intrinsic semiconductor layer is a rough surface.
  • the present application also provides a method for manufacturing a vertical structure LED chip, comprising:
  • a first bonding layer is formed on the surface of the first wafer, the first wafer includes a second substrate and an epitaxial layer on the surface of the second substrate, a first ohmic contact layer and a mirror layer, the epitaxial The layer includes an intrinsic semiconductor layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially located on the surface of the second substrate;
  • a transparent conductive layer and a metal nanowire layer are formed on the surface of the intrinsic semiconductor layer and the sidewall and bottom of the through hole.
  • the diameter of the through hole is 100 nanometers to 10 micrometers.
  • the pitch between adjacent through holes is 5 microns to 50 microns.
  • the plurality of through holes are arranged in an array, and the shape of the array is one of hexagonal, triangular, quadrilateral or circular arrays.
  • the spacing between at least some of the through holes is equal or evenly distributed or tapered from the center to the edge area of the LED chip with the vertical structure.
  • the material of the transparent conductive layer is one or more combinations of indium tin oxide, zinc aluminum oxide or graphene, and the transmittance of the transparent conductive layer is greater than 90%.
  • the material of the metal nanowire layer is one of silver nanowire layer, aluminum nanowire layer, gold nanowire layer and copper nanowire layer, and the transmittance of the metal nanowire layer is greater than 90%.
  • first electrode on the surface of the first semiconductor layer, further including the intrinsic semiconductor layer, the transparent conductive layer and the metal nanowire layer between the first electrode and the first semiconductor layer, and The first electrode covers part of the surface of the metal nanowire layer;
  • a second electrode is formed on the second surface of the first substrate.
  • a current blocking layer is formed between the first ohmic contact layer and the second semiconductor layer, and the current blocking layer is located below the first electrode and covered by the second semiconductor layer,
  • the transparent conductive layer and the metal nanowire layer are further included between the first electrode and the first semiconductor layer, and the first electrode covers part of the surface of the metal nanowire layer.
  • the first electrode is an N electrode
  • the second electrode is a P electrode
  • a passivation layer exposing the first electrode is formed on the surface of the metal nanowire layer, and the passivation layer forms a graded refractive index structure with the transparent conductive layer and the epitaxial layer.
  • An electron blocking layer is formed between the light emitting layer and the second semiconductor layer.
  • a first step is formed around the vertical structure LED chip, and the first step penetrates through the intrinsic semiconductor layer, the first semiconductor layer, the light emitting layer, and the second semiconductor layer and exposes the first semiconductor layer.
  • a first included angle is formed between the side wall and the bottom of the first step, and the first included angle is 30°-60°, wherein the passivation layer also covers the first A stepped bottom and side walls.
  • the first electrode is a composite metal layer, including a first metal layer, a second metal layer and a third metal layer sequentially located on the surface of the metal nanowire layer, and the thickness of the first metal layer is 1 Nanometer to 100 nanometers, the thickness of the second metal layer and the third metal layer are both 100 nanometers to 1 micron.
  • the first metal layer is one of chromium layer, titanium layer, vanadium layer, and hafnium layer
  • the second metal layer is one or more combinations of aluminum, titanium, platinum, and gold materials
  • a material layer, the third metal layer is a gold layer.
  • the surface of the intrinsic semiconductor layer is a rough surface.
  • the buffer layer is decomposed, and chemical wet etching technology is used to remove the decomposed products of the buffer layer, so as to expose the intrinsic semiconductor layer.
  • the LED chip with vertical structure is cut and obtained by adopting the wafer cutting technology, and the wafer cutting technology is one of the processing methods of water-guided laser, laser surface cutting or grinding wheel cutter.
  • a transparent conductive layer and a metal nanowire layer are arranged on the surface of the intrinsic semiconductor layer and the sidewalls and bottoms of a plurality of through holes penetrating through the intrinsic semiconductor layer to reach the surface of the first semiconductor layer.
  • the intrinsic semiconductor layer is a relatively high-resistance semiconductor
  • the transparent conductive layer and the metal nanowire layer are relatively low-resistance materials
  • most of the transparent conductive layer is a lateral film
  • the transparent conductive layer located in the through hole acts as a layer to the first semiconductor.
  • Layer uniform injection of current Furthermore, the vertically relatively high resistance of the first semiconductor layer and the laterally relatively low resistance of the transparent conductive layer and the metal nanowire layer are utilized to effectively improve the current distribution and expansion performance of the vertically structured LED chip.
  • both the transparent conductive layer and the metal nanowire layer have high transmittance characteristics, so that the light-emitting surface of the vertical structure LED chip has excellent light transmittance.
  • the passivation layer, the transparent conductive layer and the epitaxial layer form a graded refractive index structure, and the refractive index increases gradually from the passivation layer to the epitaxial layer, which can achieve a better light extraction effect.
  • a plurality of through holes penetrating through the intrinsic semiconductor layer and reaching the surface of the first semiconductor layer are manufactured, and then a transparent conductive layer, metal nano
  • the line layer is subsequently prepared to form the first electrode to complete the LED chip processing of the vertical reverse polarity structure.
  • This process avoids the complex process scheme of the vertical positive chip and significantly reduces the process difficulty.
  • the uniformity of carrier distribution in the light-emitting layer is improved, and the problem of reduced epitaxy efficiency is improved, so that the current distribution of the vertical reverse polarity LED chip and scaling performance has been improved.
  • Fig. 1 shows a schematic flow chart of a method for manufacturing a vertical structure LED chip according to an embodiment of the present invention
  • FIGS. 2a to 2g show structural cross-sectional views at different stages in the manufacturing process of a vertical structure LED chip provided according to an embodiment of the present invention
  • Fig. 3 shows a top view of the semiconductor structure shown in Fig. 2e.
  • Fig. 1 shows a schematic flowchart of a method for manufacturing a vertical structure LED chip according to an embodiment of the present invention.
  • 2a to 2g show structural cross-sectional views at different stages in the manufacturing process of a vertical structure LED chip provided according to an embodiment of the present invention.
  • Fig. 3 shows a top view of the semiconductor structure shown in Fig. 2e. The manufacturing method provided in this embodiment operates on the entire wafer. For the convenience of understanding, the drawings only show a vertical structure LED chip unit.
  • the method for manufacturing a vertical structure LED chip includes the following steps.
  • Step S110 forming a first bonding layer on the surface of the first wafer.
  • the first wafer includes a second substrate, an epitaxial layer on the surface of the second substrate, a first ohmic contact layer, and a mirror layer.
  • an epitaxial layer 120 is first formed on the surface of the second substrate 110 .
  • the total thickness of the epitaxial layer 120 is 5 microns to 10 microns.
  • the intrinsic semiconductor layer 122, the first semiconductor layer 123, the light emitting layer 124, and the second semiconductor layer 126 are sequentially formed on the first surface of the second substrate 110 by metal organic chemical vapor deposition process.
  • a buffer layer 121 is further formed on the surface of the second substrate 110 , and the buffer layer 121 is located between the second substrate 110 and the intrinsic semiconductor layer 122 .
  • an electron blocking layer 125 is further formed between the light emitting layer 124 and the second semiconductor layer 126 .
  • the subsequent manufacturing process herein is performed in the epitaxial layer including the buffer layer 121 , the intrinsic semiconductor layer 122 , the first semiconductor layer 123 , the light emitting layer 124 , the electron blocking layer 125 and the second semiconductor layer 126 .
  • the epitaxial layer 120 may also be formed by laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy.
  • the intrinsic semiconductor layer 122 is a non-doped gallium nitride material layer
  • the first semiconductor layer 123 is a gallium nitride material layer of the first doping type (N type)
  • the light emitting layer 124 is, for example, a multiple quantum well (MQW , multiple quantum well) layer
  • the electron blocking layer 125 is, for example, an aluminum gallium nitride material layer of the second doping type (P type)
  • the second semiconductor layer 126 is, for example, gallium nitride of the second doping type (P type).
  • the material layer, wherein the multi-quantum well layer is composed of gallium nitride/indium gallium nitride/aluminum gallium nitride material, for example.
  • the second substrate 110 includes, but is not limited to, one of a mirror surface or a micro-scale/nano-scale patterned sapphire substrate.
  • the second substrate 110 is a micron-scale patterned sapphire substrate.
  • the second substrate 110 is a kind of heterogeneous substrate, and the second substrate 110 can also be a gallium oxide, silicon carbide, silicon, zinc oxide, lithium gallate single crystal substrate or High temperature resistant metal substrate.
  • the thickness of the second substrate 110 is 300 micrometers to 2 millimeters, and the diameter of the second substrate 110 is 1 inch to 8 inches.
  • a first ohmic contact layer 131 and a reflector layer 132 are sequentially formed on the surface of the second semiconductor layer 126 to form a first wafer. Furthermore, the first ohmic contact layer 131 of the second doping type (P type) is formed on the surface of the second semiconductor layer 126 by photolithography and physical vapor deposition processes, and the first ohmic contact layer 131 is formed on the surface of the first ohmic contact layer 131. mirror layer 132 .
  • the first ohmic contact layer 131 is, for example, indium tin oxide, and the reflector layer 132 is, for example, a silver-platinum-titanium stack.
  • a first ohmic contact layer 131 is formed on the surface of the second semiconductor layer 126 and a mirror layer 132 is formed on the surface of the first ohmic contact layer 131 .
  • the first ohmic contact layer 131 may also be one of aluminum zinc oxide (AZO), indium gallium oxide (GTO), nickel gold, nickel silver, and nickel aluminum.
  • the first ohmic contact layer 131 The thickness is 1 nanometer to 200 nanometers.
  • the reflector layer 132 can also be one of silver layer, aluminum layer, magnesium layer, platinum layer, rhodium layer, and gold layer, and the thickness of the reflector layer 132 is 60 nanometers to 200 nanometers.
  • the first bonding layer 134 is one of the solutions of the binary eutectic metal system composed of high melting point metals such as copper, nickel, silver, and gold and low melting point metals such as tin and indium.
  • the first bonding layer 134 is, for example, a nickel/tin binary metal layer.
  • Step S120 forming a second bonding layer on the surface of the first substrate.
  • the second bonding layer 144 is formed on the surface of the first substrate 210 .
  • the second bonding layer 144 is one of the binary eutectic metal system solutions composed of copper, nickel, silver, gold and other high melting point metals and tin, indium and other low melting point metals.
  • the first substrate 210 is, for example, a copper-tungsten metal substrate with a diameter of 4 inches and a thickness of 200 microns.
  • the second bonding layer 144 is, for example, a nickel/tin binary metal layer.
  • the first substrate 210 may be one of silicon, copper, molybdenum, tungsten, molybdenum-copper alloy, and aluminum-silicon alloy substrates, and the diameter of the first substrate 210 is 1 inch to 8 inches. inches, and the thickness of the first substrate 210 is 100 microns to 1 micron.
  • Step S130 bonding the first wafer and the first substrate together through the first bonding layer and the second bonding layer. Specifically, as shown in FIG. 2 c , the first wafer and the first substrate 210 are bonded together in an environment with a temperature of about 260° C. by using a liquid phase transient bonding process.
  • Step S140 peeling off the second substrate.
  • the second substrate 110 is peeled off by a substrate transfer technique.
  • the substrate transfer technology may be one or a combination of laser lift-off, chemical mechanical thinning, chemical wet etching, and dry etching.
  • the buffer layer 121 is decomposed during the stripping process, and the decomposed products of the buffer layer are removed by chemical wet etching technology, so as to expose the intrinsic semiconductor layer 122 .
  • the buffer layer 121 is peeled and decomposed by using a laser with a small circular spot with a diameter of 30 microns, and then the second substrate 110 located on the surface of the buffer layer 121 is peeled off to realize the separation of the second substrate 110 and the epitaxial layer 120, and dilute
  • the hydrochloric acid solution etches the surface of the intrinsic semiconductor layer 122 to remove the metal gallium material formed by decomposing the buffer layer 121, and then obtains the semiconductor structure as shown in FIG. 2d.
  • the laser is an ultraviolet laser with a wavelength of 266nm.
  • Step S150 forming a first step in the epitaxial layer and forming a plurality of via holes penetrating through the intrinsic semiconductor layer in the epitaxial layer.
  • FIG. 2e is a schematic cross-sectional view of the semiconductor structure taken along the line AA in FIG. 3 .
  • FIG. 3 does not specifically show the top view details of the first angle formed between the side wall and the bottom of the step 154 .
  • FIG. 2 e for details of the first angle formed between the side wall and the bottom of the step 154 .
  • the periphery of the epitaxial layer 120 from which the buffer layer 121 has been removed is etched using a photolithography process and an etching process to form a first step 154.
  • the intrinsic semiconductor layer 122 , the first semiconductor layer 123 , the light emitting layer 124 , the electron blocking layer 125 and the second semiconductor layer 126 are sequentially etched to expose the surface of the first ohmic contact layer 131 .
  • the sidewall of the first step 154 forms a first included angle with the surface of the bottom (the first ohmic contact layer 131 in the first step 154), and the first included angle is 30°-60°.
  • the first included angle is 40°.
  • the surface of the intrinsic semiconductor layer 122 is also roughened.
  • a hot potassium hydroxide solution with a concentration of about 2 mol/L is used to etch the intrinsic semiconductor layer 122 to obtain a roughened surface.
  • wet etching or dry etching may also be used to form a roughened surface.
  • a plurality of through holes 153 distributed in an array are formed in the epitaxial layer by photolithography and dry etching process. Further, a plurality of through holes 153 are formed by etching in the intrinsic semiconductor layer 122 except for the first electrode by, for example, an ICP dry etching process.
  • the diameter of the through holes 153 is, for example, 100 nanometers to 10 microns. 153 penetrates through the intrinsic semiconductor layer 122 and exposes the surface of the first semiconductor layer 123 .
  • the pitch between adjacent through holes 153 is 5 microns to 50 microns.
  • the shape of the array formed by the plurality of through holes 153 is one of hexagonal, triangular, quadrilateral or circular arrays.
  • the cross-sectional shape of the through hole 153 is, for example, a circle, and the shape of the plurality of through holes 153 arranged in an array is a quadrilateral array.
  • the cross-sectional shape of the through hole 153 may also be hexagonal, quadrilateral, triangular, etc., for example.
  • the hole spacing between at least some of the through holes 153 is evenly distributed or gradually reduced along the center of the vertical structure LED chip to the edge area.
  • the intrinsic semiconductor layer 122 located in the first electrode region may also be removed during the process of forming the through hole 153 .
  • a current blocking layer (not shown) is formed on the surface of the second semiconductor layer 126 in the first electrode region after the epitaxial layer 120 is formed in the step shown in FIG. 2a.
  • the current blocking layer is prepared by plasma-enhanced chemical vapor deposition, photolithography and wet etching. The current blocking layer covers part of the second semiconductor layer 126 .
  • a first ohmic contact layer 131 is formed on the surface of the second semiconductor layer 126 and the current blocking layer, and a mirror layer 132 is formed on the surface of the first ohmic contact layer 131 .
  • Step S160 sequentially forming a transparent conductive layer and a metal nanowire layer on the surface of the intrinsic semiconductor layer of the epitaxial layer and the sidewalls and bottoms of the via holes. Specifically, as shown in FIG. 2f, a transparent conductive layer 161 and a metal nanowire layer 162 are formed on the surface of the semiconductor structure shown in FIG. 2e. Furthermore, a transparent conductive layer 161 is formed on the surface of the intrinsic semiconductor layer 122 and in the through hole 153.
  • the transparent conductive layer 161 is one or more combinations of indium tin oxide, zinc aluminum oxide, and graphene materials, which transmit The rate is greater than 90%, and the refractive index is 1.8-2.0.
  • the thickness of the transparent conductive layer 161 is 30 nm-200 nm. Then, for example, a solution template method is used to form a metal nanowire layer 162 on the surface of the transparent conductive layer 161.
  • the metal nanowire layer is one of a silver nanowire layer, an aluminum nanowire layer, a gold nanowire layer, and a copper nanowire layer. If the ratio is greater than 90%, the refractive index can be ignored.
  • the thickness of the metal nanowire layer 162 is 100 nm-600 nm.
  • the intrinsic semiconductor layer 122 is a relatively high-resistance semiconductor
  • the transparent conductive layer 161 and the metal nanowire layer 162 are relatively low-resistance materials
  • most of the transparent conductive layer 161 is a lateral film
  • the vertically relatively high resistance of the first semiconductor layer 123 and the relatively low lateral resistance of the transparent conductive layer 161 and the metal nanowire layer 162 can effectively improve the current distribution and expansion performance of the vertically structured LED chip.
  • Step S170 forming a first electrode, a second electrode and a passivation layer.
  • a first electrode (N electrode) 137 is formed on the surface of the intrinsic semiconductor layer 122 (the surface of the first semiconductor layer 123 where the first electrode region is located) using a photolithography process and an electron beam evaporation process.
  • the intrinsic semiconductor layer 122 , the transparent conductive layer 161 and the metal nanowire layer 162 are also included between the first electrode 137 and the first semiconductor layer 123 , and the first electrode 137 covers part of the surface of the metal nanowire layer 162 .
  • a current blocking layer can also be formed on the surface of the second semiconductor layer 126 in the first electrode region after the formation of the epitaxial layer 120, and the current blocking layer is located under the first electrode 137, wherein the first The electrode 137 may cover or partially cover the current blocking layer. Then the surface of the first substrate 210 away from the second bonding layer 144 is thinned, and the second electrode 139 (P electrode) is formed on the thinned surface of the first substrate 210 .
  • the first electrode 137 is a composite metal layer, including a first metal layer, a second metal layer and a third metal layer sequentially located on the surface of the metal nanowire layer 162 .
  • the first metal layer is one of a chromium layer, a titanium layer, a vanadium layer, and a hafnium layer, and the thickness of the first metal layer is 1 nanometer to 100 nanometers;
  • the second metal layer is aluminum, titanium, platinum, or gold.
  • One or more composite material layers, the third metal layer is a gold layer, and the thickness of the second metal layer and the third metal layer are both in the range of 100 nanometers to 1 micron.
  • a passivation layer 138 is formed on the surface of the remaining part of the metal nanowire layer 162 , the sidewall and the bottom of the first step 154 by using a chemical vapor deposition process, and the passivation layer 138 exposes the first electrode 137 .
  • the passivation layer 138 is, for example, an insulating material such as a silicon dioxide layer.
  • the passivation layer 138 , the transparent conductive layer 161 and the epitaxial layer excluding the buffer layer 121 form a graded refractive index structure, and the refractive index increases gradually from the passivation layer 138 to the epitaxial layer, which can achieve better light extraction effect.
  • Both the transparent conductive layer 161 and the metal nanowire layer 162 have high transmittance characteristics, so that the light-emitting surface of the vertical structure LED chip has excellent light transmittance.
  • the wafer cutting technology is one of water guide laser, laser surface cutting or grinding wheel knife processing, and the cutting scheme is one of single-sided cutting or double-sided cutting. kind.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种垂直结构LED芯片及其制造方法，垂直结构LED芯片包括：第一衬底（210）；位于第一衬底（210）的第一表面上且由下至上依次堆叠的键合层（144、134）、反射镜层（132）、第一欧姆接触层（131）以及外延层（120），外延层（120）包括位于第一欧姆接触层（131）表面上且由下至上依次堆叠的第二半导体层（126）、发光层（124）、第一半导体层（123）和本征半导体层（122）；多个贯穿本征半导体层（122）并露出第一半导体层（123）表面的通孔（153）；以及位于本征半导体层（122）表面和通孔（153）的侧壁和底部的透明导电层（161）和金属纳米线层（162）。本申请通过在本征半导体层（122）表面和多个通孔（153）侧壁和底部设置电阻率低于本征半导体层（122）的透明导电层（161）和金属纳米线层（162），提升了电流注入的均匀性、且获得更好的电流扩展效果。

Description

垂直结构LED芯片及其制造方法
本申请要求了申请日为2021年07月28日、申请号为202110854167.4、名称为“垂直结构LED芯片及其制造方法”的中国发明申请的优先权，并且通过参照上述中国发明申请的全部说明书、权利要求、附图和摘要的方式，将其引用于本申请。
技术领域
本发明属于半导体器件技术领域，更具体地，涉及一种垂直结构LED芯片及其制造方法。
背景技术
垂直结构LED芯片相比水平结构LED芯片具有高亮度的优势。一方面，垂直结构LED芯片是将外延层从绝缘和散热差的蓝宝石衬底转移到导电导热能力优异的键合衬底上，进而能承受更高的工作电流从而获得更高的亮度。另一方面，垂直结构LED芯片更容易将出光表面进行微纳加工，进而降低外延层和空气界面的全反射来增加光提取效率。目前垂直结构LED芯片主要包括垂直反极性(N电极向上)结构和垂直正极性(P电极向上)结构。
垂直反极性结构的LED芯片一般采用梳状电极结合n-GaN层来实现电流扩展的目的，但该方案在较高的电流密度下会造成较严重的电流拥堵现象，一般会采用电流阻挡层方案来缓解电流拥堵问题，但是电流阻挡层和N电极都会阻挡和吸收一部分的发光，最终导致垂直反极性结构的LED芯片光提取效率降低。
目前常采用垂直正极性结构的LED芯片设计来解决上述技术问题。但是垂直正极性结构的LED芯片需要采用同侧金属层方案，需要设计并制备复杂的金属--介质--金属叠对层方案，并且由于金属和介质之间必然有应力存在，在制造过程中尤其是键合和衬底转移过程中，应力调控会 面临较大的技术挑战，即垂直正极性结构的LED芯片的制造过程复杂。
发明内容
本发明的目的在于提供一种垂直结构LED芯片及其制造方法，其垂直结构LED芯片为具备良好的电流扩展和均匀注入效果，以及更好的光提取效果的垂直反极性结构的LED芯片；并且垂直结构LED芯片的制造方法简单，相比垂直正极性结构的制造方案，降低了工艺复杂度；整面设置的第一欧姆接触层、反射镜层和键合层具有优良的导热能力，可以有效降低垂直结构LED芯片的热阻，有效提高垂直结构LED芯片的工艺良率和器件可靠性。
本申请提供了一种垂直结构LED芯片，包括：第一衬底；
位于所述第一衬底的第一表面上且由下至上依次堆叠的键合层、反射镜层、第一欧姆接触层以及外延层，所述外延层包括位于所述第一欧姆接触层表面上且由下至上依次堆叠的第二半导体层、发光层、第一半导体层和本征半导体层；
多个贯穿所述本征半导体层并露出所述第一半导体层表面的通孔；以及
位于所述本征半导体层表面和所述通孔的侧壁和底部的透明导电层和金属纳米线层。
可选地，所述通孔的直径为100纳米～10微米。
可选地，相邻所述通孔之间的孔间距为5微米～50微米。
可选地，所述多个通孔阵列排布，阵列形状为六边形、三角形、四边形或圆形阵列中的一种。
可选地，至少部分所述通孔之间的孔间距沿垂直结构LED芯片的中心向边缘区域均匀分布或渐变缩小。
可选地，所述透明导电层的材料为氧化铟锡、氧化锌铝或石墨烯中的一种或多种组合，所述透明导电层的透射率大于90％。
可选地，所述金属纳米线层的材料为银纳米线层、铝纳米线层、金纳米线层、铜纳米线层中的一种，所述金属纳米线层的透射率大于90％。
可选地，还包括：
第一电极，位于所述第一半导体层表面，且所述第一电极与所述第一半导体层之间还包括所述本征半导体层、所述透明导电层和所述金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面；以及
第二电极，位于所述第一衬底的第二表面。
可选地，还包括：
第一电极，位于所述第一半导体层表面；
第二电极，位于所述第一衬底的第二表面；以及
电流阻挡层，位于所述第一欧姆接触层与所述第二半导体层之间，且位于所述第一电极的下方并被所述第二半导体层覆盖，
其中，所述第一电极与所述第一半导体层之间还包括所述透明导电层和金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面。
可选地，所述第一电极为N电极，所述第二电极为P电极。
可选地，还包括：
钝化层，位于所述金属纳米线层的表面并露出所述第一电极，所述钝化层与所述透明导电层和所述外延层形成折射率渐变结构。
可选地，还包括：
电子阻挡层，位于所述发光层与所述第二半导体层之间。
可选地，还包括：
第一台阶，位于所述垂直结构LED芯片的四周，贯穿所述本征半导体层、所述第一半导体层、所述发光层、所述第二半导体层并暴露所述第一欧姆接触层的表面，所述第一台阶的侧壁与底部之间形成第一夹角，所述第一夹角为30°～60°，其中，所述钝化层还覆盖所述第一台阶的底部和侧壁。
可选地，所述第一电极为复合金属层，包括依次位于所述金属纳米线层表面的第一金属层、第二金属层和第三金属层，所述第一金属层的厚度为1纳米～100纳米，所述第二金属层和所述第三金属层的厚度均为100纳米～1微米。
可选地，所述第一金属层为铬层、钛层、钒层、铪层中的一种，所 述第二金属层为铝、钛、铂、金材料中的一种或多种组合材料层，所述第三金属层为金层。
可选地，所述本征半导体层的表面为粗糙表面。
本申请还提供了一种垂直结构LED芯片的制造方法，包括：
在第一晶圆表面形成第一键合层，所述第一晶圆包括第二衬底以及位于所述第二衬底表面的外延层、第一欧姆接触层以及反射镜层，所述外延层包括依次位于所述第二衬底表面的本征半导体层、第一半导体层、发光层和第二半导体层；
在第一衬底的第一表面形成第二键合层；
通过所述第一键合层、所述第二键合层将所述第一晶圆与所述第一衬底键合在一起；
将所述第二衬底剥离；
形成多个贯穿所述本征半导体层并露出所述第一半导体层表面的通孔；以及
在所述本征半导体层表面和所述通孔的侧壁和底部形成透明导电层和金属纳米线层。
可选地，所述通孔的直径为100纳米～10微米。
可选地，相邻所述通孔之间的孔间距为5微米～50微米。
可选地，所述多个通孔阵列排布，阵列形状为六边形、三角形、四边形或圆形阵列中的一种。
可选地，至少部分所述通孔之间的孔间距相等或者沿垂直结构LED芯片的中心向边缘区域均匀分布或渐变缩小。
可选地，所述透明导电层的材料为氧化铟锡、氧化锌铝或石墨烯中的一种或多种组合，所述透明导电层的透射率大于90％。
可选地，所述金属纳米线层的材料为银纳米线层、铝纳米线层、金纳米线层、铜纳米线层中的一种，所述金属纳米线层的透射率大于90％。
可选地，还包括：
在所述第一半导体层表面形成第一电极，所述第一电极与所述第一半导体层之间还包括所述本征半导体层、所述透明导电层和所述金属纳 米线层，且所述第一电极覆盖部分所述金属纳米线层的表面；以及
在所述第一衬底的第二表面形成第二电极。
可选地，还包括：
在所述第一半导体层表面形成第一电极；
在所述第一衬底的第二表面形成第二电极；以及
在所述第一欧姆接触层与所述第二半导体层之间形成电流阻挡层，且所述电流阻挡层位于所述第一电极的下方并被所述第二半导体层覆盖，
其中，所述第一电极与所述第一半导体层之间还包括所述透明导电层和金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面。
可选地，所述第一电极为N电极，所述第二电极为P电极。
可选地，还包括：
在所述金属纳米线层的表面形成露出所述第一电极的钝化层，所述钝化层与所述透明导电层和所述外延层形成折射率渐变结构。
可选地，还包括：
在所述发光层与所述第二半导体层之间形成电子阻挡层。
可选地，还包括：
在所述垂直结构LED芯片的四周形成第一台阶，所述第一台阶贯穿所述本征半导体层、所述第一半导体层、所述发光层、所述第二半导体层并暴露所述第一欧姆接触层的表面，所述第一台阶的侧壁与底部之间形成第一夹角，所述第一夹角为30°～60°，其中，所述钝化层还覆盖所述第一台阶的底部和侧壁。
可选地，所述第一电极为复合金属层，包括依次位于所述金属纳米线层表面的第一金属层、第二金属层和第三金属层，所述第一金属层的厚度为1纳米～100纳米，所述第二金属层和所述第三金属层的厚度均为100纳米～1微米。
可选地，所述第一金属层为铬层、钛层、钒层、铪层中的一种，所述第二金属层为铝、钛、铂、金材料中的一种或多种组合材料层，所述第三金属层为金层。
可选地，所述本征半导体层的表面为粗糙表面。
可选地，还包括：
在所述第二衬底与所述本征半导体层之间形成缓冲层，
其中，在将所述第二衬底剥离的过程中，对所述缓冲层进行分解，采用化学湿法腐蚀技术将所述缓冲层分解后的产物去除，以露出所述本征半导体层。
可选地，还包括：
采用晶圆切割技术切割并得到垂直结构LED芯片，所述晶圆切割技术为水导激光、激光表切或砂轮刀加工方式中的一种。
根据本发明实施例提供的垂直结构LED芯片，在本征半导体层表面和贯穿本征半导体层到达第一半导体层表面的多个通孔的侧壁和底部设置透明导电层和金属纳米线层。其中，本征半导体层为相对高阻半导体，透明导电层和金属纳米线层为相对低阻材料，透明导电层绝大部分为横向薄膜，位于通孔中的透明导电层起到向第一半导体层均匀注入电流的作用。进而利用第一半导体层的纵向相对高阻、透明导电层和金属纳米线层的横向相对低阻的特性，使得垂直结构的LED芯片的电流分布和扩展性能有效提升。
更进一步地，透明导电层和金属纳米线层皆具备高透射率特性，使得垂直结构LED芯片的发光表面具有优异的光透射率。
更进一步地，钝化层、透明导电层和外延层形成折射率渐变结构，从钝化层到外延层的折射率递增，能够实现更好的光提取效果。
根据本发明实施例提供的垂直结构LED芯片的制造方法，制造多个贯穿本征半导体层并到达第一半导体层表面的通孔，随后在整面本征半导体层上制备透明导电层、金属纳米线层，后续制备形成第一电极完成垂直反极性结构的LED芯片加工。该工艺避免了垂直正极性芯片复杂的工艺方案，显著降低了工艺困难度。且由于采用了多通孔本征半导体层、透明导电层和金属纳米线层，提升了发光层内的载流子分布均匀性，改善了外延效率降低的问题，使得垂直反极性LED芯片的电流分布和扩展性能得到了提升。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出根据本发明实施例提供的垂直结构LED芯片的制造方法流程示意图；
图2a至2g示出根据本发明实施例提供的垂直结构LED芯片在制造过程中不同阶段的结构截面图；
图3示出了图2e所示的半导体结构的俯视图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
本发明可以各种形式呈现，以下将描述其中一些示例。
图1示出根据本发明实施例提供的垂直结构LED芯片的制造方法流程示意图。图2a至2g示出根据本发明实施例提供的垂直结构LED芯片在制造过程中不同阶段的结构截面图。图3示出了图2e所示的半导体结构的俯视图。本实施例提供的制造方法是对整片晶圆操作的，为方便理解，附图仅仅示出一个垂直结构LED芯片单元。
如图1所示，垂直结构LED芯片的制造方法包括以下步骤。
步骤S110：在第一晶圆表面形成第一键合层，第一晶圆包括第二衬底以及位于第二衬底表面的外延层、第一欧姆接触层以及反射镜层。具体地，如图2a所示，首先在第二衬底110的表面上形成外延层120。外延层120的总厚度为5微米～10微米。进一步地，制备外延层120例如采用金属有机物化学气相沉积工艺在第二衬底110的第一表面上依次形成本征半导体层122、第一半导体层123、发光层124、第二半导体层126。在其他实施例中，例如还在第二衬底110表面形成缓冲层121，缓冲层121位于第二衬底110与本征半导体层122之间。在其他实施例中，例如还在发光层124和第二半导体层126之间形成电子阻挡层125。本文 后续制造工艺在包括缓冲层121、本征半导体层122、第一半导体层123、发光层124、电子阻挡层125以及第二半导体层126的外延层中进行。
在可替代的实施例中，还可以采用激光辅助分子束外延、激光溅射或氢化物气相外延等工艺形成外延层120。其中，本征半导体层122为非掺杂的氮化镓材料层，第一半导体层123为第一掺杂类型(N型)的氮化镓材料层，发光层124例如为多量子阱(MQW，multiple quantum well)层，电子阻挡层125例如为第二掺杂类型(P型)的氮化铝镓材料层，第二半导体层126例如为第二掺杂类型(P型)的氮化镓材料层，其中，多量子阱层例如由氮化镓/氮化铟镓/氮化铝镓材料所组成。
第二衬底110包含但不限于镜面或微米级/纳米级图形化蓝宝石衬底中的一种，在优选的实施例中，第二衬底110为微米级图形化蓝宝石。在其他可替代的实施例中，第二衬底110为异质衬底的一种，第二衬底110还可以是氧化镓、碳化硅、硅、氧化锌、镓酸锂单晶衬底或耐高温金属衬底。第二衬底110的厚度为300微米～2毫米，第二衬底110的直径为1英寸～8英寸。
接着，在第二半导体层126的表面上依次形成第一欧姆接触层131和反射镜层132，进而形成第一晶圆。更进一步地，采用光刻、物理气相沉积工艺在第二半导体层126的表面上形成第二掺杂类型(P型)的第一欧姆接触层131以及在第一欧姆接触层131的表面上形成反射镜层132。第一欧姆接触层131例如为氧化铟锡，反射镜层132例如为银铂钛叠层。
之后在第二半导体层126表面形成第一欧姆接触层131以及在第一欧姆接触层131表面形成反射镜层132。
在可替代的实施例中，第一欧姆接触层131还可以是氧化锌铝(AZO)、氧化铟镓(GTO)、镍金、镍银、镍铝中的一种，第一欧姆接触层131的厚度为1纳米～200纳米。反射镜层132还可以是银层、铝层、镁层、铂层、铑层、金层中的一种，反射镜层132的厚度为60纳米～200纳米。
然后在反射镜层132远离第一欧姆接触层131的表面(第一晶圆的 表面)形成第一键合层134。第一键合层134为铜、镍、银、金等高熔点金属和锡、铟等低熔点金属组成的二元共晶金属体系方案中的一种。第一键合层134例如为镍/锡二元金属层。
步骤S120：在第一衬底表面形成第二键合层。具体地，如图2b所示，在第一衬底210的表面上形成第二键合层144。第二键合层144为铜、镍、银、金等高熔点金属和锡、铟等低熔点金属组成的二元共晶金属体系方案中的一种。更进一步地，第一衬底210例如为直径4英寸、厚度200微米的铜钨金属衬底。第二键合层144例如为镍/锡二元金属层。在其他可替代的实施例中，第一衬底210可以是硅、铜、钼、钨、钼铜合金、铝硅合金衬底中的一种，第一衬底210的直径为1英寸～8英寸，第一衬底210的厚度为100微米～1微米。
步骤S130：通过第一键合层、第二键合层将第一晶圆与第一衬底键合在一起。具体地，如图2c所示，采用液相瞬态键合工艺，在温度约260℃的环境下将第一晶圆和第一衬底210键合在一起。
步骤S140：将第二衬底剥离。具体地，如图2d所示，通过衬底转移技术将第二衬底110剥离。更进一步地，衬底转移技术可以是激光剥离、化学机械减薄、化学湿法腐蚀、干法刻蚀中的一种或多种工艺的组合。更进一步地，在剥离过程中会对缓冲层121进行分解，采用化学湿法腐蚀技术将所述缓冲层分解后的产物去除，以露出本征半导体层122。例如采用直径为30微米的圆形小光斑的激光将缓冲层121剥离分解，进而剥离位于缓冲层121表面的第二衬底110，实现第二衬底110与外延层120的分离，并采用稀盐酸溶液腐蚀本征半导体层122的表面以去除缓冲层121分解形成的金属镓材料，进而得到如图2d所示的半导体结构。其中，激光为波长为266nm的紫外激光。
步骤S150：在外延层中形成第一台阶以及形成多个贯穿外延层中本征半导体层的通孔。具体地，如图2e以及图3所示，其中，图2e的为沿图3中AA线截面得到的半导体结构的截面示意图。为清楚起见，图3中未具体示出台阶154侧壁与底部形成第一夹角的俯视细节，台阶154侧壁与底部形成第一夹角的细节请见附图2e。采用光刻工艺和刻蚀工艺 对去除了缓冲层121的外延层120的四周进行刻蚀以形成第一台阶154。具体的，依次刻蚀本征半导体层122、第一半导体层123、发光层124、电子阻挡层125和第二半导体层126以露出第一欧姆接触层131的表面。其中，第一台阶154的侧壁与底部(第一台阶154中的第一欧姆接触层131)的表面形成第一夹角，第一夹角为30°～60°，优选地，第一夹角为40°。在其他实施例中，还对本征半导体层122的表面进行粗化，例如采用浓度约为2mol/L的热氢氧化钾溶液腐蚀本征半导体层122以得到粗化表面。在其他实施例中，也可以采用湿法腐蚀或干法刻蚀形成粗化表面。
接着采用光刻和干法刻蚀工艺在外延层中形成阵列分布的多个通孔153。进一步地，例如采用ICP干法刻蚀工艺在本征半导体层122中除第一电极之外的区域刻蚀形成多个通孔153，通孔153的直径例如为100纳米～10微米，通孔153贯穿本征半导体层122并露出第一半导体层123表面。相邻通孔153之间的孔间距为5微米～50微米。多个通孔153所形成的阵列形状为六边形、三角形、四边形或圆形阵列中的一种。更进一步地，通孔153的截面形状例如为圆形，多个通孔153阵列排布的形状为四边形阵列。在其他实施例中，通孔153的截面形状例如还可以是六边形、四边形、三角形等。至少部分通孔153之间的孔间距沿垂直结构LED芯片的中心向边缘区域均匀分布或渐变缩小。
在其他实施例中，在形成通孔153的过程中还可以同时去除位于第一电极区域的本征半导体层122。进一步地，在该实例中还在如图2a所示的步骤中在形成外延层120之后在第一电极区域的第二半导体层126表面形成电流阻挡层(图中未示出)。更进一步，采用等离子体增强化学气相沉积法、光刻和湿法腐蚀工艺制备电流阻挡层。电流阻挡层覆盖部分第二半导体层126。之后在第二半导体层126和电流阻挡层表面形成第一欧姆接触层131以及在第一欧姆接触层131表面形成反射镜层132。
步骤S160：在外延层的本征半导体层表面和通孔的侧壁和底部依次形成透明导电层和金属纳米线层。具体地，如图2f所示，在如图2e所示的半导体结构的表面形成透明导电层161和金属纳米线层162。更进 一步地，在本征半导体层122的表面和通孔153中形成透明导电层161，透明导电层161为氧化铟锡、氧化锌铝、石墨烯材料中的一种或多种组合，其透射率大于90％，折射率为1.8～2.0。透明导电层161的厚度为30纳米-200纳米。接着例如采用溶液模板法在透明导电层161表面形成金属纳米线层162，金属纳米线层为银纳米线层、铝纳米线层、金纳米线层、铜纳米线层中的一种，其透射率大于90％，折射率可以考虑不计。金属纳米线层162的厚度为100纳米-600纳米。其中，本征半导体层122为相对高阻半导体，透明导电层161和金属纳米线层162是相对低阻材料，透明导电层161绝大部分为横向薄膜，位于通孔153中的透明导电层161起到向第一半导体层123均匀注入电流的作用。进而利用第一半导体层123的纵向相对高阻、透明导电层161和金属纳米线层162的横向相对低阻的特性，使得垂直结构的LED芯片的电流分布和扩展性能有效提升。
步骤S170：形成第一电极、第二电极以及钝化层。具体地，如图2g所示，采用光刻工艺和电子束蒸发工艺在本征半导体层122的表面(第一电极区域所在的第一半导体层123的表面)形成第一电极(N电极)137，第一电极137与第一半导体层123之间还包括本征半导体层122、透明导电层161和金属纳米线层162，且第一电极137覆盖部分金属纳米线层162的表面。在其他实施例中，当在形成通孔153的过程中还同时去除位于第一电极区域的本征半导体层122时，也即第一电极137与第一半导体层123之间只包括透明导电层161和金属纳米线层162，此时还可以在形成外延层120之后在第一电极区域的第二半导体层126表面形成电流阻挡层，且电流阻挡层位于第一电极137的下方，其中第一电极137可以覆盖或者部分覆盖电流阻挡层。然后对第一衬底210远离第二键合层144的表面进行减薄，并在减薄的第一衬底210表面形成第二电极139(P电极)。第一电极137为复合金属层，包括依次位于金属纳米线层162表面的第一金属层、第二金属层和第三金属层。其中，第一金属层为铬层、钛层、钒层、铪层中的一种，第一金属层的厚度为1纳米～100纳米；第二金属层为铝、钛、铂、金材料中的一种或多种组合 材料层，第三金属层为金层，第二金属层和第三金属层的厚度范围均为100纳米～1微米。
更进一步地，还包括形成钝化层。具体地，采用化学气相淀积工艺在剩余部分金属纳米线层162的表面、第一台阶154的侧壁和底部形成钝化层138，钝化层138暴露出第一电极137。钝化层138例如为二氧化硅层等绝缘材料。其中，钝化层138、透明导电层161和不包括缓冲层121的外延层形成折射率渐变结构，从钝化层138到外延层折射率递增，能够实现更好的光提取效果。透明导电层161和金属纳米线层162皆具备高透射率特性，使得垂直结构LED芯片的发光表面具有优异的光透射率。
接着采用晶圆切割技术得到多个垂直结构LED芯片，晶圆切割技术为水导激光、激光表切或砂轮刀加工方式中的一种，且切割方案为单面切割或双面切割中的一种。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (34)

  1. 一种垂直结构LED芯片，其中，包括：
    第一衬底；
    位于所述第一衬底的第一表面上且由下至上依次堆叠的键合层、反射镜层、第一欧姆接触层以及外延层，所述外延层包括位于所述第一欧姆接触层表面上且由下至上依次堆叠的第二半导体层、发光层、第一半导体层和本征半导体层；
    多个贯穿所述本征半导体层并露出所述第一半导体层表面的通孔；以及
    位于所述本征半导体层表面和所述通孔的侧壁和底部的透明导电层和金属纳米线层。
  2. 根据权利要求1所述的垂直结构LED芯片，其中，所述通孔的直径为100纳米～10微米。
  3. 根据权利要求1所述的垂直结构LED芯片，其中，相邻所述通孔之间的孔间距为5微米～50微米。
  4. 根据权利要求1所述的垂直结构LED芯片，其中，所述多个通孔阵列排布，阵列形状为六边形、三角形、四边形或圆形阵列中的一种。
  5. 根据权利要求4所述的垂直结构LED芯片，其中，至少部分所述通孔之间的孔间距沿垂直结构LED芯片的中心向边缘区域均匀分布或渐变缩小。
  6. 根据权利要求1所述的垂直结构LED芯片，其中，所述透明导电层的材料为氧化铟锡、氧化锌铝或石墨烯中的一种或多种组合，所述透明导电层的透射率大于90％。
  7. 根据权利要求1所述的垂直结构LED芯片，其中，所述金属纳米线层的材料为银纳米线层、铝纳米线层、金纳米线层、铜纳米线层中的一种，所述金属纳米线层的透射率大于90％。
  8. 根据权利要求1所述的垂直结构LED芯片，其中，还包括：
    第一电极，位于所述第一半导体层表面，且所述第一电极与所述第 一半导体层之间还包括所述本征半导体层、所述透明导电层和所述金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面；以及
    第二电极，位于所述第一衬底的第二表面。
  9. 根据权利要求1所述的垂直结构LED芯片，其中，还包括：
    第一电极，位于所述第一半导体层表面；
    第二电极，位于所述第一衬底的第二表面；以及
    电流阻挡层，位于所述第一欧姆接触层与所述第二半导体层之间，且位于所述第一电极的下方并被所述第二半导体层覆盖，
    其中，所述第一电极与所述第一半导体层之间还包括所述透明导电层和金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面。
  10. 根据权利要求8或9所述的垂直结构LED芯片，其中，所述第一电极为N电极，所述第二电极为P电极。
  11. 根据权利要求8或9所述的垂直结构LED芯片，其中，还包括：
    钝化层，位于所述金属纳米线层的表面并露出所述第一电极，所述钝化层与所述透明导电层和所述外延层形成折射率渐变结构。
  12. 根据权利要求1所述的垂直结构LED芯片，其中，还包括：
    电子阻挡层，位于所述发光层与所述第二半导体层之间。
  13. 根据权利要求11所述的垂直结构LED芯片，其中，还包括：
    第一台阶，位于所述垂直结构LED芯片的四周，贯穿所述本征半导体层、所述第一半导体层、所述发光层、所述第二半导体层并暴露所述第一欧姆接触层的表面，所述第一台阶的侧壁与底部之间形成第一夹角，所述第一夹角为30°～60°，其中，所述钝化层还覆盖所述第一台阶的底部和侧壁。
  14. 根据权利要求8或9所述的垂直结构LED芯片，其中，所述第一电极为复合金属层，包括依次位于所述金属纳米线层表面的第一金属层、第二金属层和第三金属层，所述第一金属层的厚度为1纳米～100纳米，所述第二金属层和所述第三金属层的厚度均为100纳米～1微米。
  15. 根据权利要求14所述的垂直结构LED芯片，其中，所述第一金属层为铬层、钛层、钒层、铪层中的一种，所述第二金属层为铝、钛、 铂、金材料中的一种或多种组合材料层，所述第三金属层为金层。
  16. 根据权利要求1所述的垂直结构LED芯片，其中，所述本征半导体层的表面为粗糙表面。
  17. 一种垂直结构LED芯片的制造方法，其中，包括：
    在第一晶圆表面形成第一键合层，所述第一晶圆包括第二衬底以及位于所述第二衬底表面的外延层、第一欧姆接触层以及反射镜层，所述外延层包括依次位于所述第二衬底表面的本征半导体层、第一半导体层、发光层和第二半导体层；
    在第一衬底的第一表面形成第二键合层；
    通过所述第一键合层、所述第二键合层将所述第一晶圆与所述第一衬底键合在一起；
    将所述第二衬底剥离；
    形成多个贯穿所述本征半导体层并露出所述第一半导体层表面的通孔；以及
    在所述本征半导体层表面和所述通孔的侧壁和底部形成透明导电层和金属纳米线层。
  18. 根据权利要求17所述的制造方法，其中，所述通孔的直径为100纳米～10微米。
  19. 根据权利要求17所述的制造方法，其中，相邻所述通孔之间的孔间距为5微米～50微米。
  20. 根据权利要求17所述的制造方法，其中，所述多个通孔阵列排布，阵列形状为六边形、三角形、四边形或圆形阵列中的一种。
  21. 根据权利要求20所述的制造方法，其中，至少部分所述通孔之间的孔间距相等或者沿垂直结构LED芯片的中心向边缘区域均匀分布或渐变缩小。
  22. 根据权利要求17所述的制造方法，其中，所述透明导电层的材料为氧化铟锡、氧化锌铝或石墨烯中的一种或多种组合，所述透明导电层的透射率大于90％。
  23. 根据权利要求17所述的制造方法，其中，所述金属纳米线层的 材料为银纳米线层、铝纳米线层、金纳米线层、铜纳米线层中的一种，所述金属纳米线层的透射率大于90％。
  24. 根据权利要求17所述的制造方法，其中，还包括：
    在所述第一半导体层表面形成第一电极，所述第一电极与所述第一半导体层之间还包括所述本征半导体层、所述透明导电层和所述金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面；以及
    在所述第一衬底的第二表面形成第二电极。
  25. 根据权利要求17所述的制造方法，其中，还包括：
    在所述第一半导体层表面形成第一电极；
    在所述第一衬底的第二表面形成第二电极；以及
    在所述第一欧姆接触层与所述第二半导体层之间形成电流阻挡层，且所述电流阻挡层位于所述第一电极的下方并被所述第二半导体层覆盖，
    其中，所述第一电极与所述第一半导体层之间还包括所述透明导电层和金属纳米线层，且所述第一电极覆盖部分所述金属纳米线层的表面。
  26. 根据权利要求24或25所述的制造方法，其中，所述第一电极为N电极，所述第二电极为P电极。
  27. 根据权利要求24或25所述的制造方法，其中，还包括：
    在所述金属纳米线层的表面形成露出所述第一电极的钝化层，所述钝化层与所述透明导电层和所述外延层形成折射率渐变结构。
  28. 根据权利要求17所述的制造方法，其中，还包括：
    在所述发光层与所述第二半导体层之间形成电子阻挡层。
  29. 根据权利要求27所述的制造方法，其中，还包括：
    在所述垂直结构LED芯片的四周形成第一台阶，所述第一台阶贯穿所述本征半导体层、所述第一半导体层、所述发光层、所述第二半导体层并暴露所述第一欧姆接触层的表面，所述第一台阶的侧壁与底部之间形成第一夹角，所述第一夹角为30°～60°，其中，所述钝化层还覆盖所述第一台阶的底部和侧壁。
  30. 根据权利要求24或25所述的制造方法，其中，所述第一电极为复合金属层，包括依次位于所述金属纳米线层表面的第一金属层、第 二金属层和第三金属层，所述第一金属层的厚度为1纳米～100纳米，所述第二金属层和所述第三金属层的厚度均为100纳米～1微米。
  31. 根据权利要求30所述的制造方法，其中，所述第一金属层为铬层、钛层、钒层、铪层中的一种，所述第二金属层为铝、钛、铂、金材料中的一种或多种组合材料层，所述第三金属层为金层。
  32. 根据权利要求17所述的制造方法，其中，所述本征半导体层的表面为粗糙表面。
  33. 根据权利要求17所述的制造方法，其中，还包括：
    在所述第二衬底与所述本征半导体层之间形成缓冲层，
    其中，在将所述第二衬底剥离的过程中，对所述缓冲层进行分解，采用化学湿法腐蚀技术将所述缓冲层分解后的产物去除，以露出所述本征半导体层。
  34. 根据权利要求17所述的制造方法，其中，还包括：
    采用晶圆切割技术切割并得到垂直结构LED芯片，所述晶圆切割技术为水导激光、激光表切或砂轮刀加工方式中的一种。
PCT/CN2022/078633 2021-07-28 2022-03-01 垂直结构led芯片及其制造方法 WO2023005203A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110854167.4 2021-07-28
CN202110854167.4A CN113745385B (zh) 2021-07-28 2021-07-28 垂直结构led芯片及其制造方法

Publications (1)

Publication Number Publication Date
WO2023005203A1 true WO2023005203A1 (zh) 2023-02-02

Family

ID=78729255

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/078633 WO2023005203A1 (zh) 2021-07-28 2022-03-01 垂直结构led芯片及其制造方法

Country Status (2)

Country Link
CN (1) CN113745385B (zh)
WO (1) WO2023005203A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116565093A (zh) * 2023-07-11 2023-08-08 江西兆驰半导体有限公司 一种led芯片制备方法及led芯片

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745385B (zh) * 2021-07-28 2023-11-21 厦门士兰明镓化合物半导体有限公司 垂直结构led芯片及其制造方法
CN114267760B (zh) * 2021-12-22 2024-06-25 江西兆驰半导体有限公司 一种正装led芯片及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1424773A (zh) * 2001-12-04 2003-06-18 夏普公司 氮化物基化合物半导体发光元件及其制造方法
CN102738347A (zh) * 2012-01-18 2012-10-17 许并社 具有自组成式纳米结构的白光led芯片结构
WO2015023048A1 (ko) * 2013-08-16 2015-02-19 일진엘이디(주) 나노와이어를 이용한 질화물 반도체 발광소자
CN104603961A (zh) * 2012-09-03 2015-05-06 同和电子科技有限公司 第iii族氮化物半导体发光器件及其制造方法
KR101749154B1 (ko) * 2016-08-31 2017-06-20 전북대학교산학협력단 발광 다이오드 칩 및 이의 제조방법
CN113745385A (zh) * 2021-07-28 2021-12-03 厦门士兰明镓化合物半导体有限公司 垂直结构led芯片及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7358539B2 (en) * 2003-04-09 2008-04-15 Lumination Llc Flip-chip light emitting diode with indium-tin-oxide based reflecting contacts
TWI338387B (en) * 2007-05-28 2011-03-01 Delta Electronics Inc Current spreading layer with micro/nano structure, light-emitting diode apparatus and its manufacturing method
CN103222073B (zh) * 2010-08-03 2017-03-29 财团法人工业技术研究院 发光二极管芯片、发光二极管封装结构、及用以形成上述的方法
CN105023985A (zh) * 2015-07-28 2015-11-04 聚灿光电科技股份有限公司 Led芯片及其制备方法
CN106449955A (zh) * 2016-11-17 2017-02-22 映瑞光电科技(上海)有限公司 一种垂直结构发光二极管及其制造方法
CN106876532B (zh) * 2017-01-13 2019-01-25 南京大学 一种高出光率、高可靠性的紫外发光二极管及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1424773A (zh) * 2001-12-04 2003-06-18 夏普公司 氮化物基化合物半导体发光元件及其制造方法
CN102738347A (zh) * 2012-01-18 2012-10-17 许并社 具有自组成式纳米结构的白光led芯片结构
CN104603961A (zh) * 2012-09-03 2015-05-06 同和电子科技有限公司 第iii族氮化物半导体发光器件及其制造方法
WO2015023048A1 (ko) * 2013-08-16 2015-02-19 일진엘이디(주) 나노와이어를 이용한 질화물 반도체 발광소자
KR101749154B1 (ko) * 2016-08-31 2017-06-20 전북대학교산학협력단 발광 다이오드 칩 및 이의 제조방법
CN113745385A (zh) * 2021-07-28 2021-12-03 厦门士兰明镓化合物半导体有限公司 垂直结构led芯片及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116565093A (zh) * 2023-07-11 2023-08-08 江西兆驰半导体有限公司 一种led芯片制备方法及led芯片

Also Published As

Publication number Publication date
CN113745385A (zh) 2021-12-03
CN113745385B (zh) 2023-11-21

Similar Documents

Publication Publication Date Title
WO2023005203A1 (zh) 垂直结构led芯片及其制造方法
EP2261951B1 (en) Method for fabricating an LED having vertical structure
US8383438B2 (en) Method for fabricating InGaAIN light-emitting diodes with a metal substrate
CN103117334B (zh) 一种垂直结构GaN基发光二极管芯片及其制作方法
TW201225334A (en) Optoelectronic device and method for manufacturing the same
CN1744337A (zh) 氮化物基化合物半导体发光器件
JP2007227939A (ja) 発光素子及びその製造方法
JP2013125961A (ja) 垂直発光ダイオードチップ及びその製造方法
TWI617052B (zh) 半導體裝置之製造方法
CN112186079A (zh) 垂直结构led芯片的制备方法
WO2020232587A1 (zh) 一种制作半导体发光元件的方法
TW201547053A (zh) 形成發光裝置的方法
CN105047788A (zh) 一种基于银基金属键合的薄膜结构led芯片及其制备方法
CN113594305B (zh) 垂直结构led芯片的制造方法
CN217719642U (zh) 发光二极管
TWI786503B (zh) 發光元件及其製造方法
CN115642209A (zh) 一种Micro-LED芯片结构及其制备方法
CN212874527U (zh) 垂直结构led芯片
CN104882517B (zh) 垂直结构led芯片的制造方法
TW201340397A (zh) 發光二極體元件及其製造方法
TWI282629B (en) Method for fabricating LED
CN107146833B (zh) Led倒装芯片的制备方法
CN100442560C (zh) 制造发光二极管的方法
CN217768417U (zh) 半导体晶圆
CN216054755U (zh) 垂直结构led芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22847823

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE