WO2023000355A1 - 限流电路 - Google Patents
限流电路 Download PDFInfo
- Publication number
- WO2023000355A1 WO2023000355A1 PCT/CN2021/108529 CN2021108529W WO2023000355A1 WO 2023000355 A1 WO2023000355 A1 WO 2023000355A1 CN 2021108529 W CN2021108529 W CN 2021108529W WO 2023000355 A1 WO2023000355 A1 WO 2023000355A1
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- WO
- WIPO (PCT)
- Prior art keywords
- terminal
- transistor
- electrically connected
- voltage
- control
- Prior art date
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- 230000001105 regulatory effect Effects 0.000 claims description 14
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 230000007774 longterm Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/025—Reduction of instantaneous peaks of current
Definitions
- the present application relates to the field of display technology, in particular to a current limiting circuit.
- the disadvantage of the traditional design is that the current limit value for AVDD is fixed. If the current limit value is too small, it will cause the power management integrated chip to fail to build up the voltage within the specified time due to the current limit due to the heavy load startup; if the current limit value is too large, it will also fail. When the power management integrated chip is short-circuited in the back-end load, the long-term high current will cause damage to components, such as: source driver damage and fire.
- the present application provides a current-limiting circuit, which can make the current-limiting value of the current-limiting circuit adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged by short-circuit startup.
- the present application provides a current limiting circuit, which includes:
- the input terminal of the first transistor is electrically connected to the first voltage terminal, and the output terminal of the first transistor is electrically connected to the second voltage terminal;
- a current limiting module which is electrically connected to the input terminal of the first transistor and the control terminal of the first transistor, and the current limiting module is used to control the control terminal of the first transistor and the control terminal of the first transistor
- the voltage difference between the input terminals controls the state of the first transistor, so that the current limiting value of the current limiting circuit is adjustable.
- the current limiting module includes a second transistor, a first resistor, a third transistor, and a regulation unit;
- the first end of the second transistor is electrically connected to the first control end, the second end of the second transistor is electrically connected to the input end of the first transistor, and the third end of the second transistor is electrically connected to the first control end.
- the control end of the first transistor is electrically connected; the first end of the first resistor is electrically connected to the input end of the first transistor, and the second end of the first resistor is electrically connected to the input end of the first transistor.
- the control terminal is electrically connected; the first terminal of the third transistor is electrically connected to the second control terminal, the second terminal of the third transistor is electrically connected to the control terminal of the first transistor, and the third transistor is electrically connected to the control terminal.
- the third end of the transistor is connected to the regulating unit; the regulating unit is used to control the state of the first transistor.
- the regulating unit includes a plurality of resistance control subunits arranged in parallel, the first end of the resistance control subunit is electrically connected to the third end of the third transistor, so The second terminal of the resistance control subunit is electrically connected to the ground terminal; each of the resistance control subunits includes a second resistor.
- the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor can be obtained according to the following formula:
- Vgs –V1*R1/(R1+Rx), wherein, Vgs is the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor, and V1 is the voltage of the input terminal of the first transistor voltage value, R1 is the resistance value of the first resistor, and Rx is the resistance value of x resistor control subunits arranged in parallel.
- the current limiting circuit further includes a fourth transistor; the input end of the fourth transistor is electrically connected to the first voltage end, and the output end of the fourth transistor is connected to the first voltage end.
- the second voltage end is electrically connected.
- the current limiting circuit further includes a timing unit, a comparison unit and a constant current unit;
- the timing unit is electrically connected to the first terminal of the comparison unit; the second terminal of the comparison unit is electrically connected to the second voltage terminal, and the third terminal of the comparison unit is connected to a fixed voltage signal,
- the fourth end of the comparison unit is electrically connected to the first end of the constant current unit; the second end of the constant current unit is electrically connected to the control end of the fourth transistor;
- the timing unit is used to output the control signal of the comparison unit at intervals of preset time;
- the voltage of the three terminals, the fourth terminal of the comparison unit outputs the constant current unit control signal to the first terminal of the constant current unit;
- the constant current unit is used to output a constant voltage under the control of the constant current unit control signal current.
- the timing unit includes a timer, and the timer is electrically connected to the first terminal of the comparison unit.
- the comparison unit includes a comparator; the first terminal of the comparator is electrically connected to the timing unit; the second terminal of the comparator is electrically connected to the second voltage terminal The third end of the comparator is connected to a fixed voltage signal, and the fourth end of the comparator is electrically connected to the first end of the constant current unit.
- the constant current unit includes a constant current source; the first end of the constant current source is electrically connected to the fourth end of the comparison unit, and the first end of the constant current source The two terminals are electrically connected to the control terminal of the fourth transistor, and the third terminal of the constant current source is electrically connected to the ground terminal.
- the voltage value of the fixed voltage signal is between 0.85 times the voltage value of the first voltage terminal and 0.9 times the voltage value of the first voltage terminal.
- the present application provides a current limiting circuit, which includes:
- the input terminal of the first transistor is electrically connected to the first voltage terminal, and the output terminal of the first transistor is electrically connected to the second voltage terminal;
- a current limiting module which is electrically connected to the input terminal of the first transistor and the control terminal of the first transistor, and the current limiting module is used to control the control terminal of the first transistor and the control terminal of the first transistor
- the voltage difference between the input terminals controls the state of the first transistor, so that the current limiting value of the current limiting circuit is adjustable
- the current limiting module includes a second transistor, a first resistor, a third transistor and a regulation unit;
- the first end of the second transistor is electrically connected to the first control end, the second end of the second transistor is electrically connected to the input end of the first transistor, and the third end of the second transistor is electrically connected to the first control end.
- the control end of the first transistor is electrically connected; the first end of the first resistor is electrically connected to the input end of the first transistor, and the second end of the first resistor is electrically connected to the input end of the first transistor.
- the control terminal is electrically connected; the first terminal of the third transistor is electrically connected to the second control terminal, the second terminal of the third transistor is electrically connected to the control terminal of the first transistor, and the third transistor is electrically connected to the control terminal.
- the third end of the transistor is connected to the regulating unit; the regulating unit is used to control the state of the first transistor;
- the current limiting circuit further includes a fourth transistor; the input end of the fourth transistor is electrically connected to the first voltage end, and the output end of the fourth transistor is electrically connected to the second voltage end.
- the regulating unit includes a plurality of resistance control subunits arranged in parallel, the first end of the resistance control subunit is electrically connected to the third end of the third transistor, so The second terminal of the resistance control subunit is electrically connected to the ground terminal; each of the resistance control subunits includes a second resistor.
- the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor can be obtained according to the following formula:
- Vgs –V1*R1/(R1+Rx), wherein, Vgs is the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor, and V1 is the voltage of the input terminal of the first transistor voltage value, R1 is the resistance value of the first resistor, and Rx is the resistance value of x resistor control subunits arranged in parallel.
- the current limiting circuit further includes a timing unit, a comparison unit and a constant current unit;
- the timing unit is electrically connected to the first terminal of the comparison unit; the second terminal of the comparison unit is electrically connected to the second voltage terminal, and the third terminal of the comparison unit is connected to a fixed voltage signal,
- the fourth end of the comparison unit is electrically connected to the first end of the constant current unit; the second end of the constant current unit is electrically connected to the control end of the fourth transistor;
- the timing unit is used to output the control signal of the comparison unit at intervals of preset time;
- the voltage of the three terminals, the fourth terminal of the comparison unit outputs the constant current unit control signal to the first terminal of the constant current unit;
- the constant current unit is used to output a constant voltage under the control of the constant current unit control signal current.
- the timing unit includes a timer, and the timer is electrically connected to the first end of the comparison unit.
- the comparison unit includes a comparator; the first terminal of the comparator is electrically connected to the timing unit; the second terminal of the comparator is electrically connected to the second voltage terminal The third end of the comparator is connected to a fixed voltage signal, and the fourth end of the comparator is electrically connected to the first end of the constant current unit.
- the constant current unit includes a constant current source; the first end of the constant current source is electrically connected to the fourth end of the comparison unit, and the first end of the constant current source The two terminals are electrically connected to the control terminal of the fourth transistor, and the third terminal of the constant current source is electrically connected to the ground terminal.
- the voltage value of the fixed voltage signal is between 0.85 times the voltage value of the first voltage terminal and 0.9 times the voltage value of the first voltage terminal.
- the current limiting circuit provided in this application controls the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor through the current limiting module, and controls the state of the first transistor, so that the current limiting value of the current limiting circuit can be adjusted , so as to prevent the power management integrated chip from failing to start after overloading, and to prevent the power management integrated chip from being damaged by short circuit and starting.
- FIG. 1 is a schematic structural diagram of a current limiting circuit provided by an embodiment of the present application
- FIG. 2 is a schematic circuit diagram of a current limiting circuit provided by an embodiment of the present application.
- FIG. 3 is a schematic diagram of the first state of the current limiting circuit provided by the embodiment of the present application.
- FIG. 4 is a schematic diagram of a second state of the current limiting circuit provided by the embodiment of the present application.
- FIG. 5 is another schematic circuit diagram of the current limiting circuit provided by the embodiment of the present application.
- the embodiment of the present application provides a current limiting circuit, which can make the current limiting value of the current limiting circuit adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged when it is turned on by short circuit. Details are given below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
- the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics.
- the transistors used in this embodiment of the present application may include P-type transistors and/or N-type transistors. Wherein, when the gate of the P-type transistor is at a low level, the source and the drain are turned on; when the gate is at a high level, the source and the drain are turned off. For N-type transistors, when the gate is at a high level, the source and drain are turned on; when the gate is at a low level, the source and drain are turned off.
- FIG. 1 is a schematic structural diagram of a current limiting circuit provided by an embodiment of the present application.
- the current limiting circuit 10 provided by the embodiment of the present application includes a first voltage terminal A, a second voltage terminal B, a first transistor T1 and a current limiting module 100 .
- the input end of the first transistor T1 and the output end of the first transistor T1 are connected in series on the line formed by the first voltage end A and the second voltage end B.
- the current limiting module 100 is electrically connected to the input terminal of the first transistor T1 and the control terminal of the first transistor T1.
- the current limiting module 100 is used to control the voltage difference between the control terminal of the first transistor T1 and the input terminal of the first transistor T1, and control the state of the first transistor T1, so that the current limiting value of the current limiting circuit 10 can be adjusted. It can be understood that the first end of the first transistor T1 is one of the source or the drain of the transistor, and the second end of the first transistor T1 is the other of the source or the drain of the transistor. A control terminal of the transistor T1 is the gate of the transistor.
- the first voltage terminal A may be the working voltage input terminal of the power management chip; the second voltage terminal B may be the AVDD voltage output terminal.
- the power management integrated chip will limit the current during the start-up process of the AVDD voltage. The purpose is to slowly open the isolation transistor, and the AVDD voltage will be established smoothly, preventing excessive current from damaging other electronics in the loop. components.
- the current-limiting value of the current-limiting circuit 10 is adjustable.
- the current limiting circuit 10 of the embodiment of the present application can set the current limiting value of the current limiting circuit 10 according to the actual situation, so that the current limiting value of the current limiting circuit 10 can be adjusted, thereby preventing the power management integrated chip from being overloaded. Boot failure, and prevent the power management integrated chip from short-circuiting and booting damage.
- the current limiting module 100 includes a second transistor T2 , a first resistor R1 , a third transistor T3 and a regulating unit 101 .
- the first end of the second transistor T2 is electrically connected to the first control end BB.
- the second end of the second transistor T2 is electrically connected to the input end of the first transistor T1.
- the third end of the second transistor T2 is electrically connected to the control end of the first transistor T1.
- a first end of the first resistor R1 is electrically connected to an input end of the first transistor T1.
- the second end of the first resistor R1 is electrically connected to the control end of the first transistor T1.
- the first end of the third transistor T3 is electrically connected to the second control end AA.
- the second end of the third transistor T3 is electrically connected to the control end of the first transistor T1.
- a third end of the third transistor T3 is connected to the regulating unit 101 .
- the regulating unit 101 is used to control the state of the first transistor T1.
- the regulation unit 101 includes a plurality of resistance control subunits 1011 arranged in parallel.
- the first end of the resistance control subunit 1011 is electrically connected to the third end of the third transistor T3.
- the second terminal of the resistance control subunit 1011 is electrically connected to the ground terminal GND.
- Each resistance control subunit 1011 includes a second resistance R2.
- one resistance control sub-unit 1011 is provided with only one second resistor R2, and other resistance control sub-units 1011 include a second resistance R2 and a switch S, and the second resistance R2 and the switch S are arranged in series.
- V1 is the voltage value of the input terminal of the first transistor T1
- R1 is the resistance value of the first resistor
- Rx is x resistance control subunits 1011 arranged in parallel resistance value.
- both the first transistor T1 and the second transistor T2 are P-type transistors
- the third transistor T3 is an N-type transistor.
- the transistor type in the embodiment of the present application will be taken as an example for the following description.
- FIG. 3 is a schematic diagram of a first state of the current limiting circuit provided by the embodiment of the present application.
- the first transistor T1 when the first transistor T1 is not activated, the voltage of the second control terminal AA is low, and the third transistor T3 is turned off; the potential of the first control terminal BB is low, and the second transistor T2 is turned on.
- FIG. 4 is a schematic diagram of a second state of the current limiting circuit provided by the embodiment of the present application.
- the first transistor T1 when the first transistor T1 is turned on, the voltage of the second control terminal AA is at a high potential, and the third transistor T3 is turned off; the potential of the first control terminal BB is at a high potential, and the second transistor T2 is turned off.
- the potential of node x2 is equal to the potential of the input terminal of the first transistor T1.
- the potential of the control terminal of the first transistor T1 is equal to the potential of the node y2.
- the voltage value of the input terminal of T1 R1 is the resistance value of the first resistor R1
- Rx is the resistance value of x resistors set in series to control the subunit 1011, so the first transistor T1 is turned on, and the turn-on degree is determined by x resistors set in parallel
- the resistance value of the control subunit 1011 is determined.
- the current limiting circuit 10 controls the voltage difference between the control terminal of the first transistor T1 and the input terminal of the first transistor T1 through the current limiting module 100, and controls the state of the first transistor T1, so that the limit
- the current limiting value of the current circuit 10 is adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged when it is turned on by short circuit.
- FIG. 5 is another schematic circuit diagram of the current limiting circuit provided by the embodiment of the present application.
- the difference between the current limiting circuit 20 shown in FIG. 5 and the current limiting circuit 10 shown in FIG. 2 is that the current limiting circuit 20 shown in FIG. 5 also includes: a fourth transistor T4, a timing unit 102, a comparison unit 103 and a constant current Unit 104.
- the input terminal of the fourth transistor T4 is electrically connected with the first voltage terminal A.
- the output terminal of the fourth transistor T4 is electrically connected to the second voltage terminal B.
- the timing unit 102 is electrically connected to the first terminal of the comparison unit 103 .
- the second end of the comparison unit 103 is electrically connected to the second voltage end B.
- the third terminal of the comparison unit 103 is connected to the fixed voltage signal M.
- the fourth end of the comparison unit 103 is electrically connected to the first end of the constant current unit 104 .
- the second end of the constant current unit 104 is electrically connected to the control end of the fourth transistor T4.
- the timing unit 102 is used for outputting the comparison unit control signal at intervals of preset times.
- the comparison unit 103 is used to output the constant current unit control signal to the constant current at the fourth terminal of the comparison unit 103 based on the voltage of the second terminal of the comparison unit 103 and the voltage of the third terminal of the comparison unit 103 under the control of the comparison unit control signal.
- the constant current unit 104 is used to output a constant current under the control of the constant current unit control signal.
- the timing unit 102 is a register for setting the current limiting time. That is, in the embodiment of the present application, the timing unit 102 is configured to output the comparison unit control signal at preset time intervals.
- the constant current unit 104 starts to work; when the first terminal of the constant current unit 104 does not receive the comparison unit control signal, the constant current unit 104 stops working.
- the comparison unit 103 compares two or more data items to determine whether they are equal, or to determine the size relationship and arrangement order between them, which is called comparison.
- a circuit or device that can realize this comparison function is called a comparison unit.
- the function of the comparison unit 103 is to compare the magnitude of the two voltages (using the high or low level of the output voltage to indicate the magnitude relationship between the two input voltages), when the "+" input terminal voltage is higher than the "-” input terminal, the voltage The output of the comparator is high level; when the voltage at the "+” input terminal is lower than the "-” input terminal, the output of the voltage comparator is low level.
- the comparison unit 103 is configured to output the constant current unit control signal to the constant current unit at the fourth terminal of the comparison unit based on the voltage of the second terminal of the comparison unit 103 and the voltage of the third terminal of the comparison unit 104 at the first end.
- the first terminal of the comparison unit 103 is an enabling terminal
- the second terminal of the comparison unit 103 is a “+” input terminal
- the third terminal of the comparison unit 103 is a “-” input terminal
- the second terminal of the comparison unit 103 is an input terminal of “-”.
- the four terminals are output terminals.
- the constant current unit control signal output by the fourth terminal of the comparison unit 103 was a high level;
- the constant current unit control signal output from the fourth terminal of the comparison unit 103 is at low level.
- the constant current unit 104 is a model abstracted from the actual power supply, and its terminal button can always provide a certain current to the outside regardless of the voltage at its two ends.
- the constant current unit 104 has two basic properties: first, the current it provides is a constant value, which has nothing to do with the voltage at both ends; second, the current of the constant current unit 104 itself is determined, while the voltage at both ends is arbitrary . That is, in the embodiment of the present application, the constant current unit 104 is used to output a constant current under the control of the control signal of the constant current unit 104 , and the constant current can be set according to actual needs.
- the timing unit 102 includes a timer.
- the timing unit 102 is electrically connected to the first terminal of the comparison unit 103 .
- the timing unit 102 may be other devices with the same characteristics. That is, the timing unit 102 may be other devices with a timing function.
- the timer outputs a high-level signal at preset time intervals. For example: the timer can set different detection time slots, such as 4 milliseconds, 6 milliseconds, 8 milliseconds or 10 milliseconds.
- the comparing unit 103 includes a comparator.
- the first end of the comparator is electrically connected to the timing unit 102 .
- the second terminal of the comparator is electrically connected with the second voltage terminal B.
- the third terminal of the comparator is connected to the fixed voltage signal M.
- the fourth terminal of the comparator is electrically connected to the first terminal of the constant current unit 104 .
- the first terminal of the comparator is an enable terminal
- the second terminal of the comparator is a "+" input terminal
- the third terminal of the comparator is a "-" input terminal
- the fourth terminal of the comparator is an output terminal.
- the comparator compares the voltage of the second voltage terminal B with the voltage of the fixed voltage signal M. When the voltage of the second voltage terminal B is greater than the voltage of the fixed signal M, the comparator outputs a high level; when the voltage of the second voltage terminal B is lower than the voltage of the fixed signal M, the comparator outputs a low level.
- the voltage value of the fixed voltage signal M is between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
- the voltage value of the fixed voltage signal M can be set to be between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
- a multiplier can be connected in series between the first voltage terminal A and the third terminal of the comparison unit 103, so that the voltage value of the fixed voltage signal M is between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
- the timer is a register for setting the current limit time, and the current setting is 4 milliseconds.
- the level of the control terminal of the second transistor T2 is switched from a high potential to a low potential, and the second transistor T2 conducts is turned on, the first transistor T1 is turned off, the constant current source is turned on, the voltage of the control terminal of the fourth transistor T4 is pulled down, the fourth transistor T4 is turned on, and the external fourth transistor T4 performs the isolation work of the current limiting circuit.
- the first transistor T1 and the current limiting module 100 are both disposed inside the power management chip; the fourth transistor T4, the timing unit 102 , the comparison unit 103 and the constant current unit 104 are disposed outside the power management chip. That is to say, in the embodiment of the present application, the first transistor and the current limiting unit are built into the power management chip, which has good temperature characteristics and high precision, and can ensure the accuracy of the current limiting value under high temperature and low temperature conditions. It can be understood that since the resistance and the Vgs-Id curve of the first transistor do not change much with temperature, the present application has relatively good temperature characteristics, which can be guaranteed at high temperature (85°C) and low temperature (-20°C). Stability of current limit value.
- the current limiting circuit provided by the embodiment of the present application outputs a control signal to the control terminal of the isolation transistor through the current limiting module to control the state of the isolation transistor, so that the current limiting value and current limiting time of the current limiting circuit can be adjusted, thereby preventing the power supply from The management integrated chip fails to restart after overloading, and prevents the power management integrated chip from being damaged by short circuit startup.
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Abstract
Description
Claims (18)
- 一种限流电路,其包括:第一电压端;第二电压端;第一晶体管,所述第一晶体管的输入端与第一电压端电性连接,所述第一晶体管的输出端与所述第二电压端电性连接;以及限流模块,其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接,所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差,控制所述第一晶体管的状态,以使得所述限流电路的限流值可调。
- 根据权利要求1所述的限流电路,其中,所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元;所述第二晶体管的第一端与第一控制端电性连接,所述第二晶体管的第二端与所述第一晶体管的输入端电性连接,所述第二晶体管的第三端与所述第一晶体管的控制端电性连接;所述第一电阻的第一端与所述第一晶体管的输入端电性连接,所述第一电阻的第二端与所述第一晶体管的控制端电性连接;所述第三晶体管的第一端与第二控制端电性连接,所述第三晶体管的第二端与所述第一晶体管的控制端电性连接,所述第三晶体管的第三端与所述调控单元连接;所述调控单元用于控制所述第一晶体管的状态。
- 根据权利要求2所述的限流电路,其中,所述调控单元包括多个并联设置的电阻控制子单元,所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接,所述电阻控制子单元的第二端与接地端电性连接;每个所述电阻控制子单元均包括第二电阻。
- 根据权利要求3所述的限流电路,其中,所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到:Vgs=–V1*R1/(R1+Rx),其中,Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差,V1为所述第一晶体管的输入端的电压值,R1为所述第一电阻的阻值,Rx为x个并联设置的电阻控制子单元的电阻值。
- 根据权利要求1所述的限流电路,其中,所述限流电路还包括第四晶体管;所述第四晶体管的输入端与所述第一电压端电性连接,所述第四晶体管的输出端与所述第二电压端电性连接。
- 根据权利要求5所述的限流电路,其中,所述限流电路还包括定时单元、比较单元以及恒流单元;所述定时单元与所述比较单元的第一端电性连接;所述比较单元的第二端与所述第二电压端电性连接,所述比较单元的第三端接入固定电压信号,所述比较单元的第四端与所述恒流单元的第一端电性连接;所述恒流单元的第二端与所述第四晶体管的控制端电性连接;所述定时单元用于间隔预设时间输出比较单元控制信号;所述比较单元用于在所述比较单元控制信号的控制下,基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压,在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端;所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
- 根据权利要求6所述的限流电路,其中,所述定时单元包括定时器,所述定时器与所述比较单元的第一端电性连接。
- 根据权利要求6所述的限流电路,其中,所述比较单元包括比较器;所述比较器的第一端与定时单元电性连接;所述比较器的第二端与所述第二电压端电性连接,所述比较器的第三端接入固定电压信号,比较器的第四端与所述恒流单元的第一端电性连接。
- 根据权利要求6所述的限流电路,其中,所述恒流单元包括一恒流源;所述恒流源的第一端与所述比较单元的第四端电性连接,所述恒流源的第二端与所述第四晶体管的控制端电性连接,所述恒流源的第三端与接地端电性连接。
- 根据权利要求6所述的限流电路,其中,所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
- 一种限流电路,其包括:第一电压端;第二电压端;第一晶体管,所述第一晶体管的输入端与第一电压端电性连接,所述第一晶体管的输出端与所述第二电压端电性连接;以及限流模块,其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接,所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差,控制所述第一晶体管的状态,以使得所述限流电路的限流值可调;所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元;所述第二晶体管的第一端与第一控制端电性连接,所述第二晶体管的第二端与所述第一晶体管的输入端电性连接,所述第二晶体管的第三端与所述第一晶体管的控制端电性连接;所述第一电阻的第一端与所述第一晶体管的输入端电性连接,所述第一电阻的第二端与所述第一晶体管的控制端电性连接;所述第三晶体管的第一端与第二控制端电性连接,所述第三晶体管的第二端与所述第一晶体管的控制端电性连接,所述第三晶体管的第三端与所述调控单元连接;所述调控单元用于控制所述第一晶体管的状态;所述限流电路还包括第四晶体管;所述第四晶体管的输入端与所述第一电压端电性连接,所述第四晶体管的输出端与所述第二电压端电性连接。
- 根据权利要求11所述的限流电路,其中,所述调控单元包括多个并联设置的电阻控制子单元,所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接,所述电阻控制子单元的第二端与接地端电性连接;每个所述电阻控制子单元均包括第二电阻。
- 根据权利要求12所述的限流电路,其中,所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到:Vgs=–V1*R1/(R1+Rx),其中,Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差,V1为所述第一晶体管的输入端的电压值,R1为所述第一电阻的阻值,Rx为x个并联设置的电阻控制子单元的电阻值。
- 根据权利要求11所述的限流电路,其中,所述限流电路还包括定时单元、比较单元以及恒流单元;所述定时单元与所述比较单元的第一端电性连接;所述比较单元的第二端与所述第二电压端电性连接,所述比较单元的第三端接入固定电压信号,所述比较单元的第四端与所述恒流单元的第一端电性连接;所述恒流单元的第二端与所述第四晶体管的控制端电性连接;所述定时单元用于间隔预设时间输出比较单元控制信号;所述比较单元用于在所述比较单元控制信号的控制下,基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压,在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端;所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
- 根据权利要求14所述的限流电路,其中,所述定时单元包括定时器,所述定时器与所述比较单元的第一端电性连接。
- 根据权利要求14所述的限流电路,其中,所述比较单元包括比较器;所述比较器的第一端与定时单元电性连接;所述比较器的第二端与所述第二电压端电性连接,所述比较器的第三端接入固定电压信号,比较器的第四端与所述恒流单元的第一端电性连接。
- 根据权利要求14所述的限流电路,其中,所述恒流单元包括一恒流源;所述恒流源的第一端与所述比较单元的第四端电性连接,所述恒流源的第二端与所述第四晶体管的控制端电性连接,所述恒流源的第三端与接地端电性连接。
- 根据权利要求14所述的限流电路,其中,所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
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