WO2023000355A1 - 限流电路 - Google Patents

限流电路 Download PDF

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Publication number
WO2023000355A1
WO2023000355A1 PCT/CN2021/108529 CN2021108529W WO2023000355A1 WO 2023000355 A1 WO2023000355 A1 WO 2023000355A1 CN 2021108529 W CN2021108529 W CN 2021108529W WO 2023000355 A1 WO2023000355 A1 WO 2023000355A1
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WO
WIPO (PCT)
Prior art keywords
terminal
transistor
electrically connected
voltage
control
Prior art date
Application number
PCT/CN2021/108529
Other languages
English (en)
French (fr)
Inventor
李浩然
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to KR1020217028992A priority Critical patent/KR102627170B1/ko
Priority to US17/605,024 priority patent/US20240022067A1/en
Priority to JP2021547780A priority patent/JP7434344B2/ja
Priority to EP21810269.7A priority patent/EP4376242A1/en
Publication of WO2023000355A1 publication Critical patent/WO2023000355A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current

Definitions

  • the present application relates to the field of display technology, in particular to a current limiting circuit.
  • the disadvantage of the traditional design is that the current limit value for AVDD is fixed. If the current limit value is too small, it will cause the power management integrated chip to fail to build up the voltage within the specified time due to the current limit due to the heavy load startup; if the current limit value is too large, it will also fail. When the power management integrated chip is short-circuited in the back-end load, the long-term high current will cause damage to components, such as: source driver damage and fire.
  • the present application provides a current-limiting circuit, which can make the current-limiting value of the current-limiting circuit adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged by short-circuit startup.
  • the present application provides a current limiting circuit, which includes:
  • the input terminal of the first transistor is electrically connected to the first voltage terminal, and the output terminal of the first transistor is electrically connected to the second voltage terminal;
  • a current limiting module which is electrically connected to the input terminal of the first transistor and the control terminal of the first transistor, and the current limiting module is used to control the control terminal of the first transistor and the control terminal of the first transistor
  • the voltage difference between the input terminals controls the state of the first transistor, so that the current limiting value of the current limiting circuit is adjustable.
  • the current limiting module includes a second transistor, a first resistor, a third transistor, and a regulation unit;
  • the first end of the second transistor is electrically connected to the first control end, the second end of the second transistor is electrically connected to the input end of the first transistor, and the third end of the second transistor is electrically connected to the first control end.
  • the control end of the first transistor is electrically connected; the first end of the first resistor is electrically connected to the input end of the first transistor, and the second end of the first resistor is electrically connected to the input end of the first transistor.
  • the control terminal is electrically connected; the first terminal of the third transistor is electrically connected to the second control terminal, the second terminal of the third transistor is electrically connected to the control terminal of the first transistor, and the third transistor is electrically connected to the control terminal.
  • the third end of the transistor is connected to the regulating unit; the regulating unit is used to control the state of the first transistor.
  • the regulating unit includes a plurality of resistance control subunits arranged in parallel, the first end of the resistance control subunit is electrically connected to the third end of the third transistor, so The second terminal of the resistance control subunit is electrically connected to the ground terminal; each of the resistance control subunits includes a second resistor.
  • the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor can be obtained according to the following formula:
  • Vgs –V1*R1/(R1+Rx), wherein, Vgs is the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor, and V1 is the voltage of the input terminal of the first transistor voltage value, R1 is the resistance value of the first resistor, and Rx is the resistance value of x resistor control subunits arranged in parallel.
  • the current limiting circuit further includes a fourth transistor; the input end of the fourth transistor is electrically connected to the first voltage end, and the output end of the fourth transistor is connected to the first voltage end.
  • the second voltage end is electrically connected.
  • the current limiting circuit further includes a timing unit, a comparison unit and a constant current unit;
  • the timing unit is electrically connected to the first terminal of the comparison unit; the second terminal of the comparison unit is electrically connected to the second voltage terminal, and the third terminal of the comparison unit is connected to a fixed voltage signal,
  • the fourth end of the comparison unit is electrically connected to the first end of the constant current unit; the second end of the constant current unit is electrically connected to the control end of the fourth transistor;
  • the timing unit is used to output the control signal of the comparison unit at intervals of preset time;
  • the voltage of the three terminals, the fourth terminal of the comparison unit outputs the constant current unit control signal to the first terminal of the constant current unit;
  • the constant current unit is used to output a constant voltage under the control of the constant current unit control signal current.
  • the timing unit includes a timer, and the timer is electrically connected to the first terminal of the comparison unit.
  • the comparison unit includes a comparator; the first terminal of the comparator is electrically connected to the timing unit; the second terminal of the comparator is electrically connected to the second voltage terminal The third end of the comparator is connected to a fixed voltage signal, and the fourth end of the comparator is electrically connected to the first end of the constant current unit.
  • the constant current unit includes a constant current source; the first end of the constant current source is electrically connected to the fourth end of the comparison unit, and the first end of the constant current source The two terminals are electrically connected to the control terminal of the fourth transistor, and the third terminal of the constant current source is electrically connected to the ground terminal.
  • the voltage value of the fixed voltage signal is between 0.85 times the voltage value of the first voltage terminal and 0.9 times the voltage value of the first voltage terminal.
  • the present application provides a current limiting circuit, which includes:
  • the input terminal of the first transistor is electrically connected to the first voltage terminal, and the output terminal of the first transistor is electrically connected to the second voltage terminal;
  • a current limiting module which is electrically connected to the input terminal of the first transistor and the control terminal of the first transistor, and the current limiting module is used to control the control terminal of the first transistor and the control terminal of the first transistor
  • the voltage difference between the input terminals controls the state of the first transistor, so that the current limiting value of the current limiting circuit is adjustable
  • the current limiting module includes a second transistor, a first resistor, a third transistor and a regulation unit;
  • the first end of the second transistor is electrically connected to the first control end, the second end of the second transistor is electrically connected to the input end of the first transistor, and the third end of the second transistor is electrically connected to the first control end.
  • the control end of the first transistor is electrically connected; the first end of the first resistor is electrically connected to the input end of the first transistor, and the second end of the first resistor is electrically connected to the input end of the first transistor.
  • the control terminal is electrically connected; the first terminal of the third transistor is electrically connected to the second control terminal, the second terminal of the third transistor is electrically connected to the control terminal of the first transistor, and the third transistor is electrically connected to the control terminal.
  • the third end of the transistor is connected to the regulating unit; the regulating unit is used to control the state of the first transistor;
  • the current limiting circuit further includes a fourth transistor; the input end of the fourth transistor is electrically connected to the first voltage end, and the output end of the fourth transistor is electrically connected to the second voltage end.
  • the regulating unit includes a plurality of resistance control subunits arranged in parallel, the first end of the resistance control subunit is electrically connected to the third end of the third transistor, so The second terminal of the resistance control subunit is electrically connected to the ground terminal; each of the resistance control subunits includes a second resistor.
  • the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor can be obtained according to the following formula:
  • Vgs –V1*R1/(R1+Rx), wherein, Vgs is the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor, and V1 is the voltage of the input terminal of the first transistor voltage value, R1 is the resistance value of the first resistor, and Rx is the resistance value of x resistor control subunits arranged in parallel.
  • the current limiting circuit further includes a timing unit, a comparison unit and a constant current unit;
  • the timing unit is electrically connected to the first terminal of the comparison unit; the second terminal of the comparison unit is electrically connected to the second voltage terminal, and the third terminal of the comparison unit is connected to a fixed voltage signal,
  • the fourth end of the comparison unit is electrically connected to the first end of the constant current unit; the second end of the constant current unit is electrically connected to the control end of the fourth transistor;
  • the timing unit is used to output the control signal of the comparison unit at intervals of preset time;
  • the voltage of the three terminals, the fourth terminal of the comparison unit outputs the constant current unit control signal to the first terminal of the constant current unit;
  • the constant current unit is used to output a constant voltage under the control of the constant current unit control signal current.
  • the timing unit includes a timer, and the timer is electrically connected to the first end of the comparison unit.
  • the comparison unit includes a comparator; the first terminal of the comparator is electrically connected to the timing unit; the second terminal of the comparator is electrically connected to the second voltage terminal The third end of the comparator is connected to a fixed voltage signal, and the fourth end of the comparator is electrically connected to the first end of the constant current unit.
  • the constant current unit includes a constant current source; the first end of the constant current source is electrically connected to the fourth end of the comparison unit, and the first end of the constant current source The two terminals are electrically connected to the control terminal of the fourth transistor, and the third terminal of the constant current source is electrically connected to the ground terminal.
  • the voltage value of the fixed voltage signal is between 0.85 times the voltage value of the first voltage terminal and 0.9 times the voltage value of the first voltage terminal.
  • the current limiting circuit provided in this application controls the voltage difference between the control terminal of the first transistor and the input terminal of the first transistor through the current limiting module, and controls the state of the first transistor, so that the current limiting value of the current limiting circuit can be adjusted , so as to prevent the power management integrated chip from failing to start after overloading, and to prevent the power management integrated chip from being damaged by short circuit and starting.
  • FIG. 1 is a schematic structural diagram of a current limiting circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic circuit diagram of a current limiting circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the first state of the current limiting circuit provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second state of the current limiting circuit provided by the embodiment of the present application.
  • FIG. 5 is another schematic circuit diagram of the current limiting circuit provided by the embodiment of the present application.
  • the embodiment of the present application provides a current limiting circuit, which can make the current limiting value of the current limiting circuit adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged when it is turned on by short circuit. Details are given below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in this embodiment of the present application may include P-type transistors and/or N-type transistors. Wherein, when the gate of the P-type transistor is at a low level, the source and the drain are turned on; when the gate is at a high level, the source and the drain are turned off. For N-type transistors, when the gate is at a high level, the source and drain are turned on; when the gate is at a low level, the source and drain are turned off.
  • FIG. 1 is a schematic structural diagram of a current limiting circuit provided by an embodiment of the present application.
  • the current limiting circuit 10 provided by the embodiment of the present application includes a first voltage terminal A, a second voltage terminal B, a first transistor T1 and a current limiting module 100 .
  • the input end of the first transistor T1 and the output end of the first transistor T1 are connected in series on the line formed by the first voltage end A and the second voltage end B.
  • the current limiting module 100 is electrically connected to the input terminal of the first transistor T1 and the control terminal of the first transistor T1.
  • the current limiting module 100 is used to control the voltage difference between the control terminal of the first transistor T1 and the input terminal of the first transistor T1, and control the state of the first transistor T1, so that the current limiting value of the current limiting circuit 10 can be adjusted. It can be understood that the first end of the first transistor T1 is one of the source or the drain of the transistor, and the second end of the first transistor T1 is the other of the source or the drain of the transistor. A control terminal of the transistor T1 is the gate of the transistor.
  • the first voltage terminal A may be the working voltage input terminal of the power management chip; the second voltage terminal B may be the AVDD voltage output terminal.
  • the power management integrated chip will limit the current during the start-up process of the AVDD voltage. The purpose is to slowly open the isolation transistor, and the AVDD voltage will be established smoothly, preventing excessive current from damaging other electronics in the loop. components.
  • the current-limiting value of the current-limiting circuit 10 is adjustable.
  • the current limiting circuit 10 of the embodiment of the present application can set the current limiting value of the current limiting circuit 10 according to the actual situation, so that the current limiting value of the current limiting circuit 10 can be adjusted, thereby preventing the power management integrated chip from being overloaded. Boot failure, and prevent the power management integrated chip from short-circuiting and booting damage.
  • the current limiting module 100 includes a second transistor T2 , a first resistor R1 , a third transistor T3 and a regulating unit 101 .
  • the first end of the second transistor T2 is electrically connected to the first control end BB.
  • the second end of the second transistor T2 is electrically connected to the input end of the first transistor T1.
  • the third end of the second transistor T2 is electrically connected to the control end of the first transistor T1.
  • a first end of the first resistor R1 is electrically connected to an input end of the first transistor T1.
  • the second end of the first resistor R1 is electrically connected to the control end of the first transistor T1.
  • the first end of the third transistor T3 is electrically connected to the second control end AA.
  • the second end of the third transistor T3 is electrically connected to the control end of the first transistor T1.
  • a third end of the third transistor T3 is connected to the regulating unit 101 .
  • the regulating unit 101 is used to control the state of the first transistor T1.
  • the regulation unit 101 includes a plurality of resistance control subunits 1011 arranged in parallel.
  • the first end of the resistance control subunit 1011 is electrically connected to the third end of the third transistor T3.
  • the second terminal of the resistance control subunit 1011 is electrically connected to the ground terminal GND.
  • Each resistance control subunit 1011 includes a second resistance R2.
  • one resistance control sub-unit 1011 is provided with only one second resistor R2, and other resistance control sub-units 1011 include a second resistance R2 and a switch S, and the second resistance R2 and the switch S are arranged in series.
  • V1 is the voltage value of the input terminal of the first transistor T1
  • R1 is the resistance value of the first resistor
  • Rx is x resistance control subunits 1011 arranged in parallel resistance value.
  • both the first transistor T1 and the second transistor T2 are P-type transistors
  • the third transistor T3 is an N-type transistor.
  • the transistor type in the embodiment of the present application will be taken as an example for the following description.
  • FIG. 3 is a schematic diagram of a first state of the current limiting circuit provided by the embodiment of the present application.
  • the first transistor T1 when the first transistor T1 is not activated, the voltage of the second control terminal AA is low, and the third transistor T3 is turned off; the potential of the first control terminal BB is low, and the second transistor T2 is turned on.
  • FIG. 4 is a schematic diagram of a second state of the current limiting circuit provided by the embodiment of the present application.
  • the first transistor T1 when the first transistor T1 is turned on, the voltage of the second control terminal AA is at a high potential, and the third transistor T3 is turned off; the potential of the first control terminal BB is at a high potential, and the second transistor T2 is turned off.
  • the potential of node x2 is equal to the potential of the input terminal of the first transistor T1.
  • the potential of the control terminal of the first transistor T1 is equal to the potential of the node y2.
  • the voltage value of the input terminal of T1 R1 is the resistance value of the first resistor R1
  • Rx is the resistance value of x resistors set in series to control the subunit 1011, so the first transistor T1 is turned on, and the turn-on degree is determined by x resistors set in parallel
  • the resistance value of the control subunit 1011 is determined.
  • the current limiting circuit 10 controls the voltage difference between the control terminal of the first transistor T1 and the input terminal of the first transistor T1 through the current limiting module 100, and controls the state of the first transistor T1, so that the limit
  • the current limiting value of the current circuit 10 is adjustable, so as to prevent the power management integrated chip from failing to start when it is overloaded, and to prevent the power management integrated chip from being damaged when it is turned on by short circuit.
  • FIG. 5 is another schematic circuit diagram of the current limiting circuit provided by the embodiment of the present application.
  • the difference between the current limiting circuit 20 shown in FIG. 5 and the current limiting circuit 10 shown in FIG. 2 is that the current limiting circuit 20 shown in FIG. 5 also includes: a fourth transistor T4, a timing unit 102, a comparison unit 103 and a constant current Unit 104.
  • the input terminal of the fourth transistor T4 is electrically connected with the first voltage terminal A.
  • the output terminal of the fourth transistor T4 is electrically connected to the second voltage terminal B.
  • the timing unit 102 is electrically connected to the first terminal of the comparison unit 103 .
  • the second end of the comparison unit 103 is electrically connected to the second voltage end B.
  • the third terminal of the comparison unit 103 is connected to the fixed voltage signal M.
  • the fourth end of the comparison unit 103 is electrically connected to the first end of the constant current unit 104 .
  • the second end of the constant current unit 104 is electrically connected to the control end of the fourth transistor T4.
  • the timing unit 102 is used for outputting the comparison unit control signal at intervals of preset times.
  • the comparison unit 103 is used to output the constant current unit control signal to the constant current at the fourth terminal of the comparison unit 103 based on the voltage of the second terminal of the comparison unit 103 and the voltage of the third terminal of the comparison unit 103 under the control of the comparison unit control signal.
  • the constant current unit 104 is used to output a constant current under the control of the constant current unit control signal.
  • the timing unit 102 is a register for setting the current limiting time. That is, in the embodiment of the present application, the timing unit 102 is configured to output the comparison unit control signal at preset time intervals.
  • the constant current unit 104 starts to work; when the first terminal of the constant current unit 104 does not receive the comparison unit control signal, the constant current unit 104 stops working.
  • the comparison unit 103 compares two or more data items to determine whether they are equal, or to determine the size relationship and arrangement order between them, which is called comparison.
  • a circuit or device that can realize this comparison function is called a comparison unit.
  • the function of the comparison unit 103 is to compare the magnitude of the two voltages (using the high or low level of the output voltage to indicate the magnitude relationship between the two input voltages), when the "+" input terminal voltage is higher than the "-” input terminal, the voltage The output of the comparator is high level; when the voltage at the "+” input terminal is lower than the "-” input terminal, the output of the voltage comparator is low level.
  • the comparison unit 103 is configured to output the constant current unit control signal to the constant current unit at the fourth terminal of the comparison unit based on the voltage of the second terminal of the comparison unit 103 and the voltage of the third terminal of the comparison unit 104 at the first end.
  • the first terminal of the comparison unit 103 is an enabling terminal
  • the second terminal of the comparison unit 103 is a “+” input terminal
  • the third terminal of the comparison unit 103 is a “-” input terminal
  • the second terminal of the comparison unit 103 is an input terminal of “-”.
  • the four terminals are output terminals.
  • the constant current unit control signal output by the fourth terminal of the comparison unit 103 was a high level;
  • the constant current unit control signal output from the fourth terminal of the comparison unit 103 is at low level.
  • the constant current unit 104 is a model abstracted from the actual power supply, and its terminal button can always provide a certain current to the outside regardless of the voltage at its two ends.
  • the constant current unit 104 has two basic properties: first, the current it provides is a constant value, which has nothing to do with the voltage at both ends; second, the current of the constant current unit 104 itself is determined, while the voltage at both ends is arbitrary . That is, in the embodiment of the present application, the constant current unit 104 is used to output a constant current under the control of the control signal of the constant current unit 104 , and the constant current can be set according to actual needs.
  • the timing unit 102 includes a timer.
  • the timing unit 102 is electrically connected to the first terminal of the comparison unit 103 .
  • the timing unit 102 may be other devices with the same characteristics. That is, the timing unit 102 may be other devices with a timing function.
  • the timer outputs a high-level signal at preset time intervals. For example: the timer can set different detection time slots, such as 4 milliseconds, 6 milliseconds, 8 milliseconds or 10 milliseconds.
  • the comparing unit 103 includes a comparator.
  • the first end of the comparator is electrically connected to the timing unit 102 .
  • the second terminal of the comparator is electrically connected with the second voltage terminal B.
  • the third terminal of the comparator is connected to the fixed voltage signal M.
  • the fourth terminal of the comparator is electrically connected to the first terminal of the constant current unit 104 .
  • the first terminal of the comparator is an enable terminal
  • the second terminal of the comparator is a "+" input terminal
  • the third terminal of the comparator is a "-" input terminal
  • the fourth terminal of the comparator is an output terminal.
  • the comparator compares the voltage of the second voltage terminal B with the voltage of the fixed voltage signal M. When the voltage of the second voltage terminal B is greater than the voltage of the fixed signal M, the comparator outputs a high level; when the voltage of the second voltage terminal B is lower than the voltage of the fixed signal M, the comparator outputs a low level.
  • the voltage value of the fixed voltage signal M is between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
  • the voltage value of the fixed voltage signal M can be set to be between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
  • a multiplier can be connected in series between the first voltage terminal A and the third terminal of the comparison unit 103, so that the voltage value of the fixed voltage signal M is between 0.85 times the voltage value of the first voltage terminal A and 0.9 times the voltage value of the first voltage terminal A.
  • the timer is a register for setting the current limit time, and the current setting is 4 milliseconds.
  • the level of the control terminal of the second transistor T2 is switched from a high potential to a low potential, and the second transistor T2 conducts is turned on, the first transistor T1 is turned off, the constant current source is turned on, the voltage of the control terminal of the fourth transistor T4 is pulled down, the fourth transistor T4 is turned on, and the external fourth transistor T4 performs the isolation work of the current limiting circuit.
  • the first transistor T1 and the current limiting module 100 are both disposed inside the power management chip; the fourth transistor T4, the timing unit 102 , the comparison unit 103 and the constant current unit 104 are disposed outside the power management chip. That is to say, in the embodiment of the present application, the first transistor and the current limiting unit are built into the power management chip, which has good temperature characteristics and high precision, and can ensure the accuracy of the current limiting value under high temperature and low temperature conditions. It can be understood that since the resistance and the Vgs-Id curve of the first transistor do not change much with temperature, the present application has relatively good temperature characteristics, which can be guaranteed at high temperature (85°C) and low temperature (-20°C). Stability of current limit value.
  • the current limiting circuit provided by the embodiment of the present application outputs a control signal to the control terminal of the isolation transistor through the current limiting module to control the state of the isolation transistor, so that the current limiting value and current limiting time of the current limiting circuit can be adjusted, thereby preventing the power supply from The management integrated chip fails to restart after overloading, and prevents the power management integrated chip from being damaged by short circuit startup.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

本申请公开的限流电路包括第一电压端；第二电压端；第一晶体管，其输入端与输出端串接在第一电压端与第二电压端形成的线路上；及限流模块，其与第一晶体管的输入端以及隔离晶体管的控制端电性连接，限流模块用于控制第一晶体管的控制端与第一晶体管的输入端之间的压差，控制第一晶体管的状态，以使得限流电路的限流值可调。

Description

限流电路 技术领域
本申请涉及显示技术领域，具体涉及一种限流电路。
 背景技术
在显示面板行业中，传统的电源管理集成芯片会在AVDD电压的启动过程中进行限流的动作，其目的是为了使隔离晶体管缓慢打开，AVDD电压平缓建立，防止出现过大的电流损伤环路中的其他电子元器件。
但是，传统设计的缺点是对于AVDD的限流值是固定不变的。如果这个限流值过小，会导致电源管理集成芯片在重载开机的情况下，由于被限流，导致电压无法在规定时间内建立，从而开机失败；如果这个限流值过大，也会导致电源管理集成芯片在后端负载出现短路时，长时间的大电流导致元器件损坏，比如：源极驱动器损坏起火。
 技术问题
本申请提供一种限流电路，可以使得限流电路的限流值可调，从而可以防止电源管理集成芯片重载开机失败，及防止电源管理集成芯片短路开机损坏。
 技术解决方案
第一方面，本申请提供一种限流电路，其包括：
第一电压端；
第二电压端；
第一晶体管，所述第一晶体管的输入端与第一电压端电性连接，所述第一晶体管的输出端与所述第二电压端电性连接；以及
限流模块，其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接，所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，控制所述第一晶体管的状态，以使得所述限流电路的限流值可调。
在本申请提供的限流电路中，所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元；
所述第二晶体管的第一端与第一控制端电性连接，所述第二晶体管的第二端与所述第一晶体管的输入端电性连接，所述第二晶体管的第三端与所述第一晶体管的控制端电性连接；所述第一电阻的第一端与所述第一晶体管的输入端电性连接，所述第一电阻的第二端与所述第一晶体管的控制端电性连接；所述第三晶体管的第一端与第二控制端电性连接，所述第三晶体管的第二端与所述第一晶体管的控制端电性连接，所述第三晶体管的第三端与所述调控单元连接；所述调控单元用于控制所述第一晶体管的状态。
在本申请提供的限流电路中，所述调控单元包括多个并联设置的电阻控制子单元，所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接，所述电阻控制子单元的第二端与接地端电性连接；每个所述电阻控制子单元均包括第二电阻。
在本申请提供的限流电路中，所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到：
Vgs=–V1*R1/（R1+Rx），其中，Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，V1为所述第一晶体管的输入端的电压值，R1为所述第一电阻的阻值，Rx为x个并联设置的电阻控制子单元的电阻值。
在本申请提供的限流电路中，所述限流电路还包括第四晶体管；所述第四晶体管的输入端与所述第一电压端电性连接，所述第四晶体管的输出端与所述第二电压端电性连接。
在本申请提供的限流电路中，所述限流电路还包括定时单元、比较单元以及恒流单元；
所述定时单元与所述比较单元的第一端电性连接；所述比较单元的第二端与所述第二电压端电性连接，所述比较单元的第三端接入固定电压信号，所述比较单元的第四端与所述恒流单元的第一端电性连接；所述恒流单元的第二端与所述第四晶体管的控制端电性连接；
所述定时单元用于间隔预设时间输出比较单元控制信号；所述比较单元用于在所述比较单元控制信号的控制下，基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压，在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端；所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
在本申请提供的限流电路中，所述定时单元包括定时器，所述定时器与所述比较单元的第一端电性连接。
在本申请提供的限流电路中，所述比较单元包括比较器；所述比较器的第一端与定时单元电性连接；所述比较器的第二端与所述第二电压端电性连接，所述比较器的第三端接入固定电压信号，比较器的第四端与所述恒流单元的第一端电性连接。
在本申请提供的限流电路中，所述恒流单元包括一恒流源；所述恒流源的第一端与所述比较单元的第四端电性连接，所述恒流源的第二端与所述第四晶体管的控制端电性连接，所述恒流源的第三端与接地端电性连接。
在本申请提供的限流电路中，所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
第一方面，本申请提供一种限流电路，其包括：
第一电压端；
第二电压端；
第一晶体管，所述第一晶体管的输入端与第一电压端电性连接，所述第一晶体管的输出端与所述第二电压端电性连接；以及
限流模块，其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接，所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，控制所述第一晶体管的状态，以使得所述限流电路的限流值可调；
所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元；
所述第二晶体管的第一端与第一控制端电性连接，所述第二晶体管的第二端与所述第一晶体管的输入端电性连接，所述第二晶体管的第三端与所述第一晶体管的控制端电性连接；所述第一电阻的第一端与所述第一晶体管的输入端电性连接，所述第一电阻的第二端与所述第一晶体管的控制端电性连接；所述第三晶体管的第一端与第二控制端电性连接，所述第三晶体管的第二端与所述第一晶体管的控制端电性连接，所述第三晶体管的第三端与所述调控单元连接；所述调控单元用于控制所述第一晶体管的状态；
所述限流电路还包括第四晶体管；所述第四晶体管的输入端与所述第一电压端电性连接，所述第四晶体管的输出端与所述第二电压端电性连接。
在本申请提供的限流电路中，所述调控单元包括多个并联设置的电阻控制子单元，所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接，所述电阻控制子单元的第二端与接地端电性连接；每个所述电阻控制子单元均包括第二电阻。
在本申请提供的限流电路中，所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到：
Vgs=–V1*R1/（R1+Rx），其中，Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，V1为所述第一晶体管的输入端的电压值，R1为所述第一电阻的阻值，Rx为x个并联设置的电阻控制子单元的电阻值。
在本申请提供的限流电路中，所述限流电路还包括定时单元、比较单元以及恒流单元；
所述定时单元与所述比较单元的第一端电性连接；所述比较单元的第二端与所述第二电压端电性连接，所述比较单元的第三端接入固定电压信号，所述比较单元的第四端与所述恒流单元的第一端电性连接；所述恒流单元的第二端与所述第四晶体管的控制端电性连接；
所述定时单元用于间隔预设时间输出比较单元控制信号；所述比较单元用于在所述比较单元控制信号的控制下，基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压，在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端；所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
在本申请提供的限流电路中，所述定时单元包括定时器，所述定时器与所述比较单元的第一端电性连接。
在本申请提供的限流电路中，所述比较单元包括比较器；所述比较器的第一端与定时单元电性连接；所述比较器的第二端与所述第二电压端电性连接，所述比较器的第三端接入固定电压信号，比较器的第四端与所述恒流单元的第一端电性连接。
在本申请提供的限流电路中，所述恒流单元包括一恒流源；所述恒流源的第一端与所述比较单元的第四端电性连接，所述恒流源的第二端与所述第四晶体管的控制端电性连接，所述恒流源的第三端与接地端电性连接。
在本申请提供的限流电路中，所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
 有益效果
本申请提供的限流电路，通过限流模块控制第一晶体管的控制端与第一晶体管的输入端之间的压差，控制第一晶体管的状态，以使得限流电路的限流值可调，从而可以防止电源管理集成芯片重载开机失败，以及防止电源管理集成芯片短路开机损坏。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的限流电路的结构示意图；
图2为本申请实施例提供的限流电路的电路示意图；
图3为本申请实施例提供的限流电路的第一状态示意图；
图4为本申请实施例提供的限流电路的第二状态示意图；
图5为本申请实施例提供的限流电路的另一电路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书以及说明书中的术语“第一”、“第二”、“第三”、“第四”等是用于区别不同对象，而不是用于描述特定顺序。
本申请实施例提供一种限流电路，其可以使得限流电路的限流值可调，从而可以防止电源管理集成芯片重载开机失败，以及防止电源管理集成芯片短路开机损坏。下文进行详细说明。需要说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件。
此外，本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种。其中，P型晶体管在栅极为低电平时，源极与漏极导通；在栅极为高电平时，源极与漏极截止。N型晶体管为在栅极为高电平时，源极与漏极导通；在栅极为低电平时，源极与漏极截止。
请参阅图1，图1为本申请实施例提供的限流电路的结构示意图。如图1所示，本申请实施例提供的限流电路10包括第一电压端A、第二电压端B、第一晶体管T1以及限流模块100。第一晶体管T1的输入端与第一晶体管T1的输出端串接在第一电压端A和第二电压端B形成的线路上。限流模块100与第一晶体管T1的输入端以及第一晶体管T1的控制端电性连接。限流模块100用于控制第一晶体管T1的控制端与第一晶体管T1的输入端之间的压差，控制第一晶体管T1的状态，以使得限流电路10的限流值可调。可以理解的，第一晶体管T1的第一端即为晶体管的源极或者漏极中的一者，第一晶体管T1的第二端即为晶体管的源极或者漏极中的另一者，第一晶体管T1的控制端即为晶体管的栅极。
需要说明的是，第一电压端A可以为电源管理芯片的工作电压输入端；第二电压端B可以为AVDD电压输出端。在显示面板行业中，电源管理集成芯片会在AVDD电压的启动过程中进行限流的动作，其目的是为了使隔离晶体管缓慢打开，AVDD电压平缓建立，防止出现过大电流损伤环路的其他电子元器件。
如果限流电路10的限流值过小，会导致电源管理集成芯片在重载开机的情况下，由于被限流，导致电压无法在规定时间内建立，从而开机失败；如果限流电路10的限流值过大，也会导致电源管理集成芯片在后端负载出现短路时，长时间的大电流导致元器件损坏。在本申请实施例中，限流电路10的限流值是可调的。也即，本申请实施例的限流电路10可以根据实际情况对限流电路10的限流值进行设置，可以使得限流电路10的限流值可调，从而可以防止电源管理集成芯片重载开机失败，以及防止电源管理集成芯片短路开机损坏。
其中，请参阅图2，图2为本申请实施例提供的限流电路的电路示意图。如图2所示，限流模块100包括第二晶体管T2、第一电阻R1、第三晶体管T3以及调控单元101。第二晶体管T2的第一端与第一控制端BB电性连接。第二晶体管T2的第二端与第一晶体管T1的输入端电性连接。第二晶体管T2的第三端与第一晶体管T1的控制端电性连接。第一电阻R1的第一端与第一晶体管T1的输入端电性连接。第一电阻R1的第二端与第一晶体管T1的控制端电性连接。第三晶体管T3的第一端与第二控制端AA电性连接。第三晶体管T3的第二端与第一晶体管T1的控制端电性连接。第三晶体管T3的第三端与调控单元101连接。
具体的，调控单元101用于控制第一晶体管T1的状态。调控单元101包括多个并联设置的电阻控制子单元1011。电阻控制子单元1011的第一端与第三晶体管T3的第三端电性连接。电阻控制子单元1011的第二端与接地端GND电性连接。每个电阻控制子单元1011均包括第二电阻R2。其中，一电阻控制子单元1011仅设置有一个第二电阻R2，其余电阻控制子单元1011包括一个第二电阻R2以及一个开关S，第二电阻R2与开关S串联设置。
具体的，第一晶体管T1的控制端与第一晶体管T1的输入端之间的压差可以根据以下公式得到：Vgs=–V1*R1/（R1+Rx），其中，Vgs为第一晶体管T1的控制端与第一晶体管T1的输入端之间的压差，V1为第一晶体管T1的输入端的电压值，R1为第一电阻的阻值，Rx为x个并联设置的电阻控制子单元1011的电阻值。
在本申请实施例中，第一晶体管T1以及第二晶体管T2均为P型晶体管，第三晶体管T3为N型晶体管。下面将以本申请实施例中的晶体管类型为例进行如下说明。
请参阅图3，图3为本申请实施例提供的限流电路的第一状态示意图。如图3所示，第一晶体管T1未启动时，第二控制端AA的电压为低电位，第三晶体管T3关闭；第一控制端BB的电位为低电位，第二晶体管T2开启。此时节点x1和节点y1电位相等，第一晶体管T1的控制端的电位为节点y1处的电位，第一晶体管的输入端的电位为节点x1处的电位，所以Vgs=0，第一晶体管T1未启动。
请参阅图4，图4为本申请实施例提供的限流电路的第二状态示意图。如图4所示，第一晶体管T1启动时，第二控制端AA的电压为高电位，第三晶体管T3关闭；第一控制端BB的电位为高电位，第二晶体管T2关闭。此时节点x2的电位等于第一晶体管T1的输入端的电位，根据电阻分压原理，节点y2的电位可以根据以下公式得到：y2=V1*Rx/（R1+Rx），V1为第一晶体管T1的输入端的电压值，R1为第一电阻R1的阻值，Rx为x个联设置的电阻控制子单元1011的电阻值。第一晶体管T1的控制端的电位等于节点y2的电位。此时，Vgs=y2-x2=–V1*R1/（R1+Rx），其中，Vgs为第一晶体管T1的控制端与第一晶体管T1的输入端之间的压差，V1为第一晶体管T1的输入端的电压值，R1为第一电阻R1的阻值，Rx为x个串联设置的电阻控制子单元1011的电阻值，所以第一晶体管T1开启，且开启程度由x个并联设置的电阻控制子单元1011的电阻值的大小决定。
基于此，本申请提供的限流电路10，通过限流模块100控制第一晶体管T1的控制端与第一晶体管T1的输入端之间的压差，控制第一晶体管T1的状态，以使得限流电路10的限流值可调，从而可以防止电源管理集成芯片重载开机失败，以及防止电源管理集成芯片短路开机损坏。
请参阅图5，图5为本申请实施例提供的限流电路的另一电路示意图。图5所示20的限流电路与图2所示的限流电路10的区别在于：图5所示的限流电路20还包括：第四晶体管T4、定时单元102、比较单元103以及恒流单元104。
其中，第四晶体管T4的输入端与第一电压端A电性连接。第四晶体管T4的输出端与第二电压端B电性连接。定时单元102与比较单元103的第一端电性连接。比较单元103的第二端与第二电压端B电性连接。比较单元103的第三端接入固定电压信号M。比较单元103的第四端与恒流单元104的第一端电性连接。恒流单元104的第二端与第四晶体管T4的控制端电性连接。
其中，定时单元102用于间隔预设时间输出比较单元控制信号。比较单元103用于在比较单元控制信号的控制下，基于比较单元103的第二端的电压以及比较单元103的第三端的电压，在比较单元103的第四端输出恒流单元控制信号至恒流单元104的第一端。恒流单元104用于在恒流单元控制信号的控制下输出恒定电流。
定时单元102为设定限流时间的寄存器。也即，在本申请实施例中，定时单元102用于间隔预设时间输出比较单元控制信号。当恒流单元104的第一端接收到比较单元控制信号时，恒流单元104开始工作；当恒流单元104的第一端未接收到比较单元控制信号时，恒流单元104暂停工作。
其中，比较单元103是对两个或多个数据项进行比较，以确定它们是否相等，或确定它们之间的大小关系及排列顺序称为比较。能够实现这种比较功能的电路或装置称为比较单元。比较单元103的功能为比较两个电压的大小(用输出电压的高或低电平，表示两个输入电压的大小关系)，当”+”输入端电压高于”-”输入端时，电压比较器输出为高电平；当”+”输入端电压低于”-”输入端时，电压比较器输出为低电平。
也即，在本申请实施例中，比较单元103用于基于比较单元103的第二端的电压以及比较单元的第三端的电压，在比较单元的第四端输出恒流单元控制信号至恒流单元104的第一端。
需要说明的是，比较单元103的第一端为使能端，比较单元103的第二端为“+”输入端，比较单元103的第三端为“-”输入端，比较单元103的第四端为输出端。当比较单元103的第一端接收到比较单元控制信号时，比较单元103开始工作；当比较单元103的第一端未接收到比较单元控制信号时，比较单元103暂停工作。当比较单元103的第二端的电压大于比较单元103的第三端的电压时，比较单元103的第四端输出的恒流单元控制信号为高电平；当比较单元103的第二端的电压小于比较单元103的第三端的电压时，比较单元103的第四端输出的恒流单元控制信号为低电平。
其中，恒流单元104是从实际电源抽象出来的一种模型，其端钮总能向外部提供一定的电流而不论其两端的电压为多少。恒流单元104具有两个基本的性质：第一，它提供的电流是定值，其与两端的电压无关；第二，恒流单元104自身电流是确定的，而它两端的电压是任意的。也即，在本申请实施例中，恒流单元104用于在恒流单元104控制信号的控制下输出恒定电流，恒定电流可以根据实际需要设定。
具体的，定时单元102包括定时器。定时单元102与比较单元103的第一端电性连接。需要说明的是，在一些实施例中，定时单元102可以为其他特性相同的器件。也即，定时单元102可以为其他具有定时功能的器件。其中，定时器间隔预设时间输出高电平信号。比如：定时器可以设定不同的侦测时间档位，比如4毫秒、6毫秒、8毫秒或者10毫秒。
具体的，比较单元103包括比较器。比较器的第一端与定时单元102电性连接。比较器的第二端与第二电压端B电性连接。比较器的第三端接入固定电压信号M。比较器的第四端与恒流单元104的第一端电性连接。
其中，比较器的第一端为使能端，比较器的第二端为“+”输入端，比较器的第三端为“-”输入端，比较器的第四端为输出端。当比较器的第一端为高电平时，比较器开始工作；当比较器的第一端为低电平时，比较器暂停工作。当比较器的第二端的电压大于比较器的第三端的电压时，比较器的第四端输出的恒流单元控制信号为高电平；当比较器的第二端的电压小于比较器的第三端的电压时，比较器的第四端输出的恒流单元控制信号为低电平。
其中，比较器是将第二电压端B的电压与固定电压信号M的电压进行比较。当第二电压端B的电压大于固定信号M的电压时，比较器输出高电平；当第二电压端B的电压小于固定信号M的电压时，比较器输出低电平。
其中，固定电压信号M的电压值介于0.85倍的第一电压端A的电压值与0.9倍的第一电压端A的电压值之间。在一些实施例中，可以设定固定电压信号M的电压值介于0.85倍的第一电压端A的电压值与0.9倍的第一电压端A的电压值之间。在另一些实施例中，可以在第一电压端A与比较单元103的第三端之间串联一乘法器，使得固定电压信号M的电压值介于0.85倍的第一电压端A的电压值与0.9倍的第一电压端A的电压值之间。
进一步的，以定时器设定为4毫秒、固定电压信号M设定为0.9倍的第一端的电压为例进行说明。定时器为设定限流时间的寄存器，当前设定为4毫秒。当计时器完成4ms计时后，比较第二电压端B的电压值和0.9倍的第一电压端A的电压，若第二电压端B的电压值小于0.9倍的第一电压端A的电压，则后端负载有异常，此时第二晶体管T2的控制端的电平从高电位切换为低电位，第二晶体管T2导通，第一晶体管T1关闭，恒流源关闭，电源管理集成芯片停止动作。若第二电压端B的电压值大于0.9倍的第一电压端A的电压，则电路功能正常，此时第二晶体管T2的控制端的电平从高电位切换为低电位，第二晶体管T2导通，第一晶体管T1关闭，恒流源开启，下拉第四晶体管T4的控制端的电压，第四晶体管T4开启，由外置的第四晶体管T4进行该限流电路的隔离工作。
在一些实施例中，第一晶体管T1以及限流模块100均设置在电源管理芯片内部；第四晶体管T4、定时单元102、比较单元103以及恒流单元104设置在电源管理芯片外。也即，本申请实施例通过在电源管理芯片内置第一晶体管和限流单元，其温度特性好，精度高，在高温低温的情况下都可以保证限流值的准度。可以理解的，由于电阻和第一晶体管的Vgs-Id曲线随温度变化不大，所以本申请有较为良好的温度特性，在高温(85°C)和低温(-20°C)时都可以保证限流值的稳定。
本申请实施例提供的限流电路，通过限流模块输出控制信号至隔离晶体管的控制端，控制隔离晶体管的状态，以使得限流电路的限流值和限流时间可调，从而可以防止电源管理集成芯片重载开机失败，以及防止电源管理集成芯片短路开机损坏。
以上对本申请实施例所提供的限流电路进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种限流电路，其包括：
    第一电压端；
    第二电压端；
    第一晶体管，所述第一晶体管的输入端与第一电压端电性连接，所述第一晶体管的输出端与所述第二电压端电性连接；以及
    限流模块，其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接，所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，控制所述第一晶体管的状态，以使得所述限流电路的限流值可调。
  2. 根据权利要求1所述的限流电路，其中，所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元；
    所述第二晶体管的第一端与第一控制端电性连接，所述第二晶体管的第二端与所述第一晶体管的输入端电性连接，所述第二晶体管的第三端与所述第一晶体管的控制端电性连接；所述第一电阻的第一端与所述第一晶体管的输入端电性连接，所述第一电阻的第二端与所述第一晶体管的控制端电性连接；所述第三晶体管的第一端与第二控制端电性连接，所述第三晶体管的第二端与所述第一晶体管的控制端电性连接，所述第三晶体管的第三端与所述调控单元连接；所述调控单元用于控制所述第一晶体管的状态。
  3. 根据权利要求2所述的限流电路，其中，所述调控单元包括多个并联设置的电阻控制子单元，所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接，所述电阻控制子单元的第二端与接地端电性连接；每个所述电阻控制子单元均包括第二电阻。
  4. 根据权利要求3所述的限流电路，其中，所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到：
    Vgs=–V1*R1/（R1+Rx），其中，Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，V1为所述第一晶体管的输入端的电压值，R1为所述第一电阻的阻值，Rx为x个并联设置的电阻控制子单元的电阻值。
  5. 根据权利要求1所述的限流电路，其中，所述限流电路还包括第四晶体管；所述第四晶体管的输入端与所述第一电压端电性连接，所述第四晶体管的输出端与所述第二电压端电性连接。
  6. 根据权利要求5所述的限流电路，其中，所述限流电路还包括定时单元、比较单元以及恒流单元；
    所述定时单元与所述比较单元的第一端电性连接；所述比较单元的第二端与所述第二电压端电性连接，所述比较单元的第三端接入固定电压信号，所述比较单元的第四端与所述恒流单元的第一端电性连接；所述恒流单元的第二端与所述第四晶体管的控制端电性连接；
    所述定时单元用于间隔预设时间输出比较单元控制信号；所述比较单元用于在所述比较单元控制信号的控制下，基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压，在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端；所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
  7. 根据权利要求6所述的限流电路，其中，所述定时单元包括定时器，所述定时器与所述比较单元的第一端电性连接。
  8. 根据权利要求6所述的限流电路，其中，所述比较单元包括比较器；所述比较器的第一端与定时单元电性连接；所述比较器的第二端与所述第二电压端电性连接，所述比较器的第三端接入固定电压信号，比较器的第四端与所述恒流单元的第一端电性连接。
  9. 根据权利要求6所述的限流电路，其中，所述恒流单元包括一恒流源；所述恒流源的第一端与所述比较单元的第四端电性连接，所述恒流源的第二端与所述第四晶体管的控制端电性连接，所述恒流源的第三端与接地端电性连接。
  10. 根据权利要求6所述的限流电路，其中，所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
  11. 一种限流电路，其包括：
    第一电压端；
    第二电压端；
    第一晶体管，所述第一晶体管的输入端与第一电压端电性连接，所述第一晶体管的输出端与所述第二电压端电性连接；以及
    限流模块，其与所述第一晶体管的输入端以及所述第一晶体管的控制端电性连接，所述限流模块用于控制所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，控制所述第一晶体管的状态，以使得所述限流电路的限流值可调；
    所述限流模块包括第二晶体管、第一电阻、第三晶体管以及调控单元；
    所述第二晶体管的第一端与第一控制端电性连接，所述第二晶体管的第二端与所述第一晶体管的输入端电性连接，所述第二晶体管的第三端与所述第一晶体管的控制端电性连接；所述第一电阻的第一端与所述第一晶体管的输入端电性连接，所述第一电阻的第二端与所述第一晶体管的控制端电性连接；所述第三晶体管的第一端与第二控制端电性连接，所述第三晶体管的第二端与所述第一晶体管的控制端电性连接，所述第三晶体管的第三端与所述调控单元连接；所述调控单元用于控制所述第一晶体管的状态；
    所述限流电路还包括第四晶体管；所述第四晶体管的输入端与所述第一电压端电性连接，所述第四晶体管的输出端与所述第二电压端电性连接。
  12. 根据权利要求11所述的限流电路，其中，所述调控单元包括多个并联设置的电阻控制子单元，所述电阻控制子单元的第一端与所述第三晶体管的第三端电性连接，所述电阻控制子单元的第二端与接地端电性连接；每个所述电阻控制子单元均包括第二电阻。
  13. 根据权利要求12所述的限流电路，其中，所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差可以根据以下公式得到：
    Vgs=–V1*R1/（R1+Rx），其中，Vgs为所述第一晶体管的控制端与所述第一晶体管的输入端之间的压差，V1为所述第一晶体管的输入端的电压值，R1为所述第一电阻的阻值，Rx为x个并联设置的电阻控制子单元的电阻值。
  14. 根据权利要求11所述的限流电路，其中，所述限流电路还包括定时单元、比较单元以及恒流单元；
    所述定时单元与所述比较单元的第一端电性连接；所述比较单元的第二端与所述第二电压端电性连接，所述比较单元的第三端接入固定电压信号，所述比较单元的第四端与所述恒流单元的第一端电性连接；所述恒流单元的第二端与所述第四晶体管的控制端电性连接；
    所述定时单元用于间隔预设时间输出比较单元控制信号；所述比较单元用于在所述比较单元控制信号的控制下，基于所述比较单元的第二端的电压以及所述比较单元的第三端的电压，在所述比较单元的第四端输出恒流单元控制信号至所述恒流单元的第一端；所述恒流单元用于在所述恒流单元控制信号的控制下输出恒定电流。
  15. 根据权利要求14所述的限流电路，其中，所述定时单元包括定时器，所述定时器与所述比较单元的第一端电性连接。
  16. 根据权利要求14所述的限流电路，其中，所述比较单元包括比较器；所述比较器的第一端与定时单元电性连接；所述比较器的第二端与所述第二电压端电性连接，所述比较器的第三端接入固定电压信号，比较器的第四端与所述恒流单元的第一端电性连接。
  17. 根据权利要求14所述的限流电路，其中，所述恒流单元包括一恒流源；所述恒流源的第一端与所述比较单元的第四端电性连接，所述恒流源的第二端与所述第四晶体管的控制端电性连接，所述恒流源的第三端与接地端电性连接。
  18. 根据权利要求14所述的限流电路，其中，所述固定电压信号的电压值介于0.85倍的第一电压端的电压值与0.9倍的第一电压端的电压值之间。
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