WO2023016335A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023016335A1
WO2023016335A1 PCT/CN2022/110257 CN2022110257W WO2023016335A1 WO 2023016335 A1 WO2023016335 A1 WO 2023016335A1 CN 2022110257 W CN2022110257 W CN 2022110257W WO 2023016335 A1 WO2023016335 A1 WO 2023016335A1
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Prior art keywords
display
connection
base substrate
sub
cathode
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PCT/CN2022/110257
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English (en)
French (fr)
Inventor
黎倩
卢红婷
刘柯志
胡文杰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023016335A1 publication Critical patent/WO2023016335A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of light emitting elements, and a first power line structure.
  • the base substrate includes a display area and a frame area around the display area.
  • a plurality of light-emitting elements are located in the display area, and at least one light-emitting element includes an anode, an organic light-emitting layer, and a cathode arranged in sequence along a direction away from the base substrate.
  • the first power line structure is electrically connected to the cathode and is located in the frame area.
  • the first power line structure has at least one first opening.
  • the cathode includes a frame cathode located in the frame region, the frame cathode having at least one second opening.
  • the orthographic projection of the first power line structure on the base substrate and the orthographic projection of the frame cathode on the base substrate at least partially overlap, and the orthographic projection of at least one first opening on the base substrate and the The second openings at least partially overlap in an orthographic projection of the base substrate.
  • the first power line structure includes a plurality of first repeating units, and the plurality of first repeating units are arranged in an array and connected to each other.
  • the first repeating unit includes: a first body, a first connecting bridge and a second connecting bridge extending from opposite sides of the first body along a first direction, A third connection bridge and a fourth connection bridge are formed extending from opposite sides of the first body in a direction; the first direction intersects the second direction.
  • the length of the first connecting bridge and the second connecting bridge in the first direction is greater than the length in the second direction; the third connecting bridge and the fourth connecting bridge The length in the first direction is smaller than the length in the second direction.
  • the length of the first repeating unit in the first direction is approximately the same as the length in the second direction.
  • the first main body, the first connection bridge, the second connection bridge, the third connection bridge and the fourth connection bridge are directly on the base substrate.
  • the projections are all rectangular.
  • the first connecting bridge and the second connecting bridge are substantially symmetrical about the centerline of the first body in the first direction; the third connecting bridge and the fourth connecting bridge are about The center line of the first body in the second direction is substantially symmetrical.
  • the length of the third connecting bridge in the first direction is determined according to the following formula:
  • L2 [(1-TR/0.71)*(25400/P) 2 -D1*D2-2L1*L3]/(2*L4);
  • TR is the light transmittance required by the frame area
  • P is the resolution of the display substrate
  • D1 is the length of the first body in the second direction
  • D2 is the length of the first body in the second direction.
  • L1 is the length of the first connecting bridge in the second direction
  • L3 is the length of the first connecting bridge in the first direction
  • L4 is the length of the second connecting bridge The length of the three-connection bridge in the second direction.
  • the frame cathode is located on a side of the first power line structure away from the base substrate; the connection area between the frame cathode and the first power line structure is on the base substrate
  • the orthographic projection of is located within the orthographic projection of the first body of the first power line structure on the base substrate.
  • the frame cathode includes: a plurality of second repeating units; and the plurality of second repeating units arranged along the first direction are connected to each other.
  • the orthographic projection of the first repeating unit on the base substrate includes the orthographic projection of the second repeating unit on the base substrate.
  • the second repeating unit includes: a second body, a fifth connecting bridge and a sixth connecting bridge extending from opposite sides of the second body along the first direction.
  • the fifth connecting bridge and the sixth connecting bridge are substantially symmetrical about the centerline of the second repeating unit in the first direction.
  • the orthographic projections of the second body, the fifth connecting bridge and the sixth connecting bridge on the base substrate are all rectangular.
  • the second repeating unit further includes: a seventh connecting bridge and an eighth connecting bridge extending from opposite sides of the second body along the second direction; a plurality of second The repeating units are connected into a network.
  • the cathode further includes: a display cathode located in the display area.
  • the display cathode includes: a plurality of third repeating units arranged in an array.
  • the shape, size and connection relationship of the third repeating unit of the display cathode are substantially the same as the shape, size and connection relationship of the second repeating unit of the frame cathode.
  • the third repeating unit includes: a third body, a ninth connecting bridge and a tenth connecting bridge extending from opposite sides of the third body along the first direction.
  • the display substrate further includes: a plurality of auxiliary electrodes located in the display area.
  • the plurality of auxiliary electrodes are electrically connected to the plurality of third repeating units of display cathodes.
  • the plurality of auxiliary electrodes are electrically connected to the first power line structure in the frame area through a first connection line.
  • the auxiliary electrode includes: a first sub-auxiliary electrode disposed on the same layer as the first power line structure, and a second sub-auxiliary electrode disposed on the same layer as the anode of the light emitting element, the The first sub-auxiliary electrode is electrically connected to the second sub-auxiliary electrode.
  • the third repeating unit is electrically connected to the second sub-auxiliary electrode and the first sub-auxiliary electrode.
  • a plurality of first sub-auxiliary electrode arrays are arranged and connected by fourth and fifth connection lines; a plurality of second sub-auxiliary electrode arrays are arranged.
  • the orthographic projection of the second sub-auxiliary electrode on the base substrate covers the orthographic projection of the first sub-auxiliary electrode on the base substrate.
  • the orthographic projections of the first sub-auxiliary electrode and the second sub-auxiliary electrode on the base substrate are both rectangular.
  • the first connection line extends along the second direction, and the first connection line is electrically connected to the first main body of the first power line structure.
  • a frame cathode is provided on the side of the first connection line away from the base substrate, and the orthographic projection of the first connection line on the base substrate is the same as the orthographic projection of the frame cathode on the base substrate There is an overlap.
  • the frame area includes an upper frame
  • the upper frame is provided with a second power line structure
  • the second power line structure includes a plurality of fourth repeating units arranged in an array.
  • the shape, size and connection relationship of the fourth repeating unit are substantially the same as the shape, size and connection relationship of the first repeating unit of the first power line structure of the upper frame.
  • the orthographic projection of the second repeating unit on the base substrate overlaps with the orthographic projection of the fourth repeating unit on the substrate.
  • the display area is provided with a plurality of power connection blocks; the second power line structure is electrically connected to the power connection blocks of the display area through a second connection line.
  • the second connection line has a straight line part and a bent part, and a plurality of data lines are arranged on the side of the second connection line close to the base substrate, and the positive side of the second connection line on the base substrate The projection does not overlap with the orthographic projection of the plurality of data lines on the base substrate.
  • the orthographic projection of the virtual extension of the straight line portion of the second connection line on the base substrate overlaps with the orthographic projection of the data line on the base substrate.
  • the power connection block includes: a first sub-power connection block and a second sub-power connection block that are stacked and electrically connected to each other, and the first sub-power connection block is on the base substrate
  • the orthographic projection is a strip extending along the second direction, and the orthographic projection of the second sub-power supply connection block on the base substrate includes the orthographic projection of the first sub-power supply connection block on the base substrate.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of the minimum recognition distance of the human eye
  • FIG. 2 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of the pixel circuit shown in FIG. 4;
  • FIG. 6 is a partial schematic diagram of a cathode of at least one embodiment of the present disclosure.
  • FIG. 7 is a partial plan view of a display area of at least one embodiment of the present disclosure.
  • Fig. 8 is a schematic partial cross-sectional view along the O-O' direction in Fig. 7;
  • Fig. 9 is a partial cross-sectional schematic diagram along the R-R ' direction in Fig. 7;
  • FIG. 10 is a partial plan view of a display area after forming a semiconductor layer according to at least one embodiment of the present disclosure
  • FIG. 11 is a schematic partial plan view of a display area after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 12 is a schematic partial plan view of a display area after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 13 is a partial plan view of a display area after forming a third insulating layer according to at least one embodiment of the present disclosure
  • FIG. 14 is a partial plan view of a display area after forming a third conductive layer according to at least one embodiment of the present disclosure
  • FIG. 15 is a schematic partial plan view of a display area after forming a fourth conductive layer according to at least one embodiment of the present disclosure
  • Fig. 16 is a partial schematic diagram of area A1 in Fig. 2;
  • FIG. 17 is a schematic diagram of a fourth conductive layer in FIG. 16;
  • Fig. 18 is a partial schematic diagram of area A2 in Fig. 2;
  • FIG. 19 is a schematic diagram of a fourth conductive layer in FIG. 18;
  • FIG. 20 is a partially enlarged schematic diagram of area S2 in FIG. 17;
  • FIG. 21 is an enlarged schematic view of area S1 in FIG. 16;
  • 22 is a schematic plan view of a first repeating unit and a second repeating unit of at least one embodiment of the present disclosure
  • Figure 23 is a schematic plan view of a first repeating unit of at least one embodiment of the present disclosure.
  • 24 is a schematic plan view of a second repeating unit of at least one embodiment of the present disclosure.
  • Fig. 25 is a partial cross-sectional schematic diagram along the Q-Q' direction in Fig. 21;
  • Fig. 26 is another partial sectional schematic diagram along Q-Q' direction in Fig. 21;
  • 27 is another schematic plan view of the first repeating unit and the second repeating unit of at least one embodiment of the present disclosure.
  • FIG. 28 is another schematic plan view of the frame area of at least one embodiment of the present disclosure.
  • 29 is another schematic plan view of the first repeating unit and the second repeating unit of at least one embodiment of the present disclosure.
  • FIG. 30 is another schematic plan view of the second repeating unit of at least one embodiment of the present disclosure.
  • FIG. 31 is another partial schematic diagram of a cathode according to at least one embodiment of the present disclosure.
  • FIG. 32 is another partial schematic diagram of a cathode according to at least one embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the gate may also be referred to as a control electrode. In cases where transistors with opposite polarities are used, or when the direction of current changes during circuit operation, the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • OLED display panels can meet transparent display requirements.
  • an OLED display panel includes a plurality of light-emitting elements, and each light-emitting element includes: an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.
  • light transmittance is an important parameter.
  • the light transmittance of the cathode material is about 50% to 60%, which will greatly reduce the light transmittance of the transparent display panel.
  • a patterned cathode design is generally adopted, so that the cathode material is only retained in the pixel area, and the cathode material in the transparent area between the pixel areas is removed.
  • the patterned cathode also needs to be lapped with the VSS signal line in the frame area to realize circuit connection.
  • the width represents the length in the vertical direction along the extending direction of the trace.
  • the design width of the VSS signal line in the frame area of the display substrate is relatively large (for example, greater than 200 micrometers), which will affect the transparency of the frame area and cannot realize a fully transparent product.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of light emitting elements and a first power line structure.
  • the base substrate includes a display area and a frame area around the display area.
  • a plurality of light-emitting elements are located in the display area, and at least one light-emitting element includes an anode, an organic light-emitting layer, and a cathode arranged in sequence along a direction away from the base substrate.
  • the first power line structure is electrically connected to the cathode and is located in the frame area.
  • the first power line structure has at least one first opening; the cathode includes a frame cathode located in the frame area, and the frame cathode has at least one second opening.
  • the orthographic projection of the first power line structure on the substrate and the orthographic projection of the frame cathode on the substrate at least partially overlap, and the orthographic projection of at least one first opening on the substrate and the orthographic projection of the second opening on the substrate overlap at least partially.
  • the first power line structure is a VSS signal line, which can continuously provide a low level signal.
  • the display substrate provided in this embodiment can realize the transparency of the first power line structure and the frame cathode by patterning the first power line structure and the frame cathode in the frame area, thereby improving the light transmittance of the frame area. To support the realization of fully transparent display products.
  • the first power line structure includes a plurality of first repeating units, and the plurality of first repeating units are arranged in an array and connected to each other.
  • the plurality of first repeating units of the first power line structure in the frame area of this exemplary embodiment are arranged in a regular pattern.
  • this embodiment does not limit it.
  • the multiple first repeating units of the first power line structure in the frame area may be arranged randomly.
  • the first repeating unit includes: a first body, a first connecting bridge and a second connecting bridge extending from opposite sides of the first body along a first direction, extending from the first connecting bridge along a second direction.
  • the opposite sides of the main body are extended to form a third connecting bridge and a fourth connecting bridge.
  • the first direction intersects with the second direction.
  • the first direction and the second direction are perpendicular to each other.
  • the frame cathode is located on a side of the first power line structure away from the base substrate.
  • the orthographic projection of the connection area between the frame cathode and the first power line structure on the base substrate is located within the orthographic projection of the first body of the first power line structure on the base substrate.
  • this embodiment does not limit it.
  • the frame cathode includes: a plurality of second repeating units. A plurality of second repeating units arranged along the first direction are connected to each other.
  • the orthographic projection of the first repeating unit on the base substrate may include the orthographic projection of the second repeating unit on the base substrate.
  • the size of the first repeating unit of the first power line structure is greater than or equal to the size of the second repeating unit of the frame cathode, which can reduce Small loss of light transmittance.
  • the cathode further includes a display cathode located in the display area. It is shown that the cathode comprises a plurality of third repeating units arranged in an array. The shape, size and connection relationship of the third repeating unit are substantially the same as the shape, size and connection relationship of the second repeating unit of the frame cathode.
  • the cathodes include a display cathode located in the display area and a bezel cathode located in the bezel area.
  • the light transmittance of the display area can be improved by patterning the display cathode in the display area.
  • the display cathode can be a whole-surface structure, that is, a display product that only realizes the transparency of the frame.
  • the display substrate further includes: a plurality of auxiliary electrodes located in the display area.
  • the plurality of auxiliary electrodes are electrically connected to the plurality of third repeating units of the display cathode, and are electrically connected to the first power line structure in the frame area through the first connection line.
  • the electrical connection between the display cathode and the first power line structure can be realized through the auxiliary electrode.
  • the auxiliary electrode may include a first sub-auxiliary electrode and a second sub-auxiliary electrode that are stacked and electrically connected to each other. However, this embodiment does not limit it.
  • the frame area includes an upper frame
  • the upper frame is provided with a second power line structure
  • the second power line structure includes a plurality of fourth repeating units arranged in an array, and the shape, size and The connection relationship is roughly the same as the shape, size and connection relationship of the first repeating unit of the first connection line structure of the upper frame.
  • the orthographic projection of the second repeating unit on the base substrate overlaps with the orthographic projection of the fourth repeating unit on the substrate.
  • the second power line structure may be a VDD signal line, which can continuously provide a high level signal. However, this embodiment does not limit it.
  • the display area is provided with a plurality of power connection blocks.
  • the second power line structure is electrically connected to the power connection block in the display area through the second connection line.
  • the second connecting line has a straight portion and a bent portion.
  • a side of the second connection line close to the base substrate is provided with a plurality of data lines.
  • the orthographic projection of the second connection line on the base substrate does not overlap with the orthographic projection of the plurality of data lines on the base substrate.
  • the orthographic projection of the virtual extension line of the straight line portion of the second connection line on the base substrate overlaps with the orthographic projection of the data line on the base substrate. In this example, through the bending design of the second connection line, it can be staggered with the data line of the adjacent layer to avoid signal interference.
  • FIG. 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate provided in this exemplary embodiment includes: a base substrate.
  • the base substrate includes: a display area AA and a frame area BB around the display area AA.
  • the bezel area BB may include upper, lower, left and right borders of the base substrate.
  • this embodiment does not limit it.
  • the display substrate may have a substantially rectangular shape. As shown in FIG. 2 , the display substrate may include a pair of short sides parallel to each other in the second direction X and a pair of long sides parallel to each other in the first direction Y. That is, the length of the display substrate in the second direction X is smaller than the length in the first direction Y.
  • the second direction X and the first direction Y cross each other, for example, the second direction X is perpendicular to the first direction Y.
  • this embodiment does not limit it.
  • the base substrate may be a closed polygon including linear sides, a circle or an ellipse including curved sides, or a semicircle or semi-ellipse including linear sides and curved sides, or the like.
  • the base substrate has linear sides
  • at least some of the corners of the base substrate may be curved.
  • the base substrate has a rectangular shape
  • a portion where adjacent linear sides meet each other may be replaced with a curved line having a predetermined curvature.
  • the curvature can be set according to the position of the curve. For example, the curvature can be changed depending on where the curve starts, the length of the curve, etc.
  • the display area AA at least includes: a plurality of sub-pixels PX, a plurality of gate lines G and a plurality of data lines D.
  • Multiple gate lines G extend along the second direction X and are arranged sequentially along the first direction Y; multiple data lines D extend along the first direction Y and are sequentially arranged along the second direction X.
  • Orthographic projections of multiple gate lines G and multiple data lines D on the base substrate intersect to form multiple sub-pixel regions, and a sub-pixel PX is arranged in each sub-pixel region.
  • a plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D are configured to supply data voltages to the plurality of sub-pixels PX.
  • the plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G are configured to provide gate control signals to the plurality of sub-pixels PX.
  • this embodiment does not limit it.
  • one pixel unit may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel and a blue sub-pixel.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • the display substrate of this embodiment may be a transparent display substrate. Wherein, there may be light-transmitting regions between adjacent pixel units, so as to realize transparent display. However, this embodiment does not limit it.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • the sub-pixel may include: a pixel circuit and a light emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may have a 3T1C (3 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. Capacitor) structure.
  • the light emitting element can be an OLED device.
  • the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the anode of the light emitting element can be electrically connected with the corresponding pixel circuit.
  • this embodiment does not limit it.
  • the frame area BB is provided with a first power line structure 41 .
  • the lower border of the bezel area BB may include a signal access area.
  • the first power line structure 41 can be arranged around the display area AA in the border area BB, and extend to the signal access area, so as to connect with the driver chip arranged in the signal access area, and receive a low-level signal from the driver chip.
  • this embodiment does not limit it.
  • the first power line structure may extend to the binding area of the lower frame, and be connected to the binding electrode in the binding area, so as to receive a low-level signal from the external control circuit.
  • FIG. 3 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a timing controller 21 , a data driver 22 , a scan driver 23 , an emission driver 24 and a sub-pixel array 25 .
  • the sub-pixel array 35 located in the display area AA may include a plurality of sub-pixels PX arranged regularly.
  • the scan driver 23 is configured to provide scan signals to the sub-pixels along the scan lines;
  • the data driver 22 is configured to provide data voltages to the sub-pixels along the data lines;
  • the emission driver 24 is configured to provide light emission control signals to the sub-pixels along the light emission control lines;
  • the timing controller 21 is configured to control the scan driver 23 , the emission driver 24 and the data driver 22 .
  • the timing controller 21 can provide the gray value and control signal suitable for the specifications of the data driver 22 to the data driver 22; 23 to provide the scan driver 23 with a clock signal, a start signal, etc.;
  • the data driver 22 may generate data voltages to be supplied to the data lines D1 to Dn using grayscale values and control signals received from the timing controller 21 .
  • the data driver 22 may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of sub-pixel rows.
  • the scan driver 23 may generate scan signals to be supplied to the scan lines G1 to Gm by a clock signal, a scan signal, etc. received from the timing controller 21 .
  • the scan driver 23 may sequentially supply scan signals having on-level pulses to the scan lines.
  • the scan driver 23 may include a shift register, and may generate scan signals in a manner of sequentially transmitting a scan start signal provided in the form of a conduction level pulse to a next-stage circuit under the control of a clock signal.
  • the emission driver 24 may generate light emission control signals to be supplied to the light emission control lines E1 to Eo by a clock signal received from the timing controller 21 , an emission stop signal, and the like.
  • the emission driver 24 may sequentially supply a light emission control signal having an off-level pulse to the light emission control line.
  • the emission driver 24 may include a shift register to generate emission signals in such a manner as to sequentially transmit emission stop signals provided in the form of off-level pulses to a next-stage circuit under the control of a clock signal.
  • n, m and o are all natural numbers.
  • the scan driver 23 and the emission driver 24 may be directly disposed on the base substrate.
  • the scan driver 23 and the emission driver 24 may be disposed in bezel areas (eg, left and right bezels) on the left and right sides of the display area AA.
  • the scanning driver 23 and the emitting driver 24 may be located on a side of the first power line structure 41 close to the display area AA.
  • the scan driver 23 and the emission driver 24 may be formed together with the sub-pixel in a process of forming the sub-pixel.
  • this embodiment does not limit the positions or formations of the scan driver 23 and the emission driver 24 .
  • the scan driver 23 and the emission driver 24 may be provided on separate chips or printed circuit boards to be connected to pads or pads formed on the base substrate.
  • the data driver 22 may be disposed on a separate chip or printed circuit board to be connected to the sub-pixels through signal access pins provided in the signal access area of the frame area of the base substrate.
  • the data driver 22 may adopt a chip on glass, a chip on plastic, or a chip on film to form a signal access area and be connected to a signal access pin on the base substrate.
  • the timing controller 21 may be provided separately from the data driver 22 or integrally provided with the data driver 22 . However, this embodiment does not limit it.
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of the pixel circuit shown in FIG. 4 .
  • the pixel circuit of this exemplary embodiment may include: six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and one storage capacitor Cst.
  • the six switch transistors are data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6, first reset transistor T1, and second reset transistor T7.
  • the light emitting element EL includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switch transistors may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • the pixel circuit is connected with the scan line G, the data line D, the first power line PL1, the second power line PL2, the light emission control line E, the initial signal line INIT, the first reset The control line RST1 is electrically connected to the second reset control line RST2.
  • the first power line PL1 is configured to provide a constant first voltage signal VSS to the pixel circuit
  • the second power line PL2 is configured to provide a constant second voltage signal VDD to the pixel circuit
  • the second voltage signal VDD is greater than The first voltage signal VSS.
  • the scan line G is configured to provide a scan signal SCAN to the pixel circuit
  • the data line D is configured to provide a data signal DATA to the pixel circuit
  • the light emission control line E is configured to provide a light emission control signal EM to the pixel circuit
  • the first reset control line RST1 is configured to provide a light emission control signal EM to the pixel circuit.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a second reset signal RESET2 to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line G to be input with the scan signal SCAN.
  • the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row.
  • the second reset control signal line RST2 may be input with a second reset control signal RESET2 different from the scan signal SCAN.
  • the first reset control line RST1 may be connected to the scan line G of the n-1th row of pixel circuits, so as to be input with the scan signal SCAN(n-1), that is, the first reset The control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the drive transistor T3 is electrically connected to the light emitting element EL, and is controlled by signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VSS, and the second voltage signal VDD. Output driving current to drive the light emitting element EL to emit light.
  • the gate of the data writing transistor T4 is electrically connected to the scanning line G, the first pole of the data writing transistor T4 is electrically connected to the data line D, and the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3 .
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan line G, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3 .
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line E, the first electrode of the first light emission control transistor T5 is electrically connected to the second power line PL2, and the second electrode of the first light emission control transistor T5 is electrically connected to the driving transistor T3.
  • the first pole is electrically connected.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line E
  • the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3
  • the second pole of the second light emission control transistor T6 is connected to the light emission control line E.
  • the anode of the element EL is electrically connected.
  • the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL, and is configured to reset the gate of the light-emitting element EL. Anode resets.
  • the gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected to the initial signal line INIT, and the second pole of the first reset transistor T1 is connected to the gate of the drive transistor T3. Pole electrical connection.
  • the gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected to the initial signal line INIT, and the second pole of the second reset transistor T7 is connected to the anode of the light emitting element EL. electrical connection.
  • the first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the second power line PL2.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and the
  • the connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission control transistor T6.
  • the connection point of the element EL is the connection point of the storage capacitor Cst, the first reset transistor T1, the drive transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light emission control transistor T5, the data writing transistor T4 and the
  • the connection point of the drive transistor T3, the third node N3 is the connection point of the drive transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, and the fourth node N4 is the second light emission control transistor T
  • the multiple transistors included in the pixel circuit shown in FIG. 4 are all P-type transistors as an example for description.
  • the working process of the pixel circuit may include: a first stage t1 , a second stage t2 and a third stage t3 .
  • the first stage t1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal to turn on the first reset transistor T1, and the initial signal Vinit provided by the initial signal line INIT is provided to the first node N1.
  • N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scanning signal SCAN provided by the scanning line G is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line E is a high-level signal, so that the data is written into the transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second The second light emitting control transistor T6 and the second reset transistor T7 are turned off.
  • the light emitting element EL does not emit light.
  • the second stage t2 is called a data writing stage or a threshold compensation stage.
  • the scanning signal SCAN provided by the scanning line G is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light-emitting control signal EM provided by the light-emitting control line E are both high-level signals
  • the data line DT outputs Data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line D is provided to the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2 to the second node N2.
  • a node N2 and charge the difference between the data voltage Vdata output by the data line D and the threshold voltage of the driving transistor T3 into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (that is, the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the initial signal Vinit provided by the initial signal line INIT is provided to the anode of the light-emitting element EL, and the anode of the light-emitting element EL is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure light emission.
  • the element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal to turn off the first reset transistor T1.
  • the light emission control signal EM provided by the light emission control signal line E is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.
  • the third stage t3 is called the light-emitting stage.
  • the light emission control signal EM provided by the light emission control signal line E is a low level signal
  • the scan signal SCAN provided by the scan line G and the first reset control signal RESET1 provided by the first reset control line RST1 are high level signals.
  • the light emission control signal EM provided by the light emission control signal line E is a low-level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the second voltage signal VDD output by the second power supply line PL2 passes through the turned on
  • the first light emission control transistor T5, the driving transistor T3 and the second light emission control transistor T6 provide a driving voltage to the anode of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*[(VDD-Vdata)] 2 ;
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first pole of the driving transistor T3
  • Vth is the driving current of the driving transistor T3.
  • Vdata is the data voltage output from the data line D
  • VDD is the second voltage signal output from the second power line PL2.
  • the pixel circuit of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • FIG. 6 is a partial plan view of a cathode of a display substrate according to at least one embodiment of the present disclosure.
  • a plurality of pixel units are arranged in the display area, and one pixel unit may include a first sub-pixel P1 , a second sub-pixel P2 and a third sub-pixel P3 .
  • the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 included in the pixel unit may be arranged in a vertical pattern.
  • the first sub-pixel P1 may be a green sub-pixel
  • the second sub-pixel P2 may be a red sub-pixel
  • the third sub-pixel P3 may be a blue sub-pixel.
  • this embodiment does not limit it.
  • the cathode of the display substrate may include a display cathode 33 located in the display area and a frame cathode located in the frame area.
  • the display cathode 33 may include cathodes of light emitting elements of a plurality of pixel units in the display area.
  • the cathodes of the light-emitting elements of the plurality of pixel units arranged along the first direction Y may have an integral structure.
  • the display cathode and the frame cathode may have an integrated structure.
  • the frame cathode is electrically connected to the first power line structure 41 in the frame area to realize circuit conduction.
  • FIG. 7 is a partial plan view of a display area according to at least one embodiment of the present disclosure.
  • Fig. 8 is a schematic partial cross-sectional view along the O-O' direction in Fig. 7 .
  • Fig. 9 is a schematic partial cross-sectional view along the R-R' direction in Fig. 7 .
  • FIG. 7 illustrates a planar structure of a pixel unit in a display area, wherein a pixel unit may include three sub-pixels, for example, a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3.
  • the pixel circuits of the three sub-pixels are sequentially arranged along the second direction X.
  • the pixel circuit of the first sub-pixel P1 is located between the data lines Di and Di+1, and is electrically connected to the data line Di;
  • the pixel circuit of the second sub-pixel P2 is located between the data lines Di+1 and Di+1 +2, and is electrically connected to the data line Di+1;
  • the pixel circuit of the third sub-pixel P3 is located between the data line Di+2 and the initial signal line INIT, and is electrically connected to the data line Di+2.
  • the anode 31a of the light-emitting element of the first sub-pixel P1, the anode 31b of the light-emitting element of the second sub-pixel P2, and the anode 31c of the light-emitting element of the third sub-pixel P3 may be arranged in a pattern. However, this embodiment does not limit it.
  • the display substrate in a plane perpendicular to the display substrate, may include: a semiconductor layer, a first conductive layer, a second Conductive layer, third conductive layer, fourth conductive layer and anode layer.
  • a first insulating layer 11 is disposed between the semiconductor layer and the first conductive layer
  • a second insulating layer 12 is disposed between the first conductive layer and the second conductive layer
  • the second conductive layer and the third conductive layer A third insulating layer 13 is arranged between them
  • a fourth insulating layer 14 is arranged between the third conductive layer and the fourth conductive layer
  • a fifth insulating layer 15 is arranged between the fourth conductive layer and the anode layer.
  • the first insulating layer 11 to the fourth insulating layer 14 may be inorganic insulating layers
  • the fifth insulating layer 15 may be an organic insulating layer.
  • a pixel definition layer, an organic light emitting layer, a cathode and an encapsulation layer are further disposed on the side of the anode layer away from the base substrate 10 .
  • FIG. 10 is a schematic partial plan view of a display region after forming a semiconductor layer according to at least one embodiment of the present disclosure.
  • FIG. 11 is a partial plan view of a display area after forming a first conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 12 is a partial plan view of a display area after forming a second conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic partial plan view of a display area after forming a third insulating layer according to at least one embodiment of the present disclosure.
  • FIG. 14 is a partial plan view of a display area after forming a third conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 15 is a partial plan view of a display area after forming a fourth conductive layer according to at least one embodiment of the present disclosure.
  • the following mainly takes the planar structure of a pixel circuit of a sub-pixel as an example for illustration.
  • the semiconductor layer of the display region may include: active layers of multiple transistors of multiple pixel circuits, for example, the first active layer T10 of the first reset transistor T1, The second active layer T20 of the threshold compensation transistor T2, the third active layer T30 of the drive transistor T3, the fourth active layer T40 of the data writing transistor T4, the fifth active layer T50 of the first light emission control transistor T5, The sixth active layer T60 of the second light emission control transistor T6, and the seventh active layer T70 of the second reset transistor T7.
  • the first active layer T10 to the seventh active layer T70 of a pixel circuit may be an integral structure connected to each other.
  • the material of the semiconductor layer may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • a plurality of doped regions may be on both sides of the channel region, and be doped with impurities and thus have conductivity. Impurities can vary depending on the type of transistor.
  • a doped region of an active layer may be interpreted as a source or drain electrode of a transistor.
  • the portion of the active layer between the transistors can be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors.
  • the first conductive layer of the display area may include: scan lines G, light emission control lines E, first reset control lines RST1, second reset control lines RST2, and pixel circuits
  • the gates of multiple transistors for example, the gate T13 of the first reset transistor T1, the gate T23 of the threshold compensation transistor T2, the gate T33 of the driving transistor T3, the gate T43 of the data writing transistor T4, the first light emitting transistor
  • the scan line G, the light emission control line E, the first reset control line RST1 and the second reset control line RST2 all extend along the second direction X; in the first direction Y, the first reset control line RST1, the scan line G, the light emission control line
  • the line E and the second reset control line RST2 are arranged in sequence.
  • the first electrode Cst-1 of the storage capacitor Cst and the gate T33 of the driving transistor T3 may have an integrated structure.
  • the scan line G, the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 may be of an integral structure.
  • the light emission control line E, the gate T53 of the first light emission control transistor T5 , and the gate T63 of the second light emission control transistor T6 may have an integrated structure.
  • the first reset control line RST1 and the gate T13 of the first reset transistor T1 may have an integrated structure.
  • the second reset control line RST2 and the gate T73 of the second reset transistor T7 may have an integral structure.
  • this embodiment does not limit it.
  • the second conductive layer of the display area may include: the second electrode Cst-2 of the storage capacitor Cst of the pixel circuit, the first initial connection line 51 and the second initial connection line 52.
  • the second electrode Cst- 2 of the storage capacitor Cst of the adjacent pixel circuit may have an integral structure.
  • the orthographic projection of the second electrode Cst- 2 of the storage capacitor Cst on the substrate is located between the orthographic projections of the scan line G and the light emission control line E on the substrate. There is an overlapping area between the orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate and the orthographic projection of the first electrode Cst-1 on the substrate.
  • the second electrode Cst-2 is provided with an opening OP, the opening OP exposes the second insulating layer covering the first electrode Cst-1, and the orthographic projection of the first electrode Cst-1 on the substrate includes the opening OP on the substrate Orthographic projection on a substrate.
  • the opening OP is configured to accommodate the subsequently formed second via hole H1, and the second via hole H1 is located in the opening OP and exposes the first electrode Cst-1, so that the second via hole H1 of the subsequently formed first reset transistor T1
  • the diode is electrically connected to the first electrode Cst-1. Both the first initial connection line 51 and the second initial connection line 52 extend along the second direction X.
  • the first initial connection line 51 is located on the side of the first reset control line RST1 away from the scan line G, and the second initial connection line 52 is located on the side of the second reset control line RST2 away from the light emission control line E.
  • this embodiment does not limit it.
  • a plurality of via holes are opened on the third insulating layer 13 of the display area, which may include, for example: a plurality of first via holes V1 to V5, a second via hole H1, and a plurality of third via holes K1 to K6.
  • the third insulating layer 13 in the plurality of first via holes V1 to V5 is etched away, exposing the surface of the second conductive layer; the third insulating layer 13 and the second insulating layer 12 in the second via hole H1 are etched etched away, the exposed surface of the first conductive layer; the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11 in the plurality of third via holes K1 to K6 are etched away, exposing the semiconductor layer s surface.
  • the third conductive layer of the display area may include: a plurality of data lines (for example, data lines Di, Di+1, and Di+2), initial signal lines INIT,
  • the first sub-power supply connection blocks for example, the first sub-power supply connection blocks 61, 62 and 63), the third connection line 64, and the first pole and the second pole of a plurality of transistors of the pixel circuit (for example, the first reset transistor
  • a plurality of data lines and initial signal lines INIT extend along the first direction Y and are arranged sequentially along the second direction X.
  • the first electrode T11 of the first reset transistor T1 is electrically connected to the first doped region of the first active layer T10 through the third via hole K1, and It is electrically connected to the first initial connection line 51 through the third via hole V1.
  • the second electrode T12 of the first reset transistor T1 is electrically connected to the second doped region of the first active layer T10 through the third via hole K2, and is also connected to the first electrode Cst-1 of the storage capacitor Cst through the second via hole H1. electrical connection.
  • the first electrode T41 of the data writing transistor T4 is electrically connected to the first doped region of the fourth active layer T40 through the third via hole K3.
  • the first pole T41 of the data writing transistor T4 and the data line Di may be integrally structured.
  • the first electrode T51 of the first light emission control transistor T5 is electrically connected to the first doped region of the fifth active layer T50 through the third via hole K4.
  • the second electrode T62 of the second light emission control transistor T6 is electrically connected to the second doped region of the sixth active layer T60 through the third via hole K5.
  • the first electrode T71 of the second reset transistor T7 is electrically connected to the first doped region of the seventh active layer T70 through the third via hole K6, and is also electrically connected to the second initial connection line 52 through the first via hole V4.
  • the initial signal line INIT is electrically connected to the first initial connection line 51 through the first via hole V2 , and is electrically connected to the second initial connection line 52 through the first via hole V5 .
  • the electrical connection between the initial signal line INIT and the plurality of pixel circuits is realized through the first initial connection line 51 and the second initial connection line 52 .
  • the first sub-power supply connection block 61 may pass through a plurality of first via holes V3 (for example, three first via holes arranged along the first direction Y ) is electrically connected to the second electrode Cst-2 of the storage capacitor Cst.
  • the first pole T51 of the first light emission control transistor T5 and the first sub-power supply connection block 61 may have an integral structure.
  • the first sub-power supply connection blocks 62 and 63 may be electrically connected to the second electrodes of the corresponding storage capacitors.
  • the first sub-power supply connection blocks 61 , 62 and 63 are independent of each other, and the first sub-power supply connection block 62 and the third connection line 64 may be integrally structured.
  • the third connection line 64 may extend along the first direction Y. Referring to FIG.
  • the third connection line 64 is configured to realize the electrical connection between the first sub-power supply connection blocks of adjacent pixel units.
  • the fourth conductive layer of the display area may include: a second sub-power supply connection block 65, a plurality of connection electrodes (for example, connection electrodes 66, 67 and 68), a first The sub-auxiliary electrode 420 , the fourth connection line 421 and the fifth connection line 422 .
  • the connection electrode 66 may be electrically connected to the second pole T62 of the second light emission control transistor T6 of a pixel circuit through the fourth via hole F2.
  • connection electrode 67 can be electrically connected to the second pole of the second light emission control transistor of another pixel circuit through the fourth via hole F3, and the connection electrode 68 can be connected to the second light emission control transistor of the third pixel circuit through the fourth via hole F4.
  • the second pole is electrically connected.
  • the second sub-power supply connection block 65 may be electrically connected to the first sub-power supply connection blocks 61 , 62 and 63 through a plurality of fourth via holes F1 .
  • the orthographic projection of the second sub-power supply connection block 65 on the base substrate overlaps with the orthographic projections of the three first sub-power supply connection blocks 61 , 62 and 63 on the substrate substrate.
  • the power connection block of the display area corresponds to one pixel unit.
  • the power connection block may include a second sub-power connection block and three first sub-power connection blocks electrically connected to the second sub-power connection block.
  • the electrical connection between adjacent power supply connection blocks can be realized through the third connection line 64 to transmit the second voltage signal VDD.
  • the second voltage signal VDD can be transmitted through the third connection line 64 and the second electrode Cst- 2 of the storage capacitor Cst.
  • the third connection line 64 can be electrically connected to the second connection line in the frame area, so as to realize the electrical connection with the second power line structure in the frame area.
  • the fourth connection line 421 extends along the second direction X
  • the fifth connection line 422 extends along the first direction Y.
  • the orthographic projection of the first sub-auxiliary electrode 420 on the base substrate may be a rectangle.
  • the first sub-auxiliary electrode 420 , the fourth connection line 421 and the fifth connection line 422 may have an integrated structure.
  • the fifth connection line 422 electrically connects the adjacent first sub-auxiliary electrodes 420 in the first direction Y
  • the fourth connection line 421 electrically connects the adjacent first sub-auxiliary electrodes 420 in the second direction X. .
  • the fifth connection line 422 may extend to the frame area in the first direction Y, and the fourth connection line 421 may be electrically connected to the first connection line in the frame area, so as to realize the connection between the first sub-auxiliary electrode 420 and the frame area.
  • the anode layer of the display region may include: anodes of light emitting elements of a plurality of sub-pixels (for example, anodes 31 a , 31 b and 31 c ), and a second sub-auxiliary electrode 423 .
  • the anode 31a may be electrically connected to the connection electrode 66 through the fifth via hole F5
  • the anode 31b may be electrically connected to the connection electrode 67 through the fifth via hole F6
  • the anode 31c may be electrically connected to the connection electrode 68 through the fifth via hole F7. electrical connection.
  • the second sub-auxiliary electrode 423 may be electrically connected to the first sub-auxiliary electrode 420 through the fifth via hole F8.
  • the orthographic projection of the second sub-auxiliary electrode 423 on the base substrate may be a rectangle.
  • the orthographic projection of the second sub-auxiliary electrode 423 on the base substrate may include the orthographic projection of the first sub-auxiliary electrode 420 on the base substrate.
  • the auxiliary electrode may be formed by electrically connecting the stacked first sub-auxiliary electrode 420 and the second sub-auxiliary electrode 423 .
  • the auxiliary electrode provided by the double-layer electrode can reduce the resistance and improve the signal transmission effect.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can use metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu /Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) Or more, can be a single layer, multi-layer or composite layer.
  • the fifth insulating layer 15 can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment does not limit it.
  • the light emitting element of the sub-pixel may include: an anode, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the pixel definition layer has a pixel opening exposing the anode, and the organic light emitting layer is formed in the pixel opening.
  • the organic light-emitting layer of the light-emitting element is connected to the anode, and the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode.
  • An encapsulation layer may be provided on the side of the cathode away from the base substrate.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may use inorganic materials, the second encapsulation layer may use organic materials, and the second encapsulation layer is set Between the first encapsulation layer and the third encapsulation layer, it can be ensured that external water vapor cannot enter the light-emitting element.
  • the organic light-emitting layer may include a stacked hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), an electron blocking layer (EBL, Electron Block Layer) , Emitting Layer (EML, Emitting Layer), Hole Blocking Layer (HBL, Hole Block Layer), Electron Transport Layer (ETL, Electron Transport Layer) and Electron Injection Layer (EIL, Electron Injection Layer).
  • HIL Hole Injection Layer
  • HTL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Emitting Layer
  • HBL Hole Blocking Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together
  • all sub-pixels The hole blocking layer can be a common layer connected together, and the light emitting layer and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.
  • this embodiment does not limit it.
  • organic materials such as polyimide, acrylic or polyethylene terephthalate may be used for the pixel definition layer.
  • the anode of the light-emitting element can use reflective materials such as metal, and the cathode can use semi-transparent and semi-reflective materials. However, this embodiment does not limit it.
  • the anode of the light-emitting element can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the cathode can be made of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu ) and lithium (Li), or an alloy made of any one or more of the above metals.
  • the cathodes of the display substrate may include a bezel cathode located in the bezel area BB and a display cathode located in the display area AA.
  • the frame cathode and the display cathode are of the same layer structure.
  • FIG. 16 is a partial schematic diagram of area A1 in FIG. 2 .
  • FIG. 17 is a schematic diagram of the fourth conductive layer in FIG. 16 .
  • FIG. 18 is a partial schematic diagram of area A2 in FIG. 2 .
  • FIG. 19 is a schematic diagram of the third conductive layer in FIG. 18 .
  • FIG. 16 and FIG. 18 schematically illustrate the planar structure of the fourth conductive layer and the cathode of the display substrate.
  • FIG. 20 is a partially enlarged schematic diagram of area S2 in FIG. 17 .
  • the first power line structure 41 in the frame region BB has a plurality of first openings
  • the frame cathode 34 in the frame region BB has a plurality of second openings.
  • the first power line structure 41 may include a plurality of first repeating units arranged in an array and connected to each other. A plurality of first repeating units are connected to form a network, so that the first power line structure 41 has a plurality of first openings.
  • the frame cathode 34 may include a plurality of second repeating units arranged in an array and connected to each other along the first direction Y. The plurality of second repeating units arranged along the second direction X are not connected to each other.
  • Multiple second repeating units can be connected to form multiple columns, so that the frame cathode 34 has multiple second openings.
  • the light transmittance of the frame area BB can be improved by patterning the first power line structure 41 and the frame cathode 34 in the frame area BB.
  • the total width of the first power line structure 41 is not limited.
  • the display cathode 33 of the display area AA may include a plurality of third repeating units.
  • a plurality of third repeating units arranged along the first direction Y may be connected to each other.
  • the plurality of third repeating units arranged along the second direction X are not connected to each other.
  • the plurality of second repeating units arranged along the first direction Y are connected to each other, and connected to the plurality of third repeating units arranged along the first direction Y in the display area AA.
  • the second repeating unit of the bezel cathode 34 is not connected to the third repeating unit of the display area AA.
  • the shape, size and connection relationship of the third repeating unit of display cathode 33 are substantially the same as the shape, size and connection relationship of the second repeating unit of frame cathode 34 .
  • this embodiment does not limit it.
  • the shape of the third repeating unit of the display cathode may be different than the shape of the second repeating unit of the bezel cathode.
  • the cathode can be a monolithic structure without openings.
  • the orthographic projection of the third repeating unit of the display cathode 33 in the display area AA on the base substrate can cover one pixel unit and one auxiliary electrode on the substrate. Orthographic projection on the substrate substrate.
  • this embodiment does not limit it.
  • the upper frame of the frame area BB is further provided with a second power line structure 71 .
  • the second power line structure 71 is located on a side of the first power line structure 41 close to the display area AA.
  • the second power line structure 71 and the first power line structure 41 may be the same layer structure.
  • the second power line structure 71 can be electrically connected to the power connection block of the display area AA through the second connection line 72 .
  • the second connection line 72 may be electrically connected to the third connection line 64 in the display area AA.
  • the second connecting wire 72 is located on a side of the third connecting wire 64 away from the base substrate.
  • the third connection line 64 is located on the third conductive layer, and the second connection line 72 is located on the fourth conductive layer.
  • the fifth connection line 422 electrically connected to the first sub-auxiliary electrode 420 may extend along the first direction Y to a position in the upper frame close to the second power line structure 71 .
  • the fifth connection line 422 is not electrically connected to the second power line structure 71 .
  • the second power line structure 71 may include a plurality of fourth repeating units arranged in an array and connected to each other.
  • the shape, size and connection relationship of the fourth repeating unit of the second power line structure 71 may be substantially the same as the shape, size and connection relationship of the first repeating unit of the first power line structure 41 .
  • the orthographic projection of the second repeating unit on the substrate overlaps with the orthographic projection of the fourth repeating unit on the substrate.
  • this embodiment does not limit it.
  • the shape of the fourth repeating unit of the second power line structure 71 may be different from the shape of the first repeating unit of the first power line structure 41 .
  • the second power line structure 71 of the frame area BB may adopt a patterned design, so as to further improve the light transmittance of the frame area BB.
  • the second connection line 72 and the fifth connection line 422 are located on the fourth conductive layer.
  • a plurality of data lines (for example, data lines Di, Di+1 and Di+2) are located on the third conductive layer.
  • the second connection line 72 has a straight portion and a bent portion. In the frame area, the second connection line 72 is located on one side of the fifth connection line 422 in the second direction X.
  • the orthographic projection of the second connection line 72 on the base substrate does not overlap with the orthographic projection of the plurality of data lines on the base substrate.
  • the orthographic projection of the second connection line 72 on the base substrate may be located between the orthographic projections of the data line Di+1 and the data line Di+2 on the base substrate.
  • the orthographic projection of the virtual extension of the straight line portion of the second connection line 72 on the base substrate overlaps with the orthographic projection of the data line on the base substrate.
  • the second connection line 72 includes a first straight line portion, a bent portion and a second straight line portion connected in sequence; the orthographic projection of the virtual extension line of the first straight line portion on the base substrate is the same as the data line Di+2 at The orthographic projection on the base substrate overlaps, and the orthographic projection of the virtual extension line of the second straight line portion on the base substrate overlaps with the orthographic projection of the data line Di+1 on the base substrate.
  • setting the second connection line to be staggered from the data lines of the adjacent layer can avoid signal interference.
  • a plurality of first connection lines 43 are provided in the frame area BB (for example, the left frame).
  • a plurality of first connection lines 43 may extend along the second direction X and be arranged along the first direction Y.
  • the first power line structure 41 in the frame area BB can be electrically connected to the auxiliary electrode in the display area AA through the first connection line 43 .
  • the first power line structure 41 , the first sub-auxiliary electrode 420 of the auxiliary electrode, the first connection line 43 and the fourth connection line 421 may be of an integral structure.
  • the first connection line 43 in the frame area BB is electrically connected to the fourth connection line 421 in the display area AA, so as to realize the electrical connection between the first power line structure 41 and the first sub-auxiliary electrode 420 .
  • the first sub-auxiliary electrode 420 can be electrically connected to the display cathode 33 through the second sub-auxiliary electrode 423 , so as to realize the electrical connection between the first power line structure 41 and the display cathode 33 .
  • the orthographic projection of the frame cathode 34 on the base substrate overlaps with the orthographic projection of the first connection line 43 on the base substrate.
  • this embodiment does not limit it. In some exemplary embodiments, as shown in FIG.
  • the frame cathode 34 of the left frame there may be no electrical connection between the frame cathode 34 of the left frame and the display cathode 33 of the display area AA.
  • the resistance of the first power line structure 41 can be reduced by electrically connecting the frame cathodes 34 of the left and right frames to the first power line structure 41 .
  • this embodiment does not limit it.
  • the plurality of first sub-auxiliary electrodes 420 in the display area may be arranged in an array and electrically connected through the fourth connection line 421 and the fifth connection line 422 .
  • a plurality of second sub-auxiliary electrodes 423 in the display area may be arranged in an array and be independent from each other.
  • this embodiment does not limit it.
  • the plurality of second sub-auxiliary electrodes in the display area may be electrically connected through a sixth connection line extending along the first direction and a seventh connection line extending along the second direction.
  • the first power line structure 41 can be directly electrically connected to the display cathode 33 of the display area AA through the frame cathode 34 of the upper and lower frames, and can also be connected to the display area AA through the first connection line 43 of the left and right frames.
  • the auxiliary electrodes are electrically connected, and then electrically connected to the display cathode 33 through the auxiliary electrodes, so as to realize a circuit path between the first power line structure 41 and the display cathode 33 .
  • this embodiment does not limit it.
  • the first power line structure 41 on the base substrate may include an orthographic projection of the bezel cathode 34 on the substrate substrate. In this way, the loss of light transmittance in the frame area can be reduced.
  • FIG. 21 is an enlarged schematic view of area S1 in FIG. 16 .
  • 22 is a schematic plan view of a first repeating unit and a second repeating unit of at least one embodiment of the present disclosure.
  • 23 is a schematic plan view of a first repeating unit of at least one embodiment of the present disclosure.
  • Figure 24 is a schematic plan view of a second repeating unit of at least one embodiment of the present disclosure.
  • the orthographic projection of the first repeating unit 411 of the first power line structure 41 on the base substrate may include the second repeating unit 341 of the frame cathode 34 on the substrate. Orthographic projection on the base substrate.
  • the first repeating unit 411 of the first power line structure 41 may include: a first body 4110 formed by extending from opposite sides of the first body 4110 along the first direction Y;
  • the first connecting bridge 4111 and the second connecting bridge 4112 are formed, and the third connecting bridge 4113 and the fourth connecting bridge 4114 are formed extending from opposite sides of the first body 4110 along the second direction X.
  • the orthographic projection of the first body 4110 on the base substrate may be a rectangle, such as a square. Orthographic projections of the first connection bridge 4111 and the second connection bridge 4112 on the base substrate may be rectangular.
  • the length of the first connection bridge 4111 and the second connection bridge 4112 in the first direction Y may be greater than the length in the second direction X.
  • Orthographic projections of the third connection bridge 4113 and the fourth connection bridge 4114 on the base substrate may be rectangular.
  • the length of the third connection bridge 4113 and the fourth connection bridge 4114 in the first direction Y may be smaller than the length in the second direction X.
  • this embodiment does not limit it.
  • the orthographic projection of the first body on the base substrate may be in other shapes such as a circle or an ellipse.
  • the orthographic projections of the first connection bridge, the second connection bridge, the third connection bridge and the fourth connection bridge on the base substrate may be other shapes such as a wavy line shape.
  • the shapes of the orthographic projections of the first body, the first connection bridge, the second connection bridge, the third connection bridge and the fourth connection bridge on the base substrate may be the same or partially the same or all different.
  • the first connecting bridge 4111 and the second connecting bridge 4112 of the first repeating unit 411 may be connected to the adjacent first repeating unit in the first direction Y, and the third The connecting bridge 4113 and the fourth connecting bridge 4114 may be connected with adjacent first repeating units in the second direction X.
  • the first connecting bridge 4111 and the second connecting bridge 4112 of the first repeating unit 411 may be approximately Symmetrically, the third connecting bridge 4113 and the fourth connecting bridge 4114 may be substantially symmetrical about the second centerline OX of the first body 4110 in the second direction X.
  • the first repeating unit 411 may be symmetrical about the first central line OY, and may also be symmetrical about the second central line OX.
  • this embodiment does not limit it.
  • the second repeating unit 341 includes: a second main body 3410 , fifth connecting bridges 3411 extending from opposite sides of the second main body 3410 along the first direction Y, and a fifth connecting bridge 3411 .
  • the orthographic projection of the second body 3410 on the substrate may be a rectangle, such as a square.
  • Orthographic projections of the fifth connecting bridge 3411 and the sixth connecting bridge 3412 on the base substrate may be rectangular.
  • the length of the fifth connection bridge 3411 and the sixth connection bridge 3412 in the first direction Y may be greater than the length in the second direction X.
  • this embodiment does not limit it.
  • the orthographic projection of the second body on the base substrate may be in other shapes such as a circle or an ellipse.
  • Orthographic projections of the fifth connecting bridge and the sixth connecting bridge on the base substrate may be in other shapes such as a wavy line shape.
  • the shapes of the orthographic projections of the second body, the fifth connecting bridge and the sixth connecting bridge on the base substrate may be the same or partly the same or all different.
  • the fifth connecting bridge 3411 and the sixth connecting bridge 3412 of the second repeating unit 341 may be connected to adjacent second repeating units 341 in the first direction Y.
  • the fifth connecting bridge 3411 and the sixth connecting bridge 3412 of the second repeating unit 341 may be about the third centerline OY′ of the second body 3410 in the first direction Y. Roughly symmetrical.
  • the second repeating unit 341 may be roughly symmetrical about the fourth centerline OX' in the second direction X, and may also be roughly symmetrical about the third centerline OY' in the first direction Y.
  • the third centerline OY' may coincide with the first centerline OY
  • the fourth centerline OX' may coincide with the second centerline OX.
  • this embodiment does not limit it.
  • Fig. 25 is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 21.
  • the frame cathode 34 in a plane perpendicular to the display substrate, is located on a side of the first power line structure 41 away from the base substrate 10 .
  • the first power line structure 41 is located on the fourth conductive layer.
  • the second main body 3410 of the second repeating unit 341 of the frame cathode 34 is in direct contact with the first main body 4110 of the first repeating unit 411 of the first power line structure 41, and the fifth connecting bridge 3411 of the second repeating unit 341 is in direct contact with the first repeating unit 3411.
  • the first connecting bridge 4111 of the unit 411 is in direct contact
  • the sixth connecting bridge 3412 of the second repeating unit 341 is in direct contact with the second connecting bridge 4112 of the first repeating unit 411
  • the third connecting bridge 4113 and the fourth connecting bridge 4114 of the first repeating unit 411 are not in contact with the second repeating unit 341 .
  • the orthographic projection of the first body 4110 of the first repeating unit 411 on the substrate may include the orthographic projection of the second body 3410 of the second repeating unit 341 on the substrate.
  • the orthographic projection of the second body 3410 of the second repeating unit 341 on the base substrate and the orthographic projection of the first body 4110 of the first repeating unit 411 on the substrate may coincide.
  • the orthographic projection of the first connecting bridge 4111 of the first repeating unit 411 on the substrate may include the orthographic projection of the fifth connecting bridge 3441 of the second repeating unit 341 on the substrate.
  • the orthographic projection of the first connecting bridge 4111 of the first repeating unit 411 on the base substrate and the orthographic projection of the fifth connecting bridge 3441 of the second repeating unit 341 on the substrate may coincide.
  • the orthographic projection of the second connecting bridge 4112 of the first repeating unit 411 on the substrate may include the orthographic projection of the sixth connecting bridge 3412 of the second repeating unit 341 on the substrate.
  • the orthographic projection of the second connecting bridge 4112 of the first repeating unit 411 on the base substrate and the orthographic projection of the sixth connecting bridge 3412 of the second repeating unit 341 on the substrate may coincide.
  • this embodiment does not limit it.
  • Fig. 26 is another partial cross-sectional schematic diagram along the Q-Q' direction in Fig. 21.
  • the frame cathode 34 in a plane perpendicular to the display substrate, is located on the side of the first power line structure 41 away from the base substrate 10 .
  • the first power line structure 41 is located on the fourth conductive layer.
  • the second main body 3410 of the second repeating unit 341 of the frame cathode 34 can directly contact the first main body 4110 of the first repeating unit 411 of the first power line structure 41, and the fifth connecting bridge 3411 of the second repeating unit 341 is connected to the first The first connecting bridge 4111 of the repeating unit 411 is not in contact, and the sixth connecting bridge 3412 of the second repeating unit 341 is not in contact with the second connecting bridge 4112 of the first repeating unit 411 .
  • the fifth insulating layer 15 is disposed between the fifth connecting bridge 3411 and the sixth connecting bridge 3412 of the second repeating unit 341 and the first repeating unit 411 .
  • the orthographic projection of the connection area between the frame cathode 34 and the first power line structure 41 on the base substrate 10 may be within the orthographic projection of the first body 4110 of the first power line structure 41 on the base substrate 10 .
  • this embodiment does not limit it.
  • the length of the first repeating unit 411 in the second direction X is denoted as U1
  • the length in the first direction Y is denoted as U2
  • U1 and U2 may be approximately the same.
  • the length of the first body 4110 of the first repeating unit 411 in the second direction X is denoted as D1
  • the length in the first direction Y is denoted as D2.
  • the first connecting bridge 4111 and the second connecting bridge 4112 are symmetrical about the first central line OY.
  • the lengths of the first connecting bridge 4111 and the second connecting bridge 4112 in the first direction Y may be approximately the same, and the lengths in the second direction X may be approximately the same.
  • the length of the first connecting bridge 4111 in the first direction Y is denoted as L3, and the length in the second direction X is denoted as L1.
  • the third connecting bridge 4113 and the fourth connecting bridge 4114 are symmetrical about the second central line OX.
  • the lengths of the third connecting bridge 4113 and the fourth connecting bridge 4114 in the first direction Y may be approximately the same, and the lengths in the second direction X may be approximately the same.
  • the length of the third connecting bridge 4113 in the first direction Y is denoted as L2
  • the length in the second direction X is denoted as L4.
  • the length of the second repeating unit 341 in the first direction Y is denoted as U3.
  • the length of the second repeating unit 341 in the second direction X is the length of the second body 3410 in the second direction X, for example, denoted as D3.
  • the length of the second body 3410 in the first direction Y is denoted as D4.
  • the fifth connection bridge 3411 and the sixth connection bridge 3412 are substantially symmetrical about the third center line OY'.
  • the lengths of the fifth connecting bridge 3411 and the sixth connecting bridge 3412 in the first direction Y may be approximately the same, and the lengths in the second direction X may be approximately the same.
  • the length of the fifth connecting bridge 3411 in the first direction Y is denoted as L6, and the length in the second direction X is denoted as L5.
  • U3 and U2 may be approximately the same, D3 may be less than or equal to D1, D4 may be less than or equal to D2, L5 may be less than or equal to L1, and L6 may be greater than or equal to L3.
  • the third connecting bridge 4113 of the first repeating unit 411 is in the first direction Y
  • the length L2 of can be determined according to the following formula:
  • L2 [(1-TR/0.71)*(25400/P) 2 -D1*D2-2L1*L3]/(2*L4);
  • P is the resolution of the display substrate
  • D1 is the length of the first main body 4110 of the first repeating unit 411 in the second direction X
  • D2 is the length of the first main body 4110 in the first direction Y
  • L1 is the first The length of the connecting bridge 4111 in the second direction X
  • L3 is the length of the first connecting bridge 4111 in the first direction Y
  • L4 is the length of the third connecting bridge 4113 in the second direction X.
  • the length U2 of the first repeating unit 411 in the first direction Y and the length U1 in the second direction X may be determined according to the resolution of the display substrate. For example, if the resolution of the display substrate is about 40 to 100, the range of U1 and U2 may be about 254um to 635um.
  • the length D2 of the first body 4110 in the first direction Y and the length D1 in the second direction X may be determined according to the manufacturing process and the resolution of the display substrate.
  • D1 and D2 may range from about 50um to 635um.
  • L3 and L4 can be calculated according to U1, U2, D1 and D2.
  • the minimum value of L1 may be about 70 um.
  • the resolution P of the display substrate is about 83
  • the required light transmittance of the display area is about 71%
  • the required light transmittance TR of the frame area is about 40%.
  • the required light transmittance of the display area it can be calculated that the pixel size of the display area is about 100*100, that is, D3 and D4 of the second repeating unit are the same and about 100.
  • the first repeating units D1 and D2 are roughly the same, for example, about 170um.
  • the display substrate provided in this exemplary embodiment can improve the light transmittance of the frame area by patterning the first power line structure and the frame cathode in the frame area, thereby realizing a transparent frame.
  • the third repeating unit of the display cathode in the display area may include a third body, and a third body extending from opposite sides of the third body along the first direction Y.
  • the Nine Connecting Bridge and the Tenth Connecting Bridge The structural description of the third body, the ninth connecting bridge and the tenth connecting bridge of the third repeating unit can refer to the description of the second main body, the fifth connecting bridge and the sixth connecting bridge of the second repeating unit, so it will not be repeated here. . However, this embodiment does not limit it.
  • the size of the third body of the third repeating unit and the size of the second body of the second repeating unit may be approximately the same, and the length of the ninth connecting bridge and the tenth connecting bridge of the third repeating unit in the second direction may be less than The length of the fifth connecting bridge and the sixth connecting bridge of the second repeating unit in the second direction.
  • FIG. 27 is another schematic plan view of the first repeating unit and the second repeating unit of at least one embodiment of the present disclosure.
  • the orthographic projection of the second repeating unit 341 on the base substrate is located within the orthographic projection of the first repeating unit 411 on the base substrate.
  • the length of the second body of the second repeating unit 341 in the second direction X is smaller than the length of the first body of the first repeating unit 411 in the second direction X
  • the second body of the second repeating unit 341 The length in the first direction Y is smaller than the length of the first body of the first repeating unit 411 in the first direction Y.
  • the lengths of the fifth connecting bridge and the sixth connecting bridge of the second repeating unit 341 in the second direction X are smaller than the lengths of the first connecting bridge and the second connecting bridge of the first repeating unit 411 in the second direction X.
  • FIG. 28 is another schematic plan view of the frame area of at least one embodiment of the present disclosure.
  • 29 is another schematic plan view of the first repeating unit and the second repeating unit of at least one embodiment of the present disclosure.
  • 30 is another schematic plan view of the second repeating unit of at least one embodiment of the present disclosure.
  • the second repeating unit 341 may include: a second body 3410 , and fifth connections formed by extending from opposite sides of the second body 3410 along the first direction Y.
  • the bridge 3411 and the sixth connecting bridge 3412 , and the seventh connecting bridge 3413 and the eighth connecting bridge 3414 extending from opposite sides of the second body 3410 along the second direction X are formed.
  • the orthographic projections of the seventh connection bridge 3413 and the eighth connection bridge 3414 on the base substrate may be rectangular.
  • the length of the seventh connection bridge 3413 and the eighth connection bridge 3414 in the first direction Y may be smaller than the length in the second direction X.
  • this embodiment does not limit it.
  • the fifth connecting bridge 3411 and the sixth connecting bridge 3412 of the second repeating unit 341 can connect with the adjacent second repeating unit 341 in the first direction Y. connect.
  • the seventh connection bridge 3413 and the eighth connection bridge 3414 of the second repeating unit 341 may be connected to the adjacent second repeating unit 341 in the second direction X.
  • the orthographic projection of the seventh connecting bridge 3413 on the substrate may be within the orthographic projection of the third connecting bridge 4113 of the first repeating unit 411 on the substrate, and the orthographic projection of the eighth connecting bridge 3414 on the substrate may be
  • the fourth connection bridge 4114 located in the first repeating unit 341 is within the orthographic projection of the base substrate.
  • the seventh connection bridge 3413 and the eighth connection bridge 3414 may be substantially symmetrical about the fourth centerline OX' of the second body 3410 in the second direction X.
  • the length of the seventh connecting bridge 3413 in the first direction Y is denoted as L8, and the length of the seventh connecting bridge 3413 in the second direction X is denoted as L7.
  • L7 may be greater than or equal to L4, and L8 may be less than or equal to L2.
  • this embodiment does not limit it.
  • the third repeating unit showing the cathode may include: a third body, a ninth connecting bridge and a tenth connecting bridge extending from opposite sides of the third body along the first direction, The eleventh connection bridge and the twelfth connection bridge formed by extending from opposite sides of the third body.
  • the ninth connecting bridge, the tenth connecting bridge, the eleventh connecting bridge and the twelfth connecting bridge of the third repeating unit please refer to the second main body, the fifth connecting bridge, The description of the sixth connection bridge, the seventh connection bridge and the eighth connection bridge will not be repeated here.
  • the repeating units of the display cathode 33 and the frame cathode 34 are substantially the same in shape, size and connection relationship.
  • the shape of the main body of the repeating unit of the display cathode and the frame cathode can be determined according to the arrangement of multiple sub-pixels in the pixel unit. For example, if the three sub-pixels in the pixel unit are arranged in a square pattern, the orthographic projection of the second main body of the second repeating unit on the substrate may be approximately square. In this example, the orthographic projection of the first body of the first repeating unit on the base substrate may be roughly square. However, this embodiment does not limit it.
  • the first sub-pixel P1, the two second sub-pixels P2 and the third sub-pixel P3 of the display area may be arranged in sequence along the second direction X, and the two second sub-pixels The two sub-pixels P2 are sequentially arranged along the first direction Y.
  • the orthographic projection of the third body of the third repeating unit of the display cathode and the second body of the second repeating unit of the frame cathode on the base substrate may be a rectangle, and the length of the rectangle in the first direction Y Can be smaller than the length in the second direction X.
  • the orthographic projection of the first main body of the first repeating unit of the first power line structure 41 on the base substrate may be a rectangle.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiment modes.
  • the first sub-pixel P1 , the two second sub-pixels P2 and the third sub-pixel P3 in the display area may be arranged in a diamond manner.
  • the orthographic projection of the third body of the third repeating unit of the display cathode and the second body of the second repeating unit of the frame cathode on the base substrate may be, for example, a rhombus.
  • the orthographic projection of the first main body of the first repeating unit of the first power line structure 41 on the base substrate may be a rhombus.
  • the structures of the display substrates in the above embodiments are merely illustrative. In some exemplary implementations, the corresponding structures can be changed according to actual needs.
  • the first power line structure may adopt a double-layer routing method of the fourth conductive layer and the anode layer.
  • the power connection block and the auxiliary electrodes may adopt a single-layer wiring method of the third conductive layer.
  • the display substrate may not be provided with the fourth conductive layer.
  • the orthographic projections of the first repeating unit and the second repeating unit on the base substrate may coincide. However, this embodiment does not limit it.
  • FIG. 33 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 33 , this embodiment provides a display device 91 including the display substrate 910 of the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate or a QLED display substrate.
  • the display device 91 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit it.

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Abstract

一种显示基板，包括：衬底基板、多个发光元件以及第一电源线结构。衬底基板包括显示区域和位于显示区域周围的边框区域。多个发光元件位于显示区域，至少一个发光元件包括沿着远离衬底基板的方向依次设置的阳极、有机发光层和阴极。第一电源线结构与阴极电连接，且位于边框区域。第一电源线结构具有至少一个第一开口。阴极包括位于边框区域的边框阴极，边框区域具有至少一个第二开口。第一电源线结构在衬底基板的正投影与边框阴极在衬底基板的正投影至少部分交叠，至少一个第一开口在衬底基板的正投影与第二开口在衬底基板的正投影至少部分交叠。

Description

显示基板及显示装置
本申请要求于2021年8月11日提交中国专利局、申请号为202110917744.X、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、多个发光元件以及第一电源线结构。衬底基板包括显示区域和位于显示区域周围的边框区域。多个发光元件，位于所述显示区域，至少一个发光元件包括沿着远离所述衬底基板的方向依次设置的阳极、有机发光层和阴极。第一电源线结构与阴极电连接，且位于边框区域。第一电源线结构具有至少一个第一开口。阴极包括位于边框区域的边框阴极，边框阴极具有至少一个第二开口。所述第一电源线结构在所述衬底基板的正投影与所述边框阴极在所述衬底基板的正投影至少部分交叠，至少一个第一开口在所述衬底基板的正投影与所述第二开口在所述衬底基板的正投影至少部分交叠。
在一些示例性实施方式中，所述第一电源线结构包括多个第一重复单元，所述多个第一重复单元阵列排布且相互连接。
在一些示例性实施方式中，所述第一重复单元包括：第一主体、沿第一方向从所述第一主体的相对两侧延伸形成的第一连接桥和第二连接桥、沿第二方向从所述第一主体的相对两侧延伸形成的第三连接桥和第四连接桥；所述第一方向与所述第二方向交叉。
在一些示例性实施方式中，所述第一连接桥和第二连接桥在所述第一方向上的长度大于在所述第二方向上的长度；所述第三连接桥和第四连接桥在所述第一方向上的长度小于在所述第二方向上的长度。
在一些示例性实施方式中，所述第一重复单元在所述第一方向上的长度与在所述第二方向上的长度大致相同。
在一些示例性实施方式中，所述第一主体、所述第一连接桥、所述第二连接桥、所述第三连接桥和所述第四连接桥在所述衬底基板上的正投影均为矩形。
在一些示例性实施方式中，所述第一连接桥和第二连接桥关于所述第一主体在所述第一方向上的中心线大致对称；所述第三连接桥和第四连接桥关于所述第一主体在所述第二方向上的中心线大致对称。
在一些示例性实施方式中，所述第三连接桥在所述第一方向上的长度根据以下式子确定：
L2＝[(1-TR/0.71)*(25400/P) 2-D1*D2-2L1*L3]/(2*L4)；
其中，TR为所述边框区域所需的透光率，P为所述显示基板的分辨率，D1为所述第一主体在所述第二方向上的长度，D2为所述第一主体在所述第一方向上的长度，L1为所述第一连接桥在所述第二方向上的长度，L3为所述第一连接桥在所述第一方向上的长度，L4为所述第三连接桥在所述第二方向上的长度。
在一些示例性实施方式中，所述边框阴极位于所述第一电源线结构远离所述衬底基板的一侧；所述边框阴极与所述第一电源线结构的连接区域在衬底基板上的正投影位于所述第一电源线结构的第一主体在所述衬底基板上的 正投影内。
在一些示例性实施方式中，所述边框阴极包括：多个第二重复单元；沿第一方向排布的多个第二重复单元相互连接。在所述边框阴极和第一电源线结构的交叠区域，所述第一重复单元在所述衬底基板上的正投影包含所述第二重复单元在所述衬底基板上的正投影。
在一些示例性实施方式中，所述第二重复单元包括：第二主体、沿所述第一方向从所述第二主体的相对两侧延伸形成的第五连接桥和第六连接桥。
在一些示例性实施方式中，所述第五连接桥和第六连接桥关于所述第二重复单元在第一方向上的中心线大致对称。
在一些示例性实施方式中，所述第二主体、第五连接桥和第六连接桥在所述衬底基板上的正投影均为矩形。
在一些示例性实施方式中，所述第二重复单元还包括：沿所述第二方向从所述第二主体的相对两侧延伸形成的第七连接桥和第八连接桥；多个第二重复单元连接成网状。
在一些示例性实施方式中，所述阴极还包括：位于所述显示区域的显示阴极。所述显示阴极包括：多个阵列排布的第三重复单元。所述显示阴极的第三重复单元的形状、大小和连接关系与所述边框阴极的第二重复单元的形状、大小和连接关系大致相同。
在一些示例性实施方式中，所述第三重复单元包括：第三主体、沿所述第一方向从所述第三主体的相对两侧延伸形成的第九连接桥和第十连接桥。
在一些示例性实施方式中，所述显示基板还包括：位于显示区域的多个辅助电极。所述多个辅助电极与显示阴极的多个第三重复单元电连接。所述多个辅助电极与所述边框区域的第一电源线结构通过第一连接线电连接。
在一些示例性实施方式中，所述辅助电极包括：与所述第一电源线结构同层设置的第一子辅助电极、以及与发光元件的阳极同层设置的第二子辅助电极，所述第一子辅助电极与所述第二子辅助电极电连接。所述第三重复单元与第二子辅助电极和第一子辅助电极电连接。
在一些示例性实施方式中，在所述显示区域，多个第一子辅助电极阵列 排布且通过第四连接线和第五连接线连接；多个第二子辅助电极阵列排布。所述第二子辅助电极在所述衬底基板上的正投影覆盖所述第一子辅助电极在所述衬底基板上的正投影。
在一些示例性实施方式中，所述第一子辅助电极和第二子辅助电极在所述衬底基板上的正投影均为矩形。
在一些示例性实施方式中，所述第一连接线沿所述第二方向延伸，所述第一连接线与所述第一电源线结构的第一主体电连接。所述第一连接线远离所述衬底基板一侧设置有边框阴极，所述第一连接线在所述衬底基板上的正投影与所述边框阴极在所述衬底基板上的正投影存在交叠。
在一些示例性实施方式中，所述边框区域包括上边框，所述上边框设置有第二电源线结构，所述第二电源线结构包括阵列排布的多个第四重复单元。所述第四重复单元的形状、大小和连接关系与所述上边框的第一电源线结构的第一重复单元的形状、大小和连接关系大致相同。所述第二重复单元在所述衬底基板的正投影与所述第四重复单元在所述衬底基板的正投影具有交叠。
在一些示例性实施方式中，所述显示区域设置有多个电源连接块；所述第二电源线结构通过第二连接线与所述显示区域的电源连接块电连接。所述第二连接线具有直线部分和弯折部分，所述第二连接线靠近所述衬底基板一侧设置有多条数据线，所述第二连接线在所述衬底基板上的正投影与所述多条数据线在所述衬底基板上的正投影没有交叠。所述第二连接线的直线部分的虚拟延长线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影具有交叠。
在一些示例性实施方式中，所述电源连接块包括：层叠设置且相互电连接的第一子电源连接块和第二子电源连接块，所述第一子电源连接块在衬底基板上的正投影为沿第二方向延伸的条状，所述第二子电源连接块在衬底基板上的正投影包含第一子电源连接块在衬底基板上的正投影。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为人眼最小识别距离的示意图；
图2为本公开至少一实施例的显示基板的示意图；
图3为本公开至少一实施例的显示基板的结构示意图；
图4为本公开至少一实施例的像素电路的等效电路图；
图5为图4所示的像素电路的工作时序图；
图6为本公开至少一实施例的阴极的局部示意图；
图7为本公开至少一实施例的显示区域的局部平面示意图；
图8为图7中沿O-O’方向的局部剖面示意图；
图9为图7中沿R-R’方向的局部剖面示意图；
图10为本公开至少一实施例的形成半导体层后的显示区域的局部平面示意图；
图11为本公开至少一实施例的形成第一导电层后的显示区域的局部平面示意图；
图12为本公开至少一实施例的形成第二导电层后的显示区域的局部平面示意图；
图13为本公开至少一实施例的形成第三绝缘层后的显示区域的局部平面示意图；
图14为本公开至少一实施例的形成第三导电层后的显示区域的局部平面示意图；
图15为本公开至少一实施例的形成第四导电层后的显示区域的局部平面示意图；
图16为图2中区域A1的局部示意图；
图17为图16中的第四导电层的示意图；
图18为图2中区域A2的局部示意图；
图19为图18中的第四导电层的示意图；
图20为图17中区域S2的局部放大示意图；
图21为图16中区域S1的放大示意图；
图22为本公开至少一实施例的第一重复单元和第二重复单元的平面示意图；
图23为本公开至少一实施例的第一重复单元的平面示意图；
图24为本公开至少一实施例的第二重复单元的平面示意图；
图25为图21中沿Q-Q’方向的局部剖面示意图；
图26为图21中沿Q-Q’方向的另一局部剖面示意图；
图27为本公开至少一实施例的第一重复单元和第二重复单元的另一平面示意图；
图28为本公开至少一实施例的边框区域的另一平面示意图；
图29为本公开至少一实施例的第一重复单元和第二重复单元的另一平面示意图；
图30为本公开至少一实施例的第二重复单元的另一平面示意图；
图31为本公开至少一实施例的阴极的另一局部示意图；
图32为本公开至少一实施例的阴极的另一局部示意图；
图33为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意 组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。另外，栅极还可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。本公开中的“大致相同”是指数值相差10％以内的情况。
利用OLED显示技术的特点，OLED显示面板可以满足透明显示要求。通常OLED显示面板包括多个发光元件，每个发光元件包括：阳极、阴极以及设置在阳极和阴极之间的有机发光层。对于透明显示而言，透光率是一项重要的参数。阴极材料的透光率约在50％至60％，会大大降低透明显示面板的透光率。为了提高透光率，一般采用图形化阴极的设计，使得阴极材料仅在像素区域留存，像素区域之间的透明区域的阴极材料被去掉。图形化阴极还需要在边框区域与VSS信号线搭接，来实现电路接通。
图1为人眼最小识别距离的示意图。如图1所示，人眼的最小分辨角θ为1’，根据应用环境的不同，物体距离人眼的距离H不同，人眼最小识别距离a会不同。其中，a＝2*H*tan(θ/2)。表1列举了不同应用环境下人眼的最小识别距离。
表1
Figure PCTCN2022110257-appb-000001
由表1可见，当使用环境为车载环境，走线宽度小于200um时，人眼不 可识别；当使用环境为手机应用环境，走线宽度小于70um时，人眼不可识别。宽度表示沿走线延伸方向的垂直方向的长度。然而，目前显示基板的边框区域的VSS信号线的设计宽度都较大(例如，大于200微米)，会影响边框区域的透明性，无法实现全透明产品。
本公开至少一实施例提供一种显示基板，包括：衬底基板、多个发光元件和第一电源线结构。衬底基板包括显示区域和位于显示区域周围的边框区域。多个发光元件位于显示区域，至少一个发光元件包括沿着远离衬底基板的方向依次设置的阳极、有机发光层和阴极。第一电源线结构与阴极电连接，且位于边框区域。第一电源线结构具有至少一个第一开口；阴极包括位于边框区域的边框阴极，边框阴极具有至少一个第二开口。第一电源线结构在衬底基板的正投影与边框阴极在衬底基板的正投影至少部分交叠，至少一个第一开口在衬底基板的正投影与第二开口在衬底基板的正投影至少部分交叠。在一些示例中，第一电源线结构为VSS信号线，可以持续提供低电平信号。
本实施例提供的显示基板，通过对边框区域内的第一电源线结构和边框阴极进行图案化设计，可以实现第一电源线结构和边框阴极的透明化，从而提升边框区域的透光率，以支持实现全透明显示产品。
在一些示例性实施方式中，第一电源线结构包括多个第一重复单元，多个第一重复单元阵列排布且相互连接。本示例性实施例的边框区域的第一电源线结构的多个第一重复单元排布为规则图案。然而，本实施例对此并不限定。例如，边框区域的第一电源线结构的多个第一重复单元可以无规则排布。
在一些示例性实施方式中，第一重复单元包括：第一主体、沿第一方向从第一主体的相对两侧延伸形成的第一连接桥和第二连接桥、沿第二方向从第一主体的相对两侧延伸形成的第三连接桥和第四连接桥。其中，第一方向与第二方向交叉。在一些示例中，第一方向与第二方向相互垂直。
在一些示例性实施方式中，边框阴极位于第一电源线结构远离衬底基板的一侧。边框阴极与第一电源线结构的连接区域在衬底基板上的正投影位于第一电源线结构的第一主体在衬底基板上的正投影内。然而，本实施例对此并不限定。
在一些示例性实施方式中，边框阴极包括：多个第二重复单元。沿第一 方向排布的多个第二重复单元相互连接。在边框阴极和第一电源线结构的交叠区域，第一重复单元在衬底基板上的正投影可以包含第二重复单元在衬底基板上的正投影。在本示例性实施方式中，在第一电源线结构和边框阴极的交叠区域，使第一电源线结构的第一重复单元的尺寸大于或等于边框阴极的第二重复单元的尺寸，可以减小透光率的损失。
在一些示例性实施方式中，阴极还包括位于显示区域的显示阴极。显示阴极包括多个阵列排布的第三重复单元。第三重复单元的形状、大小和连接关系与边框阴极的第二重复单元的形状、大小和连接关系大致相同。在本示例中，阴极包括位于显示区域的显示阴极和位于边框区域的边框阴极。在本示例性实施方式中，通过对显示区域的显示阴极进行图案化设计，可以提升显示区域的透光率。然而，本实施例对此并不限定。例如，显示阴极可以为整面结构，即仅实现边框透明化的显示产品。
在一些示例性实施方式中，显示基板还包括：位于显示区域的多个辅助电极。多个辅助电极与显示阴极的多个第三重复单元电连接，并与边框区域的第一电源线结构通过第一连接线电连接。在本示例中，通过辅助电极可以实现显示阴极和第一电源线结构之间的电连接。在一些示例中，辅助电极可以包括层叠设置且相互电连接的第一子辅助电极和第二子辅助电极。然而，本实施例对此并不限定。
在一些示例性实施方式中，边框区域包括上边框，上边框设置有第二电源线结构，第二电源线结构包括阵列排布的多个第四重复单元，第四重复单元的形状、大小和连接关系与上边框的第一连接线结构的第一重复单元的形状、大小和连接关系大致相同。第二重复单元在衬底基板的正投影与第四重复单元在衬底基板的正投影具有交叠。在一些示例中，第二电源线结构可以为VDD信号线，可以持续提供高电平信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域设置有多个电源连接块。第二电源线结构通过第二连接线与显示区域的电源连接块电连接。第二连接线具有直线部分和弯折部分。第二连接线靠近衬底基板的一侧设置有多条数据线。第二连接线在衬底基板上的正投影与所述多条数据线在衬底基板上的正投影没有交叠。第二连接线的直线部分的虚拟延长线在衬底基板上的正投影与数据 线在衬底基板上的正投影具有交叠。在本示例中，通过第二连接线的弯折设计，可以与相邻层的数据线错开，以避免信号干扰。
下面通过一些示例对本实施例的方案进行举例说明。
图2为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，如图2所示，本示例性实施例提供的显示基板，包括：衬底基板。衬底基板包括：显示区域AA和位于显示区域AA周围的边框区域BB。在一些示例中，边框区域BB可以包括衬底基板的上边框、下边框、左边框和右边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示基板可以具有大致矩形形状。如图2所示，显示基板可以包括在第二方向X上彼此平行的一对短边和在第一方向Y上彼此平行的一对长边。即，显示基板在第二方向X上的长度小于在第一方向Y上的长度。第二方向X与第一方向Y相互交叉，例如，第二方向X垂直于第一方向Y。然而，本实施例对此并不限定。在一些示例性实施方式中，衬底基板可以为包括线性边的闭合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中，当衬底基板具有线性边时，衬底基板的至少一些拐角可以为曲线。当衬底基板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例性实施方式中，如图2所示，显示区域AA至少包括：多个子像素PX、多条栅线G以及多条数据线D。多条栅线G沿第二方向X延伸，并沿第一方向Y依次排布；多条数据线D沿第一方向Y延伸，并沿第二方向X依次排布。多条栅线G和多条数据线D在衬底基板上的正投影交叉形成多个子像素区域，每个子像素区域内设置一个子像素PX。多条数据线D与多个子像素PX电连接，多条数据线D被配置为向多个子像素PX提供数据电压。多条栅线G与多个子像素PX电连接，多条栅线G被配置为向多个子像素PX提供栅极控制信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并 不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例性实施方式中，本实施例的显示基板可以为透明显示基板。其中，相邻像素单元之间可以具有透光区域，以实现透明显示。然而，本实施例对此并不限定。
在一些示例性实施方式中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，子像素可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(3个晶体管和1个电容)结构、7T1C(7个晶体管和1个电容)结构或者5T1C(5个晶体管和1个电容)结构。在一些示例中，发光元件可以为OLED器件。发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，边框区域BB设置有第一电源线结构41。边框区域BB的下边框可以包括信号接入区域。第一电源线结构41可以在边框区域BB内围绕显示区域AA设置，并延伸到信号接入区域，以与设置在信号接入区域内的驱动芯片连接，从驱动芯片接收低电平信号。然而，本实施例对此并不限定。在一些示例中，第一电源线结构可以延伸到下边框的绑定区域，与绑定区域内的绑定电极连接，以从外部控制电路接收低电平信号。
图3为本公开至少一实施例的显示基板的结构示意图。在一些示例性实施方式中，如图3所示，显示基板可以包括：时序控制器21、数据驱动器22、扫描驱动器23、发射驱动器24以及子像素阵列25。位于显示区域AA的子像素阵列35可以包括规则排布的多个子像素PX。扫描驱动器23配置为沿扫描线将扫描信号提供到子像素；数据驱动器22配置为沿数据线将数据电压 提供到子像素；发射驱动器24配置为沿发光控制线将发光控制信号提供到子像素；时序控制器21配置为控制扫描驱动器23、发射驱动器24和数据驱动器22。
在一些示例性实施方式中，如图3所示，时序控制器21可以将适于数据驱动器22的规格的灰度值和控制信号提供到数据驱动器22；时序控制器21可以将适于扫描驱动器23的规格的时钟信号、起始信号等提供到扫描驱动器23；时序控制器21可以将适于发射驱动器24的规格的时钟信号、起始信号等提供到发射驱动器24。数据驱动器22可以利用从时序控制器21接收的灰度值和控制信号来产生将提供到数据线D1至Dn的数据电压。例如，数据驱动器22可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn。扫描驱动器23可以通过从时序控制器21接收的时钟信号、扫描信号等来产生将提供到扫描线G1至Gm的扫描信号。例如，扫描驱动器23可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线。在一些示例中，扫描驱动器23可以包括移位寄存器，可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发射驱动器24可以通过从时序控制器21接收的时钟信号、发射停止信号等来产生将提供到发光控制线E1至Eo的发光控制信号。例如，发射驱动器24可以将具有截止电平脉冲的发光控制信号顺序地提供到发光控制线。发射驱动器24可以包括移位寄存器，以在时钟信号的控制下顺序地将截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号。其中，n、m和o均为自然数。
在一些示例性实施方式中，扫描驱动器23和发射驱动器24可以直接设置在衬底基板上。例如，扫描驱动器23和发射驱动器24可以设置在显示区域AA左右两侧的边框区域(例如，左边框和右边框)。例如，扫描驱动器23和发射驱动器24可以位于第一电源线结构41靠近显示区域AA的一侧。在一些示例中，扫描驱动器23和发射驱动器24可以在形成子像素的工艺中与子像素一起形成。然而，本实施例对于扫描驱动器23和发射驱动器24的位置或形成方式并不限定。在一些示例中，扫描驱动器23和发射驱动器24可以设置在单独的芯片或印刷电路板上，以连接到衬底基板上形成的焊盘或 焊垫。
在一些示例性实施方式中，数据驱动器22可以设置在单独的芯片或印刷电路板上，以通过衬底基板的边框区域的信号接入区域设置的信号接入引脚连接到子像素。例如，数据驱动器22可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在信号接入区域，以连接到衬底基板上的信号接入引脚。时序控制器21可以与数据驱动器22分开设置或者与数据驱动器22一体设置。然而，本实施例对此并不限定。
图4为本公开至少一实施例的像素电路的等效电路图。图5为图4所示的像素电路的工作时序图。
在一些示例性实施方式中，如图4所示，本示例性实施例的像素电路可以包括：六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括阳极、阴极以及位于阳极和阴极之间的有机发光层。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图4所示，像素电路与扫描线G、数据线 D、第一电源线PL1、第二电源线PL2、发光控制线E、初始信号线INIT、第一复位控制线RST1和第二复位控制线RST2电连接。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VSS，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VDD，并且第二电压信号VDD大于第一电压信号VSS。扫描线G配置为向像素电路提供扫描信号SCAN，数据线D配置为向像素电路提供数据信号DATA，发光控制线E配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供第二复位信号RESET2。在一些示例中，在一行像素电路中，第二复位控制线RST2可以与扫描线G相连，以被输入扫描信号SCAN。即，第n行像素电路接收的第二复位信号RESET2(n)为第n行像素电路接收的扫描信号SCAN(n)。然而，本实施例对此并不限定。例如，第二复位控制信号线RST2可以被输入不同于扫描信号SCAN的第二复位控制信号RESET2。在一些示例中，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线G连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例性实施方式中，如图4所示，驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VSS、第二电压信号VDD等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线G电连接，数据写入晶体管T4的第一极与数据线D电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。阈值补偿晶体管T2的栅极与扫描线G电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接。第一发光控制晶体管T5的栅极与发光控制线E电连接，第一发光控制晶体管T5的第一极与第二电源线PL2电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。第二发光控制晶体管T6的栅极与发光控制线E电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的阳极电连接。第一复位晶体管T1与驱动晶体管T3的栅极电连接， 并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1电连接，第一复位晶体管T1的第一极与初始信号线INIT电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接。第二复位晶体管T7的栅极与第二复位控制线RST2电连接，第二复位晶体管T7的第一极与初始信号线INIT电连接，第二复位晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一电极与驱动晶体管T3的栅极电连接，存储电容Cst的第二电极与第二电源线PL2电连接。在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图5对图4所示的像素电路的工作过程进行说明。其中，以图4所示的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图4和图5所示，在一帧显示时间段，像素电路的工作过程可以包括：第一阶段t1、第二阶段t2和第三阶段t3。
第一阶段t1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，初始信号线INIT提供的初始信号Vinit被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线G提供的扫描信号SCAN为高电平信号，发光控制线E提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段t2，称为数据写入阶段或者阈值补偿阶段。扫描线G提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线E提供的发光控制信号EM均为高电平信号，数据线DT输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平， 因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线D输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N2，并将数据线D输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线D输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得初始信号线INIT提供的初始信号Vinit提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线E提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段t3，称为发光阶段。发光控制信号线E提供的发光控制信号EM为低电平信号，扫描线G提供的扫描信号SCAN和第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线E提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第二电源线PL2输出的第二电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(VDD-Vdata+|Vth|)-Vth] 2＝K*[(VDD-Vdata)] 2；
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线D输出的数据电压，VDD为第二电源线PL2输出的第二电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
图6为本公开至少一实施例的显示基板的阴极的局部平面图。在一些示例性实施方式中，如图6所示，显示区域排布有多个像素单元，一个像素单元可以包括第一子像素P1、第二子像素P2和第三子像素P3。像素单元包括的第一子像素P1、第二子像素P2和第三子像素P3可以采用品字方式排列。在一些示例中，第一子像素P1可以为绿色子像素，第二子像素P2可以为红色子像素，第三子像素P3可以为蓝色子像素。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图6所示，显示基板的阴极可以包括位于显示区域的显示阴极33和位于边框区域的边框阴极。显示阴极33可以包括显示区域内的多个像素单元的发光元件的阴极。在显示区域内，沿第一方向Y排布的多个像素单元的发光元件的阴极可以为一体结构。显示阴极与边框阴极可以为一体结构。边框阴极在边框区域与第一电源线结构41电连接，以实现电路导通。
图7为本公开至少一实施例的显示区域的局部平面示意图。图8为图7中沿O-O’方向的局部剖面示意图。图9为图7中沿R-R’方向的局部剖面示意图。图7示意了显示区域的一个像素单元的平面结构，其中，一个像素单元可以包括三个子像素，例如，第一子像素P1、第二子像素P2和第三子像素P3。
在一些示例性实施方式中，如图7所示，三个子像素的像素电路沿第二方向X依次排布。在第二方向X上，第一子像素P1的像素电路位于数据线Di和Di+1之间，并与数据线Di电连接；第二子像素P2的像素电路位于数据线Di+1和Di+2之间，并与数据线Di+1电连接；第三子像素P3的像素电路位于数据线Di+2和初始信号线INIT之间，并与数据线Di+2电连接。第一子像素P1的发光元件的阳极31a、第二子像素P2的发光元件的阳极31b、以及第三子像素P3的发光元件的阳极31c可以按照品字方式排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7至图9所示，在垂直于显示基板的平面内，显示基板可以包括：在衬底基板10上依次设置的半导体层、第一导电层、第二导电层、第三导电层、第四导电层以及阳极层。在一些示例中，半导体层和第一导电层之间设置有第一绝缘层11，第一导电层和第二导电层之间设置有第二绝缘层12，第二导电层和第三导电层之间设置有第三绝缘层13，第三导电层和第四导电层之间设置有第四绝缘层14，第四导电层和阳极层之间设置有第五绝缘层15。在一些示例中，第一绝缘层11至第四绝缘层14可以为无机绝缘层，第五绝缘层15可以为有机绝缘层。然而，本实施例对此并不限定。在一些示例中，在阳极层远离衬底基板10的一侧还设置有像素定义层、有机发光层、阴极和封装层。
图10为本公开至少一实施例的形成半导体层后的显示区域的局部平面示意图。图11为本公开至少一实施例的形成第一导电层后的显示区域的局部平面示意图。图12为本公开至少一实施例的形成第二导电层后的显示区域的局部平面示意图。图13为本公开至少一实施例的形成第三绝缘层后的显示区域的局部平面示意图。图14为本公开至少一实施例的形成第三导电层后的显示区域的局部平面示意图。图15为本公开至少一实施例的形成第四导电层后的显示区域的局部平面示意图。下面主要以一个子像素的像素电路的平面结构为例进行说明。
在一些示例性实施方式中，如图10所示，显示区域的半导体层可以包括：多个像素电路的多个晶体管的有源层，例如，第一复位晶体管T1的第一有源层T10、阈值补偿晶体管T2的第二有源层T20、驱动晶体管T3的第三有源层T30、数据写入晶体管T4的第四有源层T40、第一发光控制晶体管T5的第五有源层T50、第二发光控制晶体管T6的第六有源层T60、第二复位晶体管T7的第七有源层T70。其中，一个像素电路的第一有源层T10至第七有源层T70可以为相互连接的一体结构。
在一些示例性实施方式中，半导体层的材料例如可以包括多晶硅。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。多个掺杂区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。在一些示例中，有源层的掺 杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
在一些示例性实施方式中，如图11所示，显示区域的第一导电层可以包括：扫描线G、发光控制线E、第一复位控制线RST1、第二复位控制线RST2、以及像素电路的多个晶体管的栅极(例如，第一复位晶体管T1的栅极T13、阈值补偿晶体管T2的栅极T23、驱动晶体管T3的栅极T33、数据写入晶体管T4的栅极T43、第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63、第二复位晶体管T7的栅极T73)。扫描线G、发光控制线E、第一复位控制线RST1和第二复位控制线RST2均沿第二方向X延伸；在第一方向Y上，第一复位控制线RST1、扫描线G、发光控制线E和第二复位控制线RST2依次排布。
在一些示例性实施方式中，如图11所示，存储电容Cst的第一电极Cst-1和驱动晶体管T3的栅极T33可以为一体结构。扫描线G、数据写入晶体管T4的栅极T43、以及阈值补偿晶体管T2的栅极T23可以为一体结构。发光控制线E、第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63可以为一体结构。第一复位控制线RST1和第一复位晶体管T1的栅极T13可以为一体结构。第二复位控制线RST2和第二复位晶体管T7的栅极T73可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图12所示，显示区域的第二导电层可以包括：像素电路的存储电容Cst的第二电极Cst-2、第一初始连接线51和第二初始连接线52。在第二方向X上，相邻像素电路的存储电容Cst的第二电极Cst-2可以为一体结构。存储电容Cst的第二电极Cst-2在衬底基板上的正投影位于扫描线G和发光控制线E在衬底基板上的正投影之间。存储电容Cst的第二电极Cst-2在衬底基板上的正投影与第一电极Cst-1在衬底基板上的正投影存在重叠区域。第二电极Cst-2上设置有开口OP，开口OP暴露出覆盖第一电极Cst-1的第二绝缘层，且第一电极Cst-1在衬底基板上的正投影包含开口OP在衬底基板上的正投影。在一些示例中，开口OP配置为容置后续形成的第二过孔H1，第二过孔H1位于开口OP内并暴露出第一电极Cst-1，使后续形成的第一复位晶体管T1的第二极与第一电极Cst-1电连接。第一初 始连接线51和第二初始连接线52均沿第二方向X延伸。在第一方向Y上，第一初始连接线51位于第一复位控制线RST1远离扫描线G的一侧，第二初始连接线52位于第二复位控制线RST2远离发光控制线E的一侧。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图13所示，显示区域的第三绝缘层13上开设有多个过孔，例如可以包括：多个第一过孔V1至V5、第二过孔H1、以及多个第三过孔K1至K6。多个第一过孔V1至V5内的第三绝缘层13被刻蚀掉，暴露出第二导电层的表面；第二过孔内H1的第三绝缘层13和第二绝缘层12被刻蚀掉，暴露出的第一导电层的表面；多个第三过孔K1至K6内的第三绝缘层13、第二绝缘层12和第一绝缘层11被刻蚀掉，暴露出半导体层的表面。
在一些示例性实施方式中，如图14所示，显示区域的第三导电层可以包括：多条数据线(例如，数据线Di、Di+1、以及Di+2)、初始信号线INIT、第一子电源连接块(例如，第一子电源连接块61、62和63)、第三连接线64、以及像素电路的多个晶体管的第一极和第二极(例如，第一复位晶体管T1的第一极T11和第二极T12、数据写入晶体管T4的第一极T41、第一发光控制晶体管T5的第一极T51、第二发光控制晶体管T6的第二极T62、第二复位晶体管T7的第一极T71)。多条数据线、初始信号线INIT沿第一方向Y延伸，且沿第二方向X依次排布。
在一些示例性实施方式中，如图13和图14所示，第一复位晶体管T1的第一极T11通过第三过孔K1与第一有源层T10的第一掺杂区电连接，还通过第三过孔V1与第一初始连接线51电连接。第一复位晶体管T1的第二极T12通过第三过孔K2与第一有源层T10的第二掺杂区电连接，还通过第二过孔H1与存储电容Cst的第一电极Cst-1电连接。数据写入晶体管T4的第一极T41通过第三过孔K3与第四有源层T40的第一掺杂区电连接。数据写入晶体管T4的第一极T41与数据线Di可以为一体结构。第一发光控制晶体管T5的第一极T51通过第三过孔K4与第五有源层T50的第一掺杂区电连接。第二发光控制晶体管T6的第二极T62通过第三过孔K5与第六有源层T60的第二掺杂区电连接。第二复位晶体管T7的第一极T71通过第三过孔 K6与第七有源层T70的第一掺杂区电连接，还通过第一过孔V4与第二初始连接线52电连接。初始信号线INIT通过第一过孔V2与第一初始连接线51电连接，通过第一过孔V5与第二初始连接线52电连接。本示例中，通过第一初始连接线51和第二初始连接线52，实现初始信号线INIT与多个像素电路的电连接。
在一些示例性实施方式中，如图13和图14所示，第一子电源连接块61可以通过多个第一过孔V3(例如，沿第一方向Y排布的三个第一过孔)与存储电容Cst的第二电极Cst-2电连接。第一发光控制晶体管T5的第一极T51与第一子电源连接块61可以为一体结构。同理，第一子电源连接块62和63可以各自与对应的存储电容的第二电极电连接。第一子电源连接块61、62和63相互独立，第一子电源连接块62与第三连接线64可以为一体结构。第三连接线64可以沿第一方向Y延伸。第三连接线64配置为实现相邻像素单元的第一子电源连接块之间的电连接。
在一些示例性实施方式中，如图15所示，显示区域的第四导电层可以包括：第二子电源连接块65、多个连接电极(例如，连接电极66、67和68)、第一子辅助电极420、第四连接线421和第五连接线422。在一些示例中，连接电极66可以通过第四过孔F2与一个像素电路的第二发光控制晶体管T6的第二极T62电连接。连接电极67可以通过第四过孔F3与另一个像素电路的第二发光控制晶体管的第二极电连接，连接电极68可以通过第四过孔F4与第三个像素电路的第二发光控制晶体管的第二极电连接。
在一些示例性实施方式中，如图15所示，第二子电源连接块65可以通过多个第四过孔F1与第一子电源连接块61、62和63电连接。第二子电源连接块65在衬底基板上的正投影与三个第一子电源连接块61、62和63在衬底基板上的正投影均存在交叠。在本示例中，显示区域的电源连接块与一个像素单元对应。例如，电源连接块可以包括一个第二子电源连接块以及与该第二子电源连接块电连接的三个第一子电源连接块。在显示区域内，相邻电源连接块之间可以通过第三连接线64实现电连接，以传输第二电压信号VDD。显示区域内的相邻像素单元之间，可以通过第三连接线64和存储电容Cst的第二电极Cst-2实现第二电压信号VDD的传输。在一些示例中，第 三连接线64可以与边框区域内的第二连接线电连接，以实现与边框区域内的第二电源线结构的电连接。
在一些示例性实施方式中，如图15所示，第四连接线421沿第二方向X延伸，第五连接线422沿第一方向Y延伸。第一子辅助电极420在衬底基板上的正投影可以为矩形。第一子辅助电极420、第四连接线421和第五连接线422可以为一体结构。在显示区域内，第五连接线422在第一方向Y上电连接相邻的第一子辅助电极420，第四连接线421在第二方向X上电连接相邻的第一子辅助电极420。在一些示例中，第五连接线422可以在第一方向Y上延伸至边框区域，第四连接线421可以与边框区域的第一连接线电连接，以实现第一子辅助电极420与边框区域内的第一电源线结构41之间的电连接。
在一些示例性实施方式中，如图7所示，显示区域的阳极层可以包括：多个子像素的发光元件的阳极(例如，阳极31a、31b和31c)、第二子辅助电极423。在一些示例中，阳极31a可以通过第五过孔F5与连接电极66电连接，阳极31b可以通过第五过孔F6与连接电极67电连接，阳极31c可以通过第五过孔F7与连接电极68电连接。第二子辅助电极423可以通过第五过孔F8与第一子辅助电极420电连接。第二子辅助电极423在衬底基板上的正投影可以为矩形。第二子辅助电极423在衬底基板上的正投影可以包含第一子辅助电极420在衬底基板上的正投影。在本示例中，辅助电极可以由叠设的第一子辅助电极420和第二子辅助电极423电连接形成。通过双层电极设置的辅助电极可以降低电阻，提高信号传输效果。
在一些示例性实施方式中，第一导电层、第二导电层、第三导电层以及第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第五绝缘层15可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。然而，本实施例对此并不限定。
在一些示例性实施方式中，子像素的发光元件可以包括：阳极、像素定 义层、有机发光层和阴极。像素定义层具有暴露出阳极的像素开口，有机发光层形成在像素开口内。发光元件的有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极的驱动下出射相应颜色的光线。在阴极远离衬底基板的一侧可以设置封装层。封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件。
在一些示例性实施方式中，有机发光层可以包括叠设的空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、电子阻挡层(EBL，Electron Block Layer)、发光层(EML，Emitting Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子传输层(ETL，Electron Transport Layer)和电子注入层(EIL，Electron Injection Layer)。在一些示例中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。然而，本实施例对此并不限定。
在一些示例性实施方式中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。发光元件的阳极可以采用金属等反射材料，阴极可以采用半透半反材料。然而，本实施例对此并不限定。在一些示例中，发光元件的阳极可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。
在一些示例性实施方式中，显示基板的阴极可以包括位于边框区域BB的边框阴极和位于显示区域AA的显示阴极。边框阴极和显示阴极为同层结构。
图16为图2中区域A1的局部示意图。图17为图16中的第四导电层的示意图。图18为图2中区域A2的局部示意图。图19为图18中第三导电层的示意图。图16和图18中示意了显示基板的第四导电层和阴极的平面结构。图20为图17中区域S2的局部放大示意图。
在一些示例性实施方式中，如图16至图19所示，边框区域BB的第一电源线结构41具有多个第一开口，边框区域BB的边框阴极34具有多个第二开口。第一电源线结构41可以包括多个阵列排布且相互连接的第一重复单元。多个第一重复单元连接形成网状，使得第一电源线结构41具有多个第一开口。边框阴极34可以包括多个阵列排布且沿第一方向Y相互连接的第二重复单元。沿第二方向X排布的多个第二重复单元没有相互连接。多个第二重复单元可以连接形成多列，使得边框阴极34具有多个第二开口。通过对边框区域BB的第一电源线结构41和边框阴极34进行图案化设计，可以提高边框区域BB的透光率。本实施例对于第一电源线结构41的总宽度并不限定。
在一些示例性实施方式中，如图16至图19所示，显示区域AA的显示阴极33可以包括多个第三重复单元。沿第一方向Y排布的多个第三重复单元可以相互连接。沿第二方向X排布的多个第三重复单元没有相互连接。在边框区域BB的上边框，沿第一方向Y排布的多个第二重复单元相互连接，并与显示区域AA内沿第一方向Y排布的多个第三重复单元连接。在边框区域BB的左边框，边框阴极34的第二重复单元没有与显示区域AA的第三重复单元连接。在一些示例中，显示阴极33的第三重复单元的形状、大小和连接关系与边框阴极34的第二重复单元的形状、大小和连接关系大致相同。然而，本实施例对此并不限定。例如，显示阴极的第三重复单元的形状可以不同于边框阴极的第二重复单元的形状。或者，显示阴极可以为整面结构，不具有开口。
在一些示例性实施方式中，如图6、图16和图18所示，显示区域AA的显示阴极33的第三重复单元在衬底基板上的正投影可以覆盖一个像素单元和一个辅助电极在衬底基板上的正投影。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图16和图17所示，边框区域BB的上边框还设置有第二电源线结构71。第二电源线结构71位于第一电源线结构41靠近显示区域AA的一侧。第二电源线结构71与第一电源线结构41可以为同层结构。第二电源线结构71可以通过第二连接线72与显示区域AA的电源连接块电连接。例如，第二连接线72可以与显示区域AA内的第三连接线64电连接。在一些示例中，第二连接线72位于第三连接线64远离衬底基板 的一侧。例如，第三连接线64位于第三导电层，第二连接线72位于第四导电层。在一些示例中，与第一子辅助电极420电连接的第五连接线422可以沿第一方向Y延伸至上边框内靠近第二电源线结构71的位置。第五连接线422与第二电源线结构71没有电连接关系。
在一些示例性实施方式中，如图17所示，第二电源线结构71可以包括阵列排布且相互连接的多个第四重复单元。在一些示例中，第二电源线结构71的第四重复单元的形状、大小和连接关系与第一电源线结构41的第一重复单元的形状、大小和连接关系可以大致相同。如图16所示，第二重复单元在衬底基板上的正投影与第四重复单元在衬底基板上的正投影存在交叠。然而，本实施例对此并不限定。例如，第二电源线结构71的第四重复单元的形状可以不同于第一电源线结构41的第一重复单元的形状。在本示例中，边框区域BB的第二电源线结构71可以采用图案化设计，从而进一步提高边框区域BB的透光率。
在一些示例性实施方式中，如图20所示，第二连接线72和第五连接线422位于第四导电层。多条数据线(例如，数据线Di、Di+1和Di+2)位于第三导电层。第二连接线72具有直线部分和弯折部分。在边框区域内，第二连接线72在第二方向X上位于第五连接线422的一侧。第二连接线72在衬底基板上的正投影与多条数据线在衬底基板上的正投影没有交叠。例如，第二连接线72在衬底基板上的正投影可以位于数据线Di+1和数据线Di+2在衬底基板上的正投影之间。第二连接线72的直线部分的虚拟延长线在衬底基板上的正投影与数据线在衬底基板上的正投影具有交叠。例如，第二连接线72包括依次连接的第一直线部分、弯折部分和第二直线部分；第一直线部分的虚拟延长线在衬底基板上的正投影与数据线Di+2在衬底基板上的正投影具有交叠，第二直线部分的虚拟延长线在衬底基板上的正投影与数据线Di+1在衬底基板上的正投影具有交叠。本示例中，设置第二连接线与相邻层的数据线错开，可以避免信号干扰。
在一些示例性实施方式中，如图18和图19所示，在边框区域BB(例如左边框)设置有多条第一连接线43。多条第一连接线43可以沿第二方向X延伸，并沿第一方向Y排布。边框区域BB的第一电源线结构41可以通 过第一连接线43与显示区域AA内的辅助电极电连接。在一些示例中，第一电源线结构41、辅助电极的第一子辅助电极420、第一连接线43和第四连接线421可以为一体结构。例如，边框区域BB的第一连接线43与显示区域AA的第四连接线421电连接，从而实现第一电源线结构41和第一子辅助电极420之间的电连接。在显示区域AA内，第一子辅助电极420通过第二子辅助电极423可以与显示阴极33电连接，从而实现第一电源线结构41与显示阴极33之间的电连接。如图18所示，在边框区域BB，边框阴极34在衬底基板上的正投影与第一连接线43在衬底基板上的正投影存在交叠。然而，本实施例对此并不限定。在一些示例性实施方式中，如图18所示，左边框的边框阴极34与显示区域AA的显示阴极33之间可以没有电连接。通过左右边框的边框阴极34与第一电源线结构41的电连接，可以降低第一电源线结构41的电阻。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域的多个第一子辅助电极420可以阵列排布，并通过第四连接线421和第五连接线422电连接。显示区域的多个第二子辅助电极423可以阵列排布，且相互独立。然而，本实施例对此并不限定。例如，显示区域的多个第二子辅助电极可以通过沿第一方向延伸的第六连接线和沿第二方向延伸的第七连接线电连接。
在本示例性实施方式中，第一电源线结构41可以通过上下边框的边框阴极34与显示区域AA的显示阴极33直接电连接，还可以通过左右边框的第一连接线43与显示区域AA的辅助电极电连接，继而通过辅助电极与显示阴极33电连接，从而实现第一电源线结构41和显示阴极33之间的电路通路。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图16和图18所示，在边框区域BB，在第一电源线结构41和边框阴极34的交叠区域，第一电源线结构41在衬底基板上的正投影可以包含边框阴极34在衬底基板上的正投影。如此一来，可以减小边框区域的透光率的损失。
图21为图16中区域S1的放大示意图。图22为本公开至少一实施例的第一重复单元和第二重复单元的平面示意图。图23为本公开至少一实施例的第一重复单元的平面示意图。图24为本公开至少一实施例的第二重复单元的 平面示意图。
在一些示例性实施方式中，如图21和图22所示，第一电源线结构41的第一重复单元411在衬底基板上的正投影可以包含边框阴极34的第二重复单元341在衬底基板上的正投影。
在一些示例性实施方式中，如图23所示，第一电源线结构41的第一重复单元411可以包括：第一主体4110、沿第一方向Y从第一主体4110的相对两侧延伸形成的第一连接桥4111和第二连接桥4112、沿第二方向X从第一主体4110的相对两侧延伸形成的第三连接桥4113和第四连接桥4114。在一些示例中，第一主体4110在衬底基板上的正投影可以为矩形，例如可以为正方形。第一连接桥4111和第二连接桥4112在衬底基板上的正投影可以为矩形。例如，第一连接桥4111和第二连接桥4112在第一方向Y上的长度可以大于在第二方向X上的长度。第三连接桥4113和第四连接桥4114在衬底基板上的正投影可以为矩形。例如，第三连接桥4113和第四连接桥4114在第一方向Y上的长度可以小于在第二方向X上的长度。然而，本实施例对此并不限定。例如，第一主体在衬底基板上的正投影可以为圆形或椭圆形等其它形状。第一连接桥、第二连接桥、第三连接桥和第四连接桥在衬底基板上的正投影可以为波浪线形状等其它形状。第一主体、第一连接桥、第二连接桥、第三连接桥和第四连接桥在衬底基板上的正投影的形状可以相同或者部分相同或者均不同。
在一些示例性实施方式中，如图21所示，第一重复单元411的第一连接桥4111和第二连接桥4112可以在第一方向Y上与相邻的第一重复单元连接，第三连接桥4113和第四连接桥4114可以在第二方向X上与相邻的第一重复单元连接。
在一些示例性实施方式中，如图23所示，第一重复单元411的第一连接桥4111和第二连接桥4112可以关于第一主体4110在第一方向Y上的第一中心线OY大致对称，第三连接桥4113和第四连接桥4114可以关于第一主体4110在第二方向X上的第二中心线OX大致对称。在本示例中，第一重复单元411可以关于第一中心线OY对称，还可以关于第二中心线OX对称。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图24所示，第二重复单元341包括：第二主体3410、沿第一方向Y从第二主体3410的相对两侧延伸形成的第五连接桥3411和第六连接桥3412。在一些示例中，第二主体3410在衬底基板上的正投影可以为矩形，例如可以为正方形。第五连接桥3411和第六连接桥3412在衬底基板上的正投影可以为矩形。例如，第五连接桥3411和第六连接桥3412在第一方向Y上的长度可以大于在第二方向X上的长度。然而，本实施例对此并不限定。例如，第二主体在衬底基板上的正投影可以为圆形或椭圆形等其它形状。第五连接桥和第六连接桥在衬底基板上的正投影可以为波浪线形状等其它形状。第二主体、第五连接桥和第六连接桥在衬底基板上的正投影的形状可以相同或者部分相同或者均不同。
在一些示例性实施方式中，如图21所示，第二重复单元341的第五连接桥3411和第六连接桥3412可以在第一方向Y上与相邻的第二重复单元341连接。
在一些示例性实施方式中，如图12所示，第二重复单元341的第五连接桥3411和第六连接桥3412可以关于第二主体3410在第一方向Y上的第三中心线OY’大致对称。本示例中，第二重复单元341可以关于第二方向X上的第四中心线OX’大致对称，还可以关于第一方向Y上的第三中心线OY’大致对称。在一些示例中，第三中心线OY’可以和第一中心线OY重合，第四中心线OX’可以和第二中心线OX重合。然而，本实施例对此并不限定。
图25为图21中沿Q-Q’方向的局部剖面示意图。在一些示例性实施方式中，如图21至图25所示，在垂直于显示基板的平面内，边框阴极34位于第一电源线结构41远离衬底基板10的一侧。第一电源线结构41位于第四导电层。边框阴极34的第二重复单元341的第二主体3410与第一电源线结构41的第一重复单元411的第一主体4110直接接触，第二重复单元341的第五连接桥3411与第一重复单元411的第一连接桥4111直接接触，第二重复单元341的第六连接桥3412与第一重复单元411的第二连接桥4112直接接触。第一重复单元411的第三连接桥4113和第四连接桥4114与第二重复单元341没有接触。在一些示例中，第一重复单元411的第一主体4110在衬底基板上的正投影可以包含第二重复单元341的第二主体3410在衬底基板上的正投影。 例如，第二重复单元341的第二主体3410在衬底基板上的正投影与第一重复单元411的第一主体4110在衬底基板上的正投影可以重合。第一重复单元411的第一连接桥4111在衬底基板上的正投影可以包含第二重复单元341的第五连接桥3441在衬底基板上的正投影。例如，第一重复单元411的第一连接桥4111在衬底基板上的正投影和第二重复单元341的第五连接桥3441在衬底基板上的正投影可以重合。第一重复单元411的第二连接桥4112在衬底基板上的正投影可以包含第二重复单元341的第六连接桥3412在衬底基板上的正投影。例如，第一重复单元411的第二连接桥4112在衬底基板上的正投影和第二重复单元341的第六连接桥3412在衬底基板上的正投影可以重合。然而，本实施例对此并不限定。
图26为图21中沿Q-Q’方向的另一局部剖面示意图。在一些示例性实施方式中，如图21至图24以及图26所示，在垂直于显示基板的平面内，边框阴极34位于第一电源线结构41远离衬底基板10的一侧。第一电源线结构41位于第四导电层。边框阴极34的第二重复单元341的第二主体3410与第一电源线结构41的第一重复单元411的第一主体4110可以直接接触，第二重复单元341的第五连接桥3411与第一重复单元411的第一连接桥4111没有接触，第二重复单元341的第六连接桥3412与第一重复单元411的第二连接桥4112没有接触。例如，第二重复单元341的第五连接桥3411和第六连接桥3412和第一重复单元411之间设置有第五绝缘层15。在本示例中，边框阴极34与第一电源线结构41的连接区域在衬底基板10上的正投影可以位于第一电源线结构41的第一主体4110在衬底基板10上的正投影内。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图23所示，第一重复单元411在第二方向X上的长度记为U1，在第一方向Y上的长度记为U2。在一些示例中，U1和U2可以大致相同。例如，U1＝U2＝25400/P，其中，P为显示基板的分辨率。第一重复单元411的第一主体4110在第二方向X上的长度记为D1，在第一方向Y上的长度记为D2。第一连接桥4111和第二连接桥4112关于第一中心线OY对称。第一连接桥4111和第二连接桥4112在第一方向Y上的长度可以大致相同，在第二方向X上的长度可以大致相同。例如，第一连接桥4111 在第一方向Y上的长度记为L3，在第二方向X上的长度记为L1。第三连接桥4113和第四连接桥4114关于第二中心线OX对称。第三连接桥4113和第四连接桥4114在第一方向Y上的长度可以大致相同，在第二方向X上的长度可以大致相同。例如，第三连接桥4113在第一方向Y上的长度记为L2，在第二方向X上的长度记为L4。
在一些示例性实施方式中，如图24所示，第二重复单元341在第一方向Y上的长度记为U3。第二重复单元341在第二方向X上的长度即为第二主体3410在第二方向X上的长度，例如，记为D3。第二主体3410在第一方向Y上的长度记为D4。第五连接桥3411和第六连接桥3412关于第三中心线OY’大致对称。第五连接桥3411和第六连接桥3412在第一方向Y上的长度可以大致相同，在第二方向X上的长度可以大致相同。例如，第五连接桥3411在第一方向Y上的长度记为L6，在第二方向X上的长度记为L5。
在一些示例性实施方式中，U3和U2可以大致相同，D3可以小于或等于D1，D4可以小于或等于D2，L5可以小于或等于L1，L6可以大于或等于L3。
在一些示例性实施方式中，以显示区域的透光率约为71％，边框区域所需的透光率为TR为例，第一重复单元411的第三连接桥4113在第一方向Y上的长度L2可以根据以下式子确定：
L2＝[(1-TR/0.71)*(25400/P) 2-D1*D2-2L1*L3]/(2*L4)；
其中，P为显示基板的分辨率，D1为第一重复单元411的第一主体4110在第二方向X上的长度，D2为第一主体4110在第一方向Y上的长度，L1为第一连接桥4111在第二方向X上的长度，L3为第一连接桥4111在第一方向Y上的长度，L4为第三连接桥4113在第二方向X上的长度。
在一些示例性实施方式中，第一重复单元411在第一方向Y上的长度U2和在第二方向X上的长度U1可以根据显示基板的分辨率确定。例如，显示基板的分辨率约为40至100，则U1和U2的范围可以约为254um至635um。
在一些示例性实施方式中，第一主体4110在第一方向Y上的长度D2和在第二方向X上的长度D1可以根据制备工艺和显示基板的分辨率确定。例如，D1和D2的范围可以约为50um至635um。
在一些示例性实施方式中，在第一重复单元411关于第一中心线OY对称且关于第二中心线OX对称的情况下，可以根据U1、U2、D1和D2来计算出L3以及L4。例如，L4＝(U1-D1)/2；L3＝(U2-D2)/2。在一些示例中，L1的取值越小透光效果越佳，例如，受限于掩模精度，L1的最小值可以约为70um。
在一些示例性实施方式中，显示基板的分辨率P约为83，显示区域所需的透光率约为71％，边框区域所需的透光率TR约为40％。第一重复单元的U1和U2大致相同，例如，U1＝U2＝306um。根据显示区域所需的透光率可以计算出显示区域的像素大小约为100*100，即第二重复单元的D3和D4相同，且约为100。根据掩模边界的单边为35，则可以得到第一重复单元D1和D2大致相同，例如，可以约为170um。根据第一重复单元的对称关系，可以计算得出L3＝L4＝(306-170)/2＝68um。以L1＝70um为例，根据以上L2的计算式，可以得到L2＝18um。
本示例性实施方式提供的显示基板，通过将边框区域的第一电源线结构和边框阴极进行图案化设计，可以提升边框区域的透光率，从而实现透明边框。
在一些示例性实施方式中，如图16和图18所示，显示区域的显示阴极的第三重复单元可以包括第三主体、沿第一方向Y从第三主体的相对两侧延伸形成的第九连接桥和第十连接桥。第三重复单元的第三主体、第九连接桥和第十连接桥的结构说明可以参照第二重复单元的第二主体、第五连接桥和第六连接桥的说明，故于此不再赘述。然而，本实施例对此并不限定。例如，第三重复单元的第三主体的尺寸和第二重复单元的第二主体的尺寸可以大致相同，第三重复单元的第九连接桥和第十连接桥在第二方向上的长度可以小于第二重复单元的第五连接桥和第六连接桥在第二方向上的长度。
图27为本公开至少一实施例的第一重复单元和第二重复单元的另一平面示意图。在一些示例性实施方式中，如图27所示，第二重复单元341在衬底基板上的正投影位于第一重复单元411在衬底基板上的正投影内。在本示例中，第二重复单元341的第二主体在第二方向X上的长度小于第一重复单元411的第一主体在第二方向X上的长度，第二重复单元341的第二主体在 第一方向Y上的长度小于第一重复单元411的第一主体在第一方向Y上的长度。第二重复单元341的第五连接桥和第六连接桥在第二方向X上的长度小于第一重复单元411的第一连接桥和第二连接桥在第二方向X上的长度。
关于本示例性实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图28为本公开至少一实施例的边框区域的另一平面示意图。图29为本公开至少一实施例的第一重复单元和第二重复单元的另一平面示意图。图30为本公开至少一实施例的第二重复单元的另一平面示意图。
在一些示例性实施方式中，如图28至图30所示，第二重复单元341可以包括：第二主体3410、沿第一方向Y从第二主体3410的相对两侧延伸形成的第五连接桥3411和第六连接桥3412、沿第二方向X从第二主体3410的相对两侧延伸形成的第七连接桥3413和第八连接桥3414。在一些示例中，第七连接桥3413和第八连接桥3414在衬底基板上的正投影可以为矩形。例如，第七连接桥3413和第八连接桥3414在第一方向Y上的长度可以小于在第二方向X上的长度。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图28至图30所示，第二重复单元341的第五连接桥3411和第六连接桥3412可以在第一方向Y上与相邻的第二重复单元341连接。第二重复单元341的第七连接桥3413和第八连接桥3414可以在第二方向X上与相邻的第二重复单元341连接。第七连接桥3413在衬底基板上的正投影可以位于第一重复单元411的第三连接桥4113在衬底基板上的正投影内，第八连接桥3414在衬底基板上的正投影可以位于第一重复单元341的第四连接桥4114在衬底基板上的正投影内。
在一些示例性实施方式中，如图30所示，第七连接桥3413和第八连接桥3414可以关于第二主体3410在第二方向X上的第四中心线OX’大致对称。第七连接桥3413在第一方向Y上的长度记为L8，第七连接桥3413在第二方向X上的长度记为L7。在一些示例中，L7可以大于或等于L4，L8可以小于或等于L2。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示阴极的第三重复单元可以包括：第三主 体、沿第一方向从第三主体的相对两侧延伸形成的第九连接桥和第十连接桥、沿第二方向从第三主体的相对两侧延伸形成的第十一连接桥和第十二连接桥。关于第三重复单元的第三主体、第九连接桥、第十连接桥、第十一连接桥和第十二连接桥的结构说明可以参照第二重复单元的第二主体、第五连接桥、第六连接桥、第七连接桥和第八连接桥的说明，故于此不再赘述。
关于本示例性实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
在一些示例性实施方式中，如图6、图16和图18所示，显示阴极33和边框阴极34的重复单元的形状、大小和连接关系大致相同。显示阴极和边框阴极的重复单元的主体的形状可以根据像素单元内的多个子像素的排布方式确定。例如，像素单元内的三个子像素按照品字方式排布，则第二重复单元的第二主体在衬底基板上的正投影可以大致为正方形。在本示例中，第一重复单元的第一主体在衬底基板上的正投影可以大致为正方形。然而，本实施例对此并不限定。
图31为本公开至少一实施例的阴极的另一局部示意图。在一些示例性实施方式中，如图31所示，显示区域的第一子像素P1、两个第二子像素P2和第三子像素P3可以沿第二方向X依次排布，且两个第二子像素P2沿第一方向Y依次排布。在本示例中，显示阴极的第三重复的第三主体和边框阴极的第二重复单元的第二主体在衬底基板上的正投影可以为矩形，且该矩形在第一方向Y上的长度可以小于在第二方向X上的长度。第一电源线结构41的第一重复单元的第一主体在衬底基板上的正投影可以为矩形。关于本示例性实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图32为本公开至少一实施例的阴极的另一局部示意图。在一些示例性实施方式中，如图32所示，显示区域的第一子像素P1、两个第二子像素P2和第三子像素P3可以按照钻石(Diamond)方式排布。在本示例中，显示阴极的第三重复单元的第三主体和边框阴极的第二重复单元的第二主体在衬底基 板上的正投影例如可以为菱形。第一电源线结构41的第一重复单元的第一主体在衬底基板上的正投影可以为菱形。关于本示例性实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
以上实施例的显示基板的结构仅仅是一些示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构。例如，第一电源线结构可以采用第四导电层和阳极层的双层走线方式。又如，电源连接块和辅助电极可以采用第三导电层的单层走线方式。又如，显示基板可以不设置第四导电层。又如，第一重复单元和第二重复单元在衬底基板上的正投影可以重合。然而，本实施例对此并不限定。
图33为本公开至少一实施例的显示装置的示意图。如图33所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板或者QLED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (25)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域和位于所述显示区域周围的边框区域；
    多个发光元件，位于所述显示区域，至少一个发光元件包括沿着远离所述衬底基板的方向依次设置的阳极、有机发光层和阴极；
    第一电源线结构，与所述阴极电连接，且位于所述边框区域；
    所述第一电源线结构具有至少一个第一开口；所述阴极包括位于所述边框区域的边框阴极，所述边框阴极具有至少一个第二开口；
    所述第一电源线结构在所述衬底基板的正投影与所述边框阴极在所述衬底基板的正投影至少部分交叠，至少一个第一开口在所述衬底基板的正投影与所述第二开口在所述衬底基板的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源线结构包括多个第一重复单元，所述多个第一重复单元阵列排布且相互连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一重复单元包括：第一主体、沿第一方向从所述第一主体的相对两侧延伸形成的第一连接桥和第二连接桥、沿第二方向从所述第一主体的相对两侧延伸形成的第三连接桥和第四连接桥；所述第一方向与所述第二方向交叉。
  4. 根据权利要求3所述的显示基板，其中，所述第一连接桥和第二连接桥在所述第一方向上的长度大于在所述第二方向上的长度，所述第三连接桥和第四连接桥在所述第一方向上的长度小于在所述第二方向上的长度。
  5. 根据权利要求3所述的显示基板，其中，所述第一重复单元在所述第一方向上的长度与在所述第二方向上的长度大致相同。
  6. 根据权利要求3所述的显示基板，其中，所述第一主体、所述第一连接桥、所述第二连接桥、所述第三连接桥和所述第四连接桥在所述衬底基板上的正投影均为矩形。
  7. 根据权利要求3所述的显示基板，其中，所述第一连接桥和第二连接桥关于所述第一主体在所述第一方向上的中心线大致对称；
    所述第三连接桥和第四连接桥关于所述第一主体在所述第二方向上的中心线大致对称。
  8. 根据权利要求7所述的显示基板，其中，所述第三连接桥在所述第一方向上的长度根据以下式子确定：
    L2＝[(1-TR/0.71)*(25400/P) 2-D1*D2-2L1*L3]/(2*L4)；
    其中，TR为所述边框区域所需的透光率，P为所述显示基板的分辨率，D1为所述第一主体在所述第二方向上的长度，D2为所述第一主体在所述第一方向上的长度，L1为所述第一连接桥在所述第二方向上的长度，L3为所述第一连接桥在所述第一方向上的长度，L4为所述第三连接桥在所述第二方向上的长度。
  9. 根据权利要求3至8中任一项所述的显示基板，其中，所述边框阴极位于所述第一电源线结构远离所述衬底基板的一侧；所述边框阴极与所述第一电源线结构的连接区域在衬底基板上的正投影位于所述第一电源线结构的第一主体在所述衬底基板上的正投影内。
  10. 根据权利要求3至8中任一项所述的显示基板，其中，所述边框阴极包括：多个第二重复单元；沿所述第一方向排布的多个第二重复单元相互连接；
    在所述边框阴极和所述第一电源线结构的交叠区域，所述第一重复单元在所述衬底基板上的正投影包含所述第二重复单元在所述衬底基板上的正投影。
  11. 根据权利要求10所述的显示基板，其中，所述第二重复单元包括：第二主体、沿所述第一方向从所述第二主体的相对两侧延伸形成的第五连接桥和第六连接桥。
  12. 根据权利要求11所述的显示基板，其中，所述第五连接桥和第六连接桥关于所述第二重复单元在所述第一方向上的中心线大致对称。
  13. 根据权利要求11所述的显示基板，其中，所述第二主体、第五连接桥和第六连接桥在所述衬底基板上的正投影均为矩形。
  14. 根据权利要求11所述的显示基板，其中，所述第二重复单元还包括： 沿所述第二方向从所述第二主体的相对两侧延伸形成的第七连接桥和第八连接桥；多个第二重复单元连接成网状。
  15. 根据权利要求10所述的显示基板，其中，所述阴极还包括：位于所述显示区域的显示阴极，所述显示阴极包括：多个阵列排布的第三重复单元；所述显示阴极的第三重复单元的形状、大小和连接关系与所述边框阴极的第二重复单元的形状、大小和连接关系大致相同。
  16. 根据权利要求15所述的显示基板，其中，所述第三重复单元包括：第三主体、沿所述第一方向从所述第三主体的相对两侧延伸形成的第九连接桥和第十连接桥。
  17. 根据权利要求15所述的显示基板，其中，所述显示基板还包括：多个辅助电极，所述多个辅助电极位于所述显示区域，与所述显示阴极的多个第三重复单元电连接，所述多个辅助电极与所述边框区域的第一电源线结构通过第一连接线电连接。
  18. 根据权利要求17所述的显示基板，其中，所述第一连接线沿所述第二方向延伸，所述第一连接线与所述第一电源线结构的第一主体电连接；所述第一连接线远离所述衬底基板一侧设置有边框阴极，所述第一连接线在所述衬底基板上的正投影与所述边框阴极在所述衬底基板上的正投影存在交叠。
  19. 根据权利要求17所述的显示基板，其中，所述辅助电极包括：与所述第一电源线结构同层设置的第一子辅助电极、以及与发光元件的阳极同层设置的第二子辅助电极，所述第一子辅助电极与所述第二子辅助电极电连接；所述第三重复单元与第二子辅助电极和第一子辅助电极电连接。
  20. 根据权利要求19所述的显示基板，其中，在所述显示区域，多个第一子辅助电极阵列排布且通过第四连接线和第五连接线连接；多个第二子辅助电极阵列排布；所述第二子辅助电极在所述衬底基板上的正投影覆盖所述第一子辅助电极在所述衬底基板上的正投影。
  21. 根据权利要求20所述的显示基板，其中，所述第一子辅助电极和第二子辅助电极在所述衬底基板上的正投影均为矩形。
  22. 根据权利要求10所述的显示基板，其中，所述边框区域包括上边框， 所述上边框设置有第二电源线结构，所述第二电源线结构包括阵列排布的多个第四重复单元，所述第四重复单元的形状、大小和连接关系与所述第一重复单元的形状、大小和连接关系大致相同；
    所述第二重复单元在所述衬底基板的正投影与所述第四重复单元在所述衬底基板的正投影具有交叠。
  23. 根据权利要求22所述的显示基板，其中，所述显示区域设置有多个电源连接块；所述第二电源线结构通过第二连接线与所述显示区域的电源连接块电连接；
    所述第二连接线具有直线部分和弯折部分，所述第二连接线靠近所述衬底基板一侧设置有多条数据线，所述第二连接线在所述衬底基板上的正投影与所述多条数据线在所述衬底基板上的正投影没有交叠，所述第二连接线的直线部分的虚拟延长线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影具有交叠。
  24. 根据权利要求23所述的显示基板，其中，所述电源连接块包括：层叠设置且相互电连接的第一子电源连接块和第二子电源连接块，所述第一子电源连接块在所述衬底基板上的正投影为沿第二方向延伸的条状，所述第二子电源连接块在所述衬底基板上的正投影包含所述第一子电源连接块在所述衬底基板上的正投影。
  25. 一种显示装置，包括如权利要求1至24中任一项所述的显示基板。
PCT/CN2022/110257 2021-08-11 2022-08-04 显示基板及显示装置 WO2023016335A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170110521A1 (en) * 2015-10-19 2017-04-20 Samsung Display Co., Ltd. Transparent display apparatus
CN210349841U (zh) * 2019-09-19 2020-04-17 昆山工研院新型平板显示技术中心有限公司 一种显示面板和显示装置
CN112667107A (zh) * 2020-12-31 2021-04-16 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN113053955A (zh) * 2019-12-27 2021-06-29 乐金显示有限公司 透明显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170110521A1 (en) * 2015-10-19 2017-04-20 Samsung Display Co., Ltd. Transparent display apparatus
CN210349841U (zh) * 2019-09-19 2020-04-17 昆山工研院新型平板显示技术中心有限公司 一种显示面板和显示装置
CN113053955A (zh) * 2019-12-27 2021-06-29 乐金显示有限公司 透明显示装置
CN112667107A (zh) * 2020-12-31 2021-04-16 上海天马有机发光显示技术有限公司 显示面板及显示装置

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