WO2022252069A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022252069A1
WO2022252069A1 PCT/CN2021/097460 CN2021097460W WO2022252069A1 WO 2022252069 A1 WO2022252069 A1 WO 2022252069A1 CN 2021097460 W CN2021097460 W CN 2021097460W WO 2022252069 A1 WO2022252069 A1 WO 2022252069A1
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WIPO (PCT)
Prior art keywords
layer
area
display panel
chip body
binding
Prior art date
Application number
PCT/CN2021/097460
Other languages
English (en)
French (fr)
Inventor
万彬
王小元
吴君辉
陈俊明
杨国栋
郑小双
范志成
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001377.7A priority Critical patent/CN115701292A/zh
Priority to PCT/CN2021/097460 priority patent/WO2022252069A1/zh
Publication of WO2022252069A1 publication Critical patent/WO2022252069A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • Liquid crystal display as the most widely used flat-panel display, occupies an important position in display panels.
  • Display products are constantly being upgraded, and users have higher and higher demands for narrow bezel display products.
  • the output pins on the left and right sides of the driver chip are now lower than those in the middle. Increase the wiring space of the fan-out line and reduce the lower edge of the display panel.
  • the driver chip is bonded, there is no support in the area on both sides of the output pin in the middle position, and this area is easy to collapse, which makes the middle position tilt up, which leads to the problem of uneven and shallow indentation of the binding pins in the middle position.
  • a display panel provided by an embodiment of the present disclosure includes:
  • the display substrate includes: a display area and a peripheral area outside the display area; the peripheral area includes a binding area; the display substrate specifically includes: a base substrate, the peripheral area is located on one side of the base substrate and extends to the binding area A plurality of fan-out lines, a plurality of first binding electrodes electrically connected to the fan-out lines in the binding area in one-to-one correspondence;
  • the driver chip includes: a driver chip body, and a plurality of pins located on the side of the driver chip body facing the display substrate; the plurality of pins include: a plurality of output pins bound to the first binding electrodes in one-to-one correspondence;
  • the supporting structure is located between the driver chip body and the substrate, and is in contact with both the driver chip body and the substrate; the orthographic projection of the support structure on the substrate and the orthographic projection of the fan-out line on the substrate do not overlap each other; The orthographic projection of the support structure on the driver chip body and the orthographic projection of the pins on the driver chip body do not overlap each other.
  • the driver chip body includes: a first area and second areas located on both sides of the first area;
  • the plurality of input pins includes: a plurality of first output pins located in the first area, and a plurality of second output pins located in the second area;
  • each first area a plurality of first output pins are arranged in at least one row of first output pins extending along the first direction; in each second area, a plurality of second output pins are arranged in at least one A row of second output pin rows; the second output pin rows located on both sides of the first area extend along the second direction and the third direction respectively, and the second direction and the third direction are away from the side of the display area relative to the first direction deflection; in each second output pin row, a plurality of second output pins are arranged along the second direction or the third direction and away from the display area;
  • At least part of the supporting structure falls into the second region in the orthographic projection of the driving chip body.
  • the driver chip body further includes: a third area located on one side of the first area;
  • the plurality of pins also includes a plurality of input pins located in the third zone;
  • At least part of the support structure falls into the third area between the input pin and the first output pin in the orthographic projection of the driver chip body.
  • the area between the input pins and the first output pins includes a plurality of support structure rows; the extension direction of the support structure rows is the same as the extension direction of the first output pin row;
  • the support structures in two adjacent support structure rows are arranged in a dislocation in the extending direction of the support structure row.
  • the distance between two adjacent support structures close to the first area is greater than the distance between two adjacent support structures far away from the first area.
  • support structures include:
  • an insulating layer located on the side of the first supporting layer away from the base substrate;
  • the second supporting layer is located on the side of the insulating layer away from the first supporting layer.
  • the supporting structure further includes: dummy pins located between the driver chip body and the second supporting layer.
  • the first supporting layer is arranged on the same layer as the fan-out line; the second supporting layer is arranged on the same layer as the first binding electrode.
  • the display area includes:
  • the first conductive layer includes: a plurality of scanning signal lines electrically connected to the fan-out lines in one-to-one correspondence;
  • the gate insulating layer is located on the side of the scanning signal line away from the substrate;
  • the pixel electrode layer is located on the side of the gate insulating layer away from the scanning signal line;
  • the second conductive layer located on the side of the pixel electrode layer away from the gate insulating layer, includes a plurality of data signal lines;
  • a protective layer located on the side of the second conductive layer away from the pixel electrode layer;
  • the common electrode layer is located on the side of the protective layer away from the second conductive layer;
  • the second supporting layer and the first binding electrode are arranged on the same layer as the common electrode layer, and the insulating layer at least includes a protective layer extending to the peripheral area.
  • the fan-out line is disposed on the same layer as the first conductive layer; the insulating layer further includes a gate insulating layer extending to the peripheral region.
  • the fan-out line is disposed on the same layer as the second conductive layer; the supporting structure further includes a gate insulating layer extending to the peripheral region.
  • support structures include:
  • a dummy pin located between the driver chip body and the insulating layer.
  • the distance between the orthographic projection of the driving chip body and the edge of the driving chip body of the supporting structure located in the second region is less than or equal to 200 microns.
  • the distance between the support structure located in the second region and the adjacent fan-out line is greater than or equal to 10 microns.
  • the display panel also includes:
  • a plurality of second binding electrodes are located on the same side of the base substrate as the first binding electrodes in the binding area; the second binding electrodes are bound to the input pins in one-to-one correspondence;
  • the length of the second binding electrode in the extending direction of the fan-out line is greater than the length of the input pin in the extending direction of the fan-out line; the length of the second binding electrode in the extending direction of the fan-out line is greater than or equal to 100 microns and less than or equal to 150 microns.
  • An embodiment of the present disclosure provides a display device, and the display device includes the display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a driving chip in a display panel provided by an embodiment of the present disclosure
  • Fig. 3 is a cross-sectional view along AA' in Fig. 1 provided by an embodiment of the present disclosure
  • Figure 4 is another cross-sectional view along AA' in Figure 1 provided by the embodiment of the present disclosure.
  • Figure 5 is another cross-sectional view along AA' in Figure 1 provided by the embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another driving chip in a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another driving chip in a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another driving chip in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display panel. As shown in FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , and FIG. 5 , the display panel includes:
  • the display substrate 37 includes: the display area 2 and the peripheral area 3 located outside the display area 2; the peripheral area 3 includes the binding area 4; the display substrate 37 specifically includes: the base substrate 1; the base substrate 1 located in the peripheral area 3 A plurality of fan-out lines 5 extending to one side of the binding area 4, and a plurality of first binding electrodes 6 electrically connected to the fan-out lines 5 in the binding area 4 in one-to-one correspondence;
  • the driver chip 7 includes: a driver chip body 8, and a plurality of pins 9 located on the side of the driver chip body 8 facing the display substrate 37; the plurality of pins 9 include: one-to-one binding electrodes 6 multiple output pins 10;
  • the supporting structure 11 is located between the driving chip body 8 and the base substrate 1, and is in contact with both the driving chip body 8 and the base substrate 1;
  • the orthographic projections of 1 do not overlap each other; the orthographic projections of the support structure 11 on the driver chip body 8 and the orthographic projections of the pins 9 on the driver chip body 8 do not overlap each other.
  • a plurality of support structures are provided between the driver chip body and the base substrate, and the support structures are in contact with both the driver chip body and the
  • the area outside the binding between the pin and the binding electrode realizes the support for the driver chip body and the substrate substrate, which can avoid the problem of easy collapse in the area outside the binding between the pin and the binding electrode, and avoid the occurrence of partial warping of the driving chip.
  • the problem of uneven indentation and shallow indentation of the binding pins can be solved, thereby improving the reliability of the display panel and improving the production yield of the display panel.
  • Fig. 3, Fig. 4 and Fig. 5 may be, for example, cross-sectional views along AA' in Fig. 1 .
  • the plurality of fan-out lines are arranged along the first direction X.
  • the driver chip body 8 includes: a first area 12 and second areas 13 located on both sides of the first area 12 ;
  • the plurality of input pins 10 includes: a plurality of first output pins 18 located in the first area 12, and a plurality of second output pins 19 located in the second area 13;
  • each first area 12 a plurality of first output pins 18 are arranged in at least one row of first output pin rows 21 extending along the first direction X; in each second area 13, a plurality of second output pins The pins 19 are arranged into at least one row of second output pin rows 22; the second output pin rows 22 located on both sides of the first area 12 extend along the second direction Z1 and the third direction Z2 respectively, and the second direction Z1 and the third direction Z2 extend respectively.
  • the direction Z2 intersects the first direction X, and the second direction Z1 and the third direction Z2 are deflected to the side away from the display area relative to the first direction X; in each second output pin row, a plurality of second output pins
  • the feet are arranged along the second direction Z1 or the third direction Z2 and away from the display area.
  • the second output pins located on both sides of the first area are arranged in a sunken manner on the side away from the display area compared with the first output pins. Since the output pin is bonded to the first bonding electrode, correspondingly, the bonding of the first bonding electrode is also arranged in a sunken arrangement, which can increase the wiring space of the fan-out line and reduce the size of the surrounding area including the bonding area , which is beneficial to realize the narrow frame of the display panel.
  • At least part of the supporting structure 11 falls into the second region 13 in the orthographic projection of the driving chip body 8 .
  • a support structure is provided at least in the second area, so as to avoid the problem that the edge of the second area is unsupported and prone to collapse due to the sunken arrangement of the output pins and the first binding electrodes. , thereby avoiding the problem of uneven and shallow indentation of the bonding pins caused by the warping of the first area of the driver chip, thereby improving the reliability of the display panel and improving the production yield of the display panel.
  • the driver chip body 8 further includes: a third area 14 located on one side of the first area 12 ;
  • the plurality of pins 9 also includes a plurality of input pins 20 located in the third zone 14;
  • At least part of the support structure 11 falls into the third area 14 between the input pin 20 and the first output pin 18 in the orthographic projection of the driver chip body 7 .
  • the area between the first output pin and the input pin is unsupported, which is prone to collapse, causing the input pin to lift and affecting the reliability of the display panel.
  • a plurality of supporting structures are provided in the third area between the first output pin and the input pin, so that the area between the first output pin and the input pin can be supported , to avoid the problem of tilting of the input pin, and avoid the problem of uneven and shallow indentation of the binding pin, thereby improving the reliability of the display panel and improving the production yield of the display panel.
  • the third area 14 between the input pin 20 and the first output pin 18 includes a row of support structures 11 as an example for illustration.
  • the third region 14 between the first output pins 18 may also include multiple support structure rows 23 . In order to further improve the supporting effect between the drive chip body and the base substrate.
  • the extending direction of the support structure row 23 is the same as the extending direction of the first output pin row 21 . That is, the support structure row 23 extends along the first direction X.
  • the supporting structures 11 in two adjacent supporting structure rows 23 are arranged in an offset direction in the extending direction of the supporting structure rows 23 . In order to further improve the supporting effect between the drive chip body and the base substrate.
  • the third area includes two rows of support structure rows as an example for illustration.
  • the third area may include more rows of support structure rows.
  • the number of support structure rows can be set according to the actual size of the area between the first output pin and the input pin.
  • the plurality of support structures 11 corresponding to each second region 13 are arranged in a row along the first direction X.
  • the distance between two adjacent support structures 11 close to the first zone 12 is greater than that far away from the first zone 12 The distance between two adjacent supporting structures 11.
  • the closer to the first area the greater the number of fan-out lines. Since the setting of the support structure needs to avoid fan-out lines, it can be set so that the distance between two adjacent support structures close to the first area is greater than the original farther away from the first area. The distance between two adjacent supporting structures in the zone.
  • the support structure can be fabricated on the base substrate, for example, that is, the support structure is fabricated during the process of fabricating the display substrate.
  • the support structure 11 includes:
  • the insulating layer 25 is located on the side of the first supporting layer 24 away from the base substrate 1;
  • the second supporting layer 26 is located on a side of the insulating layer 25 away from the first supporting layer 24 .
  • the second support layer is in contact with the driver chip body 8 as an example for illustration.
  • the support structure may be fabricated on the driver chip body, for example.
  • the support structure 11 includes:
  • a dummy pin 27 located between the driver chip body 8 and the insulating layer 24 .
  • the support structure may include, for example, a part fabricated on the base substrate and a part fabricated on the driver chip body.
  • the supporting structure 11 further includes: a dummy guide between the driver chip body 8 and the second supporting layer Feet 27.
  • the dummy pins 27 are in contact with both the driver chip body 8 and the second supporting layer 26 .
  • the first support layer 25 is set on the same layer as the fan-out line 5; the second support layer 26 is set on the same layer as the first binding electrode 6; the dummy pin 27 is set on the same layer as the driver chip Each pin is set on the same layer.
  • the first support layer is formed while forming the fan-out lines
  • the second support layer is formed while the first bonding electrodes are formed
  • the dummy pins are formed while the pins are formed when the driver chip is manufactured.
  • the display panel provided by the embodiments of the present disclosure is a liquid crystal display panel.
  • the display panel is a liquid crystal display panel, it further includes: an opposite substrate disposed opposite to the display substrate, and a liquid crystal layer located between the display substrate and the opposite substrate.
  • each film layer of the display substrate bound to the driving chip will be described as an example.
  • the display area 2 includes:
  • the first conductive layer 30 includes: a plurality of scanning signal lines 15 electrically connected to the fan-out lines 5 in one-to-one correspondence, and a gate 31 of the driving transistor;
  • the gate insulating layer 28 is located on the side of the scanning signal line 15 away from the base substrate 1;
  • the pixel electrode layer 32 is located on the side of the gate insulating layer 28 away from the first conductive layer 30;
  • the second conductive layer 33 located on the side of the pixel electrode layer 32 away from the gate insulating layer 28, includes: a plurality of data signal lines (not shown), and a source 34 and a drain 35 of the driving transistor;
  • the protection layer 29 is located on the side of the second conductive layer 33 away from the pixel electrode layer 32;
  • the common electrode layer 36 is located on a side of the protection layer 29 away from the second conductive layer 33 .
  • a plurality of scanning signal lines 15 are arranged along a first direction X, and each scanning signal line 15 extends along a fourth direction Y.
  • the first direction X intersects the fourth direction Y.
  • the first direction X is perpendicular to the fourth direction Y.
  • a plurality of scanning signal lines and a plurality of data signal lines are arranged to intersect. That is, the plurality of data signal lines are arranged along the fourth direction Y, for example, and each data signal line extends along the first direction X.
  • the second supporting layer 26 and the first binding electrode 6 are disposed on the same layer as the common electrode layer, and the insulating layer 24 at least includes a protective layer 29 extending to the peripheral area.
  • both the first supporting layer 25 and the fan-out line 5 are disposed on the same layer as the first conductive layer; the insulating layer 24 further includes a gate insulating layer 28 extending to the peripheral region.
  • the first support layer 25 and the fan-out lines 5 and the second conductive layer are arranged in the same layer; the support structure 11 further includes a gate insulating layer 28 extending to the peripheral region.
  • the display panel provided by the embodiments of the present disclosure may also be an electroluminescent display panel.
  • the electroluminescent display panel specifically includes: an active layer, a gate insulating layer, a third conductive layer, an interlayer insulating layer, a fourth conductive layer, a planarization layer, and an anode sequentially arranged on the base substrate. layer, pixel definition layer, light emitting function layer and cathode layer.
  • the third conductive layer includes, for example, gates of transistors and scanning signal lines.
  • the fourth conductive layer includes, for example, sources and drains of transistors and data signal lines.
  • the first support layer and the fan-out line of the support structure can be arranged on the same layer as the third conductive layer, the second support layer of the support structure and the first binding electrode can be arranged on the same layer as the anode layer, for example, the first
  • the insulating layer between the supporting layer and the second supporting layer includes an interlayer insulating layer and a planarization layer, and the supporting structure further includes a gate insulating layer.
  • first support layer and the fan-out line of the support structure can be arranged on the same layer as the fourth conductive layer, the second support layer and the first binding electrode of the support structure are arranged on the same layer as the anode layer, and the first support layer
  • the insulation layer between the second support layer and the second support layer includes a layer planarization layer, and the support structure further includes an inter-insulation layer and a gate insulation layer.
  • the distance between the orthographic projection of the driving chip body and the edge of the driving chip body of the supporting structure located in the second region is less than or equal to 200 microns.
  • the distance between the support structure located in the second region and the adjacent fan-out line is greater than or equal to 10 microns.
  • the display panel further includes:
  • a plurality of second binding electrodes 16 are located on the same side of the base substrate 1 in the binding area 4 as the first binding electrodes 6; the second binding electrodes 16 are bound to the input pins in one-to-one correspondence;
  • the length of the second binding electrode in the extending direction of the fan-out line is greater than the length of the input pin in the extending direction of the fan-out line, and the length of the second binding electrode in the extending direction of the fan-out line is greater than or equal to 100 microns And less than or equal to 150 microns.
  • the display panel provided by the embodiments of the present disclosure is equivalent to increasing the length of the second binding electrode in the fourth direction, which can further improve the supporting effect between the driving chip body and the base substrate.
  • the second binding electrode is disposed on the same layer as the first binding electrode.
  • the display panel further includes: connecting leads 17 .
  • the connection lead is electrically connected to the flexible circuit board, so that the flexible circuit board can be used to provide signals to the driving chip.
  • connection leads and the fan-out lines are arranged on the same layer.
  • An embodiment of the present disclosure provides a display device, and the display device includes the display panel provided by the embodiment of the present disclosure.
  • the display device is any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.
  • a plurality of support structures are provided between the driver chip body and the substrate substrate, and the support structures are connected to the driver chip body and the substrate in the area where pins are not provided.
  • the substrates are all in contact, so that the driver chip body and the substrate substrate can be supported in areas other than the binding of the pins and the binding electrodes, which can avoid the problem of easy collapse in areas other than the binding of the pins and the binding electrodes To avoid the problem of uneven and shallow indentation of the bonding pins caused by the warping of some areas of the driver chip, thereby improving the reliability of the display panel and improving the production yield of the display panel.

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Abstract

本公开实施例提供的显示面板及显示装置，显示面板包括：显示基板，包括：显示区以及位于显示区之外的周边区；周边区包括绑定区；显示基板具体包括：衬底基板，在周边区位于衬底基板的一侧且延伸至绑定区的多条扇出线，在绑定区与扇出线一一对应电连接的多个第一绑定电极；驱动芯片，包括：驱动芯片本体，以及位于驱动芯片本体面向显示基板一侧的多个引脚；多个引脚包括：与第一绑定电极一一对应绑定的多个输出引脚；支撑结构，位于驱动芯片本体与衬底基板之间，且与驱动芯片本体以及衬底基板均接触；支撑结构在衬底基板的正投影与扇出线在衬底基板的正投影互不交叠；支撑结构在驱动芯片本体的正投影与引脚在驱动芯片本体的正投影互不交叠。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着信息技术的发展，电子设备在人们日常生活中被广泛应用，液晶显示器作为一种最广泛使用的平面显示器，在显示面板中占有重要地位。显示产品不断升级换代，用户对窄边框显示产品的需求越来越高，为满足更窄边框的需求，目前将驱动芯片左右双边输出引脚相较中间位置有下沉。增大扇出线布线空间，减小显示面板下边缘。但在驱动芯片绑定之后，中间位置输出引脚两侧区域无支撑，该区域容易塌陷，使得中间位置翘起，从而导致中间位置存在绑定引脚压痕不均、压痕浅的问题，严重影响产品的信赖性。
发明内容
本公开实施例提供的一种显示面板，显示面板包括：
显示基板，包括：显示区以及位于显示区之外的周边区；周边区包括绑定区；显示基板具体包括：衬底基板，在周边区位于衬底基板的一侧且延伸至绑定区的多条扇出线，在绑定区与扇出线一一对应电连接的多个第一绑定电极；
驱动芯片，包括：驱动芯片本体，以及位于驱动芯片本体面向显示基板一侧的多个引脚；多个引脚包括：与第一绑定电极一一对应绑定的多个输出引脚；
支撑结构，位于驱动芯片本体与衬底基板之间，且与驱动芯片本体以及衬底基板均接触；支撑结构在衬底基板的正投影与扇出线在衬底基板的正投影互不交叠；支撑结构在驱动芯片本体的正投影与引脚在驱动芯片本体的正投影互不交叠。
在一些实施例中，驱动芯片本体包括：第一区以及位于第一区两侧的第二区；
多个输入引脚包括：位于第一区的多个第一输出引脚，以及位于第二区的多个第二输出引脚；
在每一第一区，多个第一输出引脚排列成至少一排沿第一方向延伸的第一输出引脚排；在每一第二区，多个第二输出引脚排列成至少一排第二输出引脚排；位于第一区两侧的第二输出引脚排分别沿第二方向以及第三方向延伸，且第二方向以及第三方向相对于第一方向远离显示区一侧偏折；每一第二输出引脚排中，多个第二输出引脚沿第二方向或第三方向且向远离显示区一侧排列；
至少部分支撑结构在驱动芯片本体的正投影落入第二区。
在一些实施例中，驱动芯片本体还包括：位于第一区一侧的第三区；
多个引脚还包括位于第三区的多个输入引脚；
至少部分支撑结构在驱动芯片本体的正投影落入输入引脚与第一输出引脚之间的第三区。
在一些实施例中，输入引脚与第一输出引脚之间的区域包括多个支撑结构排；支撑结构排的延伸方向与第一输出引脚排的延伸方向相同；
相邻两个支撑结构排中的支撑结构在支撑结构排的延伸方向上错位排列。
在一些实施例中，每一第二区，靠近第一区相邻两个支撑结构之间的距离，大于远离第一区相邻两个支撑结构之间的距离。
在一些实施例中，支撑结构包括：
第一支撑层；
绝缘层，位于第一支撑层背离衬底基板的一侧；
第二支撑层，位于绝缘层背离第一支撑层的一侧。
在一些实施例中，支撑结构还包括：位于驱动芯片本体与第二支撑层之间的虚设引脚。
在一些实施例中，第一支撑层与扇出线同层设置；第二支撑层与第一绑 定电极同层设置。
在一些实施例中，显示区包括：
第一导电层，包括：与扇出线一一对应电连接的多条扫描信号线；
栅绝缘层，位于扫描信号线背离衬底基板的一侧；
像素电极层，位于栅绝缘层背离扫描信号线的一侧；
第二导电层，位于像素电极层背离栅绝缘层的一侧，包括多条数据信号线；
保护层，位于第二导电层背离像素电极层一侧；
公共电极层，位于保护层背离第二导电层的一侧；
二支撑层以及第一绑定电极与公共电极层同层设置，绝缘层至少包括延伸到周边区的保护层。
在一些实施例中，扇出线与第一导电层同层设置；绝缘层还包括延伸到周边区的栅绝缘层。
在一些实施例中，扇出线与第二导电层同层设置；支撑结构还包括延伸到周边区的栅绝缘层。
在一些实施例中，支撑结构包括：
绝缘层；
位于驱动芯片本体与绝缘层之间的虚设引脚。
在一些实施例中，位于第二区的支撑结构在驱动芯片本体的正投影与驱动芯片本体边缘之间的距离小于等于200微米。
在一些实施例中，位于第二区的支撑结构与相邻扇出线之间的距离大于等于10微米。
在一些实施例中，显示面板还包括：
多个第二绑定电极，在绑定区与第一绑定电极位于衬底基板的同一侧；第二绑定电极与输入引脚一一对应绑定；
第二绑定电极在扇出线延伸方向上的长度大于输入引脚在扇出线延伸方向上的长度；第二绑定电极在扇出线延伸方向上的长度大于等于100微米且 小于等于150微米。
本公开实施例提供的一种显示装置，显示装置包括本公开实施例提供的显示面板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示面板的结构示意图；
图2为本公开实施例提供的一种显示面板中驱动芯片的结构示意图；
图3为本公开实施例提供的一种沿图1中AA’的截面图；
图4为本公开实施例提供的另一种沿图1中AA’的截面图；
图5为本公开实施例提供的又一种沿图1中AA’的截面图；
图6为本公开实施例提供的另一种显示面板的结构示意图；
图7为本公开实施例提供的另一种显示面板中驱动芯片的结构示意图；
图8为本公开实施例提供的又一种显示面板中驱动芯片的结构示意图；
图9为本公开实施例提供的又一种显示面板中驱动芯片的结构示意图；
图10为本公开实施例提供的又一种显示面板的结构示意图；
图11为本公开实施例提供的又一种显示面板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所 获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供了一种显示面板，如图1、图2、图3、图4、图5所示，显示面板包括：
显示基板37，包括：显示区2以及位于显示区2之外的周边区3；周边区3包括绑定区4；显示基板37具体包括：衬底基板1；在周边区3位于衬底基板1的一侧且延伸至绑定区4的多条扇出线5，在绑定区4与扇出线5一一对应电连接的多个第一绑定电极6；
驱动芯片7，包括：驱动芯片本体8，以及位于驱动芯片本体8面向显示基板37一侧的多个引脚9；多个引脚9包括：与第一绑定电极6一一对应绑定的多个输出引脚10；
支撑结构11，位于驱动芯片本体8与衬底基板1之间，且与驱动芯片本体8以及衬底基板1均接触；支撑结构11在衬底基板1的正投影与扇出线5在衬底基板1的正投影互不交叠；支撑结构11在驱动芯片本体8的正投影与引脚9在驱动芯片本体8的正投影互不交叠。
本公开实施例提供的显示面板，在驱动芯片本体与衬底基板之间设置多个支撑结构，该支撑结构在未设置引脚的区域与驱动芯片本体和衬底基板均接触，从而可以在引脚与绑定电极绑定之外的区域实现对驱动芯片本体和衬 底基板的支撑，可以避免引脚与绑定电极绑定之外的区域容易出现塌陷的问题，避免出现驱动芯片部分区域翘起导致的绑定引脚压痕不均、压痕浅的问题，从而可以提高显示面板的信赖性、提高显示面板的制作良率。
需要说明的是，图1中仅示出部分显示区，且仅采用虚线示出驱动芯片本体覆盖的区域，并未示出引脚。图3、图4、图5例如可以是沿图1中AA’的截面图。
在一些实施例中，多条扇出线沿第一方向X排列。
在一些实施例中，如图1、图2所示，驱动芯片本体8包括：第一区12以及位于第一区12两侧的第二区13；
多个输入引脚10包括：位于第一区12的多个第一输出引脚18，以及位于第二区13的多个第二输出引脚19；
在每一第一区12，多个第一输出引脚18排列成至少一排沿第一方向X延伸的第一输出引脚排21；在每一第二区13，多个第二输出引脚19排列成至少一排第二输出引脚排22；位于第一区12两侧的第二输出引脚排22分别沿第二方向Z1以及第三方向Z2延伸，第二方向Z1以及第三方向Z2与第一方向X交叉，且第二方向Z1以及第三方向Z2相对于第一方向X向远离显示区一侧偏折；每一第二输出引脚排中，多个第二输出引脚沿第二方向Z1或第三方向Z2且向远离显示区一侧排列。
即本公开实施例提供的显示面板中，位于第一区两侧的第二输出引脚相比于第一输出引脚向远离显示区一侧下沉式排列。由于输出引脚与第一绑定电极绑定，相应的，第一绑定电极绑定也采用下沉式排列，这样可以增大扇出线布线空间，减小包括绑定区的周边区的尺寸，有利于实现显示面板的窄边框。
在一些实施例中，如图1、图2所示，至少部分支撑结构11在驱动芯片本体8的正投影落入第二区13。
本公开实施例提供的显示面板，至少在第二区设置支撑结构，从而可以避免由于输出引脚以及第一绑定电极采用下沉式排列方式导致第二区边缘无 支撑而容易出现塌陷的问题，进而可以避免出现驱动芯片第一区翘起导致的绑定引脚压痕不均、压痕浅的问题，从而可以提高显示面板的信赖性、提高显示面板的制作良率。
在一些实施例中，如图6、图7所示，驱动芯片本体8还包括：位于第一区12一侧的第三区14；
多个引脚9还包括位于第三区14的多个输入引脚20；
至少部分支撑结构11在驱动芯片本体7的正投影落入输入引脚20与第一输出引脚18之间的第三区14。
需要说明的是，相关技术中，第一输出引脚与输入引脚之间的区域无支撑，容易出现塌陷，造成输入引脚翘起，影响显示面板的信赖性。
本公开实施例提供的显示面板，在第一输出引脚与输入引脚之间的第三区设置多个支撑结构，从而可以实现对第一输出引脚与输入引脚之间的区域进行支撑，避免出现输入引脚翘起的问题，避免绑定引脚压痕不均、压痕浅的问题，从而可以提高显示面板的信赖性、提高显示面板的制作良率。
需要说明的是，图6、图7中以输入引脚20与第一输出引脚18之间的第三区14包括一排支撑结构11为例进行举例说明。
在一些实施例中，如图8、图9所示，也可以是第一输出引脚18之间的第三区14包括多支撑结构排23。以进一步提高对驱动芯片本体与衬底基板之间的支撑效果。
在一些实施例中，如图8、图9所示，支撑结构排23的延伸方向与第一输出引脚排21的延伸方向相同。即支撑结构排23沿第一方向X延伸。
在一些实施例中，如图9所示，相邻两个支撑结构排23中的支撑结构11在支撑结构排23的延伸方向上错位排列。以进一步提高对驱动芯片本体与衬底基板之间的支撑效果。
需要说明的是，图8、图9中以第三区包括两排支撑结构排为例进行举例说明，当然，第三区可以包括更多排支撑结构排。在具体实施时，可以根据第一输出引脚和输入引脚之间区域的实际大小对支撑结构排数量进行设置。
在一些实施例中，如图1、图2、图6、图7、图8、图9所示，每一第二区13对应的多个支撑结构11沿第一方向X排列成一排。
从而可以在实现对驱动芯片本体与阵列基板之间支撑的同时避免过多减小扇出线布线空间。
在一些实施例中，如图1、图2、图6、图7、图8、图9所示，靠近第一区12相邻两个支撑结构11之间的距离，大于远离第一区12相邻两个支撑结构11之间的距离。
需要说明的是，越靠近第一区扇出线数量越多，由于支撑结构的设置需要避让扇出线，因此可以设置为在靠近第一区相邻两个支撑结构之间的距离大于原远离第一区相邻两个支撑结构之间的距离。
在具体实施时，支撑结构例如可以在衬底基板上制作，即在制作显示基板的过程中制作支撑结构。
在一些实施例中，如图3所示，支撑结构11包括：
第一支撑层24；
绝缘层25，位于第一支撑层24背离衬底基板1的一侧；
第二支撑层26，位于绝缘层25背离第一支撑层24的一侧。
需要说明的是，图3中以第二支撑层与驱动芯片本体8接触为例进行举例说明。
或者，在具体实施时，支撑结构例如可以在驱动芯片本体上制作。
在一些实施例中，如图5所示，支撑结构11包括：
绝缘层24；
位于驱动芯片本体8与绝缘层24之间的虚设引脚27。
或者，在具体实施时，支撑结构例如可以包括在衬底基板上制作的部分以及在驱动芯片本体上制作的部分。
在一些实施例中，如图4所示，第一支撑层24，绝缘层25，第二支撑层26；支撑结构11还包括：位于驱动芯片本体8与第二支撑层26之间的虚设引脚27。
如图4所示，虚设引脚27与驱动芯片本体8和第二支撑层26均接触。
在一些实施例中，如图4所示，第一支撑层25与扇出线5同层设置；第二支撑层26与第一绑定电极6同层设置；虚设引脚27与驱动芯片中的各引脚同层设置。
即在形成扇出线的同时形成第一支撑层，在形成第一绑定电极的同时形成第二支撑层，在制作驱动芯片时，形成引脚的同时形成虚设引脚。这样，可以在不增加显示面板制备流程的同时，实现在阴极以及扇出线之外的区域对驱动芯片本体进行支撑，可以在避免引脚翘起的同时，节省成本。
在一些实施例中，本公开实施例提供的显示面板为液晶显示面板。当显示面板为液晶显示面板时，还包括：与显示基板相对设置的对向基板，以及位于显示基板和对向基板之间的液晶层。
接下来以显示面板为液晶显示面板为例，对与驱动芯片绑定的显示基板各膜层进行举例说明。
在一些实施例中，如图1、图10所示，显示区2包括：
第一导电层30，包括：与扇出线5一一对应电连接的多条扫描信号线15，以及驱动晶体管的栅极31；
栅绝缘层28，位于扫描信号线15背离衬底基板1的一侧；
像素电极层32，位于栅绝缘层28背离第一导电层30的一侧；
第二导电层33，位于像素电极层32背离栅绝缘层28的一侧，包括：多条数据信号线(未示出)，以及驱动晶体管的源极34和漏极35；
保护层29，位于第二导电层33背离像素电极层32一侧；
公共电极层36，位于保护层29背离第二导电层33的一侧。
在一些实施例中，如图1所示，多条扫描信号线15沿第一方向X排列，每一扫描信号线15沿第四方向Y延伸。第一方向X与第四方向Y交叉，图1中，第一方向X与第四方向Y垂直。在具体实施时，多条扫描信号线和多条数据信号线交叉设置。即，多条数据信号线例如沿第四方向Y排列，每一数据信号线沿第一方向X延伸。
在一些实施例中，如图4所示，第二支撑层26以及第一绑定电极6与公共电极层同层设置，绝缘层24至少包括延伸到周边区的保护层29。
在一些实施例中，如图4所示，第一支撑层25以及扇出线5均与第一导电层同层设置；绝缘层24还包括延伸到周边区的栅绝缘层28。
在一些实施例中，如图11所示，第一支撑层25以及扇出线5扇出线与第二导电层同层设置；支撑结构11还包括延伸到周边区的栅绝缘层28。
当然，在一些实施例中，本公开实施例提供的显示面板也可以是电致发光显示面板。在一些实施例中，电致发光显示面板具体包括：在衬底基板上依次设置的有源层、栅绝缘层、第三导电层、层间绝缘层、第四导电层、平坦化层、阳极层、像素定义层、发光功能层以及阴极层。第三导电层例如包括晶体管的栅极以及扫描信号线。第四导电层例如包括晶体管的源极和漏极以及数据信号线。
在具体实施时，支撑结构的第一支撑层以及扇出线例如可以与第三导电层同层设置，支撑结构的第二支撑层以及第一绑定电极例如可以与阳极层同层设置，第一支撑层和第二支撑层之间的绝缘层包括层间绝缘层、平坦化层，支撑结构还包括栅绝缘层。当然，也可以是支撑结构的第一支撑层以及扇出线例如可以与第四导电层同层设置，支撑结构的第二支撑层以及第一绑定电极与阳极层同层设置，第一支撑层和第二支撑层之间的绝缘层包括层平坦化层，支撑结构还包括间绝缘层以及栅绝缘层。
为了进一步提高支撑结构的支撑效果，在一些实施例中，位于第二区的支撑结构在驱动芯片本体的正投影与驱动芯片本体边缘之间的距离小于等于200微米。
在一些实施例中，位于第二区的支撑结构与相邻扇出线之间的距离大于等于10微米。
这样，可以避免驱动芯片绑定时出现压伤扇出线的风险，保证显示面板良率。
在一些实施例中，如图1、图6所示，显示面板还包括：
多个第二绑定电极16，在绑定区4与第一绑定电极6位于衬底基板1的同一侧；第二绑定电极16与输入引脚一一对应绑定；
在一些实施例中，第二绑定电极在扇出线延伸方向上的长度大于输入引脚在扇出线延伸方向上的长度，且第二绑定电极在扇出线延伸方向上的长度大于等于100微米且小于等于150微米。
即本公开实施例提供的显示面板，相当于增大第二绑定电极在第四方向上的长度，可以进一步提高驱动芯片本体与衬底基板之间的支撑效果。
在一些实施例中，第二绑定电极与第一绑定电极同层设置。
在一些实施例中，如图1、图6所示，显示面板还包括：连接引线17。在具体实施时连接引线与柔性电路板电连接，从而可以利用柔性电路板向驱动芯片提供信号。
在一些实施例中，连接引线与扇出线同层设置。
本公开实施例提供了一种显示装置，显示装置包括本公开实施例提供的显示面板。
本公开实施例提供的显示装置为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
综上所述，本公开实施例提供的显示面板及显示装置，在驱动芯片本体与衬底基板之间设置多个支撑结构，该支撑结构在未设置引脚的区域与驱动芯片本体和衬底基板均接触，从而可以在引脚与绑定电极绑定之外的区域实现对驱动芯片本体和衬底基板的支撑，可以避免引脚与绑定电极绑定之外的区域容易出现塌陷的问题，避免出现驱动芯片部分区域翘起导致的绑定引脚压痕不均、压痕浅的问题，从而可以提高显示面板的信赖性、提高显示面板的制作良率。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了 基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示面板，其中，所述显示面板包括：
    显示基板，包括：显示区以及位于所述显示区之外的周边区；所述周边区包括绑定区；所述显示基板具体包括：衬底基板，在所述周边区位于所述衬底基板的一侧且延伸至所述绑定区的多条扇出线，在所述绑定区与所述扇出线一一对应电连接的多个第一绑定电极；
    驱动芯片，包括：驱动芯片本体，以及位于所述驱动芯片本体面向所述显示基板一侧的多个引脚；多个所述引脚包括：与所述第一绑定电极一一对应绑定的多个输出引脚；
    支撑结构，位于所述驱动芯片本体与所述衬底基板之间，且与所述驱动芯片本体以及所述衬底基板均接触；所述支撑结构在所述衬底基板的正投影与所述扇出线在所述衬底基板的正投影互不交叠；所述支撑结构在所述驱动芯片本体的正投影与所述引脚在所述驱动芯片本体的正投影互不交叠。
  2. 根据权利要求1所述的显示面板，其中，所述驱动芯片本体包括：第一区以及位于所述第一区两侧的第二区；
    多个所述输入引脚包括：位于所述第一区的多个第一输出引脚，以及位于所述第二区的多个第二输出引脚；
    在每一所述第一区，多个所述第一输出引脚排列成至少一排沿第一方向延伸的第一输出引脚排；在每一所述第二区，多个所述第二输出引脚排列成至少一排第二输出引脚排；位于所述第一区两侧的所述第二输出引脚排分别沿第二方向以及第三方向延伸，且所述第二方向以及所述第三方向相对于所述第一方向远离所述显示区一侧偏折；每一所述第二输出引脚排中，多个所述第二输出引脚沿所述第二方向或所述第三方向且向远离所述显示区一侧排列；
    至少部分所述支撑结构在所述驱动芯片本体的正投影落入所述第二区。
  3. 根据权利要求1或2所述的显示面板，其中，所述驱动芯片本体还包 括：位于所述第一区一侧的第三区；
    多个所述引脚还包括位于所述第三区的多个输入引脚；
    至少部分所述支撑结构在所述驱动芯片本体的正投影落入所述输入引脚与所述第一输出引脚之间的第三区。
  4. 根据权利要求3所述的显示面板，其中，所述输入引脚与所述第一输出引脚之间的区域包括多个支撑结构排；所述支撑结构排的延伸方向与所述第一输出引脚排的延伸方向相同；
    相邻两个所述支撑结构排中的所述支撑结构在所述支撑结构排的延伸方向上错位排列。
  5. 根据权利要求2～4任一项所述的显示面板，其中，每一所述第二区，靠近所述第一区相邻两个所述支撑结构之间的距离，大于远离所述第一区相邻两个所述支撑结构之间的距离。
  6. 根据权利要求1～5任一项所述的显示面板，其中，所述支撑结构包括：
    第一支撑层；
    绝缘层，位于所述第一支撑层背离所述衬底基板的一侧；
    第二支撑层，位于所述绝缘层背离所述第一支撑层的一侧。
  7. 根据权利要求6所述的显示面板，其中，所述支撑结构还包括：位于所述驱动芯片本体与所述第二支撑层之间的虚设引脚。
  8. 根据权利要求6～7任一项所述的显示面板，其中，所述第一支撑层与所述扇出线同层设置；所述第二支撑层与所述第一绑定电极同层设置。
  9. 根据权利要求8所述的显示面板，其中，所述显示区包括：
    第一导电层，包括：与所述扇出线一一对应电连接的多条扫描信号线；
    栅绝缘层，位于所述扫描信号线背离所述衬底基板的一侧；
    像素电极层，位于所述栅绝缘层背离所述扫描信号线的一侧；
    第二导电层，位于所述像素电极层背离所述栅绝缘层的一侧，包括多条数据信号线；
    保护层，位于所述第二导电层背离所述像素电极层一侧；
    公共电极层，位于所述保护层背离所述第二导电层的一侧；
    所述二支撑层以及所述第一绑定电极与所述公共电极层同层设置，所述绝缘层至少包括延伸到所述周边区的所述保护层。
  10. 根据权利要求9所述的显示面板，其中，所述扇出线与所述第一导电层同层设置；所述绝缘层还包括延伸到所述周边区的栅绝缘层。
  11. 根据权利要求9所述的显示面板，其中，所述扇出线与所述第二导电层同层设置；所述支撑结构还包括延伸到所述周边区的栅绝缘层。
  12. 根据权利要求1～5任一项所述的显示面板，其中，所述支撑结构包括：
    绝缘层；
    位于所述驱动芯片本体与所述绝缘层之间的虚设引脚。
  13. 根据权利要求2～12任一项所述的显示面板，其中，位于所述第二区的所述支撑结构在所述驱动芯片本体的正投影与所述驱动芯片本体边缘之间的距离小于等于200微米。
  14. 根据权利要求2～12任一项所述的显示面板，其中，位于所述第二区的所述支撑结构与相邻所述扇出线之间的距离大于等于10微米。
  15. 根据权利要求3或4所述的显示面板，其中，所述显示面板还包括：
    多个第二绑定电极，在所述绑定区与所述第一绑定电极位于所述衬底基板的同一侧；所述第二绑定电极与所述输入引脚一一对应绑定；
    所述第二绑定电极在所述扇出线延伸方向上的长度大于所述输入引脚在所述扇出线延伸方向上的长度；所述第二绑定电极在所述扇出线延伸方向上的长度大于等于100微米且小于等于150微米。
  16. 一种显示装置，其中，所述显示装置包括根据权利要求1～15任一项所述的显示面板。
PCT/CN2021/097460 2021-05-31 2021-05-31 显示面板及显示装置 WO2022252069A1 (zh)

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