WO2020199300A1 - 一种显示面板及其制作方法、显示装置 - Google Patents

一种显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2020199300A1
WO2020199300A1 PCT/CN2019/085505 CN2019085505W WO2020199300A1 WO 2020199300 A1 WO2020199300 A1 WO 2020199300A1 CN 2019085505 W CN2019085505 W CN 2019085505W WO 2020199300 A1 WO2020199300 A1 WO 2020199300A1
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Prior art keywords
line
substrate
layer
wire layer
power connection
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PCT/CN2019/085505
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English (en)
French (fr)
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魏锋
李金川
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020199300A1 publication Critical patent/WO2020199300A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

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  • This application relates to the technical field of display panels, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • Narrow bezels can make products more fashionable, which is the most intuitive function.
  • Display products with a narrow frame design have more advantages in the use of size.
  • the same size (including the outer frame) the narrow frame product screen display area is larger, for notebooks and mobile phones, means a smaller body, larger size.
  • the enhancement of product quality is also meaningful for users who pursue fashion.
  • the narrow frame also makes the picture look cleaner, which has a soft effect on enhancing the charm of the display.
  • the connection between the wire layer of the display device and the driving circuit is realized by the binding area located at the edge of the non-display area, and there is a problem that the binding area occupies the side space of the display device, which is not conducive to achieving narrow border display.
  • the present application provides a display panel, a manufacturing method thereof, and a display device to reduce the frame area of the display device, which is beneficial to realize a narrow frame display.
  • the embodiments of the present application provide a display panel, the display panel includes: a wire layer, the wire layer includes a binding area and a non-binding area; a substrate provided on the wire layer, the substrate is provided with conduction Holes; scan lines, data lines, and power connection lines arranged on the substrate, wherein the scan lines, data lines and power connection lines are connected to the binding area through via holes.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the display panel further includes a pixel electrode layer, the pixel electrode layer is located on the scan line, the data line and the power connection line, the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • the display panel further includes an encapsulation layer, the encapsulation layer is located on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-binding area of the wire layer.
  • the display panel further includes a thin film transistor and a flat layer sequentially arranged on the side of the substrate away from the wire layer.
  • the thin film transistor includes a gate electrode and a source/drain electrode. One end of the scan line is connected to the gate electrode, and the other end is connected to the via hole. One end of the data line is connected to the source/drain, the other end is connected to the through hole, one end of the power connection line is connected to the driving voltage input end of the thin film transistor, and the other end is connected to the through hole.
  • the embodiments of the present application also provide a method for manufacturing a display panel.
  • the manufacturing method includes: providing a substrate; making a via hole on the substrate; filling a conductive material in the via hole and forming on the substrate.
  • the wire layer, the wire layer includes a binding area and a non-binding area; on the side of the substrate away from the wire layer, a scan line, a data line and a power connection line are formed, wherein the scan line, the data line and the power connection line are conductive
  • the hole is connected to the binding area.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the method further includes: coating the entire surface of the scan lines, data lines, and power connection lines to form a pixel electrode layer, wherein,
  • the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a through hole.
  • the method further includes: forming an encapsulation layer on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-conductive layer of the wire layer. Binding area.
  • the step of forming scan lines, data lines, and power connection lines on the side of the substrate away from the wire layer specifically includes: forming a thin film transistor layer, a flat layer, and a thin film transistor layer on the side of the substrate away from the wire layer. It includes a thin film transistor, a scan line, a data line, and a power connection line.
  • the thin film transistor includes a gate, a source, and a drain. One end of the scan line is connected to the gate, the other end is connected to the via hole, and one end of the data line is connected to the The source or drain is connected, the other end is connected to the through hole, one end of the power connection line is connected to the driving voltage input end of the thin film transistor, and the other end is connected to the through hole.
  • the embodiment of the present application provides a display device, which includes a driving circuit and a display panel, wherein the display panel includes: a wire layer, the wire layer includes a binding area and a non-binding area; The substrate on the wire layer, the substrate is provided with a through hole; the scan line, the data line and the power connection line are provided on the substrate, wherein the scan line, the data line and the power connection line are connected to the binding area through the through hole; The driving circuit is connected with the scan line, the data line and the power connection line through the binding area.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area through via holes.
  • the binding areas are arranged in an array on the wire layer.
  • the display panel further includes a pixel electrode layer, the pixel electrode layer is located on the scan line, the data line and the power connection line, the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • the display panel further includes an encapsulation layer, the encapsulation layer is located on the side of the wire layer away from the substrate, and the encapsulation layer covers the non-binding area of the wire layer.
  • the display panel provided by the present application includes a wire layer and a substrate arranged on the wire layer, as well as scan lines, data lines and power connection lines arranged on the substrate.
  • the layer includes a binding area and a non-binding area.
  • the substrate is provided with vias. The scan lines, data lines and power connection lines are connected to the binding area through the vias.
  • the binding area of the display panel is designed to The non-luminous surface of the substrate can reduce the frame area of the display device, which is beneficial to realize a narrow frame display.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the structure of the wire layer in FIG. 1;
  • FIG. 3 is a schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the structure of the wire layer in FIG. 3;
  • FIG. 5 is another schematic diagram of the structure of the wire layer in FIG. 3;
  • FIG. 6 is a schematic side view of the structure of the display panel in FIG. 3;
  • FIG. 7 is a schematic bottom view of the structure of the display panel in FIG. 3;
  • FIG. 8 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the present application.
  • the present application provides a display panel.
  • the binding area located at the edge of the non-display area in the prior art is designed to the non-luminous surface of the substrate to solve the problem that the binding area occupies the side of the display device.
  • the space issue is conducive to the realization of narrow border display.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the structure of the wire layer 11 in FIG.
  • the display panel 10 includes a wire layer 11 and a substrate 12 arranged on the wire layer 11, and a scan line 13, a data line 14 and a power connection line 15 arranged on the substrate 12.
  • the wire layer 11 includes a binding area 111 and a non-binding area 112
  • the substrate 12 is provided with vias 121
  • the scan line 13, the data line 14 and the power connection line 15 are connected to the wire plate 11 through the via 121 Binding area 111.
  • the frame area of the display device can be reduced, which is beneficial to realize narrow frame display.
  • FIG. 3 is another cross-sectional structure diagram of the display panel provided by the embodiment of the present application
  • FIG. 4 is a structure diagram of the wire layer 201 in FIG. 3.
  • the display panel 200 includes a wire layer 201 and a substrate 202 disposed on the wire layer 201, and a scan line 203, a data line 204 and a power connection line 205 disposed on the substrate 202.
  • the wire layer 201 includes a bonding area 2011 and a non-bonding area 2012
  • the substrate 202 is provided with vias 2021
  • the scan lines 203, data lines 204, and power connection lines 205 are connected to the wire board 201 through the vias 2021. Binding zone 2011.
  • the display panel 200 is a top-emitting display panel.
  • the substrate 202 has a light-emitting surface and a non-light-emitting surface away from the light-emitting surface.
  • the wire layer 201 is disposed on the non-light-emitting surface of the substrate 202.
  • the gate lines 203, The data line 204 and the power connection line 205 are arranged on the light-emitting surface of the substrate 202.
  • the substrate 202 may be a glass substrate or a rigid resin substrate, and may also be a flexible substrate used to prepare a flexible display panel.
  • the via hole 2021 is filled with a material with low resistivity, such as indium tin oxide, aluminum, copper, silver, etc., for realizing the conductive connection between the light-emitting surface and the non-light-emitting surface.
  • the wire layer 201 includes a number of wire lines (not shown in the figure), one end of the wire line is at the position of the via 2021, and the other end is at the position of the binding area 2012. The wire line is used to realize the via 2021 and the binding The connection of the designated area 2012.
  • the gate line 203, the data line 204, and the power connection line 205 are first connected to the wire line via the via 2021, and then connected to the binding area 2012 via the wire line.
  • the bonding area 2012 is used to connect with a driving circuit (not shown in the figure), and transmit driving voltage signals to the scan line 203, the data line 204, and the power connection line 205.
  • a thin film transistor 206, a flat layer 207, a pixel anode 208, a pixel light emitting layer 209, and a pixel cathode 210 are sequentially arranged on the light emitting surface of the substrate 202.
  • the thin film transistor 206 includes a gate 2061, a source/drain 2062. One end of the scan line 203 is connected to the gate 2061, and the other end is connected to the via 2021.
  • the layer structure between the gate 2061 and the substrate 202 A via is provided, and the scan line 203 realizes conduction between the gate 2061 and the via 2021 through the via; one end of the data line 204 is connected to the source/drain 2062, and the other end is connected to the via 2021 If there is another layer structure between the source/drain 2062 and the substrate 202, a via is provided on the layer structure between the source/drain 2062 and the substrate 202, and the data line 204 realizes the source/drain through the via.
  • the layer structure between the driving voltage output terminal 2064 of the thin film transistor 206 and the pixel anode 208 is provided with a via, and the via is filled with conductive material, which can realize the driving voltage output terminal 2064 of the thin film transistor and the pixel anode 208
  • the conduction between 208 is to transmit the driving voltage received at the driving voltage input terminal 2063 to the pixel anode 208 and drive the pixel light-emitting layer 209 to emit light.
  • each scan line 203, data line 204, or power connection line 205 corresponds to a through hole 2021, that is, the number of through holes 2021 is not less than the total of the scan line 203, data line 204, and power connection line 205. Quantity.
  • the connection between the scan line 203, the data line 204, and the power connection line 205 and the via 2021 follows the principle of proximity, that is, the position of the via 2021 on the substrate 202 corresponds to the setting position of the three, so that The scan line 203, the data line 204, and the power connection line 205 can be connected to the via 2021 by a shorter line, which is beneficial to reduce the voltage drop.
  • the scan line 203, the data line 204 and the power connection line 205 are respectively connected to the closest bonding area 2011 through the via 2021.
  • the number of binding areas 2011 is related to the size of the display panel 200.
  • the display panel 200 includes a pixel electrode layer, the pixel electrode layer is located on the scan line 203, the data line 204 and the power connection line 205, the pixel electrode layer is a pixel cathode 210 formed by coating the entire surface.
  • the edge of the cathode 210 is connected to the wire layer 201 through the via 2021.
  • electrode traces 211 are formed on the side edge surface of the layer structure between the pixel cathode 210 and the substrate 202 for connecting the pixel cathode 210 to the through hole 2021 of the substrate 202. It is helpful to further reduce the border area of the display panel.
  • the display panel 200 may further include an encapsulation layer 212, which is disposed on the side of the wire layer 201 away from the substrate 202
  • the encapsulation layer 212 covers the non-bonding area 2012 of the wire layer 201 and exposes the bonding area 2011 of the wire layer 201 for connection with the driving circuit.
  • an encapsulation layer 212 may also be provided on the light-emitting surface of the substrate 202 to prevent water and oxygen from entering from the light-emitting surface to damage the display panel.
  • the encapsulation layer 212 may be a single layer or a stacked layer of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., or may be formed by alternately stacking inorganic layers and organic layers.
  • the display panel provided by the embodiment of the present application can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.
  • Setting multiple bonding areas can shorten the path length of the scan lines, data lines, and power connection lines connected to the bonding area through the via holes, thereby avoiding voltage drop problems caused by excessively long paths.
  • FIG. 8 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the present application.
  • the manufacturing method of the display panel includes the following steps:
  • the substrate may be a glass substrate or a rigid resin substrate, and may also be a flexible substrate used to prepare a flexible display panel.
  • a via hole is made on the substrate by means of laser etching, wherein the diameter of the via hole is 100-300 um.
  • S83 Fill a conductive material in the via hole, and form a wire layer on the substrate.
  • the wire layer includes a binding area and a non-binding area.
  • the display panel is a top-emitting display panel
  • the substrate has a light-emitting surface and a non-light-emitting surface facing away from the light-emitting surface.
  • the wire layer is made by sputtering, coating, developing, etching and other processes, and at the same time, materials with low resistivity such as indium tin oxide, aluminum, Copper, silver, etc., to realize the conduction connection between the light-emitting surface and the non-light-emitting surface.
  • the bonding area of the wire layer is used to connect with the driving circuit.
  • the wire layer includes a plurality of wire lines, one end of the wire line is at the position of the via hole and the other end is at the position of the binding area, and the wire line is used to realize the connection between the via hole and the binding area.
  • the side of the substrate away from the wire layer is the light-emitting surface, and gate lines, data lines and power connection lines are formed on the light-emitting surface.
  • a via is made in the layer structure between the source, drain and the substrate, and the data line realizes the conduction between the source, drain and the via hole through the via; one end of the power connection line is connected to the film The drive voltage input end of the transistor is connected, and the other end is connected to the through hole.
  • the layer structure between the drive voltage input end of the thin film transistor and the substrate A through hole is formed on the upper surface, and the power connection line realizes the conduction between the driving voltage input end of the thin film transistor and the through hole through the through hole.
  • each scan line, data line or power connection line corresponds to a via hole, that is, the number of via holes is not less than the total number of scan lines, data lines and power connection lines.
  • the connection of the scan lines, data lines, and power connection lines with the vias follows the principle of proximity, that is, the location of the vias on the substrate corresponds to the placement of these three, so that the scan lines, data lines and The three power connection lines can be connected to the vias with shorter lines, which is beneficial to reduce the voltage drop.
  • the scan lines, data lines, and power connection lines are respectively connected to the nearest binding area via via holes.
  • the number of binding areas is related to the size of the display panel. The larger the size of the display panel, the greater the number of binding areas.
  • multiple binding areas can be arranged in an array on the wire layer or located on the wire layer. The surrounding edge position. In this way, the path length of the via hole connected to the bonding area through the wire line can be shortened, so as to avoid the voltage drop problem caused by the excessively long path, thereby avoiding obvious uneven light emission of the display panel.
  • S85 Coating the entire surface of the scan line, data line, and power connection line to form a pixel electrode layer, where the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through the via hole.
  • the pixel electrode layer is a pixel cathode formed by coating the entire surface, and the edge of the pixel cathode is connected to the wire layer through a via hole.
  • S85 specifically includes:
  • An electrode trace is formed on the side edge surface of the layer structure between the pixel cathode and the substrate.
  • the electrode trace is used to lap the pixel cathode to the through hole of the substrate, which is beneficial to further reduce the frame area of the display panel .
  • the encapsulation layer may be a single layer or a stack of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., or may be formed by alternately stacking inorganic layers and organic layers.
  • the encapsulation layer covers the non-binding area of the wire layer to prevent water and oxygen from intruding through the via holes to damage the display panel. At the same time, the encapsulation layer does not cover the bonding area, so that the bonding area of the wire layer is exposed and can be connected to the driving circuit.
  • an encapsulation layer can also be formed on the light-emitting surface of the substrate to prevent water and oxygen from entering from the light-emitting surface and damaging the display panel.
  • the manufacturing method of the display panel provided by the embodiments of the present application can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 91 includes a driving circuit and the display panel 92 of any of the above embodiments.
  • the display panel 92 includes a wire layer and a substrate arranged on the wire layer, as well as scan lines, data lines and power connection lines arranged on the substrate.
  • the wire layer includes a binding area and a non-binding area
  • the substrate is provided with via holes
  • the scan lines, data lines and power connection wires are connected to the binding area of the wire board through the via holes.
  • the driving circuit is connected with the scan line, the data line and the power connection line through the binding area.
  • the display device provided in this embodiment can reduce the frame area of the display device by designing the binding area of the display panel to the non-luminous surface of the substrate, which is beneficial to realize narrow frame display.

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Abstract

一种显示面板（10、200、92）及其制作方法、显示装置（91），显示面板（10、200、92）包括：导线层（11、201），导线层（11、201）包括绑定区（111、2011）和非绑定区（112、2012）；设置于导线层（11、201）上的基板（12、202），基板（12、202）上设置有导通孔（121、2021）；设置于基板（12、202）上的扫描线（13、203）、数据线（14、204）和电源连接线（15、205），其中，扫描线（13、203）、数据线（14、204）和电源连接线（15、205）经导通孔（121、2021）连接至绑定区（111、2011）。

Description

一种显示面板及其制作方法、显示装置 技术领域
本申请涉及显示面板技术领域，具体涉及一种显示面板及其制作方法、显示装置。
 背景技术
伴随着电子产品柔性、超薄、窄边框等特点的发展趋势，显示屏在超薄、柔性、边框等方面不断加大技术研发，窄边框可以让产品更加的时尚，这是最直观的作用。采用窄边框设计的显示产品，对于尺寸的利用更有优势。同样的尺寸（包含外边框），窄边框的产品屏幕显示面积更大，对于笔记本以及手机来说，意味着更小的机身，更大的尺寸。对于大屏幕的显示器来说，产品的气质提升对于追求时尚的用户来说也是很有意义的。此外，窄边框也让画面显得更加干净利索，对于提升显示的魅力，具有软性的作用。
现有技术中，通过位于非显示区域边缘的绑定区域实现显示设备的导线层与驱动电路的连接，存在绑定区域占用显示设备侧边空间的问题，不利于实现窄边框显示。
 技术问题
本申请提供了一种显示面板及其制作方法、显示装置，以缩小显示设备的边框区域，有利于实现窄边框显示。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种显示面板，该显示面板包括：导线层，导线层包括绑定区和非绑定区；设置于导线层上的基板，基板上设置有导通孔；设置于基板上的扫描线、数据线和电源连接线，其中，扫描线、数据线以及电源连接线经导通孔连接至绑定区。
其中，导通孔为若干个，若干个导通孔位于基板上，且与扫描线、数据线和电源连接线的设置位置对应。
其中，绑定区为若干个，扫描线、数据线以及电源连接线经导通孔分别与距离最近的绑定区连接。
其中，绑定区在导线层上呈阵列排布。
其中，显示面板还包括像素电极层，像素电极层位于扫描线、数据线和电源连接线上，像素电极层为整面镀膜形成的像素阴极，像素阴极的边缘经导通孔连接至导线层。
其中，显示面板还包括封装层，封装层位于导线层背离基板的一侧上，封装层覆盖导线层的非绑定区。
其中，显示面板还包括在基板背离导线层的一侧上依次设置的薄膜晶体管、平坦层，薄膜晶体管包括栅极、源/漏极，扫描线的一端与栅极连接，另一端与导通孔连接，数据线的一端与源/漏极连接，另一端与导通孔连接，电源连接线的一端与薄膜晶体管的驱动电压输入端连接，另一端与导通孔连接。
为了解决上述问题，本申请实施例还提供了一种显示面板的制作方法，该制作方法包括：提供基板；在基板上制作导通孔；在导通孔内填充导电材料，并在基板上形成导线层，导线层包括绑定区和非绑定区；在基板背离导线层的一侧上，形成扫描线、数据线和电源连接线，其中，扫描线、数据线以及电源连接线经导通孔连接至绑定区。
其中，导通孔为若干个，若干个导通孔位于基板上，且与扫描线、数据线和电源连接线的设置位置对应。
其中，绑定区为若干个，扫描线、数据线以及电源连接线经导通孔分别与距离最近的绑定区连接。
其中，绑定区在导线层上呈阵列排布。
其中，在基板背离导线层的一侧上，形成扫描线、数据线和电源连接线的步骤之后，还包括：在扫描线、数据线和电源连接线上整面镀膜形成像素电极层，其中，像素电极层为整面镀膜形成的像素阴极，像素阴极的边缘经导通孔连接至导线层。
其中，在基板背离导线层的一侧上，形成扫描线、数据线、电源连接线的步骤之后，还包括：在导线层背离基板的一侧上，形成封装层，封装层覆盖导线层的非绑定区。
其中，在基板背离导线层的一侧上，形成扫描线、数据线和电源连接线的步骤，具体包括：在基板背离导线层的一侧上，依次形成薄膜晶体管层、平坦层，薄膜晶体管层包括薄膜晶体管、扫描线、数据线和电源连接线，其中，薄膜晶体管包括栅极、源极和漏极，扫描线的一端与栅极连接，另一端与导通孔连接，数据线的一端与源极或漏极连接，另一端与导通孔连接，电源连接线的一端与薄膜晶体管的驱动电压输入端连接，另一端与导通孔连接。
为了解决上述问题，本申请实施例又提供了一种显示装置，该显示装置包括驱动电路和显示面板，其中，显示面板包括：导线层，导线层包括绑定区和非绑定区；设置于导线层上的基板，基板上设置有导通孔；设置于基板上的扫描线、数据线和电源连接线，其中，扫描线、数据线以及电源连接线经导通孔连接至绑定区；驱动电路通过绑定区与扫描线、数据线和电源连接线连接。
其中，导通孔为若干个，若干个导通孔位于基板上，且与扫描线、数据线和电源连接线的设置位置对应。
其中，绑定区为若干个，扫描线、数据线以及电源连接线经导通孔分别与距离最近的绑定区连接。
其中，绑定区在导线层上呈阵列排布。
其中，显示面板还包括像素电极层，像素电极层位于扫描线、数据线和电源连接线上，像素电极层为整面镀膜形成的像素阴极，像素阴极的边缘经导通孔连接至导线层。
其中，显示面板还包括封装层，封装层位于导线层背离基板的一侧上，封装层覆盖导线层的非绑定区。
 有益效果
本申请的有益效果是：区别于现有技术，本申请提供的显示面板包括导线层和设置于导线层上的基板，以及设置于基板上的扫描线、数据线和电源连接线，其中，导线层包括绑定区和非绑定区，在基板上设置有导通孔，扫描线、数据线以及电源连接线经导通孔连接至绑定区，如此，将显示面板的绑定区设计至基板的非发光面，能够缩小显示设备的边框区域，有利于实现窄边框显示。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的剖面结构示意图；
图2是图1中的导线层的结构示意图；
图3是本申请实施例提供的显示面板的另一剖面结构示意图；
图4是图3中的导线层的结构示意图；
图5是图3中的导线层的另一结构示意图；
图6是图3中的显示面板的侧视结构示意图；
图7是图3中的显示面板的仰视结构示意图；
图8是本申请实施例提供的显示面板的制作方法的流程示意图；
图9是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
下面结合附图和实施例，对本申请作进一步地详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
为了进一步缩小显示设备的边框区域，本申请提供了一种显示面板，将现有技术中位于非显示区域边缘的绑定区设计至基板的非发光面，以解决绑定区占用显示设备侧边空间的问题，有利于实现窄边框显示。
请参阅图1和图2，图1是本申请实施例提供的显示面板的剖面结构示意图，图2是图1中导线层11的结构示意图。该显示面板10包括导线层11和设置于导线层11上的基板12，以及设置于基板12上的扫描线13、数据线14和电源连接线15。其中，导线层11包括绑定区111和非绑定区112，基板12上设置有导通孔121，扫描线13、数据线14以及电源连接线15经导通孔121连接至导线板11的绑定区111。
区别于现有技术，本实施例中的显示面板，通过将显示面板的绑定区设计至基板的非发光面，能够缩小显示设备的边框区域，有利于实现窄边框显示。
请参阅图3和图4，图3是本申请实施例提供的显示面板的另一剖面结构示意图，图4是图3中导线层201的结构示意图。该显示面板200包括导线层201和设置于导线层201上的基板202，以及设置于基板202上的扫描线203、数据线204和电源连接线205。其中，导线层201包括绑定区2011和非绑定区2012，基板202上设置有导通孔2021，扫描线203、数据线204以及电源连接线205经导通孔2021连接至导线板201的绑定区2011。
在本实施例中，显示面板200为顶发光型显示面板，基板202具有发光面和背离所述发光面的非发光面，导线层201设置于基板202的非发光面上，栅极线203、数据线204和电源连接线205设置于基板202的发光面上。
基板202可以为玻璃基板或者硬质的树脂基板，也可以为用于制备柔性显示面板的柔性基板。导通孔2021内填充有低电阻率的材料，如铟锡氧化物、铝、铜、银等，用于实现发光面和非发光面的导通连接。导线层201包括若干导线线路（图中未示出），所述导线线路的一端在导通孔2021位置，另一端在绑定区2012位置，所述导线线路用于实现导通孔2021与绑定区2012的连接。在本实施例中，栅极线203、数据线204和电源连接线205经导通孔2021先与导线线路连接，然后再经导线线路连接至绑定区2012。其中，绑定区2012用于与驱动电路（图中未示出）连接，并向扫描线203、数据线204和电源连接线205传送驱动电压信号。
具体地，在基板202的发光面上依次设置有薄膜晶体管206、平坦层207、像素阳极208、像素发光层209和像素阴极210，薄膜晶体管206包括栅极2061、源/漏极2062。其中，扫描线203的一端与栅极2061连接，另一端与导通孔2021连接，若栅极2061和基板202之间存在其他的层结构，则在栅极2061与基板202之间的层结构上设置有过孔，且扫描线203经该过孔实现栅极2061与导通孔2021之间的导通；数据线204的一端与源/漏极2062连接，另一端与导通孔2021连接，若源/漏极2062与基板202之间存在其他的层结构，则在源/漏极2062与基板202之间的层结构上设置有过孔，且数据线204经该过孔实现源/漏极2062与导通孔2021之间的导通；电源连接线205的一端与薄膜晶体管的驱动电压输入端2063连接，另一端与导通孔2021连接，若薄膜晶体管的驱动电压输入端2063和基板202之间存在其他的层结构，则在薄膜晶体管的驱动电压输入端2063与基板202之间的层结构上设置有过孔，且电源连接线205经该过孔实现薄膜晶体管的驱动电压输入端2063与导通孔2021之间的导通。
进一步地，薄膜晶体管206的驱动电压输出端2064与像素阳极208之间的层结构上设置有过孔，且该过孔内填充有导电材料，可以实现薄膜晶体管的驱动电压输出端2064与像素阳极208之间的导通，以将驱动电压输入端2063上接收到的驱动电压传送至像素阳极208，并驱动像素发光层209发光。
可选地，导通孔2021为若干个，若干个导通孔2021位于基板202上，且与扫描线203、数据线204和电源连接线205的设置位置对应。
具体地，每一条扫描线203、数据线204或电源连接线205均对应有一个导通孔2021，即导通孔2021的数量不少于扫描线203、数据线204和电源连接线205的总数量。并且，扫描线203、数据线204和电源连接线205这三者与导通孔2021的连接遵循就近原则，即将导通孔2021在基板202上的位置与这三者的设置位置相对应，使得扫描线203、数据线204和电源连接线205这三者能够以较短的线路连接至导通孔2021，从而有利于减少压降。
进一步地，请继续参阅图4，绑定区2011也可以为若干个，并且扫描线203、数据线204以及电源连接线205经导通孔2021分别与距离最近的绑定区2011连接。
具体地，绑定区2011的数量与显示面板200的尺寸有关，显示面板200的尺寸越大，绑定区2011的数量越多，并且，如图4和图5所示，多个绑定区2011可以在导线层201上呈阵列排布或者位于导线层201的四周边缘位置。如此，能够缩短导通孔2021经导线线路连接至绑定区2011的路径长度，以避免因路径过长而导致的压降问题，从而避免显示面板出现明显的发光不均匀现象。
可选地，请继续参阅图3，显示面板200包括像素电极层，像素电极层位于扫描线203、数据线204和电源连接线205上，像素电极层为整面镀膜形成的像素阴极210，像素阴极210的边缘经导通孔2021连接至导线层201。具体地，请参阅图6，在像素阴极210与基板202之间的层结构的侧边缘面上形成有电极走线211，用于将像素阴极210搭接至基板202的导通孔2021，有利于进一步缩小显示面板的边框区域。
进一步地，请参阅图3和图7，为了防止水氧通过导通孔2021侵入而破坏显示面板，显示面板200还可以包括封装层212，封装层212设置于导线层201背离基板202的一侧上，且封装层212覆盖导线层201的非绑定区2012，并使得导线层201的绑定区2011裸露，以与驱动电路连接。另外，在基板202的发光面上也可以设置封装层212，用于防止水氧从发光面上侵入而破坏显示面板。
其中，封装层212可以是氮化硅、氧化硅、氮氧化硅、氧化铝等中的单层或叠层，也可以由无机层和有机层交替层叠形成。
区别于现有技术，本申请实施例提供的显示面板，通过将显示面板的绑定区设计至基板的非发光面，能够缩小显示设备的边框区域，有利于实现窄边框显示，另外，通过分区设置多个绑定区，能够缩短扫描线、数据线和电源连接线经导通孔连接至绑定区的路径长度，从而避免因路径过长而导致的压降问题。
请参阅图8，图8是本申请实施例提供的显示面板的制作方法的流程示意图。该显示面板的制作方法包括以下步骤：
S81：提供基板。
基板可以为玻璃基板或者硬质的树脂基板，也可以为用于制备柔性显示面板的柔性基板。
S82：在基板上制作导通孔。
可选地，通过激光蚀刻的方式在基板上制作导通孔，其中，导通孔的直径为100～300um。
S83：在导通孔内填充导电材料，并在基板上形成导线层，导线层包括绑定区和非绑定区。
在本实施例中，显示面板为顶发光型显示面板，基板具有发光面和背离所述发光面的非发光面。可选地，在基板的非发光面上，通过溅射、涂布、显影、蚀刻等工艺制作导线层，同时向导通孔内溅射具有低电阻率的材料，如铟锡氧化物、铝、铜、银等，以实现发光面和非发光面的导通连接。
其中，导线层的绑定区用于与驱动电路连接。导线层包括若干导线线路，所述导线线路的一端在导通孔位置，另一端在绑定区位置，所述导线线路用于实现导通孔与绑定区的连接。
S84：在基板背离导线层的一侧上，形成扫描线、数据线和电源连接线，其中，扫描线、数据线以及电源连接线经导通孔连接至绑定区。
在本实施例中，基板背离导线层的一侧为发光面，并且在发光面上形成栅极线、数据线和电源连接线。
其中，S84具体包括：在基板的发光面上依次形成薄膜晶体管层、平坦层，薄膜晶体管层包括薄膜晶体管、扫描线、数据线和电源连接线，薄膜晶体管包括栅极、源极和漏极。其中，扫描线的一端与栅极连接，另一端与导通孔连接，若栅极和基板之间存在其他的层结构，则在栅极与基板之间的层结构上制作过孔，且扫描线经该过孔实现栅极与导通孔之间的导通；数据线的一端与源极或漏极连接，另一端与导通孔连接，若源、漏极与基板之间存在其他的层结构，则在源、漏极与基板之间的层结构上制作过孔，且数据线经该过孔实现源、漏极与导通孔之间的导通；电源连接线的一端与薄膜晶体管的驱动电压输入端连接，另一端与导通孔连接，若薄膜晶体管的驱动电压输入端和基板之间存在其他的层结构，则在薄膜晶体管的驱动电压输入端与基板之间的层结构上制作过孔，且电源连接线经该过孔实现薄膜晶体管的驱动电压输入端与导通孔之间的导通。
具体地，每一条扫描线、数据线或电源连接线均对应有一个导通孔，即导通孔的数量不少于扫描线、数据线和电源连接线的总数量。并且，扫描线、数据线和电源连接线这三者与导通孔的连接遵循就近原则，即将导通孔在基板上的位置与这三者的设置位置相对应，使得扫描线、数据线和电源连接线这三者能够以较短的线路连接至导通孔，从而有利于减少压降。
进一步地，绑定区也可以为若干个，并且扫描线、数据线以及电源连接线经导通孔分别与距离最近的绑定区连接。
具体地，绑定区的数量与显示面板的尺寸有关，显示面板的尺寸越大，绑定区的数量越多，并且，多个绑定区可以在导线层上呈阵列排布或者位于导线层的四周边缘位置。如此，能够缩短导通孔经导线线路连接至绑定区的路径长度，以避免因路径过长而导致的压降问题，从而避免显示面板出现明显的发光不均匀现象。
可选地，在S84之后，还包括:
S85：在扫描线、数据线和电源连接线上整面镀膜形成像素电极层，其中，像素电极层为整面镀膜形成的像素阴极，像素阴极的边缘经导通孔连接至导线层。
在本实施中，像素电极层为整面镀膜形成的像素阴极，像素阴极的边缘经导通孔连接至导线层。
其中，S85具体包括：
S851：在平坦层上依次形成像素阳极、像素发光层和像素阴极；
S852：在像素阴极与基板之间的层结构的侧边缘面上形成电极走线，所述电极走线用于将像素阴极搭接至基板的导通孔，有利于进一步缩小显示面板的边框区域。
可选地，在S84之后，还包括：
S86：在导线层背离基板的一侧上，形成封装层，封装层覆盖导线层的非绑定区。
其中，封装层可以是氮化硅、氧化硅、氮氧化硅、氧化铝等中的单层或叠层，也可以由无机层和有机层交替层叠形成。
具体地，封装层覆盖导线层的非绑定区，以防止水氧通过导通孔侵入而破坏显示面板。同时，封装层并不覆盖绑定区，以使得导线层的绑定区裸露，能够与驱动电路连接。
进一步地，在基板的发光面上也可以形成封装层，用于防止水氧从发光面上侵入而破坏显示面板。
区别于现有技术，本申请实施例提供的显示面板的制作方法，通过将显示面板的绑定区设计至基板的非发光面，能够缩小显示设备的边框区域，有利于实现窄边框显示。
请参阅图9，图9是本申请实施例提供的显示装置的结构示意图。该显示装置91包括驱动电路和上述任一实施例的显示面板92。
在本实施例中，显示面板92包括导线层和设置于导线层上的基板，以及设置于基板上的扫描线、数据线和电源连接线。其中，导线层包括绑定区和非绑定区，基板上设置有导通孔，扫描线、数据线以及电源连接线经导通孔连接至导线板的绑定区。驱动电路通过绑定区与扫描线、数据线和电源连接线连接。
区别于现有技术，本实施例提供的显示装置，通过将显示面板的绑定区设计至基板的非发光面，能够缩小显示设备的边框区域，有利于实现窄边框显示。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示面板，其包括：
    导线层，所述导线层包括绑定区和非绑定区；
    设置于所述导线层上的基板，所述基板上设置有导通孔；
    设置于所述基板上的扫描线、数据线和电源连接线，其中，所述扫描线、所述数据线以及所述电源连接线经所述导通孔连接至所述绑定区。
  2. 根据权利要求1所述的显示面板，其中，所述导通孔为若干个，若干个所述导通孔位于所述基板上，且与所述扫描线、所述数据线和所述电源连接线的设置位置对应。
  3. 根据权利要求2所述的显示面板，其中，所述绑定区为若干个，所述扫描线、所述数据线以及所述电源连接线经所述导通孔分别与距离最近的所述绑定区连接。
  4. 根据权利要求3所述的显示面板，其中，所述绑定区在所述导线层上呈阵列排布。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括像素电极层，所述像素电极层位于所述扫描线、所述数据线和所述电源连接线上，所述像素电极层为整面镀膜形成的像素阴极，所述像素阴极的边缘经所述导通孔连接至所述导线层。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还包括封装层，所述封装层位于所述导线层背离所述基板的一侧上，所述封装层覆盖所述导线层的所述非绑定区。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板还包括在所述基板背离所述导线层的一侧上依次设置的薄膜晶体管、平坦层，所述薄膜晶体管包括栅极、源/漏极，所述扫描线的一端与所述栅极连接，另一端与所述导通孔连接，所述数据线的一端与所述源/漏极连接，另一端与所述导通孔连接，所述电源连接线的一端与所述薄膜晶体管的驱动电压输入端连接，另一端与所述导通孔连接。
  8. 一种显示面板的制作方法，其包括：
    提供基板；
    在所述基板上制作导通孔；
    在所述导通孔内填充导电材料，并在所述基板上形成导线层，所述导线层包括绑定区和非绑定区；
    在所述基板背离所述导线层的一侧上，形成扫描线、数据线和电源连接线，其中，所述扫描线、所述数据线以及所述电源连接线经所述导通孔连接至所述绑定区。
  9. 根据权利要求8所述的制作方法，其中，所述导通孔为若干个，若干个所述导通孔位于所述基板上，且与所述扫描线、所述数据线和所述电源连接线的设置位置对应。
  10. 根据权利要求9所述的制作方法，其中，所述绑定区为若干个，所述扫描线、所述数据线以及所述电源连接线经所述导通孔分别与距离最近的所述绑定区连接。
  11. 根据权利要求10所述的制作方法，其中，所述绑定区在所述导线层上呈阵列排布。
  12. 根据权利要求8所述的制作方法，其中，所述在所述基板背离所述导线层的一侧上，形成扫描线、数据线和电源连接线的步骤之后，还包括：
    在所述扫描线、所述数据线和所述电源连接线上整面镀膜形成像素电极层，其中，所述像素电极层为整面镀膜形成的像素阴极，所述像素阴极的边缘经所述导通孔连接至所述导线层。
  13. 根据权利要求8所述的制作方法，其中，所述在所述基板背离所述导线层的一侧上，形成扫描线、数据线、电源连接线的步骤之后，还包括：
    在所述导线层背离所述基板的一侧上，形成封装层，所述封装层覆盖所述导线层的所述非绑定区。
  14. 根据权利要求8所述的制作方法，其中，在所述基板背离所述导线层的一侧上，形成扫描线、数据线和电源连接线的步骤，具体包括：
    在所述基板背离所述导线层的一侧上，依次形成薄膜晶体管层、平坦层，薄膜晶体管层包括薄膜晶体管、扫描线、数据线和电源连接线，其中，所述薄膜晶体管包括栅极、源极和漏极，所述扫描线的一端与所述栅极连接，另一端与所述导通孔连接，所述数据线的一端与所述源极或所述漏极连接，另一端与所述导通孔连接，所述电源连接线的一端与所述薄膜晶体管的驱动电压输入端连接，另一端与所述导通孔连接。
  15. 一种显示装置，其包括驱动电路和显示面板，其中，所述显示面板包括：
    导线层，所述导线层包括绑定区和非绑定区；
    设置于所述导线层上的基板，所述基板上设置有导通孔；
    设置于所述基板上的扫描线、数据线和电源连接线，其中，所述扫描线、所述数据线以及所述电源连接线经所述导通孔连接至所述绑定区；
    所述驱动电路通过所述绑定区与所述扫描线、所述数据线和所述电源连接线连接。
  16. 根据权利要求15所述的显示装置，其中，所述导通孔为若干个，若干个所述导通孔位于所述基板上，且与所述扫描线、所述数据线和所述电源连接线的设置位置对应。
  17. 根据权利要求16所述的显示装置，其中，所述绑定区为若干个，所述扫描线、所述数据线以及所述电源连接线经所述导通孔分别与距离最近的所述绑定区连接。
  18. 根据权利要求17所述的显示装置，其中，所述绑定区在所述导线层上呈阵列排布。
  19. 根据权利要求15所述的显示装置，其中，所述显示面板还包括像素电极层，所述像素电极层位于所述扫描线、所述数据线和所述电源连接线上，所述像素电极层为整面镀膜形成的像素阴极，所述像素阴极的边缘经所述导通孔连接至所述导线层。
  20. 根据权利要求15所述的显示装置，其中，所述显示面板还包括封装层，所述封装层位于所述导线层背离所述基板的一侧上，所述封装层覆盖所述导线层的所述非绑定区。
PCT/CN2019/085505 2019-04-02 2019-05-05 一种显示面板及其制作方法、显示装置 WO2020199300A1 (zh)

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