WO2022236765A1 - 显示面板、显示装置及终端设备 - Google Patents

显示面板、显示装置及终端设备 Download PDF

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Publication number
WO2022236765A1
WO2022236765A1 PCT/CN2021/093562 CN2021093562W WO2022236765A1 WO 2022236765 A1 WO2022236765 A1 WO 2022236765A1 CN 2021093562 W CN2021093562 W CN 2021093562W WO 2022236765 A1 WO2022236765 A1 WO 2022236765A1
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WIPO (PCT)
Prior art keywords
hole
holes
light
lead
area
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PCT/CN2021/093562
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English (en)
French (fr)
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WO2022236765A9 (zh
Inventor
杜丽丽
程羽雕
龙跃
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/093562 priority Critical patent/WO2022236765A1/zh
Priority to CN202180001135.8A priority patent/CN115943755A/zh
Priority to US17/789,301 priority patent/US20240188355A1/en
Publication of WO2022236765A1 publication Critical patent/WO2022236765A1/zh
Publication of WO2022236765A9 publication Critical patent/WO2022236765A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel, a display device, and a terminal device.
  • the area of the screen corresponding to the camera usually needs to have a hole, so that no light can be emitted, which is not conducive to increasing the screen-to-body ratio.
  • the area of the screen corresponding to the camera is prone to color shift when displaying images, especially prone to color shift.
  • the green phenomenon affects the display effect.
  • the purpose of the present disclosure is to provide a display panel, a display device and a terminal device.
  • a display panel comprising:
  • the driving backplane has a light-transmitting area and a driving area at least partially surrounding the light-transmitting area, the driving area has a plurality of pixel circuits, and the pixel circuits include a first pixel circuit and a second pixel circuit; the The driving backplane has a plurality of first transfer holes, and any one of the pixel circuits is connected to one of the first transfer holes;
  • the transfer layer is arranged on one side of the driving backplane and covers the light transmission area and the driving area; spaced leads; the transition layer has a transition area corresponding to the light-transmitting area and a wiring area corresponding to the driving area, and the transition area includes two transitions separated on both sides of the first central axis
  • the first central axis is the central axis extending along the column direction of the transition zone; each of the transition zones has a plurality of second transition holes, and any of the second transition holes passes through a
  • the lead wire is connected to one of the first transfer holes;
  • the light-emitting layer is arranged on the side of the transfer layer away from the driving backplane, and includes a plurality of light-emitting devices, and the light-emitting devices include a plurality of first light-emitting devices located in each of the transfer partitions and located in the A plurality of second light-emitting devices in the wiring area; any one of the first light-emitting devices is connected to a second via hole, and any second light-emitting device is connected to a first via hole;
  • the first transition holes and the second transition holes are arranged in a plurality of hole rows distributed along the column direction, and each of the second transition holes is located in a part of the hole rows;
  • a transfer hole and a second connection hole are located in the same hole row and form a hole group; in two adjacent hole groups, the first transfer hole and the second transfer hole of a hole group are located Between the first transfer hole and the second transfer hole of the other hole group;
  • the length of any one of the leads in the row direction is the same as or different from the distance between the first via hole and the second via hole to which it is connected by a specified length.
  • N hole rows there are N hole rows, and each of the second transfer holes is located in each of the i-th hole rows; N, i, and j are Positive integer, and 1 ⁇ i ⁇ j ⁇ N;
  • At least part of the lead wires connected to the second transition holes of a hole row are located between the two adjacent hole rows.
  • the lead wire connected to the second transition hole in the k-th hole row is located between the k-1 and k-th hole rows; k is a positive integer , and i ⁇ k ⁇ j;
  • the leads connected to the second transition holes of the i-th hole row are located on the side of the i-th hole row away from the j-th hole row.
  • At least part of the part of the lead wire connected to the second transition hole is located in the i-th hole row.
  • the wiring area includes a main body area and a peripheral area, the main body area at least partially surrounds the transfer area, and the peripheral area surrounds the main body area and the peripheral area. Outside the transfer area; at least part of the first pixel circuit is distributed in the area of the driving backplane corresponding to the main body area;
  • At least part of the lead wires connected to at least some of the second transition holes are located in the peripheral area.
  • At least part of the lead wires connected to at least part of the second transition holes are located in the j-th hole row.
  • the transit partition includes a plurality of sub-partitions distributed along the row direction, and each of the sub-partitions is provided with the second transit hole;
  • the leads connected to the second via holes in the same sub-section are located in the same lead layer.
  • the multi-layer wiring layers at least include a first wiring layer, a second wiring layer and a third wiring layer sequentially distributed from the driving backplane to the light emitting layer;
  • the leads of the first lead layer include first leads, the leads of the second lead layer include second leads, and the leads of the third lead layer include third leads;
  • the sub-sections of the same transfer sub-section include a first sub-section, a second sub-section and a third sub-section which are sequentially distributed along the row direction toward the first central axis, and each second sub-section in the first sub-section
  • the leads connected to the holes are the first leads
  • the leads connected to the second transition holes in the second sub-section are the second leads
  • the second transition holes in the third sub-section The lead connected to the hole is the third lead.
  • the first lead wire, the second lead wire and the third lead wire connected to the second transition hole of the kth hole row are located between the k-1 and kth hole rows;
  • the first lead wire, the second lead wire and the third lead wire connected to the second transition hole in the i-th hole row are located on the side of the i-th hole row away from the j-th hole row.
  • the leads of the first lead layer further include fourth leads;
  • the sub-sections of the same transfer sub-section include a fourth sub-section located between the third sub-section and the first central axis; the leads connected to the second transfer holes in the fourth sub-section is the fourth lead;
  • At least a partial area of at least part of the fourth lead is located on the side of the i-th hole row away from the j-th hole row;
  • At least a partial area of at least part of the fourth lead is located on a side of the j-th hole row away from the i-th hole row.
  • the fourth sub-section includes a first sub-section and a second sub-section separated on both sides of a second central axis, and the second central axis is the transition area The central axis extending along the row direction; part of the second transfer holes of the i-th row of holes is located in the first sub-division, and part of the second transfer holes of the k+1-th row of holes Located in said second subdivision; k+1 ⁇ j;
  • At least a partial area of the fourth lead connected to the second transfer hole of the first sub-section is located on the side of the i-th hole row away from the j-th hole row;
  • At least a partial area of the fourth lead connected to the second transition hole of the second sub-region is located on the side of the j-th hole row away from the i-th hole row.
  • the lead includes two lead-out segments and an extension segment connecting the two lead-out segments; the lead-out segment extends along the row direction, and the extension segment extends along the Execution direction extension;
  • the length of the extension section of any one of the first lead, the second lead and the third lead is the same as the distance between the first transition hole and the second transition hole connected thereto.
  • the lead-out section of the fourth lead connected to the k-th row of holes includes a first section, a second section, and a third section distributed along the column direction, and one end of the first section is connected to a second turn. The other end is connected with one end of the second section, the other end of the second section is connected with one end of the third section, and the other end of the third section is connected with one end of the extension section ;
  • the first segment and the third segment extend linearly along the column direction, and the third segment is located at a position where the second transfer hole connected to the first segment is away from or close to the first central axis side;
  • the length of the extension section of the fourth lead connected to the kth row of holes is different from the distance between the first transition hole and the second transition hole connected to it by a specified length.
  • the length of the extension section of the fourth lead connecting the i-th and j-th hole rows is the same as the distance between the first via hole and the second via hole connected thereto.
  • the fourth lead wire connected to the second via hole in the first sub-section and the fourth lead wire connected to the second via hole in the second sub-section are related to the The second central axis is arranged symmetrically.
  • the leads connecting the second transition holes of the two transition zones are arranged symmetrically with respect to the first central axis.
  • the light emitting device includes:
  • the first electrode is arranged on the surface of the transfer layer away from the driving backplane; the first electrode has an electrode portion and a connection portion located outside the edge of the electrode portion; the connection portion passes through a second The transfer hole is connected with one of the leads;
  • a light-emitting functional layer disposed on the surface of the first electrode away from the driving backplane;
  • the second electrode is arranged on the surface of the light-emitting functional layer away from the driving backplane.
  • a display device including the display panel described in any one of the above.
  • a terminal device including:
  • the imaging device is arranged on the backlight side of the driving backplane away from the light-emitting layer, and facing the light-transmitting area, for capturing images through the light-transmitting area.
  • FIG. 1 is a schematic diagram of a driving backplane in an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a schematic diagram of connection between a pixel circuit and a light emitting device in an embodiment of a display panel of the present disclosure.
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit in an embodiment of the display panel of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel circuit in an embodiment of a display panel of the present disclosure.
  • FIG. 5 is a schematic cross-sectional view of a display panel in an embodiment of the present disclosure.
  • FIG. 6 is a top view of a first electrode in an embodiment of the display panel of the present disclosure.
  • FIG. 7 is a schematic diagram of each routing area of the transfer layer in an embodiment of the display panel of the present disclosure.
  • FIG. 8 is a schematic diagram of connection of the first wiring layer in an embodiment of the display panel of the present disclosure.
  • FIG. 9 is a schematic diagram of connection of the second wiring layer in an embodiment of the display panel of the present disclosure.
  • FIG. 10 is a schematic diagram of connection of the third wiring layer in an embodiment of the display panel of the present disclosure.
  • FIG. 11 is a schematic diagram of first leads in an embodiment of the display panel of the present disclosure.
  • FIG. 12 is a schematic diagram of a fourth lead in an embodiment of the display panel of the present disclosure.
  • FIG. 13 is a schematic diagram of an embodiment of a display device of the present disclosure.
  • Driving backplane 101, light transmission area; 102, driving area; 1021, pixel area; 1022, peripheral area; 10, pixel circuit; 110, first pixel circuit; 120, second pixel circuit; 100, first Transfer hole;
  • Transfer layer; 210 transfer area; 2101, transfer partition; 21011, sub partition; 21011a, first sub partition; 21011b, second sub partition; 21011c, third sub partition; 21011d, fourth sub partition ; 21011d1, the first sub-division; 21011d2, the second sub-division; 220, the wiring area; 21, the lead layer; 211, the lead; 21a, the first lead layer; 211a, the first lead; 21b, the second lead layer; 211b, second lead; 21c, third lead layer; 211c, third lead; 211d, fourth lead; 201, transfer hole; 2110, lead-out section; 21101, first section; The third section; 2120, the extension section; 22, the first flat layer; 23, the second flat layer; 24, the third flat layer;
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a display panel for realizing under-screen photography has a light-transmitting area and a driving area outside the light-transmitting area, and a plurality of light-emitting devices are provided in the light-transmitting area and the driving area.
  • pixel circuits for driving all light-emitting devices are provided in the driving area, and there are no pixel circuits in the light-transmitting area, so as to improve the degree of light transmission, so that images can be taken by the camera through the light-transmitting area.
  • the light-emitting devices in the light-transmitting area can be connected to the corresponding pixel circuits in the driving area through the leads extending from the light-transmitting area to the driving area, and the light-emitting devices in the driving area can be connected to each other.
  • the device is directly connected to the corresponding pixel circuit in the drive area.
  • the light emitting devices at least include red light emitting light emitting devices, green light emitting light emitting devices and blue light emitting light emitting devices. Due to the different light-emitting materials of light-emitting devices with different light-emitting colors, there are differences in response time, resulting in different turn-on times. It has been verified through experiments that even when the driving signals are received at the same time, the turn-on time of the light-emitting device that emits green light is generally later than that of the light-emitting device that emits red light and the light emitter that emits blue light.
  • the parasitic capacitance between the leads and between the leads and other conductive film layers such as pixel circuits Due to the parasitic capacitance between the leads and between the leads and other conductive film layers such as pixel circuits, it causes different degrees of delay in the turn-on time of the light-emitting device. After superimposing with the inherent delay of the light-emitting device, the screen appears visible to the human eye. color cast.
  • the light-emitting device that emits green light emits light significantly later than the light-emitting device that emits red light and the light-emitting device that emits blue light. Before the light-emitting device that emits green light emits light, there are only red and blue in the picture, thus showing purple stripes Or other purple screen.
  • the area of the overlapping area can be adjusted by changing the length of the leads, so that the parasitic capacitances of different leads tend to be consistent, but this will cause large differences in the length of the leads and lack of regularity.
  • the paths of the leads need to be specially designed according to different overlapping areas, and because there are many overlapping film layers and the structure is complex, it is impossible to truly make the parasitic capacitance consistent.
  • an embodiment of the present disclosure provides a display panel, which may be an OLED (Organic Light-Emitting Diode, Organic Light-Emitting Diode) display panel, as shown in Figures 1, 2, and 5-10.
  • the display panel includes a driving backplane 1, an transfer layer 2 and a light emitting layer 3, wherein:
  • the driving backplane 1 has a light transmission area 101 and a driving area 102 at least partially surrounding the light transmission area 101.
  • the driving area 102 has a plurality of pixel circuits 10, and the pixel circuits 10 include a first pixel circuit 110 and a second pixel circuit 120;
  • the driving backplane 1 has a plurality of first via holes 100, and each pixel circuit 10 is connected to a first via hole 100;
  • the transfer layer 2 is arranged on one side of the driving backplane 1 and covers the light-transmitting area 101 and the driving area 102; the transfer layer 2 includes multiple layers of lead layers 21 spaced apart from each other, and each lead layer 21 includes a plurality of lead lines 211 spaced apart from each other.
  • the transition layer 2 has a transition area 210 corresponding to the light transmission area 101 and a wiring area 220 corresponding to the drive area 102, the transition area 210 includes two transition areas 2110 separated on both sides of the first central axis S1;
  • the first central axis S1 is the central axis extending along the column direction of the transition area 210; each transition area 2101 has a plurality of second transition holes 201, and each second transition hole 201 connects a lead wire 211 with a first transition
  • the socket 100 is connected.
  • the light-emitting layer 3 is arranged on the side of the transfer layer 2 away from the driving backplane 1, and includes a plurality of light-emitting devices 30.
  • the light-emitting devices 30 include a plurality of first light-emitting devices 301 located in each transfer area 2101 and located in the wiring area 220.
  • the first transfer hole 100 and the second transfer hole 201 are arranged in a plurality of hole rows 001 distributed along the column direction, and the second transfer hole 201 is located in a part of the hole row 001; the first transfer hole 100 connected by the same lead wire 21 It is located in the same hole row 001 as the second connection hole 201, and forms a hole group 002; in two adjacent hole groups 002, the first transfer hole 100 and the second transfer hole 201 of a hole group 002 are located in the other hole Between the first transfer hole 100 and the second transfer hole 200 of group 002.
  • the length of any lead wire 21 in the row direction is the same as or different from the distance between the first via hole 100 and the second via hole 201 connected thereto by a specified length.
  • the row direction in the embodiments of the present disclosure may be the X direction in Figures 7-10, and the column direction may be the Y direction in Figures 7-10.
  • the actual orientation of the row direction and the column direction may change, not limited to the X and Y directions in the figure.
  • the row direction in the embodiment of the present disclosure The and column directions refer only to two directions perpendicular to each other.
  • the first pixel circuit 110 for driving the first light-emitting device 301 is arranged in the driving region 102 outside the light-transmitting region 101 , which can improve the performance without reducing the number of light-emitting devices 30 .
  • the degree of light transmission of the light transmission area 101 is convenient for the imaging device to capture images.
  • the first light-emitting device 301 in the light-transmitting area 101 is connected to the first pixel circuit 110 through the lead 211 of the multi-layer lead layer 21 and the first via hole 100 and the second via hole 201, so that the light-transmitting area 101 Images can be displayed normally, and multiple lead layers 21 can increase the layout space of lead wires 211.
  • each first light-emitting device 301 can still be It is connected with the first pixel circuit 110 to avoid reducing the quantity of the first light emitting device 301 due to the inability to provide enough lead wires 211 .
  • the second light-emitting device 302 is connected to the second pixel circuit 120 and can display images outside the light-transmitting region 101 .
  • the length of the lead wire 21 in the row direction is the same as or differs from the distance between the first via hole 100 and the second via hole 201 by a specified length, so as long as the interconnected first via hole is known 100 and the second transfer hole 201, the length of the lead wire 21 connecting the two in the row direction can be determined, so that the driving signal can be controlled by means of external compensation, at least the delay in the turn-on time caused by the lead wire 21 can be compensated , thereby improving the color cast phenomenon.
  • the external compensation method may be external optical compensation (demura) or other methods, as long as the lighting time of different first light emitting devices 301 can be supplemented to make them tend to be consistent.
  • Compensation data is generated according to the display data of the identified color shift area, the length of the lead wire, and a preset compensation algorithm; the display data may include brightness values and timings of brightness values, and the like. As long as the distance between the interconnected first transition hole 100 and the second transition hole 201 is known, the length of the lead wire 21 connecting the two in the row direction can be determined. Compared with setting the extension path of the lead wire 21 irregularly, it is easier Compensation algorithms are easily predetermined.
  • the compensation data is stored in the internal or external control circuit of the display panel.
  • the compensation data can be used to compensate the driving signal of the first light-emitting device 301 that causes color shift, thereby eliminating the color shift.
  • the driving backplane 1 is provided with a pixel circuit 10 for driving the light-emitting device 30 to emit light, and the driving backplane 1 at least includes a light-transmitting region 101 and a driving region 102 outside the light-transmitting region 101, wherein the pixel circuit 10 is located in the driving area 102, and the pixel circuit 10 is not provided in the light-transmitting area 101 to improve transparency, and the imaging device can capture images through the light-transmitting area 101, thereby realizing off-screen imaging.
  • the pixel circuit 10 in the driving area 102 includes at least a first pixel circuit 110 and a second pixel circuit 120, wherein the first pixel circuit 110 is used to drive the light-emitting device corresponding to the light-transmitting area 101, that is, the second A light emitting device 301 ; the second pixel circuit 120 is used to drive the light emitting device corresponding to the driving region 102 , that is, the second light emitting device 302 .
  • the driving region 102 may include a pixel region 1021 and an edge region 1022 , wherein the pixel region 1021 is at least partially surrounded by the light-transmitting region 101 , and the light-transmitting region 101 A side of the pixel area 1021 may at least partially overlap with a side of the pixel region 1021 .
  • the edge area 1022 can surround the pixel area 1021, and a peripheral circuit for inputting a driving signal to the pixel circuit 10 can be provided in the edge area 1022, and the peripheral circuit can include a gate drive circuit, a light emission control circuit, a power supply circuit, etc., here No special restrictions are made.
  • the pixel area 1021 can also completely surround the light-transmitting area 101 , and the edge area 1022 can surround the pixel area 1021 .
  • all the first pixel circuits 110 may be distributed in the pixel area 1021 , and all the second pixel circuits 120 are also distributed in the pixel area 1021 .
  • a part of the second pixel circuits 120 may also be arranged in the pixel region 1021 , all the first pixel circuits 110 are also distributed in the pixel region 1021 , and other second pixel circuits 120 are arranged in the edge region 1022 .
  • a plurality of first via holes 100 are provided in the pixel area 1021 , and each first via hole 100 is connected to each pixel circuit 10 in a one-to-one correspondence so as to output a driving signal.
  • each column of first pixel circuits 110 is located between each column of second pixel circuits 120, and at most one column of first pixel circuits 110 is provided between two adjacent columns of second pixel circuits 120;
  • One or more columns of second pixel circuits 120 may be disposed between two adjacent columns of first pixel circuits 110 .
  • the driving region 102 In order not to reduce the number of pixel circuits 10 , there is enough space in the driving region 102 to accommodate the first pixel circuit 110 and the second pixel circuit 120 . At least part of the pixel circuits 10 can be compressed along the row direction to reduce the width of the pixel circuits 10 in the row direction. On the premise that the size of the driving backplane 1 is the same, more areas can be added in the driving region 102, and the The first pixel circuit 110 is provided at the large area.
  • the width of the pixel circuit 10 refers to the length of the orthographic projection of the pixel circuit 10 on the driving backplane 1 along the row direction.
  • the structure of the pixel circuit 10 is illustrated as follows:
  • the pixel circuit 10 (the first pixel circuit 110 and the second pixel circuit 120 ) may have a 7T1C structure, that is, it includes 7 transistors and 1 capacitor.
  • the 7T1C pixel circuit includes a drive transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7 and a storage capacitor C1.
  • the pixel circuit can be connected with the gate signal terminal Gate, the data signal terminal Data, the reset signal terminals RST1 and RST2, the light emission control signal terminal EM, the power supply terminal VDD, the initial power supply terminals Vinit1 and Vinit2, and the light emitting device.
  • the light emitting device can also be Connect with the power supply terminal VSS.
  • the pixel circuit 10 can be used to drive the connected light emitting device 30 to emit light in response to the signals provided by the connected signal terminals.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors are P-type transistors as an example for description. Based on the description and teaching of this implementation in the present disclosure, those skilled in the art can easily think of using N-type transistors for at least some of the transistors in the pixel circuit structure of the embodiments of the present disclosure, that is, using N-type transistors without creative work. Type transistors or combinations of N-type transistors and P-type transistors, therefore, these implementations are also within the protection scope of the embodiments of the present disclosure.
  • the pixel circuit 10 may also adopt other structures as long as it can drive the light emitting device 30 to emit light, and no special limitation is imposed on the structure here.
  • the driving backplane 1 may include an active layer, a first gate insulating layer, a gate, a second gate insulating layer, a dielectric layer,
  • the first source-drain layer, the first planarization layer, the second source-drain layer and the second planarization layer form a transistor, and the specific structure of the transistor is not specifically limited here.
  • the first via hole 100 can be disposed in the second planarization layer, so that the lead 21 can be connected with the second source-drain layer.
  • the transfer layer 2 is disposed on the side of the driving backplane 1 , for example, the transfer layer 2 is disposed on the surface of the second planarization layer away from the substrate.
  • the transfer layer 2 can cover the light-transmitting region 101 and the driving region 102, and the transfer layer 2 includes multiple layers of wiring layers 21 spaced apart from each other.
  • the orthographic projections on the driving backplane 1 extend from the light-transmitting area 101 to the driving area 102, and are connected to a first pixel circuit 110 through a first transfer hole 100, that is, each lead 211 is only used for transmission A signal from a first pixel circuit 110.
  • the transfer layer 2 has a transfer region 210 corresponding to the light-transmitting region 101 and a wiring region 220 corresponding to the driving region 102.
  • the boundary of the line region 220 coincides with the boundary of the drive region 102 .
  • the transition area 210 may include two transition zones 2101 separated on both sides of the first central axis S1.
  • the first central axis S1 is the central axis extending along the column direction of the transition area 210; each transition area 2101 has a plurality of second transition holes 201, and each second transition hole 201 is connected to each lead wire 211 in a one-to-one correspondence, Any first light-emitting device 301 can be connected to the corresponding first pixel circuit 110 through a second via hole 201 and a lead wire 211 .
  • the second via hole 201 may be a via structure in the transfer layer 2, but since the leads 211 connected to the second via hole 201 may be located in different lead layers 21, different second via holes 201 Depth can vary.
  • the material of the lead 211 of each lead layer 21 may be a transparent material such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO).
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the number of wiring layers 21 may be three layers, including the first wiring layer 21a, the second wiring layer 21b and the The third wiring layer 21c.
  • the leads 211 of the first lead layer 21a include first leads 211a
  • the leads 211 of the second lead layer 21b include second leads 211b
  • the leads 211 of the third lead layer 21c include third leads 211c.
  • FIG. 5 is only schematically shown for illustrating the relationship between the various film layers of the display panel, and is not limited to the specific structure of the lead layer 21 .
  • the transfer layer 2 further includes a first flat layer 22, a second flat layer 23 and a third flat layer 24, wherein:
  • the first wiring layer 21a can be disposed on the surface of the driving backplane 1 close to the light-emitting layer 3 .
  • the first flat layer 22 covers the first wiring layer 21 a and the surface of the driving backplane 1 close to the light emitting layer 3 .
  • the second wiring layer 21 b is disposed on the surface of the first flat layer 22 away from the driving backplane 1 .
  • the second flat layer 23 covers the surface of the second wiring layer 21b and the first flat layer 22 close to the light-emitting layer 3 .
  • the third wiring layer 21c is disposed on the surface of the second flat layer 23 away from the driving backplane 1 .
  • the third flat layer 24 covers the surface of the third wiring layer 21 c and the second flat layer 23 close to the light-emitting layer 3 ; the light-emitting layer 3 is disposed on the surface of the third flat layer 24 away from the driving backplane 1 .
  • the light-emitting layer 3 is disposed on the side of the transfer layer 2 away from the driving backplane 1 , for example, the light-emitting layer 3 is disposed on the surface of the third flat layer 24 away from the driving backplane 1 .
  • the light-emitting layer 3 covers the transition area 210 and the wiring area 220 on the driving backplane 1, and the light-emitting layer 3 may include a plurality of light-emitting devices 30, and the light-emitting devices 30 include a first light-emitting device 301 located in the transition area 210 and The second light emitting device 302 located in the wiring area 220 .
  • Any first light-emitting device 301 can be connected to a first pixel circuit 110 through a second transfer hole 201, a lead wire 211 and the first transfer hole 201, and any second light-emitting device 32 can be connected to a first pixel circuit 110 through a first transfer hole 201.
  • the hole 210 is connected to a second pixel circuit 120 .
  • each light-emitting device 30 can be an OLED, which can include a first electrode 311, a light-emitting functional layer 312, and a second electrode 313, wherein:
  • the first electrodes 311 may be disposed on the surface of the transfer layer 2 away from the driving backplane 1 , for example, the first electrodes 311 are disposed on the surface of the third flat layer 24 away from the driving backplane 1 .
  • the first electrode 311 is used as the anode of the OLED light-emitting device, and has an electrode portion 3111 and a connection portion 3112 located outside the edge of the electrode portion 3111.
  • the connection portion 3112 is connected to the electrode portion 3111 or adopts an integral structure.
  • each first electrode 311 is connected to a lead wire 211 through a connection portion 3112 and a second via hole 201 , so as to connect the first pixel circuit 110 to the first electrode 311 of the corresponding light emitting device 30 .
  • Orthographic projections of the interconnected wiring portion 3112 and the second transition hole 201 on the drive backplane 1 are at least partially coincident.
  • the light-emitting functional layer 312 can be disposed on the surface of the first electrode 311 away from the driving backplane 1 , and can include a hole transport layer, an organic light-emitting layer and an electron transport layer stacked on the first electrode 311 in sequence.
  • the second electrode 313 serves as a cathode of the OLED light-emitting device, and can be disposed on the surface of the light-emitting functional layer 312 away from the driving backplane 1 .
  • the light-emitting functional layer 312 can be driven to emit light by applying electrical signals to the first electrode 311 and the second electrode 313 .
  • each light emitting device 30 can be made of the same material and formed simultaneously through a patterning process. The materials are different. Meanwhile, each light emitting device 30 can share the same second electrode 313 , that is, the second electrode 313 can cover each light emitting functional layer 312 at the same time.
  • the light-emitting layer 3 may further include a pixel definition layer 314, which may be disposed on the surface of the transfer layer 2 away from the driving backplane 1, and has an opening exposing each of the first electrodes 311 , the light-emitting functional layer 312 can cover the first electrode 311 in each opening, and expose the electrode part 3111, the wiring part 3112 is located outside the opening, and the second electrode 313 can cover the surface of the pixel definition layer away from the driving backplane 1, and be recessed to the opening Inside.
  • a pixel definition layer 314 may be disposed on the surface of the transfer layer 2 away from the driving backplane 1, and has an opening exposing each of the first electrodes 311
  • the light-emitting functional layer 312 can cover the first electrode 311 in each opening, and expose the electrode part 3111
  • the wiring part 3112 is located outside the opening
  • the second electrode 313 can cover the surface of the pixel definition layer away from the driving backplane 1, and be recessed to the opening Inside.
  • the density of the first light-emitting devices 301 in the region corresponding to the light-transmitting region 101 can be made the same as the density of the second light-emitting devices 302 in the region corresponding to the driving region 102 .
  • the light-transmissive region 101 can be divided into two transfer regions 2101 distributed along the row direction.
  • the first light emitting devices 301 are distributed in the two transfer zones 2101 .
  • the two transition sections 2101 are symmetrical about the first central axis S1, and the first light emitting device 301 and the lead wires 211 connected thereto in the two transition sections 2101 are also arranged symmetrically about the first central axis S1.
  • the first transfer holes 100 and the second transfer holes 201 are arranged in a plurality of hole rows 001 distributed along the column direction, each hole row 001 includes a plurality of first transfer holes 100, And each second via hole 201 is located in the partial hole row 001 .
  • the first transition hole 100 and the second connection hole 201 connected by the same lead wire 211 are located in the same hole row 001 and form a hole group 002 .
  • the first transfer hole 100 and the second transfer hole 201 of one hole group 002 are located between the first transfer hole 100 and the second transfer hole 201 of the other hole group 002 .
  • the length of the lead wire 211 in the row direction is the same as or different from the distance between the first pixel circuit 110 and the first light emitting device 301 by a specified length, so as to compensate by means of external compensation and improve color shift.
  • N hole rows 001 there are N hole rows 001 , and each second transfer hole 201 is located in each of the i-th hole rows.
  • N, i and j are all positive integers, and 1 ⁇ i ⁇ j ⁇ N.
  • any adjacent two of the i-th hole rows 001 at least part of the lead wires 211 connected to the second transition holes 201 of a hole row 001 are located between the two adjacent hole rows 001 .
  • the leads 21 connected to the second transition holes 201 in the k-th hole row 001 are located between the k-1th hole row 001 and the k-th hole row 001; k is a positive integer, and i ⁇ k ⁇ j;
  • the leads 211 connected to the second transition holes 201 of the i-th hole row are located on the side of the i-th hole row 001 away from the j-th hole row 001 .
  • the space between two adjacent hole rows 001 can accommodate a limited number of lead wires 211, therefore, in at least one of the i-th hole rows 001, at least part of the second transition holes 201 connected A part of the lead wire 211 is located on the side of the i-th hole row 001 away from the j-th hole row 001 .
  • the wiring area 220 includes a main body area and a peripheral area, the main body area is at least partially surrounded by the transfer area 210, and the peripheral area is surrounded by the main body area and the outer transfer area 210; at least part of the first pixel circuits 110 are distributed on the drive back Plate 1 corresponds to the area of the main body area.
  • At least part of the lead wires 211 connected to at least some of the second via holes 201 are located in the peripheral area.
  • At least a partial area of the leads 211 connected to at least some of the second transition holes 201 is located on the side of the j-th hole row 001 away from the i-th hole row 001.
  • the transition section 2101 may include a plurality of sub-sections 21011 distributed along the row direction, and each sub-section 21011 is provided with a second via hole 201 .
  • the leads 211 connected to the first light emitting devices 301 in the same subregion 21011 are located in the same lead layer 21 .
  • the sub-sections 21011 of the same transfer section 2101 include the first sub-section 21011a, the second sub-section 21011b, and the third sub-section 21011c that are sequentially distributed along the row direction toward the first central axis S1, and the first sub-section 21011a
  • the leads 211 connected to the second transition holes 201 in the second sub-division 201 are the first leads 211a
  • the leads 211 connected to the second transition holes 201 in the second sub-section 21011b are the second leads 211b
  • the lead wires 211 connected to the second transition holes 201 are the third lead wires 211c.
  • the first lead wire 211a, the second lead wire 211b and the third lead wire 211c connected to the second transfer hole 201 of the k-th hole row 001 are located in the k-1 and k-th hole rows between 001.
  • the first lead 211a, the second lead 211b and the third lead 211c connected to the second transition hole 201 in the i-th hole row 001 are located on the side of the i-th hole row 001 away from the j-th hole row 001 .
  • the leads 211 of the first lead layer 21a further include fourth leads 211d.
  • the sub-section 21011 of the same transfer section 2101 includes a fourth sub-section 21011d located between the third sub-section 21011c and the first central axis S1; the leads 211 connected to the second transfer holes 201 in the fourth sub-section 21011d is the fourth lead 211d.
  • At least a partial area of at least part of the fourth lead 211d is located on the side of the i-th hole row 001 away from the j-th hole row 001 . At least a partial area of at least part of the fourth lead 211d is located on the side of the j-th hole row 001 away from the i-th hole row 001 .
  • the fourth subdivision 21011d includes a first subdivision 21011d1 and a second subdivision 21011d2 separated on both sides of the second central axis S2, and the second central axis S2 is the transfer area 210 A central axis extending in the row direction.
  • Part of the second transfer holes 201 of the i-th hole row 001 are located in the first sub-division 21011d1, and some of the second transfer holes 201 of the k+1-j-th hole row 001 are located in the second sub-division 21011d2; k+ 1 ⁇ j.
  • At least a partial area of the fourth lead wire 211d connected to the second via hole 201 of the first sub-region 21011d1 is located on the side of the i-th hole row 001 away from the j-th hole row 001 .
  • At least a partial area of the fourth lead wire 211d connected to the second transition hole 201 of the second sub-section 21011d2 is located on the side of the j-th hole row 001 away from the i-th hole row 001 .
  • the lead wire 211 may include two lead-out segments 2110 and an extension segment 2120 connecting the two lead-out segments 2110.
  • the lead-out segment 2110 extends along the column direction, and the extension segment 2120 extends in the row direction.
  • the length of the extension section 2120 of any one of the first lead 211a, the second lead 211b and the third lead 211c is the same as the distance between the first transfer hole 100 and the second transfer hole 201 connected thereto.
  • the length of the lead-out section 2110 of any one of the second lead 211b and the third lead 211c along the column direction is smaller than the distance between two adjacent hole rows 001 .
  • the distance between the first transfer hole 100 and the second transfer hole 201 is: the distance between the center of the first transfer hole 100 and the center of the orthographic projection of the second transfer hole 201 on the driving backplane 1 .
  • the lead-out segment 2110 of the fourth lead 211d connected to the k-th hole row 001 may include the first segment 21101 distributed along the column direction , the second section 21102 and the third section 21103, one end of the first section 21101 is connected to a second transition hole 201, the other end is connected to one end of the second section 21102, the other end of the second section 21102 is connected to the third section 21103 One end of the third section 21103 is connected to one end of the extension section 2120;
  • the first section 21101 and the third section 21103 extend straight along the column direction, and the third section 21103 is located on the side of the second transfer hole 201 connected to the first section 21101 away from or close to the first central axis S1;
  • the connection hole 201 is located on the extension line of the extension path of the first segment 21101 .
  • the second section 21102 extends along a straight line and forms a specified angle with the first section 21101 and the third section 21103 so that the third section 21103 is arranged parallel to the first section 21101 .
  • the length of the extension section 2120 of the fourth lead wire 211d connected to the kth hole row 001 is different from the distance between the first transition hole 100 and the second transition hole 201 connected to it by a specified length, and the specified length is the first section 21101 and the second transition hole 201.
  • the length of the extension section 2120 of the fourth lead wire 211d connecting the i-th and j-th hole rows 001 is the same as the distance between the first via hole 100 and the second via hole 201 connected thereto.
  • Embodiments of the present disclosure also provide a display device, which may include the display panel in any of the above embodiments.
  • a display device which may include the display panel in any of the above embodiments.
  • the structure and beneficial effects of the display panel reference may be made to the above embodiment of the display panel, which will not be repeated here.
  • Embodiments of the present disclosure also provide a terminal device.
  • the terminal device may include a display device 1000 and a camera device 2000, wherein:
  • the display device 1000 can be a display device in any of the above-mentioned implementation manners, and its structure and beneficial effects can refer to the implementation manners of the display panel and the display device above, and will not be repeated here.
  • the imaging device 2000 can be arranged on the backlight side of the display device 1000, that is, the back side where the light is directed.
  • the light emitting device of the display device 1000 is a top emission structure, that is, emits light in a direction away from the driving backplane 1, and the imaging device 2000 can be set On the side of the driving backplane 1 away from the light-emitting layer 3 , and the imaging device 2000 can face the light-transmitting region 101 for capturing images through the light-transmitting region 101 .
  • the imaging device 2000 can be disposed on the side of the light emitting layer 3 away from the driving backplane 1 .
  • the camera device 2000 may include a lens, a photoelectric sensor, etc., and the specific structure of the camera device 2000 is not limited here, as long as it can capture images.
  • the terminal device of the present disclosure may be a mobile phone, a tablet computer, a television, and other electronic devices with display and shooting functions, which will not be listed here.

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Abstract

一种显示面板、显示装置（1000）及终端设备。显示面板包括驱动背板（1）、转接层（2）和发光层（3），驱动背板（1）具有透光区（101）和驱动区（102），驱动区（102）的像素电路（10）包括第一像素电路（110）和第二像素电路（120）；驱动背板（1）具有第一转接孔（100），像素电路（10）与第一转接孔（100）连接；转接层（2）包括多层引线层（21），转接层（2）的转接区（210）包括两转接分区（2110）；转接分区（2110）的第二转接孔（201）通过引线（211）与第一转接孔（100）连接；发光层（3）的发光器件（30）包括与第二转接孔（201）连接的第一发光器件（301）和与第一转接孔（100）连接的第二发光器件（302）；第一转接孔（100）和第二转接孔（201）排列成沿列方向分布的多个孔行（001）；同一引线（211）连接的第一转接孔（100）和第二连接孔（201）位于同一孔行（001）并组成一孔组（002）；相邻两孔组（002）中的一孔组（002）的第一转接孔（100）和第二转接孔（201）位于另一孔组（002）的第一转接孔（100）和第二转接孔（201）之间。

Description

显示面板、显示装置及终端设备 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板、显示装置及终端设备。
背景技术
对于手机、平板电脑等具有摄像头的电子设备的屏幕而言，屏幕对应于摄像头的区域通常需要开孔，从而无法发光，这不利于提高屏占比。目前，虽然存在屏下摄像技术，使得摄像头所在区域也可显示图像，避免开孔，并可正常拍摄，但屏幕对应于摄像头的区域在显示图像时，容易出现色偏现象，特别是容易出现偏绿的现象，影响显示效果。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种显示面板、显示装置及终端设备。
根据本公开的一个方面，提供一种显示面板，包括：
驱动背板，具有透光区和至少部分围绕于所述透光区外的驱动区，所述驱动区具有多个像素电路，所述像素电路包括第一像素电路和第二像素电路；所述驱动背板具有多个第一转接孔，任一所述像素电路与一所述第一转接孔连接；
转接层，设于所述驱动背板一侧且覆盖所述透光区和所述驱动区；所述转接层包括多层相互间隔的引线层，每个所述引线层包括多个相互间隔的引线；所述转接层具有对应于所述透光区的转接区和对应于所述驱动区的走线区，所述转接区包括分隔于第一中轴线两侧的两转接分区；所述第一中轴线为所述转接区沿列方向延伸的中轴线；各所述转接分区具有多个第二转接孔，任一所述第二转接孔通过一所述引线与一所述第一转接孔连接；
发光层，设于所述转接层背离所述驱动背板的一侧，且包括多个发光器件，所述发光器件包括位于各所述转接分区的多个第一发光器件和位于所述走线区的多个第二发光器件；任一所述第一发光器件与一所述第二转接孔连接，任一所述第二发光器件与一所述第一转接孔连接；
所述第一转接孔和所述第二转接孔排列成沿列方向分布的多个孔行，各所述第二转接孔位于部分所述孔行中；同一所述引线连接的第一转接孔和第二连接孔位于同一所述孔行，并组成一孔组；在相邻两所述孔组中，一所述孔组的第一转接孔和第二转接孔位于另一所述孔组的第一转接孔和第二转接孔之间；
任一所述引线在所述行方向上的长度与其连接的第一转接孔和第二转接孔的间距相同或相差指定长度。
在本公开的一种示例性实施例中，所述孔行有N个，各所述第二转接孔位于第i至j个所述孔行中的每一个；N、i和j均为正整数，且1≤i＜j≤N；
在第i至j个所述孔行中的任意相邻两个中，一所述孔行的至少部分第二转接孔所连接的引线位于该相邻两个所述孔行之间。
在本公开的一种示例性实施例中，第k个所述孔行中的第二转接孔所连接的引线，位于第k-1和k个所述孔行之间；k为正整数，且i＜k≤j；
第i个所述孔行的第二转接孔所连接的引线位于第i个所述孔行背离第j个所述孔行的一侧。
在本公开的一种示例性实施例中，在第i至j个所述孔行的至少一个中，至少部分所述第二转接孔所连接的引线的部分区域，位于第i个所述孔行背离第j个所述孔行的一侧。
在本公开的一种示例性实施例中，所述走线区包括主体区和***区，所述主体区至少部分围绕于所述转接区外，所述***区围绕于所述主体区和所述转接区外；至少部分所述第一像素电路分布于所述驱动背板对应于所述主体区的区域内；
在第i个所述孔行中，至少部分所述第二转接孔所连接的引线的至少部分区域位于所述***区。
在本公开的一种示例性实施例中，在第i至j个所述孔行的至少一个中，至少部分所述第二转接孔所连接的引线的至少部分区域，位于第j个所述孔行背离第i个所述孔行的一侧。
在本公开的一种示例性实施例中，所述转接分区包括沿所述行方向分布的多个子分区，各所述子分区均设有所述第二转接孔；
同一所述子分区内的第二转接孔所连接的引线位于同一所述引线层。
在本公开的一种示例性实施例中，多层所述引线层中至少包括从所述驱动背板向所述发光层依次分布的第一引线层、第二引线层和第三引线层；所述第一引线层的引线包括第一引线，所述第二引线层的引线包括第二引线，所述第三引线层的引线包括第三引线；
同一所述转接分区的子分区包括沿行方向朝所述第一中轴线依次分布的第一子分区、第二分区和第三子分区，所述第一子分区内的各第二转接孔所连接的引线为所述第一引线，所述第二子分区内的各第二转接孔所连接的引线为所述第二引线，所述第三子分区内的各第二转接孔所连接的引线为所述第三引线。
在本公开的一种示例性实施例中，若i＜k≤j；
连接第k个所述孔行的第二转接孔的第一引线、第二引线和第三引线，位于第k-1和k个所述孔行之间；
第i个所述孔行中的第二转接孔所连接的第一引线、第二引线和第三引线位于第i个所述孔行背离第j个所述孔行的一侧。
在本公开的一种示例性实施例中，所述第一引线层的引线还包括第四引线；
同一所述转接分区的子分区包括位于所述第三子分区和所述第一中轴线之间的第四子分区；所述第四子分区内的各第二转接孔所连接的引线为所述第四引线；
至少部分所述第四引线的至少部分区域位于第i个所述孔行背离第j个所述孔行的一侧；
至少部分所述第四引线的至少部分区域位于第j个所述孔行背离第i个所述孔行的一侧。
在本公开的一种示例性实施例中，所述第四子分区包括分隔于第二中轴线两侧的第一亚分区和第二亚分区，所述第二中轴线为所述转接区沿行方向延伸的中轴线；第i至k个所述孔行的部分第二转接孔位于所述第一亚分区，第k+1至j个所述孔行的部分第二转接孔位于所述第二亚分区；k+1≤j；
所述第一亚分区的第二转接孔所连接的第四引线的至少部分区域位于第i个所述孔行背离第j个所述孔行的一侧；
所述第二亚分区的所述第二转接孔所连接的第四引线的至少部分区域位于第j个所述孔行背离第i个所述孔行的一侧。
在本公开的一种示例性实施例中，所述引线包括两个所述引出段以及连接两所述引出段的延伸段；所述引出段沿所述列方向延伸，所述延伸段沿所述行方向延伸；
所述第一引线、所述第二引线和所述第三引线中的任一个的延伸段的长度与其连接的第一转接孔和第二转接孔的间距相同。
在本公开的一种示例性实施例中，若i＜k＜j；
连接第k个所述孔行的第四引线的引出段，包括沿所述列方向分布的第一段、第二段和第三段，所述第一段的一端与一所述第二转接孔连接，另一端与所述第二段的一端连接，所述第二段的另一端与所述第三段的一端连接，所述第三段的另一端与所述延伸段的一端连接；
所述第一段和所述第三段沿所述列方向直线延伸，且所述第三段位于所述第一段所连接的第二转接孔背离或靠近所述第一中轴线的一侧；
连接第k个所述孔行的第四引线的延伸段的长度，与其连接的所述第一转接孔和第二转接孔的间距相差指定长度。
在本公开的一种示例性实施例中，连接第i和j个所述孔行的第四引线的延伸段的长度，与其连接的第一转接孔和第二转接孔的间距相同。
在本公开的一种示例性实施例中，连接所述第一亚分区中的第二转接孔的第四引线与连接所述第二亚分区的第二转接孔的第四引线关于所述第二中轴线对称设置。
在本公开的一种示例性实施例中，连接两所述转接分区的第二转接孔的引线关 于所述第一中轴线对称设置。
在本公开的一种示例性实施例中，所述发光器件包括：
第一电极，设于所述转接层背离所述驱动背板的表面；所述第一电极具有电极部和位于所述电极部边缘以外的接线部；所述接线部通过一所述第二转接孔与一所述引线连接；
发光功能层，设于所述第一电极背离所述驱动背板的表面；
第二电极，设于所述发光功能层背离所述驱动背板的表面。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
根据本公开的一个方面，提供一种终端设备，包括：
上述任意一项所述的显示装置；
摄像装置，设于所述驱动背板背离所述发光层的背光侧，且与所述透光区正对设置，用于透过所述透光区拍摄图像。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式中驱动背板的示意图。
图2为本公开显示面板一实施方式中像素电路与发光器件连接的示意图。
图3为本公开显示面板一实施方式中像素电路的等效电路图。
图4为本公开显示面板一实施方式中像素电路的结构示意图。
图5为本公开显示面板一实施方式中显示面板的截面示意图。
图6为本公开显示面板一实施方式中第一电极的俯视图。
图7为本公开显示面板一实施方式中转接层的各走线区的示意图。
图8为本公开显示面板一实施方式中第一引线层的连接示意图。
图9为本公开显示面板一实施方式中第二引线层的连接示意图。
图10为本公开显示面板一实施方式中第三引线层的连接示意图。
图11为本公开显示面板一实施方式中第一引线的示意图。
图12为本公开显示面板一实施方式中第四引线的示意图。
图13为本公开显示装置一实施方式的示意图。
附图标记说明：
1、驱动背板；101、透光区；102、驱动区；1021、像素区；1022、***区；10、像素电路；110、第一像素电路；120、第二像素电路；100、第一转接孔；
2、转接层；210、转接区；2101、转接分区；21011、子分区；21011a、第一子分区；21011b、第二子分区；21011c、第三子分区；21011d、第四子分区；21011d1、第一亚分区；21011d2、第二亚分区；220、走线区；21、引线层；211、引线；21a、第一引线层；211a、第一引线；21b、第二引线层；211b、第二引线；21c、第三引线层；211c、第三引线；211d、第四引线；201、转接孔；2110、引出段；21101、第一段；21102、第二段；21103、第三段；2120、延伸段；22、第一平坦层；23、第二平坦层；24、第三平坦层；
3、发光层；30、发光器件；301、第一发光器件；302、第二发光器件；311、第一电极；3111、电极部；3112、接线部；312、发光功能层；313、第二电极；314、像素定义层；301、第一发光器件；302、第二发光器件；
001、孔行；002、孔组；
1000、显示装置；2000、摄像装置。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，用于实现屏下摄像的显示面板具有透光区和透光区外的驱动区，透光区和驱动区均设有多个发光器件。同时，驱动区内设有用于驱动全部发光器件的像素电路，透光区内则无像素电路，以便提高透光程度，从而可利用摄像装置通过透光区拍摄图像。为了便于驱动透光区内的发光器件发光，可通过由透光区延伸至驱动区的引线，将透光区内的发光器件与驱动区内对应的像素电路连接起来，而驱动区内的发光器件则直接与驱动区内对应的像素电路连接。
发光器件中至少包括发红光的发光器件，发绿光的发光器件和发蓝光的发光器件。由于发光颜色不同的发光器件的发光材料不同，使其响应时间存在差异，导致启亮时间不同。经过试验验证，即便在同时接收到驱动信号的情况下，发绿光的发光器件的启亮时间通常也晚于发红光的发光器件和发蓝光的发光器。
由于引线之间以及引线与像素电路等其它导电膜层之间存在寄生电容，对发光器件的启亮时间造成了不同程度的延迟，在与发光器件固有的延迟叠加后，使得画面出现人眼可见的色偏。特别是，发绿光的发光器件的明显晚于发红光的发光器件和发蓝光的发光器发光，在发绿光的发光器件发光前，画面中只有红色和蓝色，因而呈现出紫色条纹或其它偏紫的画面。
为了减小引线的寄生电容的影响，可通过改变引线的长度，调节该交叠区域的面积，使不同引线的寄生电容趋于一致，但这会使引线的长度差异较大，且缺乏规律，需要根据不同的交叠区域专门设计引线的路径，而且，由于存在交叠的膜层较多，结构复杂，无法真正使寄生电容一致。
基于以上分析，本公开实施例提供了一种显示面板，该显示面板可为OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，如图1、图2、图5-图10所示，该显示面板包括驱动背板1、转接层2和发光层3，其中：
驱动背板1具有透光区101和至少部分围绕于透光区101外的驱动区102，驱动区102具有多个像素电路10，像素电路10包括第一像素电路110和第二像素电路120；驱动背板1具有多个第一转接孔100，每个像素电路10与一第一转接孔100连接；
转接层2设于驱动背板1一侧且覆盖透光区101和驱动区102；转接层2包括多层相互间隔的引线层21，每个引线层21包括多个相互间隔的引线211；转接层2具有对应于透光区101的转接区210和对应于驱动区102的走线区220，转接区210包括分隔于第一中轴线S1两侧的两转接分区2110；第一中轴线S1为转接区210沿列方向延伸的中轴线；各转接分区2101具有多个第二转接孔201，每个第二转接孔201通过一引线211与一第一转接孔100连接。
发光层3设于转接层2背离驱动背板1的一侧，且包括多个发光器件30，发光器件30包括位于各转接分区2101的多个第一发光器件301和位于走线区220的多个第二发光器件302；各第一发光器件301与各第二转接孔201一一对应地连接，各第二发光器件302与各第一转接孔100一一对应地连接。
第一转接孔100和第二转接孔201排列成沿列方向分布的多个孔行001，第二转接孔201位于部分孔行001中；同一引线21连接的第一转接孔100和第二连接孔201位于同一孔行001，并组成一孔组002；在相邻两孔组002中，一孔组002的第一转接孔100和第二转接孔201位于另一孔组002的第一转接孔100和第二转接孔200之间。
任一引线21在行方向上的长度与其连接的第一转接孔100和第二转接孔201的间距相同或相差指定长度。
需要说明的是，本公开实施方式中的行方向可为图7-图10中的X方向，列方 向可为图7-图10中Y方向。但是，本领域技术人员可以知晓的是，若显示面板发生转动，则行方向和列方向的实际朝向可能发生变化，而不限于是图中的X和Y方向，本公开实施方式中的行方向和列方向仅指相互垂直的两个方向。
本公开实施方式的显示面板，将用于驱动第一发光器件301的第一像素电路110设置在了透光区101以外的驱动区102，在不减少发光器件30的数量的情况下，可提升透光区101的透光程度，便于摄像装置拍摄图像。同时，通过多层引线层21的引线211以及第一转接孔100和第二转接孔201，将透光区101的第一发光器件301与第一像素电路110连接，使得透光区101可正常显示图像，且多个引线层21可增大引线211的布设空间，在透光区101的范围内的第一发光器件301较多的情况下，仍可将每个第一发光器件301与第一像素电路110连接，避免因为无法设置足够的引线211而减少第一发光器件301的数量。第二发光器件302与第二像素电路120连接，可在透光区101以外显示图像。
此外，由于在任一孔组002中，引线21在行方向上的长度与第一转接孔100和第二转接孔201的间距相同或相差指定长度，使得只要知道相互连接的第一转接孔100和第二转接孔201的间距，就可以确定连接二者的引线21在行方向上的长度，从而可通过外部补偿的方式对驱动信号进行控制，至少补偿引线21造成的启亮时间的延迟，从而改善色偏现象。该外部补偿的方式可以是外部光学补偿(demura)或其它方式，只要能对不同第一发光器件301的启亮时间进行补充，使其趋于一致即可。
以外部光学补偿为例，可至少通过如下步骤进行补偿：
使显示面板显示测试画面；
用拍摄装置对测试画面进行拍摄；通过对拍摄的图像进行分析，识别出透光区101的色偏区域；
根据识别出的色偏区域的显示数据、引线长度以及预设的补偿算法，生成补偿数据；显示数据可包括亮度值及亮度值的时序等。只要知道相互连接的第一转接孔100和第二转接孔201的间距，就可以确定连接二者的引线21在行方向上的长度，相较于无规律的设置引线21的延伸路径，更容易预先确定补偿算法。
将补偿数据存储于显示面板内设或外接的控制电路中，在驱动显示面板显示画面时，可通过补偿数据对引起色偏的第一发光器件301的驱动信号进行补偿，从而消除色偏。
下面对本公开显示面板进行详细说明：
如图1所示，驱动背板1中设有用于驱动发光器件30发光的像素电路10，且驱动背板1至少包括透光区101和透光区101外的驱动区102，其中，像素电路10位于驱动区102，而透光区101中则不设置像素电路10，以提高透明度，摄像装置可透过透光区101拍摄图像，从而实现屏下摄像。
如图2所示，驱动区102中的像素电路10至少包括第一像素电路110和第二像素电路120，其中，第一像素电路110用于驱动对应于透光区101的发光器件，即第一发光器件301；第二像素电路120用于驱动对应于驱动区102的发光器件，即第二发光器件302。
在本公开的一些实施例中，如图1和图2所示，驱动区102可包括像素区1021和边缘区1022，其中，像素区1021至少部分围绕于透光区101外，透光区101的一侧边可与像素区1021的一侧边至少部分重合。边缘区1022可围绕于像素区1021以外，边缘区1022内可设有用于向像素电路10输入驱动信号的***电路，该***电路可包括栅极驱动电路、发光控制电路、电源电路等，在此不做特殊限定。
当然，在本公开的另一些实施方式中，像素区1021也可完全包围透光区101，边缘区1022可围绕于像素区1021外。
进一步的，第一像素电路110可全部分布于像素区1021内，所有第二像素电路120也分布于像素区1021内。当然，也可将一部分第二像素电路120设置在像素区1021内，所有第一像素电路110也分布于像素区1021内，并将其它第二像素电路120设置在边缘区1022内。同时，像素区1021中设有多个第一转接孔100，各第一转接孔100与各像素电路10一一对应的连接，以便输出驱动信号。
进一步的，像素电路10阵列分布，且各列第一像素电路110位于各列第二像素电路120之间，且相邻两列第二像素电路120之间至多设有一列第一像素电路110；相邻两列第一像素电路110之间可设有一列或多列第二像素电路120。
为了在不降低像素电路10数量的情况下，使驱动区102内具有足够的空间容纳第一像素电路110和第二像素电路120。可沿行方向对至少部分像素电路10进行压缩，减小像素电路10在行方向上的宽度，在驱动背板1的尺寸相同的前提下，使驱动区102内能够多出较多区域，并可在该较多区域处设置第一像素电路110。像素电路10的宽度是指沿行方向像素电路10在驱动背板1上的正投影的长度。
下面对像素电路10的结构进行示例性说明：
在本公开的一些实施例中，如图3和图4所示，像素电路10(第一像素电路110和第二像素电路120)可以为7T1C结构，即包括7个晶体管和1个电容。该7T1C像素电路包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。该像素电路可以与栅极信号端Gate，数据信号端Data，复位信号端RST1和RST2，发光控制信号端EM，电源端VDD，初始电源端Vinit1和Vinit2，以及发光器件连接，该发光器件还可以与电源端VSS连接。该像素电路10可以用于响应于所连接的各信号端提供的信号，驱动所连接的发光器件30发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和 教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开实施例的保护范围内的。
当然，在本公开的其它实施例中，像素电路10还可以采用其它结构，只要能驱动发光器件30发光既可，在此不对其结构做特殊限定。
基于上述像素电路10，以一个晶体管的结构为例，驱动背板1可包括依次层叠于衬底上的有源层、第一栅绝缘层、栅极、第二栅绝缘层、介电层、第一源漏层、第一平坦化层、第二源漏层和第二平坦化层，从而形成晶体管，在此不对晶体管的具体结构做特殊限定。第一转接孔100可设于第二平坦化层，使得引线21可与第二源漏层连接。
如图5所示，转接层2设于驱动背板1一侧，例如，转接层2设于第二平坦化层背离衬底的表面。转接层2可覆盖透光区101和驱动区102，且转接层2包括多层相互间隔的引线层21，每个引线层21均包括多个相互间隔的引线211，每个引线211在驱动背板1上的正投影均由透光区101延伸至驱动区102，并通过一第一转接孔100与一第一像素电路110连接，也就是说，每个引线211只用于传输来自一个第一像素电路110的信号。
如图7所示，转接层2具有对应于透光区101的转接区210和对应于驱动区102的走线区220，转接区210的边界与透光区101的边界重合，走线区220的边界与驱动区102的边界重合。同时，转接区210可包括分隔于第一中轴线S1两侧的两转接分区2101。第一中轴线S1为转接区210沿列方向延伸的中轴线；各转接分区2101均具有多个第二转接孔201，各第二转接孔201与各引线211一一对应连接，使得任一第一发光器件301可通过一第二转接孔201和一引线211与对应的第一像素电路110连接。第二转接孔201可为转接层2内的过孔结构，但由于第二转接孔201所连接的引线211可能位于不同的引线层21，因此，不同的第二转接孔201的深度可以不同。
每个引线层21的引线211的材料均可以是氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料。
在本公开的一些实施例中，如图5所示，引线层21的数量可以为三层，包括从驱动背板1向发光层3依次分布的第一引线层21a、第二引线层21b和第三引线层21c。其中，第一引线层21a的引线211包括第一引线211a，第二引线层21b的引线211包括第二引线211b，第三引线层21c的引线211包括第三引线211c。
需要说明的是，图5仅为了说明显示面板的各膜层的关系而示意性示出，并不限定为引线层21的具体结构。
如图5所示，为了使各引线层21之间绝缘，转接层2还包括第一平坦层22、 第二平坦层23和第三平坦层24，其中：
可将第一引线层21a设于驱动背板1靠近发光层3的表面。第一平坦层22覆盖第一引线层21a和驱动背板1靠近发光层3的表面。
第二引线层21b设于第一平坦层22背离驱动背板1的表面。第二平坦层23覆盖第二引线层21b和第一平坦层22靠近发光层3的表面。
第三引线层21c设于第二平坦层23背离驱动背板1的表面。第三平坦层24覆盖第三引线层21c和第二平坦层23靠近发光层3的表面；发光层3设于第三平坦层24背离驱动背板1的表面。
如图5所示，发光层3设于转接层2背离驱动背板1的一侧，例如，发光层3设于第三平坦层24背离驱动背板1的表面。
发光层3在驱动背板1上的覆盖转接区210和走线区220，且发光层3可包括多个发光器件30，发光器件30包括位于转接区210内的第一发光器件301以及位于走线区220内的第二发光器件302。任一第一发光器件301可通过一第二转接孔201、一引线211和第一转接孔201与一第一像素电路110连接，任一第二发光器件32可通过一第一转接孔210与一第二像素电路120连接。
在本公开的一些实施方式中，各发光器件30可为OLED，其可包括第一电极311、发光功能层312和第二电极313，其中：
第一电极311可设于转接层2背离驱动背板1的表面，例如，第一电极311设于第三平坦层24背离驱动背板1的表面。如图5和图6所示，第一电极311作为OLED发光器件的阳极，具有电极部3111和位于电极部3111边缘以外的接线部3112，接线部3112与电极部3111连接或采用一体结构。每个第一电极311的电极部3111通过接线部3112和一第二转接孔201与一引线211连接，从而将第一像素电路110与对应的发光器件30的第一电极311连接起来。相互连接的接线部3112和第二转接孔201在驱动背板1上的正投影至少部分重合。
发光功能层312可设于第一电极311背离驱动背板1的表面，其可包括依次层叠于第一电极311上的空穴传输层、有机发光层和电子传输层。
第二电极313作为OLED发光器件的阴极，可设于发光功能层312背离驱动背板1的表面。通过向第一电极311和第二电极313施加电信号可驱动发光功能层312发光。
以上为一个发光器件30的结构，在整个显示面板中，各个发光器件30的第一电极311可采用相同的材料，通过一次构图工艺同时形成，不同发光颜色的发光器件3的发光功能层312的材料不同。同时，各个发光器件30可共用同一第二电极313，也就是说，第二电极313可同时覆盖各个发光功能层312。此外，为了便于限定各个发光器件30的发光范围，发光层3还可包括像素定义层314，其可设于转接层2背离驱动背板1的表面，且具有露出各个第一电极311的开口，发光功能层312 可在各个开口内覆盖第一电极311，且露出电极部3111，接线部3112位于开口以外，第二电极313可覆盖像素定义层背离驱动背板1的表面，且凹陷至开口内。
进一步的，为了使发光层3对应于透光区101的区域与对应于驱动区102的区域的亮度一致。可使第一发光器件301在对应于透光区101的区域的密度与第二发光器件302在对应于驱动区102的区域的密度相同。
下面对通过引线211连接发光器件和像素电路的方式进行详细说明：
如图7-图12所示，以转接区210沿列方向的中轴线为第一中轴线S1，可将透光区101划分为沿行方向分布的两个转接分区2101。第一发光器件301分布于两个转接分区2101内。
两个转接分区2101关于第一中轴线S1对称，且两个转接分区2101中的第一发光器件301及其连接的引线211也关于第一中轴线S1对称设置。
以一个转接分区2101为例：第一转接孔100和第二转接孔201排列成沿列方向分布的多个孔行001，每个孔行001包括多个第一转接孔100，且各第二转接孔201位于部分孔行001中。同一引线211连接的第一转接孔100和第二连接孔201位于同一孔行001，并组成一孔组002。在相邻两孔组002中，一孔组002的第一转接孔100和第二转接孔201位于另一孔组002的第一转接孔100和第二转接孔201之间。
在任一孔组002中，引线211在行方向上的长度与第一像素电路110和第一发光器件301间的距离相同或相差指定长度，以便通过外部补偿的方式进行补偿，改善色偏。
在本公开的一些实施方式中，孔行001有N个，各第二转接孔201位于第i至j个孔行中的每一个。其中，N、i和j均为正整数，且1≤i＜j≤N。
在第i至j个孔行001中的任意相邻两个中，一孔行001的至少部分第二转接孔201所连接的引线211位于该相邻两个孔行001之间。
举例而言，第k个孔行001中的第二转接孔201所连接的引线21，位于第k-1和k个孔行001之间；k为正整数，且i＜k≤j；
第i个孔行的第二转接孔201所连接的引线211位于第i个孔行001背离第j个孔行001的一侧。
进一步的，由于相邻两孔行001之间的空间能容纳的引线211的数量有限，因此，在第i至j个孔行001的至少一个中，至少部分第二转接孔201所连接的引线211的部分区域，位于第i个孔行001背离第j个孔行001的一侧。
进一步的，走线区220包括主体区和***区，主体区至少部分围绕于转接区210外，***区围绕于主体区和转接区210外；至少部分第一像素电路110分布于驱动背板1对应于主体区的区域内。
在第i个孔行001中，至少部分第二转接孔201所连接的引线211的至少部分 区域位于***区。
在第i至j个孔行001的至少一个中，至少部分第二转接孔201所连接的引线211的至少部分区域，位于第j个孔行001背离第i个孔行001的一侧。
在本公开的一些实施方式中，转接分区2101可包括沿行方向分布的多个子分区21011，各子分区21011均设有第二转接孔201。同一子分区21011内的第一发光器件301所连接的引线211位于同一引线层21。
举例而言，同一转接分区2101的子分区21011包括沿行方向朝第一中轴线S1依次分布的第一子分区21011a、第二子分区21011b和第三子分区21011c，第一子分区21011a内的各第二转接孔201所连接的引线211为第一引线211a，第二子分区21011b内的各第二转接孔201所连接的引线211为第二引线211b，第三子分区21011c内的各第二转接孔201所连接的引线211为第三引线211c。
进一步的，若i＜k≤j，连接第k个孔行001的第二转接孔201的第一引线211a、第二引线211b和第三引线211c，位于第k-1和k个孔行001之间。同时，第i个孔行001中的第二转接孔201所连接的第一引线211a、第二引线211b和第三引线211c位于第i个孔行001背离第j个孔行001的一侧。
进一步的，在本公开的一些实施方式中，第一引线层21a的引线211还包括第四引线211d。同一转接分区2101的子分区21011包括位于第三子分区21011c和第一中轴线S1之间的第四子分区21011d；第四子分区21011d内的各第二转接孔201所连接的引线211为第四引线211d。
至少部分第四引线211d的至少部分区域位于第i个孔行001背离第j个孔行001的一侧。至少部分第四引线211d的至少部分区域位于第j个孔行001背离第i个孔行001的一侧。
更进一步，如图7和图8所示，第四子分区21011d包括分隔于第二中轴线S2两侧的第一亚分区21011d1和第二亚分区21011d2，第二中轴线S2为转接区210沿行方向延伸的中轴线。第i至k个孔行001的部分第二转接孔201位于第一亚分区21011d1，第k+1至j个孔行001的部分第二转接孔201位于第二亚分区21011d2；k+1≤j。
第一亚分区21011d1的第二转接孔201所连接的第四引线211d的至少部分区域位于第i个孔行001背离第j个孔行001的一侧。
所述第二亚分区21011d2的第二转接孔201所连接的第四引线211d的至少部分区域位于第j个孔行001背离第i个孔行001的一侧。
在本公开的一些实施方式中，如图11和图12所示，引线211可包括两个引出段2110以及连接两引出段2110的延伸段2120，引出段2110沿所述列方向延伸，延伸段2120沿行方向延伸。第一引线211a、第二引线211b和第三引线211c中的任一个的延伸段2120的长度与其连接的第一转接孔100和第二转接孔201的间距相同， 第一引线211a、第二引线211b和第三引线211c中的任一个的引出段2110沿列方向的长度小于相邻两孔行001的间距。第一转接孔100和第二转接孔201的间距为：第一转接孔100的中心与第二转接孔201在驱动背板1上的正投影的中心之间的距离。
在本公开的一些实施方式中，如图12所示，若i＜k＜j，连接第k个孔行001的第四引线211d的引出段2110，可包括沿列方向分布的第一段21101、第二段21102和第三段21103，第一段21101的一端与一第二转接孔201连接，另一端与第二段21102的一端连接，第二段21102的另一端与第三段21103的一端连接，第三段21103的另一端与延伸段2120的一端连接；
第一段21101和第三段21103沿列方向直线延伸，且第三段21103位于第一段21101所连接的第二转接孔201背离或靠近第一中轴线S1的一侧；一列第二转接孔201位于第一段21101的延伸路径的延伸线上。第二段21102沿直线延伸，且与第一段21101和第三段21103呈一指定夹角，以使第三段21103于第一段21101平行设置。
连接第k个孔行001的第四引线211d的延伸段2120的长度，与其连接的第一转接孔100和第二转接孔201的间距相差指定长度，该指定长度为第一段21101和第三段21103在行方向上的间距。
连接第i和j个孔行001的第四引线211d的延伸段2120的长度，与其连接的第一转接孔100和第二转接孔201的间距相同。
本公开实施方式还提供一种显示装置，其可包括上述任意实施方式的显示面板，该显示面板的结构以及有益效果可参考上文中显示面板的实施方式，在此不再赘述。
本公开实施方式还提供一种终端设备，如图13所示，该终端设备可包括显示装置1000和摄像装置2000，其中：
该显示装置1000可为上述任意实施方式的显示装置，其结构可有益效果可参考上文中显示面板和显示装置的实施方式，在此不再赘述。
摄像装置2000可设于显示装置1000的背光侧，即发光朝向的背侧，例如，显示装置1000的发光器件为顶发射结构，即向背离驱动背板1的方向发光，则摄像装置2000可设于驱动背板1背离发光层3的一侧，且摄像装置2000可与透光区101正对，用于透过透光区101拍摄图像。若显示装置1000的发光器件为底发射结构，则摄像装置2000可设于发光层3背离驱动背板1的一侧。摄像装置2000可以包括镜头和光电传感器等，在此不对摄像装置2000的具体结构做特殊限定，只要能拍摄图像既可。
本公开的终端设备可以是手机、平板电脑、电视等具有显示和拍摄功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种显示面板，其中，包括：
    驱动背板，具有透光区和至少部分围绕于所述透光区外的驱动区，所述驱动区具有多个像素电路，所述像素电路包括第一像素电路和第二像素电路；所述驱动背板具有多个第一转接孔，任一所述像素电路与一所述第一转接孔连接；
    转接层，设于所述驱动背板一侧且覆盖所述透光区和所述驱动区；所述转接层包括多层相互间隔的引线层，每个所述引线层包括多个相互间隔的引线；所述转接层具有对应于所述透光区的转接区和对应于所述驱动区的走线区，所述转接区包括分隔于第一中轴线两侧的两转接分区；所述第一中轴线为所述转接区沿列方向延伸的中轴线；各所述转接分区具有多个第二转接孔，任一所述第二转接孔通过一所述引线与一所述第一转接孔连接；
    发光层，设于所述转接层背离所述驱动背板的一侧，且包括多个发光器件，所述发光器件包括位于各所述转接分区的多个第一发光器件和位于所述走线区的多个第二发光器件；任一所述第一发光器件与一所述第二转接孔连接，任一所述第二发光器件与一所述第一转接孔连接；
    所述第一转接孔和所述第二转接孔排列成沿列方向分布的多个孔行，各所述第二转接孔位于部分所述孔行中；同一所述引线连接的第一转接孔和第二连接孔位于同一所述孔行，并组成一孔组；在相邻两所述孔组中，一所述孔组的第一转接孔和第二转接孔位于另一所述孔组的第一转接孔和第二转接孔之间；
    任一所述引线在所述行方向上的长度与其连接的第一转接孔和第二转接孔的间距相同或相差指定长度。
  2. 根据权利要求1所述的显示面板，其中，所述孔行有N个，各所述第二转接孔位于第i至j个所述孔行中的每一个；N、i和j均为正整数，且1≤i＜j≤N；
    在第i至j个所述孔行中的任意相邻两个中，一所述孔行的至少部分第二转接孔所连接的引线位于该相邻两个所述孔行之间。
  3. 根据权利要求2所述的显示面板，其中，第k个所述孔行中的第二转接孔所连接的引线，位于第k-1和k个所述孔行之间；k为正整数，且i＜k≤j；
    第i个所述孔行的第二转接孔所连接的引线位于第i个所述孔行背离第j个所述孔行的一侧。
  4. 根据权利要求2所述的显示面板，其中，在第i至j个所述孔行的至少一个中，至少部分所述第二转接孔所连接的引线的部分区域，位于第i个所述孔行背离第j个所述孔行的一侧。
  5. 根据权利要求4所述的显示面板，其中，所述走线区包括主体区和***区，所述主体区至少部分围绕于所述转接区外，所述***区围绕于所述主体区和所述转接区外；至少部分所述第一像素电路分布于所述驱动背板对应于所述主体区的区域 内；
    在第i个所述孔行中，至少部分所述第二转接孔所连接的引线的至少部分区域位于所述***区。
  6. 根据权利要求2所述的显示面板，其中，在第i至j个所述孔行的至少一个中，至少部分所述第二转接孔所连接的引线的至少部分区域，位于第j个所述孔行背离第i个所述孔行的一侧。
  7. 根据权利要求1-6任一项所述的显示面板，其中，所述转接分区包括沿所述行方向分布的多个子分区，各所述子分区均设有所述第二转接孔；
    同一所述子分区内的第二转接孔所连接的引线位于同一所述引线层。
  8. 根据权利要求7所述的显示面板，其中，多层所述引线层中至少包括从所述驱动背板向所述发光层依次分布的第一引线层、第二引线层和第三引线层；所述第一引线层的引线包括第一引线，所述第二引线层的引线包括第二引线，所述第三引线层的引线包括第三引线；
    同一所述转接分区的子分区包括沿行方向朝所述第一中轴线依次分布的第一子分区、第二分区和第三子分区，所述第一子分区内的各第二转接孔所连接的引线为所述第一引线，所述第二子分区内的各第二转接孔所连接的引线为所述第二引线，所述第三子分区内的各第二转接孔所连接的引线为所述第三引线。
  9. 根据权利要求8所述的显示面板，其中，若i＜k≤j；
    连接第k个所述孔行的第二转接孔的第一引线、第二引线和第三引线，位于第k-1和k个所述孔行之间；
    第i个所述孔行中的第二转接孔所连接的第一引线、第二引线和第三引线位于第i个所述孔行背离第j个所述孔行的一侧。
  10. 根据权利要求8或9所述的显示面板，其中，所述第一引线层的引线还包括第四引线；
    同一所述转接分区的子分区包括位于所述第三子分区和所述第一中轴线之间的第四子分区；所述第四子分区内的各第二转接孔所连接的引线为所述第四引线；
    至少部分所述第四引线的至少部分区域位于第i个所述孔行背离第j个所述孔行的一侧；
    至少部分所述第四引线的至少部分区域位于第j个所述孔行背离第i个所述孔行的一侧。
  11. 根据权利要求10所述的显示面板，其中，所述第四子分区包括分隔于第二中轴线两侧的第一亚分区和第二亚分区，所述第二中轴线为所述转接区沿行方向延伸的中轴线；第i至k个所述孔行的部分第二转接孔位于所述第一亚分区，第k+1至j个所述孔行的部分第二转接孔位于所述第二亚分区；k+1≤j；
    所述第一亚分区的第二转接孔所连接的第四引线的至少部分区域位于第i个所 述孔行背离第j个所述孔行的一侧；
    所述第二亚分区的所述第二转接孔所连接的第四引线的至少部分区域位于第j个所述孔行背离第i个所述孔行的一侧。
  12. 根据权利要求11所述的显示面板，其中，所述引线包括两个所述引出段以及连接两所述引出段的延伸段；所述引出段沿所述列方向延伸，所述延伸段沿所述行方向延伸；
    所述第一引线、所述第二引线和所述第三引线中的任一个的延伸段的长度与其连接的第一转接孔和第二转接孔的间距相同。
  13. 根据权利要求12所述的显示面板，其中，若i＜k＜j；
    连接第k个所述孔行的第四引线的引出段，包括沿所述列方向分布的第一段、第二段和第三段，所述第一段的一端与一所述第二转接孔连接，另一端与所述第二段的一端连接，所述第二段的另一端与所述第三段的一端连接，所述第三段的另一端与所述延伸段的一端连接；
    所述第一段和所述第三段沿所述列方向直线延伸，且所述第三段位于所述第一段所连接的第二转接孔背离或靠近所述第一中轴线的一侧；
    连接第k个所述孔行的第四引线的延伸段的长度，与其连接的所述第一转接孔和第二转接孔的间距相差指定长度。
  14. 根据权利要求12所述的显示面板，其中，连接第i和j个所述孔行的第四引线的延伸段的长度，与其连接的第一转接孔和第二转接孔的间距相同。
  15. 根据权利要求11所述的显示面板，其中，连接所述第一亚分区中的第二转接孔的第四引线与连接所述第二亚分区的第二转接孔的第四引线关于所述第二中轴线对称设置。
  16. 根据权利要求1所述的显示面板，其中，连接两所述转接分区的第二转接孔的引线关于所述第一中轴线对称设置。
  17. 根据权利要求1-6任一项所述的显示面板，其中，所述发光器件包括：
    第一电极，设于所述转接层背离所述驱动背板的表面；所述第一电极具有电极部和位于所述电极部边缘以外的接线部；所述接线部通过一所述第二转接孔与一所述引线连接；
    发光功能层，设于所述第一电极背离所述驱动背板的表面；
    第二电极，设于所述发光功能层背离所述驱动背板的表面。
  18. 一种显示装置，其中，包括权利要求1-17任一项所述的显示面板。
  19. 一种终端设备，其中，包括：
    权利要求18所述的显示装置；
    摄像装置，设于所述驱动背板背离所述发光层的背光侧，且与所述透光区正对设置，用于透过所述透光区拍摄图像。
PCT/CN2021/093562 2021-05-13 2021-05-13 显示面板、显示装置及终端设备 WO2022236765A1 (zh)

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CN112271203A (zh) * 2020-10-29 2021-01-26 京东方科技集团股份有限公司 显示面板及显示装置
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