WO2022067965A1 - 终端设备、显示装置、显示面板及其制造方法 - Google Patents

终端设备、显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2022067965A1
WO2022067965A1 PCT/CN2020/127186 CN2020127186W WO2022067965A1 WO 2022067965 A1 WO2022067965 A1 WO 2022067965A1 CN 2020127186 W CN2020127186 W CN 2020127186W WO 2022067965 A1 WO2022067965 A1 WO 2022067965A1
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Prior art keywords
lead
light
area
layer
sub
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PCT/CN2020/127186
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English (en)
French (fr)
Inventor
杜丽丽
龙跃
黄炜赟
王本莲
王琦伟
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/427,151 priority Critical patent/US20220376000A1/en
Priority to CN202080002653.7A priority patent/CN114730799A/zh
Publication of WO2022067965A1 publication Critical patent/WO2022067965A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
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    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a terminal device, a display device, a display panel, and a method for manufacturing the display panel.
  • the area of the screen corresponding to the camera usually needs to have a hole, so that no light can be emitted, which is not conducive to improving the screen ratio.
  • the brightness of the area on the screen corresponding to the camera is low, which affects the display effect of the entire screen.
  • the purpose of the present disclosure is to provide a terminal device, a display device, a display panel and a manufacturing method of the display panel.
  • a display panel comprising:
  • a driving backplane which has a light-transmitting area and a driving area at least partially surrounding the light-transmitting area, the driving area has a plurality of pixel circuits, and at least includes a first pixel circuit and a second pixel circuit;
  • the transfer layer is arranged on one side of the driving backplane, and includes multiple layers of mutually insulated lead layers, each of the lead layers includes a plurality of mutually insulated leads; each lead extends from the light-transmitting area to the driving region and connected to a first pixel circuit;
  • the light-emitting layer which is arranged on the side of the transition layer away from the driving backplane, and includes a plurality of light-emitting devices;
  • the light-emitting device includes a plurality of first light-emitting devices located in the light-transmitting area and a plurality of first light-emitting devices located in the driving backplane a plurality of second light emitting devices in the region;
  • the first light emitting device is connected to the first pixel circuit through the leads in each of the lead layers in a one-to-one correspondence; the second pixel circuit is connected to the second light-emitting device in a one-to-one correspondence.
  • the light emitting device includes:
  • first electrode arranged on the surface of the transfer layer away from the driving backplane; the first electrode has an electrode part and a wiring part located outside the edge of the electrode part; each of the first electrodes passes through the The wiring part and a transfer hole located in the transfer layer are connected with a lead;
  • a light-emitting functional layer disposed on the surface of the first electrode away from the driving backplane
  • the second electrode is disposed on the surface of the light-emitting functional layer facing away from the driving backplane.
  • the multiple layers of the lead layers at least include a first lead layer, a second lead layer and a third lead layer that are sequentially distributed from the driving backplane to the light emitting layer;
  • the leads of the first lead layer include first leads, the leads of the second lead layer include second leads, and the leads of the third lead layer include third leads;
  • the area of the transition layer corresponding to the light-transmitting area includes a plurality of routing areas distributed in an array, each of the routing areas includes a target routing area, and the target routing area is located at the center of the first central axis.
  • the target routing area includes a first sub-area, a second sub-area and a third sub-area that are sequentially distributed along the row direction toward the first central axis; the first central axis is the light transmission the central axis of the area along the column direction;
  • the transfer hole in the first sub-region is the first transfer hole
  • the transfer hole in the second sub-region is the second transfer hole
  • the transfer hole in the third sub-region is the third transfer hole transfer hole
  • the wiring portion corresponding to the first sub-region is connected to the corresponding first pixel circuit through the first transfer hole and the first lead; the wiring portion corresponding to the second sub-region passes through the The second transfer hole and the second lead are connected to the corresponding first pixel circuit; the wiring portion corresponding to the third sub-region is connected to the corresponding through the third transfer hole and the third lead The first pixel circuit is connected.
  • the first via holes are distributed in N rows and M columns, and any two adjacent rows of the first via holes are arranged between N rows and M columns. There are at most M first leads distributed among them; N and M are both positive integers.
  • the second via holes are distributed in N rows and M columns, and any two adjacent rows of the second via holes are arranged between N rows and M columns. There are at most M second leads distributed among them.
  • the third via holes are distributed in N rows and M columns, and any two adjacent rows of the third via holes are arranged between N rows and M columns. At most M third leads are distributed among them.
  • the target routing area further includes a fourth sub-area, and the fourth sub-area is located on a side of the third sub-area away from the first sub-area, so The transfer hole in the fourth sub-region is a fourth transfer hole;
  • the lead of the first lead layer further includes a fourth lead that is insulated from the first lead; and at least part of the wiring portion corresponding to the fourth sub-region passes through the fourth transfer hole and the The fourth lead is connected to the corresponding first pixel circuit.
  • the leads of the second lead layer further include fifth leads insulated from the second leads and corresponding to at least part of the wires in the fourth sub-region The part is connected to the corresponding first pixel circuit through the fourth connection hole and the fifth lead.
  • the lead of the third lead layer further includes a sixth lead that is insulated from the third lead and corresponds to at least part of the wire in the fourth sub-region The part is connected to the corresponding first pixel circuit through the fourth connection hole and the sixth lead.
  • the fourth subregion includes a first subregion and a second subregion, and the first subregion and the second subregion are symmetrical about the second central axis , and the leads located in the first sub-sub-region and the leads located in the second sub-sub-region are symmetrical about the second central axis; the second central axis is the edge of the target routing area The central axis of the row direction.
  • the first lead, the second lead, and the third lead include:
  • the lead-out section extends along the column direction and is connected with the transfer hole
  • the extension section extends along the row direction, one end is connected to the lead-out section, and the other end extends to the area of the transition layer corresponding to the driving area.
  • the fourth lead, the fifth lead, and at least part of the sixth lead include:
  • the lead-out section extends along the column direction and is connected with the transfer hole
  • the extension section includes a first extension section and a second extension section.
  • the first extension section extends along the row direction, one end is connected to the lead-out section, and the other end is located in the target routing area;
  • the second extension section It extends along the column direction, one end is connected to the first extension section, and the other end extends to the area of the transfer layer corresponding to the driving area.
  • the second extension of the fourth lead is located in the second sub-region; the second extension of the fifth lead is located in the third sub-region; the The second extension of the sixth lead is located in the fourth sub-region.
  • the fourth transfer holes are distributed into i rows and j columns, and any two adjacent columns of the fourth transfer holes are arranged between There are at most j-1 of the second extension segments distributed between them; i and j are both positive integers.
  • the leads on both sides of the first central axis are symmetrical about the first central axis
  • the leads on both sides of the third central axis are symmetrical with respect to the third central axis, and the third central axis is the central axis of the light-transmitting area along the row direction.
  • the first lead layer is disposed on a surface of the driving backplane close to the light-emitting layer
  • the transfer layer also includes:
  • the second lead layer is disposed on the surface of the first flat layer away from the driving backplane;
  • the third lead layer is provided on the surface of the second flat layer away from the driving backplane;
  • a third flat layer covers the surface of the third lead layer and the second flat layer close to the light-emitting layer; the light-emitting layer is disposed on the surface of the third flat layer away from the driving backplane.
  • the density of the first light emitting device in the light-transmitting region is the same as the density of the second light emitting device in the driving region.
  • the driving region includes:
  • a pixel area at least partially surrounding the light-transmitting area, and one side of the light-transmitting area coincides with one side of the pixel area;
  • At least a part of the first pixel circuits are distributed in the pixel area, and at most a part of the first pixel circuits are distributed in the frame area.
  • a method for manufacturing a display panel including:
  • a driving backplane is formed, the driving backplane has a light-transmitting area and a driving area at least partially surrounding the light-transmitting area, the driving area has a plurality of pixel circuits, and at least includes a first pixel circuit and a second pixel circuit ;
  • a transfer layer is formed on one side of the drive backplane, the transfer layer includes multiple layers of mutually insulated lead layers, each of the lead layers includes a plurality of mutually insulated leads; each lead is formed by the transparent The light area extends to the driving area and is connected with a first pixel circuit;
  • a light-emitting layer is formed on the surface of the transition layer away from the driving backplane, the light-emitting layer includes a plurality of light-emitting devices; the light-emitting device includes a plurality of first light-emitting devices located in the light-transmitting area and a plurality of first light-emitting devices located in the a plurality of second light-emitting devices in the driving area; the first light-emitting devices are connected to the first pixel circuits through the leads in the lead layers in a one-to-one correspondence; the second pixel circuits are in a one-to-one correspondence connected with the second light emitting device.
  • a display device including the display panel described in any one of the above.
  • a terminal device comprising:
  • the camera device is disposed on the backlight side of the display panel, and is disposed opposite to the light-transmitting area, and is used for capturing images through the light-transmitting area.
  • FIG. 1 is a schematic diagram of a driving backplane in an embodiment of the disclosed display panel.
  • FIG. 2 is a schematic diagram of the connection between a pixel circuit and a light-emitting device in an embodiment of the display panel of the present disclosure.
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit in an embodiment of the disclosed display panel.
  • FIG. 4 is a schematic structural diagram of a pixel circuit in an embodiment of the disclosed display panel.
  • FIG. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosed display panel.
  • FIG. 6 is a top view of the first electrode in an embodiment of the disclosed display panel.
  • FIG. 7 is a schematic diagram of each wiring area of an interposer layer in an embodiment of a display panel of the present disclosure.
  • FIG. 8 is a schematic diagram of a first sub-region in an embodiment of a display panel of the present disclosure.
  • FIG. 9 is a schematic diagram of a second sub-region in an embodiment of the display panel of the present disclosure.
  • FIG. 10 is a schematic diagram of a third sub-region in an embodiment of the disclosed display panel.
  • FIG. 11 is a schematic diagram of the leads of the fourth sub-region in an embodiment of the display panel of the present disclosure.
  • FIG. 12 is a schematic diagram of the wiring of the fourth sub-region in another embodiment of the display panel of the present disclosure.
  • FIG. 13 is a schematic diagram of the wiring of the fourth sub-region in still another embodiment of the display panel of the present disclosure.
  • FIG. 14 is a schematic diagram of a lead wire in an embodiment of the disclosed display panel.
  • FIG. 15 is a schematic diagram of another lead wire in an embodiment of the disclosed display panel.
  • FIG. 16 is a flowchart of an embodiment of the disclosed manufacturing method.
  • FIG. 17 is a schematic diagram of an embodiment of the disclosed display device.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the row direction and the column direction are only two vertical directions, and their specific orientations are not limited.
  • the row direction can be the horizontal X direction in FIG. 8-FIG. 13, and the column direction can be the vertical Y direction in FIG. 8-FIG. 13. direction.
  • the actual orientation of the row direction and the column direction may change.
  • the display panel may be an OLED (Organic Light-Emitting Diode, organic light emitting diode) display panel, as shown in FIG. 1 , FIG. 2 and FIG. 5 , the display panel includes a driving backplane 1.
  • OLED Organic Light-Emitting Diode, organic light emitting diode
  • the driving backplane 1 has a light-transmitting area 101 and a driving area 102 at least partially surrounding the light-transmitting area 101 .
  • the transfer layer 2 is arranged on one side of the driving backplane 1 and includes multiple layers of mutually insulated lead layers 21 , each lead layer 21 includes a plurality of mutually insulated leads 211 ; each lead 211 extends from the light-transmitting area 101 to the driving region 102 and connected to a first pixel circuit 110 .
  • the light-emitting layer 3 is disposed on the side of the transition layer 2 away from the driving backplane 1, and includes a plurality of light-emitting devices 30; the light-emitting device 30 includes a plurality of first light-emitting devices 301 corresponding to the light-transmitting area 101 and corresponding the plurality of second light emitting devices 302 .
  • the first light emitting device 301 is connected to the first pixel circuit 110 through the leads 211 in each lead layer 21 in a one-to-one correspondence; the second pixel circuit 120 is connected to the second light-emitting device 302 in a one-to-one correspondence.
  • the first pixel circuit 110 for driving the first light-emitting device 301 in the light-transmitting region 101 is disposed in the driving region 102 outside the light-transmitting region 101 , without reducing the number of light-emitting devices 30 .
  • the degree of light transmission of the light transmission area 101 can be improved, which is convenient for the camera device to capture images.
  • the first light-emitting device 301 in the light-transmitting area 101 is connected to the first pixel circuit 110 through the leads 211 of the multilayer lead layers 21 , so that the light-transmitting area 101 can display images normally, and the plurality of lead layers 21 can increase the number of leads
  • each of the first light-emitting devices 301 can still be connected to the first pixel circuit 110 to avoid the reduction of the layout space of 211 due to the inability to provide enough leads 211.
  • the number of the first light emitting devices 301 is connected to the second pixel circuit 120 and can display images outside the light-transmitting area 101 .
  • the driving backplane 1 is provided with a pixel circuit 10 for driving the light-emitting device 30 to emit light, and the driving backplane 1 at least includes a light-transmitting area 101 and a driving area 102, wherein the pixel circuit 10 is located in the driving area 102,
  • the pixel circuit 10 is not provided in the light-transmitting area 101 to improve the transparency, and the camera device can capture images through the light-transmitting area 101, thereby realizing under-screen photography.
  • the pixel circuit 10 in the driving area 102 includes at least a first pixel circuit 110 and a second pixel circuit 120, wherein the first pixel circuit 110 is used to drive the light-emitting device corresponding to the light-transmitting area 101, that is, the first pixel circuit 110.
  • a light-emitting device 301 ; the second pixel circuit 120 is used to drive the light-emitting device corresponding to the driving region 102 , that is, the second light-emitting device 302 .
  • the driving area 102 may include a pixel area 1021 and a frame area 1022 , wherein the pixel area 1021 at least partially surrounds the light-transmitting area 101 , and the light-transmitting area 101 One side of the pixel region 1021 may at least partially overlap with one side of the pixel region 1021 .
  • the frame area 1022 may surround the pixel area 1021.
  • the frame area 1022 may be provided with a peripheral circuit for inputting driving signals to the pixel circuit 10.
  • the peripheral circuit may include a gate driving circuit, a light-emitting control circuit, etc., which are not specially described here. limited.
  • the pixel region 1021 can also completely surround the light-transmitting region 101 .
  • all the first pixel circuits 110 may be distributed in the pixel area 1021 , and all the second pixel circuits 120 may also be distributed in the pixel area 1021 .
  • a part of the first pixel circuits 110 can also be arranged in the pixel area 1021
  • all the second pixel circuits 120 are also distributed in the pixel area 1021
  • other first pixel circuits 110 are arranged in the frame area 1022 .
  • all the first pixel circuits 110 may also be arranged in the frame area 1022 .
  • first pixel circuits 110 and the second pixel circuits 120 in the pixel area 1021 are distributed in an array, and the first pixel circuits 110 in each column are located between the second pixel circuits 120 in each column, and the second pixel circuits 120 in two adjacent columns are arranged in an array.
  • a row of first pixel circuits 110 is disposed therebetween; multiple rows of second pixel circuits 120 may be disposed between two adjacent rows of first pixel circuits 110 .
  • one or more columns of pixel circuits 10 closest to the light-transmitting area 101 in the row direction may not be connected to the first light-emitting device 301 and the second light-emitting device 302, and these pixel circuits 10 may be used as dummy pixel circuits (Fig. (not shown), in order to increase the distance between the second pixel circuit 120 connected to the first light-emitting device 301 and the closest to the light-transmitting area 101 and the light-transmitting area 101, and increase the minimum length of the corresponding lead 211, so as to avoid the length of the lead 211 If the difference is too large, the turn-on timings of the first light emitting devices 301 in different columns are too different, which improves the picture quality.
  • each pixel circuit 10 can be compressed along the row direction to reduce the width of the pixel circuit 10 in the row direction.
  • the second pixel circuit 120 is disposed at the more areas.
  • the width of the pixel circuit 10 refers to the length of the orthographic projection of the pixel circuit 10 on the driving backplane 1 in the row direction.
  • the structure of the pixel circuit 10 is exemplarily described below:
  • the pixel circuit 10 (the first pixel circuit 110 and the second pixel circuit 120 ) may be a 7T1C structure, that is, including 7 transistors and 1 capacitor.
  • the 7T1C pixel circuit includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7 and a storage capacitor C1.
  • the pixel circuit can be connected to the gate signal terminal Gate, the data signal terminal Data, the reset signal terminals RST1 and RST2, the light-emitting control signal terminal EM, the power supply terminal VDD, the initial power supply terminals Vinit1 and Vinit2, and the light-emitting device.
  • the light-emitting device can also be connected Connect to the power supply terminal VSS.
  • the pixel circuit 10 can be used to drive the connected light-emitting device 30 to emit light in response to the signals provided by the connected signal terminals.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the embodiments of the present disclosure are described by taking the transistors all adopting P-type transistors as an example. Based on the description and teachings of the present disclosure, those of ordinary skill in the art can easily think of using N-type transistors for at least part of the transistors in the pixel circuit structure of the embodiments of the present disclosure, that is, using N-type transistors without any creative work. Therefore, these implementations are also within the protection scope of the embodiments of the present disclosure.
  • the pixel circuit 10 may also adopt other structures, as long as the light emitting device 30 can be driven to emit light, and its structure is not limited herein.
  • the driving backplane 1 may include an active layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a dielectric layer, an active layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a dielectric layer,
  • the first source-drain layer, the first planarization layer, the second source-drain layer, and the second planarization layer form a transistor, and the specific structure of the transistor is not limited herein.
  • the transition layer 2 is provided on one side of the driving backplane 1 , for example, on the surface of the second planarization layer facing away from the substrate.
  • the transition layer 2 can cover the light-transmitting area 101 and the driving area 102, and the transition layer 2 includes multiple layers of mutually insulated lead layers 21, each lead layer 21 includes a plurality of mutually insulated leads 211, and each lead 211 is It extends from the light-transmitting area 101 to the driving area 102 and is connected to a first pixel circuit 110 , that is, each lead 211 is only used for transmitting a signal from one first pixel circuit 110 .
  • the transfer layer 2 is provided with transfer holes 201 which are connected with each lead 211 in a one-to-one correspondence.
  • the via holes 201 may be via holes in the via layer 2 , but since the leads 211 connected to the via holes 201 may be located in different lead layers 21 , the depths of the via holes 201 may be different.
  • the material of the leads 211 of each lead layer 21 may be transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO).
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the number of lead layers 21 may be three, including a first lead layer 21 a , a second lead layer 21 b and a first lead layer 21 a , a second lead layer 21 b and The third wiring layer 21c.
  • the leads 211 of the first lead layer 21a include first leads 211a
  • the leads 211 of the second lead layer 21b include second leads 211b
  • the leads 211 of the third lead layer 21c include third leads 211c.
  • FIG. 5 is only schematically shown for explaining the relationship of each film layer of the display panel, and is not limited to the specific structure of the lead layer 21 .
  • the transition layer 2 further includes a first flat layer 22, a second flat layer 23 and a third flat layer 24, wherein:
  • the first lead layer 21 a can be disposed on the surface of the driving backplane 1 close to the light emitting layer 3 .
  • the first flat layer 22 covers the first lead layer 21 a and the surface of the driving backplane 1 close to the light emitting layer 3 .
  • the second lead layer 21b is disposed on the surface of the first flat layer 22 facing away from the driving backplane 1 .
  • the second flat layer 23 covers the second lead layer 21 b and the surface of the first flat layer 22 close to the light emitting layer 3 .
  • the third lead layer 21c is disposed on the surface of the second flat layer 23 facing away from the driving backplane 1 .
  • the third flat layer 24 covers the surfaces of the third lead layer 21 c and the second flat layer 23 close to the light emitting layer 3 ;
  • the light-emitting layer 3 may include a plurality of light-emitting devices 30 , and each light-emitting device 30 may be connected to a first pixel circuit 110 through a lead 211 .
  • the light-emitting device 30 may be an OLED light-emitting device, which may include a first electrode 311, a light-emitting functional layer 312 and a second electrode 313, wherein:
  • the first electrode 311 can be disposed on the surface of the transition layer 2 away from the driving backplane 1 .
  • the first electrode 311 can be disposed on the surface of the third flat layer 24 facing away from the driving backplane 1 .
  • the first electrode 311 serves as the anode of the OLED light-emitting device, and has an electrode portion 3111 and a wiring portion 3112 located outside the edge of the electrode portion 3111 .
  • the electrode portion 3111 of each first electrode 311 is connected to a lead 211 through the wiring portion 3112 and a via hole 201 in the via layer 2 , so as to connect the first pixel circuit 110 to the corresponding first electrode of the light emitting device 30 311 to connect.
  • the light-emitting functional layer 312 may be disposed on the surface of the first electrode 311 away from the driving backplane 1 , and may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer and an electron layer sequentially stacked on the first electrode 311 . injection layer.
  • the second electrode 313 serves as the cathode of the OLED light-emitting device, and can be disposed on the surface of the light-emitting functional layer 312 away from the driving backplane 1 .
  • the light-emitting functional layer 312 can be driven to emit light by applying an electrical signal to the first electrode 311 and the second electrode 313 .
  • each light-emitting device 30 In the entire display panel, the first electrodes 311 of each light-emitting device 30 can be made of the same material and formed simultaneously through a patterning process, and each light-emitting functional layer 312 can also be made of the same material. A patterning process is formed at the same time. Meanwhile, each light emitting device 30 can share the same second electrode 313 , that is, the second electrode 313 can cover each light emitting functional layer 312 at the same time.
  • the light-emitting layer 3 may further include a pixel definition layer 314 , which may be disposed on the surface of the transition layer 2 away from the driving backplane 1 and has openings exposing the first electrodes 311 .
  • the light-emitting functional layer 312 can cover the first electrode 311 in each opening, and expose the electrode part 3111, and the wiring part 3112 is located outside the opening.
  • the density of the first light emitting device 301 in the region corresponding to the light-transmitting region 101 can be made the same as the density of the second light emitting device 302 in the region corresponding to the driving region 102 .
  • the area of the transition layer 2 corresponding to the light-transmitting area 101 may be partitioned to obtain a plurality of wiring areas 20 , the leads 211 in each wiring area 20 It is used to connect the light emitting device 30 corresponding to the wiring area 20 .
  • the area of the transition layer 2 corresponding to the transparent area 101 may include a plurality of routing areas 20 distributed in an array, that is, the orthographic projection of each routing area 20 on the driving backplane 1 is located within the transparent area 101 .
  • each routing area 20 includes a target routing area 20a, the target routing area 20a is located on one side of the first central axis S1, and the target routing area 20a includes a plurality of target routing areas sequentially distributed along the row direction toward the first central axis S1.
  • the sub-regions include a first sub-region 2011, a second sub-region 2012 and a third sub-region 2013, and the widths of the first sub-region 2011, the second sub-region 2012 and the third sub-region 2013 in the row direction may be equal.
  • the transfer holes 201 in the first sub-region 2011 are first transfer holes 201a, and each of the first transfer holes 201a can be connected to a first lead 211a, so the first transfer holes 201a pass through The first flat layer 22 , the second flat layer 23 and the third flat layer 24 .
  • the transfer holes 201 in the second sub-region 2012 are second transfer holes 201b, and each second transfer hole 201b can be connected to a second lead 211b, so the second transfer holes 201b pass through The second flat layer 23 and the third flat layer 24 .
  • FIG. 9 the transfer holes 201 in the second sub-region 2012 are second transfer holes 201b, and each second transfer hole 201b can be connected to a second lead 211b, so the second transfer holes 201b pass through The second flat layer 23 and the third flat layer 24 .
  • the transfer holes 201 in the third sub-region 2013 are third transfer holes 201c, and each second transfer hole 201c can be connected to a third lead 211c, so the third transfer hole 201c penetrates through The third flat layer 24 .
  • the first transfer hole 201 a , the second transfer hole 201 b and the third transfer hole 201 c can be respectively connected to the corresponding first light emitting device 301 , so as to realize the connection between the lead 211 and the first light emitting device 301 .
  • the wiring portion 3112 corresponding to the first sub-region 2011 can be connected to the corresponding first pixel circuit 110 through the first via hole 201 a and the first lead 211 a .
  • the wiring portion 3112 corresponding to the second sub-region 2012 may be connected to the corresponding first pixel circuit 110 through the second via hole 201b and the second lead 211b.
  • the wiring portion 3112 corresponding to the third sub-region 2013 may be connected to the corresponding first pixel circuit 110 through the third via hole 201c and the third lead 211c.
  • the first transfer holes 201a are distributed into N rows and M columns, and at most M first leads 211a are distributed between any two adjacent rows of the first transfer holes 201a .
  • the second via holes 201b are distributed in N rows and M columns, and at most M second leads 211b are distributed between any two adjacent rows of the second via holes 201b.
  • the third via holes 201c are distributed in N rows and M columns, and at most M third leads 211c are distributed between any two adjacent rows of the third via holes 201c.
  • N and M are both positive integers, and their specific values are not particularly limited here.
  • M can be 13, that is, at most 13 leads 211 can be distributed between two adjacent rows of transfer holes 201, and N can be 50. , 80, 100, etc.
  • the target routing area 20a may further include a fourth sub-area 2014, and the fourth sub-area 2014 is located on the side of the third sub-area 2013 away from the first sub-area 2011.
  • the transfer hole 201 in the sub-region 2014 is the fourth transfer hole 201d.
  • the lead 211 of the first lead layer 21a may further include a fourth lead 211d insulated from the first lead 211a; and at least part of the wiring portion 3112 corresponding to the fourth sub-region 2014 passes through the fourth transfer hole 201d and the fourth lead 211d Connect to the corresponding first pixel circuit 110 . That is to say, the first lead layer 21a can be used not only to connect the first light emitting devices 301 corresponding to the first sub-regions 2011 , but also to connect the first light-emitting devices 301 corresponding to the fourth sub-regions 2014 .
  • the lead 211 of the second lead layer 21b further includes a fifth lead 211e insulated from the second lead 211b, and at least part of the wiring portion 3112 corresponding to the fourth sub-region 2014 is connected to the fourth through hole 201d and the fifth lead 211e through the fourth transfer hole 201d and the fifth lead 211e.
  • the corresponding first pixel circuits 110 are connected. That is to say, the second lead layer 21b can be used not only to connect the light emitting devices corresponding to the second sub-region 2012 , but also to connect the light emitting devices corresponding to the fourth sub-region 2014 .
  • the lead 211 of the third lead layer 21c further includes a sixth lead 211f insulated from the third lead 211c, and at least part of the wiring portion 3112 corresponding to the fourth sub-region 2014 is connected to the fourth through hole 201d and the sixth lead 211f through the fourth transfer hole 201d and the sixth lead 211f.
  • the corresponding first pixel circuits 110 are connected. That is to say, the third lead layer 21c can be used to connect the light-emitting devices corresponding to the third sub-region 2013 and the light-emitting devices corresponding to the fourth sub-region 2014 .
  • the fourth sub-region 2014 may be divided into multiple sub-sub-regions.
  • the fourth sub-region 2014 may include a first sub-sub-region 2014a and a second sub-sub-region 2014b, the first sub-sub-region 2014a and the second sub-sub-region 2014b are symmetrical about the second central axis S2.
  • the second central axis S2 is the central axis of the target routing area 20a along the row direction, and the leads 211 corresponding to the first sub-sub-region 2014a and the leads 211 corresponding to the second sub-sub-region 2014b can be symmetrically arranged with respect to the second central axis S2 .
  • the fourth via hole 201 d of the first sub-sub-region 2014 a corresponds to the driving region 102 through the fourth lead 211 d , the fifth lead 211 e and the sixth lead 211 f respectively.
  • the first pixel circuit 110 is connected. All the sixth leads 211f can be divided into a first group and a second group. The first group of sixth leads 211f can be connected to a row of fourth transfer holes 201d in the first sub-sub-region 2014a that is closest to the edge of the display panel. The number of a group of sixth leads 211f is equal to the number of columns of the fourth via holes 201d of the first sub-sub-region 2014a.
  • the first group of sixth leads 211f can extend to the border region 1022 along the column direction. If the corresponding first pixel circuit 110 is located in the border region 1022, the first group of sixth leads 211f can be in the border region 1022 with its corresponding first pixel circuit 111f. The pixel circuit 110 is connected. Of course, if the first pixel circuit 110 is not disposed in the frame area 1022, the first group of sixth leads 211f can be connected to the first pixel circuit 110 in the pixel area 1021 through the frame area 1022 through other wirings.
  • the first to fifth leads 211 a to 211 e and the second group of sixth leads 211 f include a lead-out section 210 and an extension section 220 , wherein:
  • the lead-out section 210 may extend along the column direction and be connected to the transfer hole 201.
  • the lead-out section 210 of the first lead 211a may be connected to the first transfer hole 201a; the lead-out section 210 of the second lead 211b may be connected to the second lead
  • the contact hole 201b is connected; the lead-out section 210 of the third lead 211c can be connected with the third transfer hole 201c.
  • the lead-out sections 210 of the fourth lead 211d, the fifth lead 211e, and the sixth lead 211f may be connected to the fourth transfer hole 201d, but the lead-out sections 210 of the fourth lead 211d, the fifth lead 211e, and the sixth lead 211f are connected
  • the fourth transfer hole 201d is different.
  • extension section 220 is connected to the lead-out section 210 , and the other end extends to the area of the transition layer 2 corresponding to the driving region 102 so as to be connected to the first pixel circuit 110 .
  • the extension sections 220 of the first lead 211a, the second lead 211b and the third lead 211c may extend in the row direction.
  • the extending sections 220 of the fourth lead 211d, the fifth lead 211e and the second group of sixth leads 211f include at least two sections, namely the first extending section 2201 and the second extending section 2202, wherein:
  • the first extension section 2201 can extend along the row direction, and one end is connected to the lead-out section 210;
  • the second extension section 2202 can extend in the column direction, and one end is connected to the first extension section 2201 , and the other end extends into the area of the transfer layer 2 corresponding to the driving region 102 to be connected to the first pixel circuit 110 .
  • the second extension section 2202 may be directly connected to the first pixel circuit 110, or may be connected through other extension lines.
  • the second extending section 2202 of the fourth lead 211d is located in the second sub-region 2012 and avoids contact with the first lead 211a.
  • the second extending section 2202 of the fifth lead 211e is located in the third sub-region 2013 and avoids contact with the second lead 211b.
  • the second extension section 2202 of the second group of sixth leads 211f is located in the fourth sub-region 2014 and avoids contact with the third lead 211c.
  • the second extension section 2202 extends from the space between the fourth transfer holes 201d in the column direction.
  • the fourth transfer holes 201d are distributed in row i and column j, and any two adjacent columns are At most j-1 second extension sections 2202 are distributed among the four adapter holes 201d.
  • Both i and j are positive integers, and their specific values are not particularly limited here.
  • j can be 5, that is, at most four second extension sections 2202 can be distributed between two adjacent rows of transfer holes 201
  • i can be 50, 80, 100, etc., which can be equal to N above.
  • more or less second extension sections 2202 may also be disposed between two adjacent rows of transfer holes 201 .
  • each extension section 220 is connected to each lead-out section 210 respectively, so that each extension section 220 is distributed in parallel between two adjacent rows of transfer holes 201 .
  • the lengths of the lead-out segments 210 connected to the same row of the transfer holes 201 are different, and the lengths gradually increase toward the first central axis S1.
  • the lead-out sections 210 are connected so that the first extension sections 2201 are distributed in parallel between two adjacent rows of transfer holes 201 .
  • the lengths of the lead-out segments 210 connected to the same row of the transfer holes 201 in the second group of sixth leads 211f may be the same, and the lengths of the first extension segments 2201 may also be the same, so as to be compatible with the corresponding ones in the frame area 1022 or the pixel area 1021
  • the first pixel circuit 110 is connected.
  • the fourth via hole 201d in the first sub-sub-region 2014a can be connected to the corresponding first pixel circuit 110 only through the fourth lead 211d without setting The fifth lead 211e and the sixth lead 211f.
  • the fourth lead 211d can be divided into a first group and a second group.
  • the fourth lead 211d of the first group is connected to the row of fourth transfer holes 201d connected to the first group of sixth leads 211f above, and is arranged along the column direction extend.
  • the fourth via hole 201 d in the first sub-sub-region 2014 a can communicate with the corresponding first pixel circuit 110 only through the fourth lead 211 d and the fifth lead 211 e connected without providing the sixth lead 211f.
  • the fifth lead 211e can be divided into a first group and a second group.
  • the fifth lead 211e of the first group is connected to the row of fourth transfer holes 201d connected to the sixth lead 211f of the first group, and is arranged in the column direction. extend.
  • the leads 211 on both sides of the first central axis S1 may be symmetrically arranged with respect to the first central axis S1 .
  • the leads 211 on both sides of the third central axis may be symmetrical with respect to the third central axis S3, which is the central axis of the light-transmitting region 101 along the row direction.
  • the routing areas 20 of the transition layer 2 are also symmetrically distributed about the first central axis S1 and the third central axis S3, and the light emitting devices 30 are also symmetrically distributed about the first central axis S1 and the third central axis S3.
  • FIGS. 8 to 13 are only schematic diagrams for explaining the paths of the leads 211 , and do not limit the specific structures of elements such as the leads 211 and the wiring portion 3112 .
  • An embodiment of the present disclosure provides a method for manufacturing a display panel.
  • the display panel may be the display panel of any of the above-mentioned embodiments, and its structure will not be described in detail here.
  • the manufacturing method may include steps S110-S130, wherein:
  • Step S110 forming a driving backplane, the driving backplane has a light-transmitting area and a driving area at least partially surrounding the light-transmitting area, the driving area has a plurality of pixel circuits, and at least includes a first pixel circuit and a first pixel circuit. Two pixel circuit;
  • Step S120 forming a transfer layer on one side of the driving backplane, the transfer layer includes multiple layers of mutually insulated lead layers, each of the lead layers includes a plurality of mutually insulated leads; each lead is composed of the light-transmitting area extends to the driving area and is connected to a first pixel circuit;
  • Step S130 forming a light-emitting layer on the surface of the transition layer away from the driving backplane, where the light-emitting layer includes a plurality of light-emitting devices; the light-emitting device includes a plurality of first light-emitting devices located in the light-transmitting area and a plurality of second light-emitting devices located in the driving region; the first light-emitting devices are connected to the first pixel circuits through the leads in the lead layers in a one-to-one correspondence; the second pixel circuits are One corresponding to the second light emitting device is connected.
  • an embodiment of the present disclosure provides a display device
  • the display device may include the display panel of any of the above-mentioned embodiments, and the structure and beneficial effects can be referred to the above-mentioned embodiments of the display panel, which will not be repeated here.
  • the terminal device may include a display panel 100 and a camera device 200, wherein:
  • the display panel 100 can be the display panel of any of the above-mentioned embodiments, and its structure and beneficial effects can be referred to the above-mentioned embodiments of the display panel, which will not be repeated here.
  • the camera device 200 can be disposed on the backlight side of the display panel 100 , that is, the back side that emits light.
  • the OLED light-emitting device of the display panel 100 is a top-emission structure, that is, the camera device 200 can emit light in the direction away from the driving backplane.
  • the camera device 200 can be directly opposite to the light-transmitting area 101 for capturing images through the light-transmitting area 101 .
  • the OLED light-emitting device of the display panel 100 has a bottom emission structure, the camera device 200 can be disposed on the side of the light-emitting functional layer 312 away from the driving backplane 1 .
  • the camera device 200 may include a lens, a photoelectric sensor, etc., and the specific structure of the camera device 200 is not particularly limited here, as long as it can capture images.
  • the terminal device of the present disclosure may be an electronic device with display and photographing functions, such as a mobile phone, a tablet computer, a TV, etc., which will not be listed one by one here.

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Abstract

本公开是关于一种终端设备、显示装置、显示面板及其制造方法，涉及显示技术领域。该显示面板包括：驱动背板，具有透光区和至少部分围绕透光区的驱动区，驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；转接层，设于驱动背板一侧，且包括多层相互绝缘的引线层，每个引线层均包括多个相互绝缘的引线；每个引线均由透光区延伸至驱动区，并与一第一像素电路连接；发光层，设于转接层背离驱动背板的一侧，且包括多个发光器件；发光器件包括位于透光区的多个第一发光器件和位于驱动区的多个第二发光器件；第一发光器件通过各引线层中的引线一一对应地与第一像素电路连接；第二像素电路一一对应地与第二发光器件连接。 (图5)

Description

终端设备、显示装置、显示面板及其制造方法
交叉引用
本公开要求于2020年9月30日提交的国际申请号为PCT/CN2020/119673，名称为“显示面板及显示装置”的PCT申请的优先权，该PCT专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种终端设备、显示装置、显示面板及显示面板的制造方法。
背景技术
对于手机、平板电脑等具有摄像头的电子设备的屏幕而言，屏幕对应于摄像头的区域通常需要开孔，从而无法发光，这不利于提高屏占比。目前，虽然存在屏下摄像技术，使得摄像头所在区域也可显示图像，避免开孔，并可正常拍摄，但屏幕对应于摄像头的区域的亮度较低，从而影响整个屏幕的显示效果。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种终端设备、显示装置、显示面板及显示面板的制造方法。
根据本公开的一个方面，提供一种显示面板，包括：
驱动背板，具有透光区和至少部分围绕所述透光区的驱动区，所述驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；
转接层，设于所述驱动背板一侧，且包括多层相互绝缘的引线层，每个所述引线层均包括多个相互绝缘的引线；每个引线均由所述透光区延伸至所述驱动区，并与一所述第一像素电路连接；
发光层，设于所述转接层背离所述驱动背板的一侧，且包括多个发光器件；所述发光器件包括位于所述透光区的多个第一发光器件和位于所述驱动区的多个第二发光器件；
所述第一发光器件通过各所述引线层中的所述引线一一对应地与所述第一像素电路连接；所述第二像素电路一一对应地与所述第二发光器件连接。
在本公开的一种示例性实施例中，所述发光器件包括：
第一电极，设于所述转接层背离所述驱动背板的表面；所述第一电极具有电极部和位于所述电极部边缘以外的接线部；每个所述第一电极通过所述接线部和位于所述转接层中的一转接孔与一所述引线连接；
发光功能层，设于所述第一电极背离所述驱动背板的表面；
第二电极，设于所述发光功能层背离所述驱动背板的表面。
在本公开的一种示例性实施例中，多层所述引线层中至少包括从所述驱动背板向所述发光层依次分布的第一引线层、第二引线层和第三引线层；所述第一引线层的引线包括第一引线，所述第二引线层的引线包括第二引线，所述第三引线层的引线包括第三引线；
所述转接层对应于所述透光区的区域包括阵列分布的多个走线区，各所述走线区中包括一目标走线区，所述目标走线区位于第一中轴线的一侧，且所述目标走线区包括沿行方向朝所述第一中轴线依次分布的第一子区域、第二子区域和第三子区域；所述第一中轴线为所述透光区沿列方向的中轴线；
所述第一子区域内的转接孔为第一转接孔，所述第二子区域内的转接孔为第二转接孔；所述第三子区域内的转接孔为第三转接孔；
对应于所述第一子区域的接线部通过所述第一转接孔和所述第一引线与对应的所述第一像素电路连接；对应于所述第二子区域的接线部通过所述第二转接孔和所述第二引线与对应的所述第一像素电路连接；对应于所述第三子区域的接线部通过所述第三转接孔和所述第三引线与对应的所述第一像素电路连接。
在本公开的一种示例性实施例中，在所述第一子区域中，所述第一转接孔分布成N行和M列，且任意相邻两行所述第一转接孔之间至多分布有M个所述第一引线；N和M均为正整数。
在本公开的一种示例性实施例中，在所述第二子区域中，所述第二转接孔分布成N行和M列，且任意相邻两行所述第二转接孔之间至多分布有M个所述第二引线。
在本公开的一种示例性实施例中，在所述第三子区域中，所述第三转接孔分布成N行和M列，且任意相邻两行所述第三转接孔之间至多分布有M个所述第三引线。
在本公开的一种示例性实施例中，所述目标走线区还包括第四子区域，所述第四子区域位于所述第三子区域背离所述第一子区域的一侧，所述第四子区域的所述转接孔为第四转接孔；
所述第一引线层的引线还包括与所述第一引线绝缘设置的第四引线；且对应于所述第四子区域的至少部分所述接线部通过所述第四转接孔和所述第四引线与对应的所述第一像素电路连接。
在本公开的一种示例性实施例中，所述第二引线层的引线还包括与所述第二引线绝缘设置的第五引线，且对应于所述第四子区域的至少部分所述接 线部通过所述第四转接孔和所述第五引线与对应的所述第一像素电路连接。
在本公开的一种示例性实施例中，所述第三引线层的引线还包括与所述第三引线绝缘设置的第六引线，且对应于所述第四子区域的至少部分所述接线部通过所述第四转接孔和所述第六引线与对应的所述第一像素电路连接。
在本公开的一种示例性实施例中，所述第四子区域包括第一亚子区域和第二亚子区域，所述第一亚子区域和第二亚子区域关于第二中轴线对称，且位于所述第一亚子区域的所述引线和位于所述第二亚子区域的所述引线关于所述第二中轴线对称；所述第二中轴线为所述目标走线区沿行方向的中轴线。
在本公开的一种示例性实施例中，所述第一引线、所述第二引线和所述第三引线包括：
引出段，沿列方向延伸，且与所述转接孔连接；
延伸段，沿行方向延伸，且一端与所述引出段连接，另一端延伸至所述转接层对应于所述驱动区的区域。
在本公开的一种示例性实施例中，所述第四引线、所述第五引线和至少部分第六引线包括：
引出段，沿列方向延伸，且与所述转接孔连接；
延伸段，包括第一延伸段和第二延伸段，是第一延伸段沿行方向延伸，且一端与所述引出段连接，另一端位于所述目标走线区内；所述第二延伸段沿列方向延伸，且一端与所述第一延伸段连接，另一端延伸至所述转接层对应于所述驱动区的区域。
在本公开的一种示例性实施例中，所述第四引线的第二延伸段位于所述第二子区域；所述第五引线的第二延伸段位于所述第三子区域；所述第六引线的第二延伸段位于所述第四子区域。
在本公开的一种示例性实施例中，在所述第四子区域中，所述第四转接孔分布成i行和j列，且任意相邻两列所述第四转接孔之间至多分布有j-1个所述第二延伸段；i和j均为正整数。
在本公开的一种示例性实施例中，所述第一中轴线两侧的所述引线关于所述第一中轴线对称；
第三中轴线两侧的所述引线关于所述第三中轴线对称，所述第三中轴线为所述透光区沿行方向的中轴线。
在本公开的一种示例性实施例中，所述第一引线层设于所述驱动背板靠近所述发光层的表面；
所述转接层还包括：
第一平坦层，覆盖所述第一引线层和所述驱动背板靠近所述发光层的表面；所述第二引线层设于所述第一平坦层背离所述驱动背板的表面；
第二平坦层，覆盖所述第二引线层和所述第一平坦层靠近所述发光层的表面；所述第三引线层设于所述第二平坦层背离所述驱动背板的表面；
第三平坦层，覆盖所述第三引线层和所述第二平坦层靠近所述发光层的表面；所述发光层设于所述第三平坦层背离所述驱动背板的表面。
在本公开的一种示例性实施例中，所述第一发光器件在所述透光区的密度与所述第二发光器件在所述驱动区的密度相同。
在本公开的一种示例性实施例中，所述驱动区包括：
像素区，至少部分围绕于所述透光区外，所述透光区的一侧边与所述像素区的一侧边重合；
边框区，围绕于所述像素区以外；
至少一部分所述第一像素电路分布于所述像素区，至多有一部分第一像素电路分布于所述边框区。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
形成驱动背板，所述驱动背板具有透光区和至少部分围绕所述透光区的驱动区，所述驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；
在所述驱动背板一侧形成转接层，所述转接层包括多层相互绝缘的引线层，每个所述引线层均包括多个相互绝缘的引线；每个引线均由所述透光区延伸至所述驱动区，并与一所述第一像素电路连接；
在所述转接层背离所述驱动背板的表面形成发光层，所述发光层包括多个发光器件；所述发光器件包括位于所述透光区的多个第一发光器件和位于所述驱动区的多个第二发光器件；所述第一发光器件通过各所述引线层中的所述引线一一对应地与所述第一像素电路连接；所述第二像素电路一一对应地与所述第二发光器件连接。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
根据本公开的一个方面，提供一种终端设备，包括：
上述任意一项所述的显示面板；
摄像装置，设于所述显示面板的背光侧，且与所述透光区正对设置，用于透过所述透光区拍摄图像。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施例中驱动背板的示意图。
图2为本公开显示面板一实施例中像素电路与发光器件连接的示意图。
图3为本公开显示面板一实施例中像素电路的等效电路图。
图4为本公开显示面板一实施例中像素电路的结构示意图。
图5为本公开显示面板一实施例中显示面板的截面示意图。
图6为本公开显示面板一实施例中第一电极的俯视图。
图7为本公开显示面板一实施例中转接层的各走线区的示意图。
图8为本公开显示面板一实施例中第一子区域的示意图。
图9为本公开显示面板一实施例中第二子区域的示意图。
图10为本公开显示面板一实施例中第三子区域的示意图。
图11为本公开显示面板一实施例中第四子区域的引线示意图。
图12为本公开显示面板另一实施例中第四子区域的引线示意图。
图13为本公开显示面板再一实施例中第四子区域的引线示意图。
图14为本公开显示面板一实施例中一种引线的示意图。
图15为本公开显示面板一实施例中另一种引线的示意图。
图16为本公开制造方法一实施例的流程图。
图17为本公开显示装置一实施例的示意图。
附图标记说明：
1、驱动背板；101、透光区；102、驱动区；1021、像素区；1022、边框区；10、像素电路；110、第一像素电路；120、第二像素电路；2、转接层；20、走线区；20a、目标走线区；2011、第一子区域；2012、第二子区域；2013、第三子区域；2014、第四子区域；2014a、第一亚子区域；2014b、第二亚子区域；21、引线层；211、引线；21a、第一引线层；211a、第一引线；21b、第二引线层；211b、第二引线；21c、第三引线层；211c、第三引线；211d、第四引线；211e、第五引线；211f、第六引线；201、转接孔；201a、第一转接孔；201b、第二转接孔；201c、第三转接孔；201d、第四转接孔；210、引出段；220、延伸段；2201、第一延伸段；2202、第二延伸段；22、第一平坦层；23、第二平坦层；24、第三平坦层；3、发光层；30、发光器件；301、第一发光器件；302、第二发光器件；311、第一电极；3111、电极部；3112、接线部；312、发光功能层；313、第二电极；314、像素定义层；301、第一发光器件；302、第二发光器件；100、显示面板；200、摄像装置。
具体实施例
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个 或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
行方向和列方向仅只两个垂直的方向，并不限定其具体的朝向，例如，行方向可以是图8-图13中的横向X方向，列方向可以是图8-图13中的纵向Y方向。本领域技术人员可以知晓的是，若显示面板发生旋转，行方向和列方向的实际朝向可能发生变化。
本公开实施例提供了一种显示面板，该显示面板可为OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，如图1、图2和图5所示，该显示面板包括驱动背板1、转接层2和发光层3，其中：
驱动背板1具有透光区101和至少部分围绕透光区101的驱动区102，驱动区102内具有多个像素电路10，且至少包括第一像素电路110和第二像素电路120。
转接层2设于驱动背板1一侧，且包括多层相互绝缘的引线层21，每个引线层21均包括多个相互绝缘的引线211；每个引线211均由透光区101延伸至驱动区102，并与一第一像素电路110连接。
发光层3设于转接层2背离驱动背板1的一侧，且包括多个发光器件30；发光器件30包括对应于透光区101的多个第一发光器件301和对应于驱动区102的多个第二发光器件302。
第一发光器件301通过各引线层21中的引线211一一对应地与第一像素电路110连接；第二像素电路120一一对应地与第二发光器件302连接。
本公开实施例的显示面板，将用于驱动透光区101的第一发光器件301的第一像素电路110设置在了透光区101以外的驱动区102，在不减少发光器件30的数量的情况下，可提升透光区101的透光程度，便于摄像装置拍摄图像。同时，通过多层引线层21的引线211将透光区101的第一发光器件301与第一像素电路110连接，使得透光区101可正常显示图像，且多个引线层21可增大引线211的布设空间，在透光区101的第一发光器件301较多的情况下，仍可将每个第一发光器件301与第一像素电路110连接，避免因为无法设置足够的引线211而减少第一发光器件301的数量。此外，第二发光器件302与第二像素电路120连接，可在透光区101以外显示图像。
下面对显示面板的各部分进行说明：
如图1所示，驱动背板1中设有用于驱动发光器件30发光的像素电路10，且驱动背板1至少包括透光区101和驱动区102，其中，像素电路10位于驱动区102，而透光区101中则不设置像素电路10，以提高透明度，摄像装置可透过透光区101拍摄图像，从而实现屏下摄像。
如图2所示，驱动区102中的像素电路10至少包括第一像素电路110和第二像素电路120，其中，第一像素电路110用于驱动对应于透光区101 的发光器件，即第一发光器件301；第二像素电路120用于驱动对应于驱动区102的发光器件，即第二发光器件302。
在本公开的一些实施例中，如图1和图2所示，驱动区102可包括像素区1021和边框区1022，其中，像素区1021至少部分围绕于透光区101外，透光区101的一侧边可与像素区1021的一侧边至少部分重合。边框区1022可围绕于像素区1021以外，边框区1022内可设有用于向像素电路10输入驱动信号的***电路，该***电路可包括栅极驱动电路、发光控制电路等，在此不做特殊限定。当然，像素区1021也可完全包围透光区101。
进一步的，第一像素电路110可全部分布于像素区1021内，所有第二像素电路120也分布于像素区1021内。当然，也可将一部分第一像素电路110设置在像素区1021内，所有第二像素电路120也分布于像素区1021内，并将其它第一像素电路110设置在边框区1022内。此外，还可以将所有第一像素电路110设置在边框区1022内。
进一步的，像素区1021中的第一像素电路110和第二像素电路120阵列分布，各列第一像素电路110位于各列第二像素电路120之间，且相邻两列第二像素电路120之间设有一列第一像素电路110；相邻两列第一像素电路110之间可设有多列第二像素电路120。
此外，可将在行方向上距离所述透光区101最近的一列或多列像素电路10不与第一发光器件301和第二发光器件302连接，将这些像素电路10作为虚设像素电路(图中未示出)，以便增加与第一发光器件301连接的距离透光区101最近的第二像素电路120与透光区101的距离，增加对应的引线211的最小长度，避免因引线211的长度差异过大而引起不同列的第一发光器件301的启亮时刻差别过大，提高画面质量。
为了在不降低像素电路10数量的情况下，使驱动区102内具有足够的空间容纳第一像素电路110和第二像素电路120。可沿行方向对各像素电路10进行压缩，减小像素电路10在行方向上的宽度，在驱动背板1的尺寸相同的前提下，使驱动区102内能够多出较多区域，并可在该较多区域处设置第二像素电路120。像素电路10的宽度是指沿行方向像素电路10的在驱动背板1上的正投影的长度。
下面对像素电路10的结构进行示例性说明：
在本公开的一些实施例中，如图3和图4所示，像素电路10(第一像素电路110和第二像素电路120)可以为7T1C结构，即包括7个晶体管和1个电容。该7T1C像素电路包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。该像素电路可以与栅极信号端Gate，数据信号端Data，复位信号端RST1和RST2，发光控制信号端EM，电源端VDD，初始电源端Vinit1和Vinit2，以及发光器件连接，该发光器件还可以与电源端VSS连接。该像素电路10可以用于响应于 所连接的各信号端提供的信号，驱动所连接的发光器件30发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开实施例的保护范围内的。
当然，在本公开的其它实施例中，像素电路10还可以采用其它结构，只要能驱动发光器件30发光既可，在此不对其结构做特殊限定。
基于上述像素电路10，以一个晶体管的结构为例，驱动背板1可包括依次层叠于衬底上的有源层、第一栅绝缘层、栅极、第二栅绝缘层、介电层、第一源漏层、第一平坦化层、第二源漏层和第二平坦化层，从而形成晶体管，在此不对晶体管的具体结构做特殊限定。
如图5所示，转接层2设于驱动背板1一侧，例如，设于第二平坦化层背离衬底的表面。转接层2可覆盖透光区101和驱动区102，且转接层2包括多层相互绝缘的引线层21，每个引线层21均包括多个相互绝缘的引线211，每个引线211均由透光区101延伸至驱动区102，并与一第一像素电路110连接，也就是说，每个引线211只用于传输来自一个第一像素电路110的信号。同时，转接层2内设有与各引线211一一对应连接的转接孔201，任一第一发光器件301可通过一转接孔201和引线211与对应的第一像素电路110连接。转接孔201可为转接层2内的过孔结构，但由于转接孔201所连接的引线211可能位于不同的引线层21，因此，不同转接孔201的深度可以不同。
每个引线层21的引线211的材料均可以是由氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料。
在本公开的一些实施例中，如图5所示，引线层21的数量可以为三层，包括从驱动背板1向发光层3依次分布的第一引线层21a、第二引线层21b和第三引线层21c。其中，第一引线层21a的引线211包括第一引线211a，第二引线层21b的引线211包括第二引线211b，第三引线层21c的引线211包括第三引线211c。
需要说明的是，图5仅为了说明显示面板的各膜层的关系而示意性示出，并不限定为引线层21的具体结构。
如图5所示，为了使各引线层21之间绝缘，转接层2还包括第一平坦层22、第二平坦层23和第三平坦层24，其中：
可将第一引线层21a设于驱动背板1靠近发光层3的表面。第一平坦层22覆盖第一引线层21a和驱动背板1靠近发光层3的表面。
第二引线层21b设于第一平坦层22背离驱动背板1的表面。第二平坦层23覆盖第二引线层21b和第一平坦层22靠近发光层3的表面。
第三引线层21c设于第二平坦层23背离驱动背板1的表面。第三平坦层24覆盖第三引线层21c和第二平坦层23靠近发光层3的表面；发光层3设于第三平坦层24背离驱动背板1的表面。
如图5所示，发光层3可包括多个发光器件30，每个发光器件30可通过一引线211与一第一像素电路110连接。发光器件30可为OLED发光器件，其可包括第一电极311、发光功能层312和第二电极313，其中：
第一电极311可设于转接层2背离驱动背板1的表面，例如，第一电极311设于第三平坦层24背离驱动背板1的表面。如图6所示，第一电极311作为OLED发光器件的阳极，具有电极部3111和位于电极部3111边缘以外的接线部3112，接线部3112与电极部3111连接或采用一体结构。每个第一电极311的电极部3111通过接线部3112和位于转接层2中的一转接孔201与一引线211连接，从而将第一像素电路110与对应的发光器件30的第一电极311连接起来。
发光功能层312可设于第一电极311背离驱动背板1的表面，其可包括依次层叠于第一电极311上的空穴注入层、空穴传输层、有机发光层、电子传输层和电子注入层。
第二电极313作为OLED发光器件的阴极，可设于发光功能层312背离驱动背板1的表面。通过向第一电极311和第二电极313施加电信号可驱动发光功能层312发光。
以上为一个发光器件30的结构，在整个显示面板中，各个发光器件30的第一电极311可采用相同的材料，通过一次构图工艺同时形成，各个发光功能层312也可采用相同的材料，通过一次构图工艺同时形成。同时，各个发光器件30可共用同一第二电极313，也就是说，第二电极313可同时覆盖各个发光功能层312。此外，为了便于限定各个发光器件30的发光范围，发光层3还可包括像素定义层314，其可设于转接层2背离驱动背板1的表面，且具有露出各个第一电极311的开口，发光功能层312可在各个开口内覆盖第一电极311，且露出电极部3111，接线部3112位于开口以外。
为了使发光层3对应于透光区101的区域与对应于驱动区102的区域的亮度一致。可使第一发光器件301在对应于透光区101的区域的密度与第二发光器件302在对应于驱动区102的区域的密度相同。
下面结合转接层2的具体结构对引线211的走线方式进行详细说明：
在本公开的一些实施例中，如图7所示，可对转接层2对应于透光区101的区域进行分区，得到多个走线区20，每个走线区20内的引线211用于连接该走线区20对应的发光器件30。具体而言，转接层2对应于透光区101的区域可包括阵列分布的多个走线区20，即各走线区20在驱动背板1上的正投影均位于透光区101以内。
如图7所示，以透光区101沿列方向的中轴线为第一中轴线S1。各走线区20中包括一目标走线区20a，该目标走线区20a位于第一中轴线S1的 一侧，且目标走线区20a包括沿行方向朝第一中轴线S1依次分布的多个子区域，其中包括第一子区域2011、第二子区域2012和第三子区域2013，第一子区域2011、第二子区域2012和第三子区域2013在行方向上的宽度可以相等。
如图8所示，第一子区域2011内的转接孔201为第一转接孔201a，每个第一转接孔201a可与一第一引线211a连接，因而第一转接孔201a贯穿第一平坦层22、第二平坦层23和第三平坦层24。如图9所示，第二子区域2012内的转接孔201为第二转接孔201b，每个第二转接孔201b可与一第二引线211b连接，因而第二转接孔201b贯穿第二平坦层23和第三平坦层24。如图10所示，第三子区域2013内的转接孔201为第三转接孔201c，每个第二转接孔201c可与一第三引线211c连接，因而第三转接孔201c贯穿第三平坦层24。此外，第一转接孔201a、第二转接孔201b和第三转接孔201c可分别与其对应的第一发光器件301连接，从而实现引线211与第一发光器件301的连接。
同时，如图8-图10所示，发光层3中，对应于第一子区域2011的接线部3112可通过第一转接孔201a和第一引线211a与对应的第一像素电路110连接。对应于第二子区域2012的接线部3112可通过第二转接孔201b和第二引线211b与对应的第一像素电路110连接。对应于第三子区域2013的接线部3112可通过第三转接孔201c和第三引线211c与对应的第一像素电路110连接。
进一步的，在第一子区域2011的区域中，第一转接孔201a分布成N行和M列，且任意相邻两行第一转接孔201a之间至多分布有M个第一引线211a。
在所述第二子区域2012中，第二转接孔201b分布成N行和M列，且任意相邻两行第二转接孔201b之间至多分布有M个第二引线211b。
在所述第三子区域2013中，第三转接孔201c分布成N行和M列，且任意相邻两行第三转接孔201c之间至多分布有M个所述第三引线211c。
上述的N和M均为正整数，其具体数值在此不做特殊限定，例如，M可为13，即相邻两行转接孔201之间至多可分布13个引线211，N可为50、80，100等。
更进一步的，如图11-图13所示，目标走线区20a还可包括第四子区域2014，第四子区域2014位于第三子区域2013背离第一子区域2011的一侧，第四子区域2014内的转接孔201为第四转接孔201d。
第一引线层21a的引线211还可包括与第一引线211a绝缘设置的第四引线211d；且对应于第四子区域2014的至少部分接线部3112通过第四转接孔201d和第四引线211d与对应的第一像素电路110连接。也就说是说，第一引线层21a既可用于连接对应于第一子区域2011的第一发光器件301，还可用于连接对应于第四子区域2014的第一发光器件301。
第二引线层21b的引线211还包括与第二引线211b绝缘设置的第五引线211e，且对应于第四子区域2014的至少部分接线部3112通过第四转接孔201d和第五引线211e与对应的第一像素电路110连接。也就说是说，第二引线层21b既可用于连接对应于第二子区域2012的发光器件，还可用于连接对应于第四子区域2014的发光器件。
第三引线层21c的引线211还包括与第三引线211c绝缘设置的第六引线211f，且对应于第四子区域2014的至少部分接线部3112通过第四转接孔201d和第六引线211f与对应的第一像素电路110连接。也就说是说，第三引线层21c既可用于连接对应于第三子区域2013的发光器件，还可用于连接对应于第四子区域2014的发光器件。
如图11-图13所示，为了便于走线，可将第四子区域2014划分为多个亚子区域，例如，第四子区域2014可包括第一亚子区域2014a和第二亚子区域2014b，第一亚子区域2014a和第二亚子区域2014b关于第二中轴线S2对称。第二中轴线S2为目标走线区20a沿行方向的中轴线，对应于第一亚子区域2014a的引线211和对应于第二亚子区域2014b的引线211可关于第二中轴线S2对称设置。
下面对引线211的结构进行说明：
在本公开的一些实施例中，如图11所示，第一亚子区域2014a的第四转接孔201d分别通过第四引线211d、第五引线211e和第六引线211f与驱动区102中对应的第一像素电路110连接。其中，所有第六引线211f可分为第一组和第二组，第一组第六引线211f可与第一亚子区域2014a中距离显示面板边缘最近的一行第四转接孔201d连接，第一组第六引线211f的数量等于第一亚子区域2014a的第四转接孔201d的列数。第一组第六引线211f可沿列方向延伸至边框区1022，若其对应的第一像素电路110位于边框区1022，则第一组第六引线211f可在边框区1022内与其对应的第一像素电路110连接。当然，若边框区1022内不设置第一像素电路110，第一组第六引线211f可通过其它走线经过边框区1022再连接至像素区1021内的第一像素电路110。
如图11、图14和图15所示，第一引线211a至第五引线211e以及第二组第六引线211f包括引出段210和延伸段220，其中：
引出段210可沿列方向延伸，且与转接孔201连接，例如，第一引线211a的引出段210可与第一转接孔201a连接；第二引线211b的引出段210可与第二转接孔201b连接；第三引线211c的引出段210可与第三转接孔201c连接。第四引线211d、第五引线211e和第六引线211f的引出段210可与第四转接孔201d连接，但第四引线211d、第五引线211e和第六引线211f的引出段210所连接的第四转接孔201d不同。
延伸段220的一端与引出段210连接，另一端延伸至转接层2对应于驱动区102的区域，以便与第一像素电路110连接。
第一引线211a、第二引线211b和第三引线211c的延伸段220可沿行方向延伸。第四引线211d、第五引线211e和第二组第六引线211f的延伸段220至少包括两段，即第一延伸段2201和第二延伸段2202，其中：
第一延伸段2201可沿行方向延伸，且一端与引出段210连接；
第二延伸段2202可沿列方向延伸，且一端与第一延伸段2201连接，另一端延伸至转接层2对应于驱动区102的区域内，以便与第一像素电路110连接。当然，第二延伸段2202可以直接与第一像素电路110连接，也可通过其它延伸线路连接。
第四引线211d的第二延伸段2202位于第二子区域2012，避免与第一引线211a接触。第五引线211e的第二延伸段2202位于第三子区域2013，避免与第二引线211b接触。第二组第六引线211f的第二延伸段2202位于第四子区域2014，避免与第三引线211c接触。
第二延伸段2202从第四转接孔201d之间的空间沿列方向延伸，在第四子区域2014中，第四转接孔201d分布成i行和j列，且任意相邻两列第四转接孔201d之间至多分布有j-1个第二延伸段2202。i和j均为正整数，其具体数值在此不做特殊限定，例如，j可为5，即相邻两列转接孔201之间至多可分布4个第二延伸段2202，i可为50、80，100等，其可与上文的N相等。当然，相邻两列转接孔201之间也可设置更多或更少的第二延伸段2202。
此外，为了避免引线211交叉，对于第一引线211a、第二引线211b和第三引线211c而言，连接同一行转接孔201的各引出段210的长度不同，且长度向第一中轴线S1逐渐增大，各延伸段220分别与各引出段210连接，使得各延伸段220平行分布于相邻两行转接孔201之间。对于第四引线211d和第五引线211e而言，连接同一行转接孔201的各引出段210的长度不同，且长度向第一中轴线S1逐渐增大，各第一延伸段2201分别与各引出段210连接，使得各第一延伸段2201平行分布于相邻两行转接孔201之间。第二组第六引线211f中连接同一行转接孔201的各引出段210的长度可以相同，而第一延伸段2201的长度也可相同，以便在边框区1022或像素区1021内与对应的第一像素电路110连接。
在本公开的另一实施例中，如图12所示，第一亚子区域2014a中的第四转接孔201d可仅通过第四引线211d与对应的第一像素电路110连接，而不设置第五引线211e和第六引线211f。其中，第四引线211d可分为第一组和第二组，第一组第四引线211d与上文中第一组第六引线211f所连接的一行第四转接孔201d连接，并沿列方向延伸。第二组第四引线211e的结构可参考上文中的第四引线211d和第二组第五引线211e，在此不再赘述。
在本公开的再一实施例中，如图13所示，第一亚子区域2014a中的第四转接孔201d可仅通过第四引线211d和第五引线211e与对应的第一像素电路110连接，而不设置第六引线211f。其中，第五引线211e可分为第一 组和第二组，第一组第五引线211e与上文中第一组第六引线211f所连接的一行第四转接孔201d连接，并沿列方向延伸。第四引线211d和第二组第五引线211e的结构可参考上文中的第四引线211d和第二组第五引线211e，在此不再赘述。
进一步的，在透光区101中，第一中轴线S1两侧的引线211可关于第一中轴线S1对称设置。第三中轴线两侧的引线211可关于第三中轴线S3对称，第三中轴线S3为透光区101沿行方向的中轴线。相应的，转接层2的走线区20也关于第一中轴线S1和第三中轴线S3对称分布，发光器件30也关于第一中轴线S1和第三中轴线S3对称分布。
需要说明的是，图8-图13仅为说明引线211的路径而示意性示出，并不构成对引线211和接线部3112等要素的具体结构的限定。
本公开实施例提供一种显示面板的制造方法，该显示面板可以是上述任意实施例的显示面板，在此不再详述其结构。如图16所示，该制造方法可包括步骤S110-步骤S130，其中：
步骤S110、形成驱动背板，所述驱动背板具有透光区和至少部分围绕所述透光区的驱动区，所述驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；
步骤S120、在所述驱动背板一侧形成转接层，所述转接层包括多层相互绝缘的引线层，每个所述引线层均包括多个相互绝缘的引线；每个引线均由所述透光区延伸至所述驱动区，并与一所述第一像素电路连接；
步骤S130、在所述转接层背离所述驱动背板的表面形成发光层，所述发光层包括多个发光器件；所述发光器件包括位于所述透光区的多个第一发光器件和位于所述驱动区的多个第二发光器件；所述第一发光器件通过各所述引线层中的所述引线一一对应地与所述第一像素电路连接；所述第二像素电路一一对应地与所述第二发光器件连接。
需要说明的是，尽管在附图中以特定顺序描述了本公开中制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施例提供一种显示装置，该显示装置可包括上述任意实施例的显示面板，其结构可有益效果可参考上文中显示面板的实施例，在此不再赘述。
本公开实施例还提供了一种终端设备，如图17所示，该终端设备可包括显示面板100和摄像装置200，其中：
该显示面板100可为上述任意实施例的显示面板，其结构可有益效果可参考上文中显示面板的实施例，在此不再赘述。
摄像装置200可设于显示面板100的背光侧，即发光朝向的背侧，例如， 显示面板100的OLED发光器件为顶发射结构，即向背离驱动背板的方向发光，则摄像装置200可设于驱动背板1背离发光功能层312的一侧，且摄像装置200可与透光区101正对，用于透过透光区101拍摄图像。若显示面板100的OLED发光器件为底发射结构，则摄像装置200可设于发光功能层312背离驱动背板1的一侧。摄像装置200可以包括镜头和光电传感器等，在此不对摄像装置200的具体结构做特殊限定，只要能拍摄图像既可。
本公开的终端设备可以是手机、平板电脑、电视等具有显示和拍摄功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种显示面板，其中，包括：
    驱动背板，具有透光区和至少部分围绕所述透光区的驱动区，所述驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；
    转接层，设于所述驱动背板一侧，且包括多层相互绝缘的引线层，每个所述引线层均包括多个相互绝缘的引线；每个引线均由所述透光区延伸至所述驱动区，并与一所述第一像素电路连接；
    发光层，设于所述转接层背离所述驱动背板的一侧，且包括多个发光器件；所述发光器件包括位于所述透光区的多个第一发光器件和位于所述驱动区的多个第二发光器件；
    所述第一发光器件通过各所述引线层中的所述引线一一对应地与所述第一像素电路连接；所述第二像素电路一一对应地与所述第二发光器件连接。
  2. 根据权利要求1所述的显示面板，其中，所述发光器件包括：
    第一电极，设于所述转接层背离所述驱动背板的表面；所述第一电极具有电极部和位于所述电极部边缘以外的接线部；每个所述第一电极通过所述接线部和位于所述转接层中的一转接孔与一所述引线连接；
    发光功能层，设于所述第一电极背离所述驱动背板的表面；
    第二电极，设于所述发光功能层背离所述驱动背板的表面。
  3. 根据权利要求2所述的显示面板，其中，多层所述引线层中至少包括从所述驱动背板向所述发光层依次分布的第一引线层、第二引线层和第三引线层；所述第一引线层的引线包括第一引线，所述第二引线层的引线包括第二引线，所述第三引线层的引线包括第三引线；
    所述转接层对应于所述透光区的区域包括阵列分布的多个走线区，各所述走线区中包括一目标走线区，所述目标走线区位于第一中轴线的一侧，且所述目标走线区包括沿行方向朝所述第一中轴线依次分布的第一子区域、第二子区域和第三子区域；所述第一中轴线为所述透光区沿列方向的中轴线；
    所述第一子区域内的转接孔为第一转接孔，所述第二子区域内的转接孔为第二转接孔；所述第三子区域内的转接孔为第三转接孔；
    对应于所述第一子区域的接线部通过所述第一转接孔和所述第一引线与对应的所述第一像素电路连接；对应于所述第二子区域的接线部通过所述第二转接孔和所述第二引线与对应的所述第一像素电路连接；对应于所述第三子区域的接线部通过所述第三转接孔和所述第三引线与对应的所述第一像素电路连接。
  4. 根据权利要求3所述的显示面板，其中，在所述第一子区域中，所述第一转接孔分布成N行和M列，且任意相邻两行所述第一转接孔之间至多分布有M个所述第一引线；N和M均为正整数。
  5. 根据权利要求3所述的显示面板，其中，在所述第二子区域中，所述第二转接孔分布成N行和M列，且任意相邻两行所述第二转接孔之间至 多分布有M个所述第二引线。
  6. 根据权利要求3所述的显示面板，其中，在所述第三子区域中，所述第三转接孔分布成N行和M列，且任意相邻两行所述第三转接孔之间至多分布有M个所述第三引线。
  7. 根据权利要求3所述的显示面板，其中，所述目标走线区还包括第四子区域，所述第四子区域位于所述第三子区域背离所述第一子区域的一侧，所述第四子区域的所述转接孔为第四转接孔；
    所述第一引线层的引线还包括与所述第一引线绝缘设置的第四引线；且对应于所述第四子区域的至少部分所述接线部通过所述第四转接孔和所述第四引线与对应的所述第一像素电路连接。
  8. 根据权利要求7所述的显示面板，其中，所述第二引线层的引线还包括与所述第二引线绝缘设置的第五引线，且对应于所述第四子区域的至少部分所述接线部通过所述第四转接孔和所述第五引线与对应的所述第一像素电路连接。
  9. 根据权利要求8所述的显示面板，其中，所述第三引线层的引线还包括与所述第三引线绝缘设置的第六引线，且对应于所述第四子区域的至少部分所述接线部通过所述第四转接孔和所述第六引线与对应的所述第一像素电路连接。
  10. 根据权利要求9所述的显示面板，其中，所述第四子区域包括第一亚子区域和第二亚子区域，所述第一亚子区域和第二亚子区域关于第二中轴线对称，且位于所述第一亚子区域的所述引线和位于所述第二亚子区域的所述引线关于所述第二中轴线对称；所述第二中轴线为所述目标走线区沿行方向的中轴线。
  11. 根据权利要求10所述的显示面板，其中，所述第一引线、所述第二引线和所述第三引线包括：
    引出段，沿列方向延伸，且与所述转接孔连接；
    延伸段，沿行方向延伸，且一端与所述引出段连接，另一端延伸至所述转接层对应于所述驱动区的区域。
  12. 根据权利要求10所述的显示面板，其中，所述第四引线、所述第五引线和至少部分第六引线包括：
    引出段，沿列方向延伸，且与所述转接孔连接；
    延伸段，包括第一延伸段和第二延伸段，是第一延伸段沿行方向延伸，且一端与所述引出段连接，另一端位于所述目标走线区内；所述第二延伸段沿列方向延伸，且一端与所述第一延伸段连接，另一端延伸至所述转接层对应于所述驱动区的区域。
  13. 根据权利要求12所述的显示面板，其中，所述第四引线的第二延伸段位于所述第二子区域；所述第五引线的第二延伸段位于所述第三子区域；所述第六引线的第二延伸段位于所述第四子区域。
  14. 根据权利要求12所述的显示面板，其中，在所述第四子区域中，所述第四转接孔分布成i行和j列，且任意相邻两列所述第四转接孔之间至多分布有j-1个所述第二延伸段；i和j均为正整数。
  15. 根据权利要求3所述的显示面板，其中，所述第一中轴线两侧的所述引线关于所述第一中轴线对称；
    第三中轴线两侧的所述引线关于所述第三中轴线对称，所述第三中轴线为所述透光区沿行方向的中轴线。
  16. 根据权利要求3所述的显示面板，其中，所述第一引线层设于所述驱动背板靠近所述发光层的表面；
    所述转接层还包括：
    第一平坦层，覆盖所述第一引线层和所述驱动背板靠近所述发光层的表面；所述第二引线层设于所述第一平坦层背离所述驱动背板的表面；
    第二平坦层，覆盖所述第二引线层和所述第一平坦层靠近所述发光层的表面；所述第三引线层设于所述第二平坦层背离所述驱动背板的表面；
    第三平坦层，覆盖所述第三引线层和所述第二平坦层靠近所述发光层的表面；所述发光层设于所述第三平坦层背离所述驱动背板的表面。
  17. 根据权利要求1所述的显示面板，其中，所述第一发光器件在所述透光区的密度与所述第二发光器件在所述驱动区的密度相同。
  18. 根据权利要求1所述的显示面板，其中，所述驱动区包括：
    像素区，至少部分围绕于所述透光区外，所述透光区的一侧边与所述像素区的一侧边重合；
    边框区，围绕于所述像素区以外；
    至少一部分所述第一像素电路分布于所述像素区，至多有一部分第一像素电路分布于所述边框区。
  19. 一种显示面板的制造方法，其中，包括：
    形成驱动背板，所述驱动背板具有透光区和至少部分围绕所述透光区的驱动区，所述驱动区内具有多个像素电路，且至少包括第一像素电路和第二像素电路；
    在所述驱动背板一侧形成转接层，所述转接层包括多层相互绝缘的引线层，每个所述引线层均包括多个相互绝缘的引线；每个引线均由所述透光区延伸至所述驱动区，并与一所述第一像素电路连接；
    在所述转接层背离所述驱动背板的表面形成发光层，所述发光层包括多个发光器件；所述发光器件包括位于所述透光区的多个第一发光器件和位于所述驱动区的多个第二发光器件；所述第一发光器件通过各所述引线层中的所述引线一一对应地与所述第一像素电路连接；所述第二像素电路一一对应地与所述第二发光器件连接。
  20. 一种显示装置，其中，包括权利要求1-18任一项所述的显示面板。
  21. 一种终端设备，其中，包括：
    权利要求1-18任一项所述的显示面板；
    摄像装置，设于所述显示面板的背光侧，且与所述透光区正对设置，用于透过所述透光区拍摄图像。
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