WO2022179309A1 - 一种时钟管理装置、时钟分频模块以及片上*** - Google Patents

一种时钟管理装置、时钟分频模块以及片上*** Download PDF

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Publication number
WO2022179309A1
WO2022179309A1 PCT/CN2021/143716 CN2021143716W WO2022179309A1 WO 2022179309 A1 WO2022179309 A1 WO 2022179309A1 CN 2021143716 W CN2021143716 W CN 2021143716W WO 2022179309 A1 WO2022179309 A1 WO 2022179309A1
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Prior art keywords
clock
state
synchronization signal
output
current
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PCT/CN2021/143716
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English (en)
French (fr)
Inventor
何雅乾
童力
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乐鑫信息科技（上海）股份有限公司
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Priority to US18/548,044 priority Critical patent/US20240146310A1/en
Publication of WO2022179309A1 publication Critical patent/WO2022179309A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/406—Synchronisation of counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a clock management device, a clock frequency division module, and a system-on-chip.
  • SoC System-on-a-chip
  • SoC System-on-a-chip
  • the current SoC divides each functional module into different clock domains. Different clock domains work at different clock frequencies, and the working clock frequency of a certain clock domain can be adjusted according to the current task load, or the clocks of modules that do not participate in the current task can be turned off.
  • the turn-off of the clock and the adjustment of the frequency often lead to the phase shift between the clocks in different clock domains, which makes the transmission of signals across the clock domain have relatively large circuit and timing overhead, resulting in an increase in chip area and a decrease in performance.
  • an existing adjustment method is: when each clock is switched or frequency adjusted, all the clocks are first turned off, and then turned on together after the frequency adjustment setting is completed, so as to achieve the purpose of phase consistency.
  • the clock is turned off during the adjustment process, and the process is complicated, which affects the performance of the system.
  • a clock management device including:
  • the clock synchronization signal generator is configured to generate a synchronization signal of a predetermined period
  • the multiple clock gating units are in one-to-one correspondence with the multiple clock frequency dividing modules, and one of the multiple clock gating units is connected in series with one of the multiple clock frequency dividing modules to form a signal processing branch
  • a plurality of the signal processing branches are connected in parallel, and are configured to receive a source clock signal
  • the clock gating unit is configured to control the switch of the signal processing branches
  • the clock frequency division module is configured to receive After reaching the synchronization signal output by the clock synchronization signal generator, phase adjustment is performed on the clock signal of the signal processing branch, and the clock signals in the plurality of signal processing branches are adjusted from an asynchronous state to a synchronous state.
  • the clock signals output by a plurality of the signal processing branches are used as working clocks of a plurality of clock domains.
  • the predetermined period is a common multiple of periods of operating clocks of the multiple clock domains.
  • the clock frequency division module includes: a state machine, a synchronization signal delay circuit and a clock generation circuit;
  • the synchronization signal delay circuit is configured to delay the synchronization signal after receiving the synchronization signal output by the clock synchronization signal generator;
  • the state machine is configured to control the clock generation circuit to adjust the phase of the output clock if the clock signals in the multiple signal processing branches are currently in an asynchronous state after receiving the delayed synchronization signal.
  • the clock frequency dividing module further includes: a counter and a comparator
  • the counter is configured to perform periodic counting under the control of the state machine to determine the current count value
  • the comparator is configured to compare the current count value with the maximum count threshold of the clock frequency dividing module, and output status information of whether the current state is synchronized; when the current count value is consistent with the maximum count threshold , output the state information that the current state is the synchronous state; when the current count value is inconsistent with the maximum count threshold, output the state information that the current state is the asynchronous state;
  • the state machine is configured to receive the state information sent by the comparator
  • the maximum count threshold is a value obtained by subtracting one from the preset frequency dividing ratio of the clock frequency dividing module.
  • the clock frequency dividing module further includes: a frequency dividing ratio register configured to store the maximum count threshold.
  • the numerical value of the preset frequency dividing ratio when the numerical value of the preset frequency dividing ratio is adjusted, the numerical value of the maximum count threshold stored in the frequency dividing ratio register is in a synchronous state when the clock signal is in a synchronous state and the clock frequency dividing module receives the In the case of a synchronization signal, the value of the maximum count threshold is modified.
  • the state machine is configured to switch to the asynchronous state after receiving the state information that the current state is the asynchronous state, and control the clock generation circuit to turn off the clock output; after the counter counts to the maximum count After the threshold value, the state machine is configured to switch to the phase adjustment state, and the counter records the current count value when the synchronization signal occurs as the phase offset value; when the counter continues to count to the phase offset value, The state machine controls the clock generation circuit to turn on the clock output.
  • the clock generation circuit is implemented by a clock gating unit or flip-flop flipping.
  • the state machine when a signal corresponding to the clock gating unit is enabled or reset, the state machine jumps to an asynchronous state.
  • the synchronization signal delay circuit is configured to, after receiving the synchronization signal output by the synchronization signal generator, according to a preset frequency division clock phase offset value, take the cycle of the source clock as a unit to The sync signal is delayed.
  • the application also provides a clock frequency division module, including: a state machine, a synchronization signal delay circuit, and a clock generation circuit;
  • the synchronization signal delay circuit is configured to delay the synchronization signal after receiving the synchronization signal
  • the state machine is configured to control the clock generation circuit to adjust the phase of the output clock if the current clock signal and other clock signals are in an asynchronous state after receiving the delayed synchronization signal.
  • it also includes: a counter and a comparator
  • the counter is configured to perform periodic counting under the control of the state machine to determine the current count value
  • the comparator is configured to compare the current count value with the maximum count threshold of the clock frequency dividing module, and output status information of whether the current state is synchronized; when the current count value is consistent with the maximum count threshold , output the state information that the current state is the synchronous state; when the current count value is inconsistent with the maximum count threshold, output the state information that the current state is the asynchronous state;
  • the state machine is configured to receive the state information sent by the comparator
  • the maximum count threshold is a value obtained by subtracting one from the preset frequency dividing ratio of the clock frequency dividing module.
  • the present application also provides a system-on-chip, including any of the clock management apparatuses described above, where clock signals output by the clock management apparatus are used for the same or different functional modules of the system-on-chip.
  • the clock management device, the clock frequency division module and the system-on-chip provided by the present application includes a clock synchronization signal generator, a plurality of clock gating units and a plurality of clock frequency division modules; Synchronization signal; a plurality of clock gating units are in one-to-one correspondence with a plurality of clock frequency division modules, and one of the plurality of clock gating control units is connected in series with one of the plurality of clock frequency division modules to form a signal processing branch; a plurality of signal processing The branches are connected in parallel to receive the source clock signal, the clock gating unit controls the switch of the signal processing branch, the clock frequency division module is configured to The signals are phase adjusted, and the clock signals in the multiple signal processing branches are adjusted from an asynchronous state to a synchronous state.
  • the clock management device, clock frequency division module, and system-on-chip provided by the present application realize controllable phase of the working clock of each clock domain, and can realize adjustment without shutting down the system, which simplifies the adjustment process
  • FIG. 1 schematically shows a structural block diagram of a specific implementation manner of a clock management apparatus provided by the present application
  • FIG. 2 schematically shows a schematic diagram of a clock frequency dividing module provided by the present application
  • Fig. 3 schematically shows the state diagram of the state machine in the clock frequency dividing module
  • FIG. 4 schematically shows a schematic diagram of the phase adjustment of the clock management apparatus provided by the present application.
  • FIG. 1 shows a structural block diagram of a specific implementation manner of a clock management apparatus provided by the present application.
  • the clock management apparatus 1 includes a clock synchronization signal generator 10 , a plurality of clock gating units 12 and a plurality of clock frequency division modules 14 .
  • the clock synchronization signal generator 10 is configured to generate a synchronization signal of a predetermined period; the clock gating units 12 are in one-to-one correspondence with the clock frequency dividing modules 14, and the clock gating One of the units 12 is connected in series with one of the plurality of clock frequency division modules 14 to form a signal processing branch; a plurality of the signal processing branches are connected in parallel and are configured to receive a source clock signal, and the clock gating unit 12 is configured to control the switch of the signal processing branch, and the clock frequency dividing module 14 is configured to, after receiving the synchronization signal output by the clock synchronization signal generator 10, change the clock of the signal processing branch Phase adjustment is performed on the signal to adjust the clock signals in the plurality of signal processing branches from an asynchronous state to a synchronous state.
  • the working clock of each clock domain is obtained by the source clock through the switch control of the clock gating unit and the clock frequency dividing module. That is, the clock signals output by the plurality of signal processing branches are used as the operating clocks of the plurality of clock domains.
  • the clock synchronization signal generator can be composed of a source clock driven counter, can generate a pulse synchronization signal of a predetermined period according to the software configuration, and can be used as a unified reference for the whole chip clock.
  • the predetermined period may be a common multiple of the periods of the operating clocks of the multiple clock domains. It can be understood that the period of the working clock of each clock domain is adjustable.
  • the clock management device provided by the present application realizes the controllable phase of the working clock of each clock domain, and can realize adjustment without shutting down the system, which simplifies the adjustment process and improves the performance of the system.
  • the clock frequency division module 14 may include: a state machine 140 , a synchronization signal delay circuit 142 and a clock generation circuit 144 .
  • FIG. 2 is a schematic diagram of the clock frequency dividing module provided by the present application.
  • the synchronization signal delay circuit 142 is configured to delay the synchronization signal after receiving the synchronization signal output by the synchronization signal generator 10;
  • the state machine 140 is configured to receive the delayed synchronization signal Afterwards, if the clock signals in the plurality of signal processing branches are currently in an asynchronous state, the clock generating circuit 144 is controlled to adjust the phase of the output clock.
  • the clock frequency dividing module 14 may further include: a counter 146 and a comparator 148 .
  • the counter 146 is configured to perform periodic counting under the control of the state machine to determine the current count value
  • the comparator 148 is configured to compare the current count value with the maximum value of the clock frequency dividing module Compare the count threshold, and output the status information of whether the current state is synchronized; when the current count value is consistent with the maximum count threshold, output the status information that the current state is a synchronous state; when the current count value and the maximum count When the thresholds are inconsistent, output state information that the current state is an asynchronous state
  • the state machine 140 is configured to receive the state information sent by the comparator 148 .
  • the clock frequency dividing module may further include: a frequency dividing ratio register 150 for storing the above-mentioned maximum count threshold.
  • the value of the preset frequency division ratio can be set according to the actual situation. As a specific implementation manner, when the value of the preset frequency division ratio is adjusted, the value of the maximum count threshold value stored in the frequency division ratio register is in a synchronized state when the clock signal is in a synchronized state and the clock frequency division module receives the received In the case of the synchronization signal, the value of the maximum count threshold is modified. When the frequency division ratio of the frequency divider is adjusted, the new frequency division coefficient will only update the maximum count threshold stored in the frequency division ratio register when the frequency divider is in a synchronous state and receives a synchronization signal.
  • the state machine 140 may be a finite state machine, which is configured to control the clock frequency division module.
  • the counter 146 performs periodic counting according to the preset frequency division ratio to determine the current count value.
  • the comparator compares the current count value with the maximum count threshold to determine whether the current state is a synchronous state or an asynchronous state. When the current count value is consistent with the maximum count threshold, the current state is the synchronization state. When the current count value is inconsistent with the maximum count threshold, the current state is an asynchronous state.
  • the state machine 140 controls the clock generation circuit 144 to adjust the phase of the output clock according to the state information obtained by the comparator.
  • the state machine is configured to switch to the asynchronous state after receiving the state information that the current state is the asynchronous state, and control the clock generation circuit to turn off the clock output; after the counter counts to the maximum count threshold, the state The machine is configured to switch to the phase adjustment state, and the counter records the current count value when the synchronization signal occurs as the phase offset value; when the counter continues to count to the phase offset value, the state machine controls all The clock generation circuit turns on the clock output.
  • the clock generation circuit can be realized by a clock gating unit or by flip-flop. None of this affects the implementation of this application.
  • the states of the state machine in the clock frequency dividing module include a synchronous state, an asynchronous state and a phase adjustment state.
  • the state of the state machine jumps to an asynchronous state.
  • the clock frequency division module receives the synchronization signal and the counter count reaches the maximum count threshold, the state of the state machine jumps to the synchronization state.
  • the asynchronous state is phase-adjusted, and the state of the state machine jumps to the synchronous state.
  • the state machine when the chip is reset or the clock is turned off, the state machine is in an asynchronous state.
  • the synchronization signal delay circuit delays the synchronization signal.
  • the comparator judges whether the current state is synchronous according to the count value of the current counter. If it is determined to be in the synchronous state, the state machine changes to the synchronous state. If it is in the asynchronous state, the counter records the current count value as the phase offset value and enters the phase adjustment state. The count limit of the counter is adjusted to the phase offset value. After the phase adjustment is completed, the state machine enters the synchronization state.
  • both the working clock A and the working clock B are divided by five of the source clock, and the phases are deviated.
  • the phase synchronization is realized.
  • the working clock A and the working clock B are both periodic signals divided by five, and the corresponding counter counts from 0 to 4 as a cycle.
  • the counter counts to 0 it corresponds to the rising edge of the signal
  • the counter counts to 3 corresponds to the falling edge of the signal. It can be seen that there is a phase deviation between the working clock A and the working clock B, the corresponding preset frequency division ratios are both 5, and the maximum count thresholds are both 4.
  • the current count value recorded by the counter is 3, and the comparator compares whether the current count value is consistent with the maximum count threshold value 4.
  • the current count value recorded by the counter is 2, and the comparator compares whether the current count value is consistent with the maximum count threshold value of 4. If it is inconsistent in this embodiment, it is determined that the current state is an asynchronous state.
  • the state machine After determining that the current state is the asynchronous state, the state machine switches from the synchronous state to the asynchronous state, and turns off the clock output. Referring to FIG. 4 , the clock signals corresponding to the operating clock A and the operating clock B are output as 0. After this round of counting of the counter is completed, that is, after the count reaches the maximum count threshold of 4, the state machine switches to the phase adjustment state.
  • the counter records the current count value when the synchronization signal occurs as the phase offset value. In this embodiment, for the frequency divider A, when the synchronization signal occurs, the current count value corresponding to the frequency divider A is 3, and the phase offset value is 3.
  • the frequency divider A counter performs phase adjustment according to the phase offset value of 3 after counting from 0 to the maximum value of 4 in the previous round, that is, it continues to count from 0 to 3 in the next round.
  • the frequency divider B when the synchronization signal occurs, the current count value corresponding to the frequency divider B is 2, and the phase offset value is 2.
  • the frequency divider B counter performs phase adjustment according to the phase offset value of 2 after counting from 0 to the maximum value of 4 in the previous round, that is, it continues to count from 0 to 2 in the next round.
  • the state machine switches to the synchronous state, and then turns on the clock output. At this time, the output working clock A and working clock B can be realized. Synchronize.
  • the synchronization signal delay circuit is configured to, after receiving the synchronization signal output by the synchronization signal generator, delay the synchronization signal in units of a period of the source clock according to a preset frequency-divided clock phase offset value.
  • phase control is achieved by delaying the synchronization signal. For example, if there is a phase difference between the clock of the first clock domain and the clock of the second clock domain, the synchronization signal received in the first clock domain is delayed by one cycle, so that the clock frequency division module keeps the delayed synchronization signal. If synchronized, the clock output from the first clock domain and the second clock domain also have a phase difference of one cycle.
  • the present application also provides a clock frequency dividing module.
  • the clock frequency division module 14 provided by the present application may include: a state machine 140 , a synchronization signal delay circuit 142 and a clock generation circuit 144 .
  • FIG. 2 is a schematic diagram of the clock frequency dividing module provided by the present application.
  • the synchronization signal delay circuit 142 is configured to delay the synchronization signal after receiving the synchronization signal, and phase control can be achieved by delaying the synchronization signal.
  • the phase offset value of frequency divider A can be set to delay the synchronization signal received by clock domain A by one cycle, so that the clock domain A will have a phase difference of one cycle with other clock domains.
  • the state machine 140 is configured to, after receiving the delayed synchronization signal, control the clock generation circuit 144 to perform the phase of the output clock if the current clock signals in the plurality of signal processing branches are in an asynchronous state. Adjustment.
  • the clock frequency dividing module 14 may further include: a counter 146 and a comparator 148 .
  • the counter 146 is configured to perform periodic counting under the control of the state machine to determine the current count value;
  • the comparator 148 is configured to compare the current count value with the maximum count threshold of the clock frequency dividing module Compare, output the status information of whether the current state is synchronous; when the current count value is consistent with the maximum count threshold, output the status information that the current state is a synchronous state; when the current count value is inconsistent with the maximum count threshold
  • the state information that the current state is an asynchronous state is output; the state machine 140 is configured to receive the state information sent by the comparator 148 .
  • clock frequency division module provided in the embodiment of the present application can be used independently, or can be used as one of the modules of the above clock management apparatus, and its specific structure and function refer to the above content, which will not be repeated here.
  • the present application also provides a system-on-chip, comprising any of the clock management apparatuses described above, and the clock signal output by the clock management apparatus is used for the same or different functional modules of the system-on-chip.
  • the clock management device, clock frequency division module, and system-on-chip provided by the present application realize controllable phase of the working clock of each clock domain, and can realize adjustment without shutting down the system, which simplifies the adjustment process and improves the performance of the system.

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Abstract

本申请公开了一种时钟管理装置、时钟分频模块以及片上***，时钟管理装置包括时钟同步信号发生器、多个时钟门控单元以及多个时钟分频模块；通过时钟同步信号发生器产生预定周期的同步信号；多个时钟门控单元的一个与多个时钟分频模块的一个串联，以构成信号处理支路；多个信号处理支路并联连接来接收源时钟信号，时钟门控单元控制信号处理支路的开关，时钟分频模块被配置为在接收到时钟同步信号发生器输出的同步信号后，对信号处理支路的时钟信号进行相位调整，将多个信号处理支路中的时钟信号由非同步状态调整为同步状态。本申请实现了对各时钟域的工作时钟相位可控，不需要关闭***即可实现调整，简化了调整过程，提升了***的性能。

Description

一种时钟管理装置、时钟分频模块以及片上*** 技术领域
本申请涉及集成电路技术领域，尤其涉及一种时钟管理装置、时钟分频模块以及片上***。
背景技术
片上***(SoC：System-on-a-chip)是指在单个芯片上集成一个完整的***，对所有或部分必要的电子电路进行包分组的技术。当前片上***芯片为了满足低功耗的要求，会将各个功能模块划分为不同的时钟域。不同的时钟域工作在不同的时钟频率，并且可以根据当前任务负载选择对某一时钟域的工作时钟频率进行调整，或者关闭不参与当前任务的模块的时钟。然而时钟的关断和频率的调整往往会导致不同时钟域时钟之间相位的偏移，使得跨时钟域信号的传输出现比较大的电路和时序上的开销，导致芯片面积增加、性能降低。
针对该情况，现有的一种调整方法为：在各个时钟进行开关或进行频率调整时，先将所有的时钟关闭，等待频率调整设定完成后再一起打开，从而达到相位一致的目的。该方法在调整过程中时钟被关闭，且过程复杂，影响了***的性能。
因此，提供一种方案以解决片上***各时钟域的工作时钟在调频或者开关之后出现的相位偏移的问题是非常有必要的。
发明内容
为解决上述问题，本申请提供了一种时钟管理装置，包括：
时钟同步信号发生器、多个时钟门控单元以及多个时钟分频模块；
其中，所述时钟同步信号发生器被配置为产生预定周期的同步信号；
所述多个时钟门控单元与所述多个时钟分频模块一一对应，所述多个时钟门控单元的一个与所述多个时钟分频模块的一个串联，以构成信号处 理支路；多个所述信号处理支路并联连接，被配置为接收源时钟信号，所述时钟门控单元被配置为控制所述信号处理支路的开关，所述时钟分频模块被配置为在接收到所述时钟同步信号发生器输出的同步信号后，对所述信号处理支路的时钟信号进行相位调整，将多个所述信号处理支路中的时钟信号由非同步状态调整为同步状态。
可选地，多个所述信号处理支路输出的时钟信号作为多个时钟域的工作时钟。
可选地，所述预定周期为所述多个时钟域的工作时钟的周期的公倍数。
可选地，所述时钟分频模块包括：状态机、同步信号延迟电路以及时钟产生电路；
其中，所述同步信号延迟电路被配置为接收到所述时钟同步信号发生器输出的同步信号后，对所述同步信号进行延迟；
所述状态机被配置为接收到延迟后的同步信号后，若当前多个所述信号处理支路中的时钟信号处于非同步状态，则控制所述时钟产生电路对输出时钟的相位进行调整。
可选地，所述时钟分频模块还包括：计数器以及比较器；
其中，所述计数器被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；
所述比较器被配置为将所述当前计数值与所述时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；
所述状态机被配置为接收所述比较器发送的状态信息；
其中，所述最大计数阈值为所述时钟分频模块的预设分频比率减一后的数值。
可选地，所述时钟分频模块还包括：被配置为存储所述最大计数阈值的分频比率寄存器。
可选地，所述预设分频比率的数值被调整时，所述分频比率寄存器中存储的最大计数阈值的数值在所述时钟信号处于同步状态且所述时钟分频模块收到所述同步信号的情况下，对所述最大计数阈值的数值进行修改。
可选地，所述状态机被配置为接收到当前状态为非同步状态的状态信息后，切换至非同步状态，控制所述时钟产生电路关闭时钟输出；在所述计数器计数到所述最大计数阈值后，所述状态机被配置为切换到相位调整状态，所述计数器记录同步信号发生时的当前计数值，作为相位偏移值；在所述计数器继续计数至所述相位偏移值时，所述状态机控制所述时钟产生电路开启时钟输出。
可选地，所述时钟产生电路采用时钟门控单元或触发器翻转实现。
可选地，在所述时钟门控单元对应的信号使能或复位时，所述状态机跳转为非同步状态。
可选地，所述同步信号延迟电路被配置为接收到所述同步信号发生器输出的同步信号后，根据预设分频时钟相位偏移值，以所述源时钟的周期为单位对所述同步信号进行延迟。
本申请还提供了一种时钟分频模块，包括：状态机、同步信号延迟电路以及时钟产生电路；
其中，所述同步信号延迟电路被配置为接收到同步信号后，对所述同步信号进行延迟；
所述状态机被配置为接收到延迟后的同步信号后，若当前时钟信号与其他时钟信号处于非同步状态，则控制所述时钟产生电路对输出时钟的相位进行调整。
可选地，还包括：计数器以及比较器；
其中，所述计数器被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；
所述比较器被配置为将所述当前计数值与所述时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所 述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；
所述状态机被配置为接收所述比较器发送的状态信息；
其中，所述最大计数阈值为所述时钟分频模块的预设分频比率减一后的数值。
本申请还提供了一种片上***，包括上述任一种所述的时钟管理装置，所述时钟管理装置输出的时钟信号用于所述片上***的相同或不同功能模块。
本申请提供的时钟管理装置、时钟分频模块以及片上***，时钟管理装置包括时钟同步信号发生器、多个时钟门控单元以及多个时钟分频模块；通过时钟同步信号发生器产生预定周期的同步信号；多个时钟门控单元与多个时钟分频模块一一对应，多个时钟门控单元的一个与多个时钟分频模块的一个串联，以构成信号处理支路；多个信号处理支路并联连接来接收源时钟信号，时钟门控单元控制信号处理支路的开关，时钟分频模块被配置为在接收到时钟同步信号发生器输出的同步信号后，对信号处理支路的时钟信号进行相位调整，将多个信号处理支路中的时钟信号由非同步状态调整为同步状态。本申请提供的时钟管理装置、时钟分频模块以及片上***，实现了对各时钟域的工作时钟相位可控，不需要关闭***即可实现调整，简化了调整过程，提升了***的性能。
附图说明
在下文中，将基于实施例参考附图进一步解释本申请。
图1示意性地示出本申请所提供的时钟管理装置的一种具体实施方式的结构框图；
图2示意性地示出本申请所提供的时钟分频模块的示意图；
图3示意性地示出时钟分频模块中状态机的状态示意图；
图4示意性地示出本申请所提供的时钟管理装置的相位调整示意图。
具体实施方式
以下将结合附图和具体的实施方式，对本申请的装置进行详细说明。应理解，附图所示以及下文所述的实施例仅仅是说明性的，而不作为对本申请的限制。
图1示出了本申请所提供的时钟管理装置的一种具体实施方式的结构框图。本实施例中，时钟管理装置1包括时钟同步信号发生器10、多个时钟门控单元12以及多个时钟分频模块14。
其中，所述时钟同步信号发生器10被配置为产生预定周期的同步信号；所述多个时钟门控单元12与所述多个时钟分频模块14一一对应，所述多个时钟门控单元12的一个与所述多个时钟分频模块14的一个串联，以构成信号处理支路；多个所述信号处理支路并联连接，被配置为接收源时钟信号，所述时钟门控单元12被配置为控制所述信号处理支路的开关，所述时钟分频模块14被配置为在接收到所述时钟同步信号发生器10输出的同步信号后，对所述信号处理支路的时钟信号进行相位调整，将多个所述信号处理支路中的时钟信号由非同步状态调整为同步状态。
可以理解的是，各个时钟域的工作时钟由源时钟经过时钟门控单元的开关控制以及时钟分频模块得到。即，多个信号处理支路输出的时钟信号作为多个时钟域的工作时钟。
其中，时钟同步信号发生器可以由源时钟驱动计数器构成，可以按照软件配置产生预定周期的脉冲同步信号，可以作为全片时钟的统一的参照物。预定周期可以为多个时钟域的工作时钟的周期的公倍数。可以理解的是，各个时钟域的工作时钟的周期是可调节的。
本申请提供的时钟管理装置，实现了对各时钟域的工作时钟相位可控，不需要关闭***即可实现调整，简化了调整过程，提升了***的性能。
作为一种具体实施方式，本申请所提供的时钟分频模块14可以包括：状态机140、同步信号延迟电路142以及时钟产生电路144。如图2本申请所提供的时钟分频模块的示意图所示。其中，所述同步信号延迟电路142被 配置为接收到所述同步信号发生器10输出的同步信号后，对所述同步信号进行延迟；所述状态机140被配置为接收到延迟后的同步信号后，若当前多个所述信号处理支路中的时钟信号处于非同步状态，则控制所述时钟产生电路144对输出时钟的相位进行调整。
进一步地，本申请所提供的时钟分频模块14还可以包括：计数器146以及比较器148。其中，所述计数器146被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；所述比较器148被配置为将所述当前计数值与所述时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；所述状态机140被配置为接收所述比较器148发送的状态信息。其中，最大计数阈值为时钟分频模块的预设分频比率减一后的数值。例如，对于工作时钟为五分频的时钟，其对应的预设分频比率为5，则最大计数阈值为5-1＝4。
其中，时钟分频模块还可以进一步包括：分频比率寄存器150，用于存储上述最大计数阈值。预设分频比率的数值可以根据实际进行设置。作为一种具体实施方式，预设分频比率的数值被调整时，所述分频比率寄存器中存储的最大计数阈值的数值在所述时钟信号处于同步状态且所述时钟分频模块收到所述同步信号的情况下，对所述最大计数阈值的数值进行修改。当分频器分频比率调整时，新的分频系数须在分频器处于同步状态且收到同步信号时，才会更新分频比率寄存器中存储的最大计数阈值。
其中，状态机140可以为有限状态机，其被配置为对时钟分频模块进行控制。计数器146根据预设分频比率进行周期性计数，确定出当前计数值。比较器将当前计数值与最大计数阈值进行比较，以判断当前状态为同步状态或非同步状态。在当前计数值与最大计数阈值一致时，当前状态为同步状态。在当前计数值与最大计数阈值不一致时，当前状态为非同步状态。状态机140根据比较器得到的状态信息，控制时钟产生电路144对输出时钟的相位进行调整。
状态机被配置为接收到当前状态为非同步状态的状态信息后，切换至非同步状态，控制所述时钟产生电路关闭时钟输出；在所述计数器计数到所述最大计数阈值后，所述状态机被配置为切换到相位调整状态，所述计数器记录同步信号发生时的当前计数值，作为相位偏移值；在所述计数器继续计数至所述相位偏移值时，所述状态机控制所述时钟产生电路开启时钟输出。时钟产生电路可以采用时钟门控单元实现，也可以采用触发器翻转实现。这均不影响本申请的实现。
参照图3时钟分频模块中状态机的状态示意图，如图3所示，时钟分频模块中状态机的状态包括同步状态、非同步状态以及相位调整状态。在所述时钟门控单元对应的信号使能或复位时，状态机的状态跳转为非同步状态。时钟分频模块接收到同步信号并且计数器计数达到最大计数阈值时，状态机的状态跳转为同步状态。非同步状态经过相位调整，状态机的状态跳转为同步状态。
具体地，当芯片复位或者时钟关闭时，状态机处于非同步状态。当收到同步信号发生器输出的同步信号后，同步信号延迟电路会对同步信号进行延迟。比较器根据当前计数器的计数值判断当前是否为同步状态。如果判定为同步状态则状态机转为同步状态。如果为非同步状态，则计数器记录当前计数值作为相位偏移值，并进入相位调整状态。计数器的计数限调整为相位偏移值，待相位调整完成后，状态机进入同步状态。
参照图4本申请所提供的时钟管理装置的相位调整示意图，工作时钟A和工作时钟B皆为源时钟的五分频，且相位有偏差。经过同步信号校准后，实现了相位同步。如图4所示，最初工作时钟A与工作时钟B均五分频的周期信号，其对应计数器从0计数到4为一个周期，在计数器计数为0时对应信号上升沿，在计数器计数为3时对应信号下降沿。可以看出工作时钟A与工作时钟B存在相位偏差，对应的预设分频比率均为5，最大计数阈值均为4。
如图4所示，时钟分频模块在接收到同步信号后，对于分频器A，通过计数器记录的当前计数值为3，通过比较器比较当前计数值与最大计数阈值 4是否一致。而对于分频器B，通过计数器记录的当前计数值为2，通过比较器比较当前计数值与最大计数阈值4是否一致。在本实施例中是不一致的，则判定当前状态为非同步状态。
在判定当前状态为非同步状态后，状态机由同步状态切换为非同步状态，并且关闭时钟输出。参照图4，工作时钟A与工作时钟B对应的时钟信号输出为0。在计数器这一轮计数完成，即计数达到最大计数阈值4后，状态机切换为相位调整状态。计数器记录同步信号发生时的当前计数值，作为相位偏移值。在本实施例中，对于分频器A，在同步信号发生时分频器A对应的当前计数值为3，则相位偏移值为3。分频器A计数器在上一轮从0计数到最大值4之后，按照相位偏移值为3进行相位调整，即在下一轮继续从0计数到3。对于分频器B，在同步信号发生时分频器B对应的当前计数值为2，则相位偏移值为2。分频器B计数器在上一轮从0计数到最大值4之后，按照相位偏移值为2进行相位调整，即在下一轮继续从0计数到2。在分频器A以及分频器B的计数器计数到各自的相位偏移值后，状态机切换至同步状态，此时再打开时钟输出，此时输出的工作时钟A与工作时钟B即可实现同步。
同步信号延迟电路被配置为接收到所述同步信号发生器输出的同步信号后，根据预设分频时钟相位偏移值，以所述源时钟的周期为单位对所述同步信号进行延迟。本申请中通过对同步信号进行延迟以实现相位可控。例如若第一时钟域的时钟与第二时钟域的时钟之间存在一个相位差，则将第一时钟域收到的同步信号延迟一个周期，这样时钟分频模块再跟延迟后的同步信号保持同步的话，则第一时钟域输出的时钟与第二时钟域也相差一个周期的相位差。
此外，本申请还提供了一种时钟分频模块。参照图2所示，本申请所提供的时钟分频模块14可以包括：状态机140、同步信号延迟电路142以及时钟产生电路144。如图2本申请所提供的时钟分频模块的示意图所示。其中，所述同步信号延迟电路142被配置为接收到同步信号后，对所述同步信 号进行延迟，通过延迟同步信号可以实现实现相位可控。例如，如果本领域技术人员希望时钟域A的时钟信号跟别的时钟域相比有一个相位差，则可以设置分频器A的相位偏移值，将时钟域A收到的同步信号延迟一个周期，从而时钟域A就会和别的时钟域存在一个周期的相位差了。所述状态机140被配置为接收到延迟后的同步信号后，若当前多个所述信号处理支路中的时钟信号处于非同步状态，则控制所述时钟产生电路144对输出时钟的相位进行调整。
进一步地，本申请所提供的时钟分频模块14还可以包括：计数器146以及比较器148。其中，所述计数器146被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；所述比较器148被配置为将所述当前计数值与时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；所述状态机140被配置为接收所述比较器148发送的状态信息。
可以理解的是，本申请实施例所提供的时钟分频模块可以独立使用，也可以作为上述时钟管理装置的其中一个模块，其具体结构和功能参照上述内容，在此不再赘述。
此外，本申请还提供了一种片上***，包括上述任一种所述的时钟管理装置，该时钟管理装置输出的时钟信号用于片上***的相同或不同功能模块。
本申请提供的时钟管理装置、时钟分频模块以及片上***，实现了对各时钟域的工作时钟相位可控，不需要关闭***即可实现调整，简化了调整过程，提升了***的性能。
虽然出于本公开的目的已经描述了本申请各方面的各种实施例，但是不应理解为将本公开的教导限制于这些实施例。在一个具体实施例中公开的特征并不限于该实施例，而是可以和不同实施例中公开的特征进行组合。例如， 在一个实施例中描述的根据本申请的方法的一个或多个特征和/或操作，亦可单独地、组合地或整体地应用在另一实施例中。本领域技术人员应理解，还存在可能的更多可选实施方式和变型，可以对上述***进行各种改变和修改，而不脱离由本申请权利要求所限定的范围。

Claims (14)

  1. 一种时钟管理装置，其特征在于，包括：
    时钟同步信号发生器、多个时钟门控单元以及多个时钟分频模块；
    其中，所述时钟同步信号发生器被配置为产生预定周期的同步信号；
    所述多个时钟门控单元与所述多个时钟分频模块一一对应，所述多个时钟门控单元的一个与所述多个时钟分频模块的一个串联，以构成信号处理支路；多个所述信号处理支路并联连接，被配置为接收源时钟信号，所述时钟门控单元被配置为控制所述信号处理支路的开关，所述时钟分频模块被配置为在接收到所述时钟同步信号发生器输出的同步信号后，对所述信号处理支路的时钟信号进行相位调整，将多个所述信号处理支路中的时钟信号由非同步状态调整为同步状态。
  2. 根据权利要求1所述的时钟管理装置，其特征在于，多个所述信号处理支路输出的时钟信号作为多个时钟域的工作时钟。
  3. 根据权利要求2所述的时钟管理装置，其特征在于，所述预定周期为所述多个时钟域的工作时钟的周期的公倍数。
  4. 根据权利要求1至3任一项所述的时钟管理装置，其特征在于，所述时钟分频模块包括：状态机、同步信号延迟电路以及时钟产生电路；
    其中，所述同步信号延迟电路被配置为接收到所述时钟同步信号发生器输出的同步信号后，对所述同步信号进行延迟；
    所述状态机被配置为接收到延迟后的同步信号后，若当前多个所述信号处理支路中的时钟信号处于非同步状态，则控制所述时钟产生电路对输出时钟的相位进行调整。
  5. 根据权利要求4所述的时钟管理装置，其特征在于，所述时钟分频模块还包括：计数器以及比较器；
    其中，所述计数器被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；
    所述比较器被配置为将所述当前计数值与所述时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所 述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；
    所述状态机被配置为接收所述比较器发送的状态信息；
    其中，所述最大计数阈值为所述时钟分频模块的预设分频比率减一后的数值。
  6. 根据权利要求5所述的时钟管理装置，其特征在于，所述时钟分频模块还包括：被配置为存储所述最大计数阈值的分频比率寄存器。
  7. 根据权利要求6所述的时钟管理装置，其特征在于，所述预设分频比率的数值被调整时，所述分频比率寄存器中存储的最大计数阈值的数值在所述时钟信号处于同步状态且所述时钟分频模块收到所述同步信号的情况下，对所述最大计数阈值的数值进行修改。
  8. 根据权利要求5所述的时钟管理装置，其特征在于，所述状态机被配置为接收到当前状态为非同步状态的状态信息后，切换至非同步状态，控制所述时钟产生电路关闭时钟输出；在所述计数器计数到所述最大计数阈值后，所述状态机被配置为切换到相位调整状态，所述计数器记录同步信号发生时的当前计数值，作为相位偏移值；在所述计数器继续计数至所述相位偏移值时，所述状态机控制所述时钟产生电路开启时钟输出。
  9. 根据权利要求8所述的时钟管理装置，其特征在于，所述时钟产生电路采用时钟门控单元或触发器翻转实现。
  10. 根据权利要求4所述的时钟管理装置，其特征在于，在所述时钟门控单元对应的信号使能或复位时，所述状态机跳转为非同步状态。
  11. 根据权利要求4所述的时钟管理装置，其特征在于，所述同步信号延迟电路被配置为接收到所述同步信号发生器输出的同步信号后，根据预设分频时钟相位偏移值，以所述源时钟的周期为单位对所述同步信号进行延迟。
  12. 一种时钟分频模块，其特征在于，包括：状态机、同步信号延迟电路以及时钟产生电路；
    其中，所述同步信号延迟电路被配置为接收到同步信号后，对所述同步信号进行延迟；
    所述状态机被配置为接收到延迟后的同步信号后，若当前时钟信号与其他时钟信号处于非同步状态，则控制所述时钟产生电路对输出时钟的相位进行调整。
  13. 如权利要求12所述的时钟分频模块，其特征在于，还包括：计数器以及比较器；
    其中，所述计数器被配置为在所述状态机的控制下进行周期性计数，确定当前计数值；
    所述比较器被配置为将所述当前计数值与所述时钟分频模块的最大计数阈值进行比较，输出当前状态是否同步的状态信息；在所述当前计数值与所述最大计数阈值一致时，输出当前状态为同步状态的状态信息；在所述当前计数值与所述最大计数阈值不一致时，输出当前状态为非同步状态的状态信息；
    所述状态机被配置为接收所述比较器发送的状态信息；
    其中，所述最大计数阈值为所述时钟分频模块的预设分频比率减一后的数值。
  14. 一种片上***，其特征在于，包括如权利要求1至11任一项所述的时钟管理装置，所述时钟管理装置输出的时钟信号用于所述片上***的相同或不同功能模块。
PCT/CN2021/143716 2021-02-25 2021-12-31 一种时钟管理装置、时钟分频模块以及片上*** WO2022179309A1 (zh)

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