WO2022141705A1 - 显示面板、阵列基板及其制备方法 - Google Patents

显示面板、阵列基板及其制备方法 Download PDF

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Publication number
WO2022141705A1
WO2022141705A1 PCT/CN2021/073766 CN2021073766W WO2022141705A1 WO 2022141705 A1 WO2022141705 A1 WO 2022141705A1 CN 2021073766 W CN2021073766 W CN 2021073766W WO 2022141705 A1 WO2022141705 A1 WO 2022141705A1
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Prior art keywords
layer
insulating
array substrate
film transistor
thin film
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PCT/CN2021/073766
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English (en)
French (fr)
Inventor
戴星强
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/263,951 priority Critical patent/US11869901B2/en
Publication of WO2022141705A1 publication Critical patent/WO2022141705A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, an array substrate and a preparation method thereof.
  • the display panel may include a liquid crystal display panel and/or an organic light emitting display panel.
  • a display panel includes an array substrate and a color filter substrate disposed opposite to the array substrate.
  • the array substrate includes a substrate and a thin film transistor layer disposed on the substrate, and the thin film transistor layer has a plurality of thin film transistors.
  • an encapsulation structure is provided outside the thin film transistor layer, and the encapsulation structure is usually an inorganic layer (such as SiO 2 ) to simply protect the thin film transistor.
  • the package structure is too simple, once it is subjected to mechanical impact or repeated water and oxygen erosion, it will be easily damaged, thereby damaging the thin film transistor and affecting the yield of the array substrate.
  • the purpose of the present invention is to provide a display panel, an array substrate and a preparation method thereof, so as to solve the technical problem that the existing thin film transistor layer has poor water and oxygen barrier capability.
  • the present invention provides an array substrate, which includes: a substrate; a thin film transistor layer, disposed on the substrate; an insulating nanoparticle layer, disposed on the substrate and covering the thin film transistor layer; and an organic
  • the polymer layer is stacked and disposed on the side of the insulating nanoparticle layer away from the thin film transistor layer, and covers the insulating nanoparticle layer.
  • the material used in the organic polymer layer is a polystyrene derivative
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl structure connected to the polystyrene main chain structure
  • the The insulating nanoparticle layer is an oxide nanoparticle, and a hydrogen bond is formed between the carboxyl structure and the oxide nanoparticle.
  • the array substrate further includes: an inorganic layer disposed on the side of the thin film transistor layer away from the insulating nanoparticle layer.
  • the insulating nanoparticle layer is made of the same material as the inorganic layer.
  • both the insulating nanoparticle layer and the inorganic layer are made of SiO 2 , and the SiO 2 nanoparticles in the insulating nano particle layer and the SiO 2 in the inorganic layer form a silicon-oxygen bond.
  • the materials used for the insulating nanoparticle layer and the inorganic layer are both silicon oxide or zeolite.
  • the nanoparticle size of the insulating nanoparticle layer is 20nm-80nm.
  • the present invention also provides a method for preparing an array substrate, which includes the following steps: providing a substrate; forming a thin film transistor layer on the substrate; providing a mixed solution to obtain the following components: insulating nanoparticles , organic polymer and solvent; apply the mixed solution on the substrate and the thin film transistor layer to form an uncured mixed film layer; heat and anneal the uncured mixed film layer to form a cured an insulating nanoparticle layer and an organic polymer layer, the insulating nanoparticle layer is disposed on the substrate and covers the thin film transistor layer, the organic polymer layer is laminated and disposed on the insulating nanoparticle layer away from the thin film transistor one side of the layer and cover the insulating nanoparticle layer.
  • the step of heating and annealing the uncured mixed film layer includes: heating the uncured mixed film layer to a molten state, and cooling the molten state of the mixed film layer to form a layered phase separation protection layer, the layered phase separation protective layer includes an insulating nanoparticle layer and an organic polymer layer.
  • the material used in the organic polymer layer is a polystyrene derivative
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl structure connected to the polystyrene main chain structure
  • the The insulating nanoparticle layer is an oxide nanoparticle
  • the step of cooling the mixed film layer in a molten state to form a layered phase separation protective layer includes: forming a hydrogen bond between the carboxyl structure and the oxide nanoparticle .
  • the insulating nanoparticles, the organic polymer and the solvent are obtained according to a volume ratio of (0.9-1.1):(0.9-1.1):(0.7-1.2).
  • the present invention also provides a display panel, which includes the aforementioned array substrate; and a color filter substrate, which is disposed opposite to the array substrate.
  • the material used in the organic polymer layer is a polystyrene derivative
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl structure connected to the polystyrene main chain structure
  • the The insulating nanoparticle layer is an oxide nanoparticle, and a hydrogen bond is formed between the carboxyl structure and the oxide nanoparticle.
  • the array substrate further includes: an inorganic layer disposed on the side of the thin film transistor layer away from the insulating nanoparticle layer.
  • the insulating nanoparticle layer is made of the same material as the inorganic layer.
  • both the insulating nanoparticle layer and the inorganic layer are made of SiO 2 , and the SiO 2 nanoparticles in the insulating nano particle layer and the SiO 2 in the inorganic layer form a silicon-oxygen bond.
  • the materials used for the insulating nanoparticle layer and the inorganic layer are both silicon oxide or zeolite.
  • the nanoparticle size of the insulating nanoparticle layer is 20nm-80nm.
  • the technical effect of the present invention is to provide a display panel, an array substrate and a preparation method thereof.
  • the array substrate includes a substrate, a thin film transistor layer, an insulating nanoparticle layer and an organic polymer layer.
  • the thin film transistor layer is arranged on the substrate; the insulating nanoparticle layer is arranged on the substrate and covers the thin film transistor layer; the organic polymer layer is stacked and arranged on the side of the insulating nanoparticle layer away from the thin film transistor layer and covers the insulating nanoparticle layer.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a flowchart of a method for preparing an array substrate provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of the formation of a layered phase separation protective layer provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • This embodiment provides an array substrate 100 including a substrate 10 , a thin film transistor layer 20 , an inorganic layer 40 and a layered phase separation protective layer 30 .
  • the substrate 10 may be a glass substrate, a PI substrate, a ceramic substrate, or the like.
  • the thin film transistor layer 20 is disposed on the substrate 10 .
  • the thin film transistor layer 20 includes an active layer, a gate insulating layer, a gate layer, a passivation layer, and a source and drain layer.
  • the gate layer is arranged on the substrate; the gate insulating layer is arranged on the gate layer and the substrate, and covers the gate layer; the active layer is arranged on the on the gate insulating layer and facing the gate layer; the passivation layer is provided on the active layer and the gate insulating layer and covers the gate insulating layer; the source and drain A layer is connected to the upper surface of the active layer through the passivation layer and the gate insulating layer.
  • An inorganic layer 40 is disposed on the thin film transistor layer 20 and covers the thin film transistor layer 20 .
  • the inorganic layer 40 is disposed on the source and drain layers and the passivation layer to protect the thin film transistor and prevent the thin film transistor from being corroded by water and oxygen.
  • the second passivation layer and the flat layer, as long as the film layer is made of inorganic materials, are not particularly limited here.
  • the layered phase separation protective layer 30 is disposed on the thin film transistor layer 20 .
  • the layered phase separation protective layer 30 includes an insulating nanoparticle layer 301 and an organic polymer layer 302 which are arranged in layers.
  • the insulating nanoparticle layer 301 is disposed on the substrate 10 and covers the thin film transistor layer 20 , in other words, the insulating nanoparticle layer 301 is closely attached to and wrapping on the thin film
  • the inorganic layer 40 on the outer side of the transistor layer 20 makes the inorganic layer 40 closely adhere to the insulating nanoparticle layer 301 .
  • the insulating nanoparticle layer 301 and the inorganic layer 40 are made of the same material, and the insulating nanoparticle layer 301 and the inorganic layer 40 are both made of silicon oxide (such as SiO 2 , etc.) or zeolite , the nanoparticle size of the insulating nanoparticle layer 301 is 20nm-80nm.
  • both the insulating nanoparticle layer and the inorganic layer 40 are made of SiO 2
  • the SiO 2 nanoparticles in the insulating nano particle layer and the SiO 2 in the inorganic layer 40 form a silicon-oxygen bond, which is beneficial to Improve the compactness between film layers.
  • the materials used for the insulating nanoparticle layer and the inorganic layer are other kinds of raw materials
  • other kinds of chemical bonds may also be formed between the insulating nanoparticle layer and the inorganic layer , in order to improve the compactness between the film layers.
  • the organic polymer layer 302 is stacked on a side of the insulating nanoparticle layer 301 away from the thin film transistor layer 20 and covers the insulating nanoparticle layer 301 .
  • a chemical bond is formed between the insulating nanoparticle layer 301 and the organic polymer layer 302 , which can improve the density between the insulating nanoparticle layer 301 and the organic polymer layer 302 , thereby facilitating the improvement of the The performance of the array substrate 100 to block water and oxygen.
  • the material used for the organic polymer layer 302 is a polystyrene derivative
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl group connected to the polystyrene main chain structure
  • the insulating nanoparticle layer is an oxide nanoparticle (such as an oxygen-containing compound such as SiO 2 ), so that a hydrogen bond can be formed between the carboxyl structure and the oxide nanoparticle.
  • the molecular weight of the polystyrene derivative is controlled above 10,000, and at least one end of the polystyrene derivative is connected with a carboxyl structure, which can be used to strengthen the gap between the insulating nanoparticle layer 301 and the organic polymer layer 302 the interaction strength.
  • the organic polymer layer 302 can also use other kinds of polymers
  • the insulating nanoparticle layer 301 can also use other kinds of compounds, as long as the organic polymer layer 302 and the insulating nanoparticle layer can be formed between the organic polymer layer 302 and the insulating nanoparticle. It is sufficient to form chemical bonds between the particle layers 301 , and the present application does not specifically limit the types of chemical bonds.
  • the layered phase separation protective layer 30 is a dense bifunctional layered phase obtained by a phase separation method under thermodynamic control, that is, a layered insulating nanoparticle layer 301 and an organic polymer layer 302, Since its phase separation is the result of thermodynamic control, and through the addition of auxiliary chemical modification means, a more stable encapsulation structure can be formed outside the thin film transistor layer 20 . Since the formed layered phase separation protective layer 30 is finally in a thermodynamically stable state, the thin film transistor layer 20 is very stable and not easily damaged, which ensures the stability of the thin film transistor device and improves the array substrate. 100% of the performance of isolating water and oxygen.
  • This embodiment provides an array substrate 100, which includes the thin film transistor layer 20 and the layered phase separation protective layer 30, and the layered phase separation protective layer 30 includes the insulating nanoparticle layer 301 and the organic
  • the polymer layer 302 the insulating nanoparticle layer 301 forms a silicon-oxygen bond with the inorganic layer 40 outside the thin film transistor layer 20, so that the insulating nanoparticle layer 301 and the inorganic layer 40 are closely attached together
  • the insulating nanoparticle layer 301 also forms hydrogen bonds with the organic polymer layer 302, so that the insulating nanoparticle layer 301 and the organic polymer layer 302 are closely attached together, thereby making the thin film transistor layer 20 is in close contact with the layered phase separation protective layer 30 layer by layer, which is beneficial to improve the compact performance of the entire package structure of the array substrate 100 and effectively block the intrusion of water and oxygen from the outside.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • This embodiment provides a method for preparing an array substrate, including the following steps S1)-S5).
  • the substrate 10 may be a glass substrate, a PI substrate or a ceramic substrate, etc.
  • the thin film transistor layer 20 includes an active layer, a gate insulating layer, a gate layer, a passivation layer, and a source and drain layer.
  • the gate layer is arranged on the substrate; the gate insulating layer is arranged on the gate layer and the substrate, and covers the gate layer; the active layer is arranged on the on the gate insulating layer and facing the gate layer; the passivation layer is provided on the active layer and the gate insulating layer and covers the gate insulating layer; the source and drain A layer is connected to the upper surface of the active layer through the passivation layer and the gate insulating layer.
  • An inorganic layer 40 is disposed on the thin film transistor layer 20 .
  • the inorganic layer 40 is disposed on the source and drain layers and the passivation layer to protect the thin film transistor and prevent the thin film transistor from being corroded by water and oxygen.
  • the second passivation layer and the flat layer, as long as the film layer is made of inorganic materials, are not particularly limited here.
  • the following components of insulating nanoparticles, organic polymers and solvents are obtained.
  • the volume ratio of insulating nanoparticles:organic polymer:solvent is 1:1:1.
  • the insulating nanoparticles are oxide nanoparticles, which include silicon oxide (such as SiO 2 ) or zeolite, the size of the insulating nanoparticles is 20nm-80nm, and the organic polymer is a polystyrene derivative, so
  • the solvent includes n-hexane and/or dichloromethane.
  • the material used in the organic polymer layer is a polystyrene derivative
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl structure connected to the polystyrene main chain structure.
  • the insulating nanoparticle layer is oxide nanoparticles; heating the uncured hybrid film layer to a molten state, and cooling the molten hybrid film layer to form hydrogen between the carboxyl structure and the oxide nanoparticles key.
  • the polystyrene derivative includes a polystyrene main chain structure and a carboxyl structure connected to the polystyrene main chain structure (for example, the end of the polystyrene main chain structure),
  • a carboxyl structure connected to the polystyrene main chain structure (for example, the end of the polystyrene main chain structure)
  • the polystyrene derivative is heated to 98°C-110°C
  • hydrogen bonds are formed between the carboxyl structure and the insulating nanoparticle layer.
  • the heating and annealing temperature is greater than or equal to 180° C., the solvent is volatilized, and the layered phase-separation protective layer forms two stacked insulating nanoparticle layers and organic polymer layers.
  • the above-mentioned "heating annealing treatment” process actually activates each component in a disordered uncured mixed film layer (including insulating nanoparticles and organic polymers), that is, the The SiO 2 particles in the insulating nanoparticle layer and the polymer chains of the polystyrene derivatives in the organic polymer layer move to recombine.
  • the SiO 2 particles in the components may not move well, but they can
  • the polymer chain of the polystyrene derivative is moved to further induce the formation of a layered phase, and the polymer chain of the polystyrene derivative only needs to be heated to a temperature above the melting temperature.
  • the melting temperature of the polystyrene derivative is 100°C. Therefore, when the melting temperature of the polystyrene derivative is 100° C. or higher, the polymer chain of the polystyrene derivative can be reorganized.
  • the molecular weight of the polystyrene derivative is controlled to be above 10,000, and a carboxyl group is attached to the end thereof, so as to enhance the interaction strength between the insulating nanoparticle and the polystyrene derivative.
  • FIG. 3 is a schematic structural diagram of the formation of the layered phase separation protective layer provided in the embodiment of the present application.
  • the polystyrene derivative forms the dense organic polymer layer 302 , and the organic polymer layer 302 forms a very good hydrophobic protective layer, which plays a good role in The effect of blocking water and oxygen. Since the carboxyl group (-COOH) at the end of the polystyrene derivative will form a hydrogen bond with the oxygen in the oxidized nanoparticles (such as SiO 2 ) in the insulating nanoparticle layer 301 , the organic polymer layer is increased. 302 and the bonding strength of the insulating nanoparticle layer 301.
  • the insulating nanoparticle layer 301 itself is formed with abundant silicon-oxygen bonds (Si-O) and will be closely arranged with each other. 20
  • the outermost inorganic layer 40 is in close contact, and the formed silicon-oxygen bond (Si-O) is further closely attached to the outermost inorganic layer 40 of the thin film transistor layer 20, so that the thin film transistor layer 20 is
  • the packaging structures are closely connected layer by layer, and have good densification performance, thereby improving the water and oxygen barrier performance of the array substrate 100 .
  • the insulating nanoparticle layer 301 is disposed on the substrate 10 and covers the thin film transistor layer 20 .
  • the insulating nanoparticle layer 301 is closely attached and The outermost inorganic layer 40 of the thin film transistor layer 20 is wrapped, so that the inorganic layer 40 is closely attached to the insulating nanoparticle layer 301 .
  • the insulating nanoparticle layer 301 and the inorganic layer 40 use the same material, and the insulating nanoparticle layer 301 and the inorganic layer 40 use both silicon oxide (eg, SiO 2 ) or zeolite.
  • silicon oxide eg, SiO 2
  • zeolite e.g., zeolite
  • the material used for the organic polymer layer 302 is a polystyrene derivative.
  • the polystyrene derivative reaches the melting temperature, the polymer chain of the polystyrene derivative is induced to form a layered shape. phase, the oxide nanoparticles (such as SiO 2 ) in the insulating nanoparticle layer 301 form hydrogen bonds with the carboxyl groups in the polystyrene derivative, so that the insulating nanoparticle layer and the organic polymer The layers fit tightly together.
  • the molecular weight of the polystyrene derivative is controlled above 10,000, and at least one end of the polystyrene derivative is connected with a carboxyl structure, which can be used to enhance the interaction strength between the insulating nanoparticle layer 301 and the organic polymer layer 302 .
  • the layered phase separation protective layer 30 is a dense bifunctional layered phase obtained by a phase separation method under thermodynamic control, that is, a layered insulating nanoparticle layer 301 and an organic polymer layer 302, Since its phase separation is the result of thermodynamic control, and through the addition of auxiliary chemical modification means, the thin film transistor layer 20 can have a more stable structure. Since the formed layered phase separation protective layer 30 is finally in a thermodynamically stable state, the thin film transistor layer 20 is very stable and not easily damaged, which ensures the stability of the thin film transistor device and improves the array substrate. 100% of the performance of isolating water and oxygen.
  • the oxide nanoparticles (such as SiO 2 ) are introduced, on the one hand, to further compensate the inorganic layer 40 (such as SiO 2 ) on the outside of the thin film transistor layer 20 2 , etc.)
  • the oxide nanoparticles and organic polymers are blended and heated and annealed to form the layered phase separation protective layer 30, the oxide nanoparticles are increased.
  • the bonding strength between the particles and the organic polymer improves the compactness between the film layers; on the other hand, the oxide nanoparticles themselves form abundant silicon-oxygen bonds (Si-O), which will be closely arranged with each other, After heating and annealing, it will be closely arranged into a regular layer, and will be in close contact with the inorganic layer 40 outside the thin film transistor layer 20, and the formed silicon-oxygen bond (Si-O) is further attached to the thin film transistor layer. layer 20, so that the thin film transistor layer 20 and the layered phase separation protective layer 30 are in close contact layer by layer, which is beneficial to improve the compact performance of the entire packaging structure of the array substrate 100, thereby effectively blocking the intrusion of water and oxygen from the outside. .
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • This embodiment also provides a display panel 1000 , including the array substrate 100 and the color filter substrate 200 described above, the array substrate 100 and the color filter substrate 200 being disposed opposite to each other.
  • the technical effect of the present invention is to provide a display panel, an array substrate and a preparation method thereof.
  • the array substrate includes a substrate, a thin film transistor layer, an insulating nanoparticle layer and an organic polymer layer.
  • the thin film transistor layer is arranged on the substrate; the insulating nanoparticle layer is arranged on the substrate and covers the thin film transistor layer; the organic polymer layer is stacked and arranged on the side of the insulating nanoparticle layer away from the thin film transistor layer and covers the insulating nanoparticle layer.
  • a display panel, an array substrate and a manufacturing method thereof provided by the embodiments of the present application have been described in detail above.
  • the principles and implementations of the present application are described with specific examples.
  • the descriptions of the above embodiments are only for the purpose of Help to understand the technical solution of the present application and its core idea; those of ordinary skill in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications Or alternatively, the essence of the corresponding technical solution does not deviate from the scope of the technical solutions of the embodiments of the present application.

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

一种显示面板（1000）、阵列基板（100）及其制备方法，所述阵列基板（100）包括基板（10）、薄膜晶体管层（20）、绝缘纳米颗粒层（301）以及有机聚合物层（302）。薄膜晶体管层（20）设于基板（10）上；绝缘纳米颗粒层（301）设于基板（10）上且覆盖薄膜晶体管层（20）；有机聚合物层（302）层叠设置于绝缘纳米颗粒层（301）远离薄膜晶体管层（20）的一侧，且覆盖绝缘纳米颗粒层（301）。

Description

显示面板、阵列基板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、阵列基板及其制备方法。
 背景技术
通常，电子用品(例如监视器、TV、膝上型计算机和数码相机)包括用于实现图像的显示面板。例如，显示面板可以包括液晶显示面板和/或有机发光显示面板。
一般来说，显示面板包括阵列基板和与所述阵列基板相对设置的彩膜基板。所述阵列基板包括基板以及设于所述基板上的薄膜晶体管层，所述薄膜晶体管层具有多个薄膜晶体管。为了提升薄膜晶体管的器件性能，会在所述薄膜晶体管层外部设置封装结构，该封装结构通常为无机层（如SiO 2），对所述薄膜晶体管进行简单的保护。然而，由于该封装结构过于简单，一旦受到机械冲击或者反复的水氧侵蚀很容易就会破坏，进而损坏所述薄膜晶体管，影响所述阵列基板的良率。
技术问题
本发明的目的在于，提供一种显示面板、阵列基板及其制备方法，以解决现有薄膜晶体管层阻隔水氧能力较差的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，其包括：基板；薄膜晶体管层，设于所述基板上； 绝缘纳米颗粒层，设于所述基板上且覆盖所述薄膜晶体管层；以及有机聚合物层，层叠设置于所述绝缘纳米颗粒层远离所述薄膜晶体管层的一侧，且覆盖所述绝缘纳米颗粒层。
进一步地，所述绝缘纳米颗粒层与所述有机聚合物层之间形成有化学键。
进一步地，所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒，所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
进一步地，所述的阵列基板还包括：一无机层，设于所述薄膜晶体管层背离所述绝缘纳米颗粒层的一侧。
进一步地，所述绝缘纳米颗粒层与所述无机层所用材料相同。
进一步地，所述绝缘纳米颗粒层和所述无机层所用材料均为SiO 2，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层中的SiO 2形成硅氧键。
进一步地，所述绝缘纳米颗粒层与所述无机层所用材料均为氧化硅或者沸石。
进一步地，所述绝缘纳米颗粒层的纳米颗粒尺寸为20nm-80nm。
为实现上述目的，本发明还提供一种阵列基板的制备方法，其包括如下步骤：提供一基板；形成一薄膜晶体管层于所述基板上；提供一混合溶液，获取以下组分：绝缘纳米颗粒、有机聚合物以及溶剂；涂布所述混合溶液于所述基板和所述薄膜晶体管层上，形成未固化的混合膜层；对所述未固化的混合膜层进行加热退火处理，形成固化的绝缘纳米颗粒层以及有机聚合物层，所述绝缘纳米颗粒层设于所述基板上且覆盖所述薄膜晶体管层，所述有机聚合物层层叠设置于所述绝缘纳米颗粒层远离所述薄膜晶体管层的一侧，且覆盖所述绝缘纳米颗粒层。
进一步地，对所述未固化的混合膜层进行加热退火处理的步骤包括：加热所述未固化的混合膜层至熔融状态，并冷却所述熔融状态的混合膜层以形成层状相分离保护层，所述层状相分离保护层包括绝缘纳米颗粒层以及有机聚合物层。
进一步地，所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒；所述冷却所述熔融状态的混合膜层以形成层状相分离保护层的步骤包括：在所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
进一步地，在提供一混合溶液的步骤中，按照体积比为（0.9-1.1）:（0.9-1.1）:（0.7-1.2）获取所述绝缘纳米颗粒、所述有机聚合物以及所述溶剂。
为实现上述目的，本发明还提供一种显示面板，其包括前文所述的阵列基板；以及彩膜基板，与所述阵列基板相对设置。
进一步地，所述绝缘纳米颗粒层与所述有机聚合物层之间形成有化学键。
进一步地，所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒，所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
进一步地，所述阵列基板还包括：一无机层，设于所述薄膜晶体管层背离所述绝缘纳米颗粒层的一侧。
进一步地，所述绝缘纳米颗粒层与所述无机层所用材料相同。
进一步地，所述绝缘纳米颗粒层和所述无机层所用材料均为SiO 2，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层中的SiO 2形成硅氧键。
进一步地，所述绝缘纳米颗粒层与所述无机层所用材料均为氧化硅或者沸石。
进一步地，所述绝缘纳米颗粒层的纳米颗粒尺寸为20nm-80nm。
 有益效果
本发明的技术效果在于，提供一种显示面板、阵列基板及其制备方法，阵列基板包括基板、薄膜晶体管层、绝缘纳米颗粒层以及有机聚合物层。薄膜晶体管层设于基板上；绝缘纳米颗粒层设于基板上且覆盖薄膜晶体管层；有机聚合物层层叠设置于绝缘纳米颗粒层远离薄膜晶体管层的一侧，且覆盖绝缘纳米颗粒层。本申请通过在所述薄膜晶体管层上形成层叠设置的绝缘纳米颗粒层和有机聚合物层，有利于提升整个阵列基板的致密性能，有效阻隔外界的水氧入侵，并有利于提高显示面板的使用寿命。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的阵列基板的结构示意图；
图2为本申请实施例提供的阵列基板的制备方法的流程图；
图3为本申请实施例提供的层状相分离保护层形成的结构示意图；
图4为本申请实施例提供的显示面板的结构示意图。
附图部件标识如下：
100阵列基板；             10基板；
20薄膜晶体管层；          30层状相分离保护层；
301绝缘纳米颗粒层；       302有机聚合物层；
40无机层。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
如图1所示，图1为本申请实施例提供的阵列基板的结构示意图。
本实施例提供一种阵列基板100，包括基板10、薄膜晶体管层20、无机层40以及层状相分离保护层30。
所述基板10可以为玻璃基板、PI基板或者陶瓷基板等。
所述薄膜晶体管层20设于所述基板10上。所述薄膜晶体管层20包括有源层、栅极绝缘层、栅极层、钝化层以及源漏极层。其中，所述栅极层设于所述基板上；所述栅极绝缘层设于所述栅极层和所述基板上，且包覆所述栅极层；所述有源层设于所述栅极绝缘层上且正对于所述栅极层；所述钝化层设于所述有源层和所述栅极绝缘层上且包覆所述栅极绝缘层；所述源漏极层贯穿所述钝化层和所述栅极绝缘层连接至所述有源层的上表面。
一无机层40设于所述薄膜晶体管层20上，且包覆所述薄膜晶体管层20。具体的，所述无机层40设于所述源漏极层和所述钝化层上，用于保护薄膜晶体管，避免薄膜晶体管被水氧侵蚀，其可以作为保护所述薄膜晶体管层20的第二钝化层、平坦层，只要该膜层采用无机材料即可，在此不做特别的限定。
所述层状相分离保护层30设于所述薄膜晶体管层20上。其中，所述层状相分离保护层30包括层叠设置的绝缘纳米颗粒层301和有机聚合物层302。
具体的，所述绝缘纳米颗粒层301设于所述基板10上且覆盖所述薄膜晶体管层20，换句话来说，所述绝缘纳米颗粒层301紧密地贴附并包裹设于所述薄膜晶体管层20外侧的无机层40，使得该无机层40与所述绝缘纳米颗粒层301紧密贴合。
在本实施例中，所述绝缘纳米颗粒层301与所述无机层40所用材料相同，所述绝缘纳米颗粒层301与所述无机层40所用材料均为氧化硅（例如SiO 2 等）或者沸石,所述绝缘纳米颗粒层301的纳米颗粒尺寸为20nm-80nm。
当所述绝缘纳米颗粒层和所述无机层40所用材料均为SiO 2时，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层40中的SiO 2形成硅氧键，有利于提升膜层间的致密性。
或者，在其他实施例中，当所述绝缘纳米颗粒层和所述无机层所用材料为其他种类的原料时，还可以在所述绝缘纳米颗粒层和所述无机层之间形成其他种类的化学键，以提升膜层间的致密性。
所述有机聚合物层302层叠设置于所述绝缘纳米颗粒层301远离所述薄膜晶体管层20的一侧，且覆盖所述绝缘纳米颗粒层301。所述绝缘纳米颗粒层301与所述有机聚合物层302之间形成有化学键，可以提升所述绝缘纳米颗粒层301和所述有机聚合物层302之间的致密性，进而有利于提升所述阵列基板100的阻隔水氧的性能。
在本实施例中，所述有机聚合物层302所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒（如SiO 2等含氧化合物），如此，可以在所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
可选地，所述聚苯乙烯衍生物的分子量控制在10000以上，并且其至少一末端接有一个羧基结构，可以用以增强所述绝缘纳米颗粒层301和所述有机聚合物层302之间的相互作用强度。
或者，在其他可选地实施例中，有机聚合物层302还可以采用其他种类的聚合物，绝缘纳米颗粒层301同样也可以采用其他种类的化合物，只要能够在有机聚合物层302和绝缘纳米颗粒层301之间形成化学键即可，本申请对化学键的种类不做具体限定。
需要强调的是，所述层状相分离保护层30是在热力学控制下利用相分离方法获得的致密的双功能层状相，即叠层设置的绝缘纳米颗粒层301和有机聚合物层302，由于其相分离是热力学控制的结果，并且通过辅助的化学修饰手段的加入，可以在所述薄膜晶体管层20外形成具有更加稳定的封装结构。由于形成的所述层状相分离保护层30结构最终处于热力学的稳定状态下，因此所述薄膜晶体管层20非常稳定且不易被破坏，保证了薄膜晶体管器件的稳定性，提升了所述阵列基板的100的隔绝水氧的性能。
本实施例提供一种阵列基板100，其包括所述薄膜晶体管层20和所述层状相分离保护层30，所述层状相分离保护层30包括所述绝缘纳米颗粒层301和所述有机聚合物层302，所述绝缘纳米颗粒层301与所述薄膜晶体管层20外侧的无机层40形成硅氧键，使得所述绝缘纳米颗粒层301与所述无机层40紧密地贴合在一起，所述绝缘纳米颗粒层301还与所述有机聚合物层302形成氢键，使得所述绝缘纳米颗粒层301与所述有机聚合物层302紧密地贴合在一起，进而使得所述薄膜晶体管层20和所述层状相分离保护层30层层紧密接触，有利于提升整个所述阵列基板100封装结构的致密性能，有效阻隔外界的水氧入侵。
如图2所示，图2为本申请实施例提供的阵列基板的制备方法的流程图。
本实施例提供一种阵列基板的制备方法，包括如下步骤S1）-S5）。
S1）提供一基板。
如图1所示，所述基板10可以为玻璃基板、PI基板或者陶瓷基板等
S2）形成一薄膜晶体管层于所述基板上。
具体的，如图1所示，所述薄膜晶体管层20包括有源层、栅极绝缘层、栅极层、钝化层以及源漏极层。其中，所述栅极层设于所述基板上；所述栅极绝缘层设于所述栅极层和所述基板上，且包覆所述栅极层；所述有源层设于所述栅极绝缘层上且正对于所述栅极层；所述钝化层设于所述有源层和所述栅极绝缘层上且包覆所述栅极绝缘层；所述源漏极层贯穿所述钝化层和所述栅极绝缘层连接至所述有源层的上表面。
一无机层40设于所述薄膜晶体管层20上。具体的，所述无机层40设于所述源漏极层和所述钝化层上，用于保护薄膜晶体管，避免薄膜晶体管被水氧侵蚀，其可以作为保护所述薄膜晶体管层20的第二钝化层、平坦层，只要该膜层采用无机材料即可，在此不做特别的限定。
S3）提供一混合溶液，获取以下组分：绝缘纳米颗粒、有机聚合物以及溶剂。
具体的，按照体积比为（0.9-1.1）:（0.9-1.1）:（0.7-1.2）获取以下组分绝缘纳米颗粒、有机聚合物以及溶剂。优选地，绝缘纳米颗粒：有机聚合物：溶剂的体积比为1:1:1。其中，所述绝缘纳米颗粒为氧化物纳米颗粒，其包括氧化硅（例如SiO 2）或者沸石，所述绝缘纳米颗粒的尺寸为20nm-80nm，所述有机聚合物为聚苯乙烯衍生物，所述溶剂包括正己烷和/或二氯甲烷。
S4）涂布所述混合溶液于所述基板和所述薄膜晶体管层上，形成未固化的混合膜层。
S5）对所述未固化的混合膜层进行加热退火处理，形成固化的绝缘纳米颗粒层以及有机聚合物层，所述绝缘纳米颗粒层设于所述基板上且覆盖所述薄膜晶体管层，所述有机聚合物层层叠设置于所述绝缘纳米颗粒层远离所述薄膜晶体管层的一侧，且覆盖所述绝缘纳米颗粒层。
具体的，所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒；加热所述未固化的混合膜层至熔融状态，并冷却所述熔融状态的混合膜层以在所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
在加热退火处理的过程中，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构上（例如所述聚苯乙烯主链结构末端）的羧基结构，当将所述聚苯乙烯衍生物加热至98℃-110℃时，所述羧基结构与所述绝缘纳米颗粒层之间形成氢键。当加热退火的温度大于或等于180℃时，所述溶剂挥发，所述层状相分离保护层形成两层层叠设置的绝缘纳米颗粒层和有机聚合物层。
需要说明的是，上述提到的“加热退火处理”过程，其实是将一个无序的未固化的混合膜层（包含绝缘纳米颗粒和有机聚合物）中的每一组分动起来，即所述绝缘纳米颗粒层中的SiO 2颗粒和所述有机聚合物层的所述聚苯乙烯衍生物的高分子链动起来，从而进行重组，组分中的SiO 2颗粒可能不好动，但是可以让所述聚苯乙烯衍生物的高分子链动起来进一步诱导形成层状相，而让所述聚苯乙烯衍生物的高分子链动起来只需要加热到熔融温度（melting temperature）以上即可。
在本实施例中，所述聚苯乙烯衍生物的熔融温度为100℃。因此，当所述聚苯乙烯衍生物的熔融温度为100℃以上时，可以使所述聚苯乙烯衍生物的高分子链发生重组。所述聚苯乙烯衍生物的分子量控制在10000以上，并且其末端接有一个羧基，用以增强所述绝缘纳米颗粒与所述聚苯乙烯衍生物之间的相互作用强度。
如图3所示，图3为本申请实施例提供的层状相分离保护层形成的结构示意图。
在加热退火之后，结合图1所示，所述聚苯乙烯衍生物形成致密性的所述有机聚合物层302，所述有机聚合物层302形成了非常好的疏水保护层，起到了良好的阻隔水氧的效果。由于所述聚苯乙烯衍生物末端的羧基（-COOH）会和所述绝缘纳米颗粒层301中氧化纳米颗粒（如SiO 2）中的氧之间形成氢键，增加了所述有机聚合物层302和所述绝缘纳米颗粒层301的结合强度。所述绝缘纳米颗粒层301自身形成有丰富的硅氧键（Si-O）会相互紧密的排列在一起，在经过加热退火后会紧密的排列成规整的一层，并与所述薄膜晶体管层20最外层的无机层40紧密接触，形成的硅氧键（Si-O），进一步紧密的附着在所述薄膜晶体管层20最外层的无机层40上，使得所述薄膜晶体管层20的封装结构层层紧密相连，具有良好的致密性能，进而提升所述阵列基板100的阻隔水氧的性能。
具体的，如图1所示，所述绝缘纳米颗粒层301设于所述基板10上且覆盖所述薄膜晶体管层20，换句话来说，所述绝缘纳米颗粒层301紧密地贴附并包裹所述薄膜晶体管层20最外层的无机层40，使得该无机层40与所述绝缘纳米颗粒层301紧密贴合。
在本实施例中，所述绝缘纳米颗粒层301与所述无机层40所用材料相同，所述绝缘纳米颗粒层301与所述无机层40所用材料均为氧化硅（例如SiO2）或者沸石。当所述绝缘纳米颗粒层和所述无机层40所用材料均为SiO 2时，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层40中的SiO 2形成硅氧键，有利于提升膜层间的致密性。
在本实施例中，所述有机聚合物层302所用材料为聚苯乙烯衍生物，当所述聚苯乙烯衍生物达到熔融温度时，所述聚苯乙烯衍生物的高分子链诱导形成层状相，所述绝缘纳米颗粒层301中的所述氧化物纳米颗粒（如SiO 2）与所述聚苯乙烯衍生物中的羧基形成氢键，使得所述绝缘纳米颗粒层与所述有机聚合物层紧密地贴合在一起。所述聚苯乙烯衍生物的分子量控制在10000以上，并且其至少一末端接有一个羧基结构，可以用以增强所述绝缘纳米颗粒层301和所述有机聚合物层302之间的相互作用强度。
需要强调的是，所述层状相分离保护层30是在热力学控制下利用相分离方法获得的致密的双功能层状相，即叠层设置的绝缘纳米颗粒层301和有机聚合物层302，由于其相分离是热力学控制的结果，并且通过辅助的化学修饰手段的加入，可以使得所述薄膜晶体管层20具有更加稳定的结构。由于形成的所述层状相分离保护层30结构最终处于热力学的稳定状态下，因此所述薄膜晶体管层20非常稳定且不易被破坏，保证了薄膜晶体管器件的稳定性，提升了所述阵列基板的100的隔绝水氧的性能。
总的来说，在制备层状相分离保护层30的过程中，引入的氧化物纳米颗粒（如SiO 2），一方面是为了进一步补偿所述薄膜晶体管层20外侧的无机层40（如SiO 2等）引起器件阻隔水氧差的技术问题，当所述氧化物纳米颗粒与有机聚合物经过了共混、加热退火形成所述层状相分离保护层30时，增加了所述氧化物纳米颗粒与有机聚合物之间的结合强度，提高膜层间的致密性；另一方面，所述氧化物纳米颗粒自身形成有丰富的硅氧键（Si-O）会相互紧密的排列在一起，在经过加热退火后会紧密的排列成规整的一层，并与所述薄膜晶体管层20外侧的无机层40紧密接触，形成的硅氧键（Si-O），进一步地附着在所述薄膜晶体管层20上，进而使得所述薄膜晶体管层20和所述层状相分离保护层30层层紧密接触，有利于提升整个所述阵列基板100封装结构的致密性能，进而有效阻隔外界的水氧入侵。
如图4所示，图4为本申请实施例提供的显示面板的结构示意图。
本实施例还提供一种显示面板1000，包括前文所述的阵列基板100以及彩膜基板200，所述阵列基板100与所述彩膜基板200相对设置。
本发明的技术效果在于，提供一种显示面板、阵列基板及其制备方法，阵列基板包括基板、薄膜晶体管层、绝缘纳米颗粒层以及有机聚合物层。薄膜晶体管层设于基板上；绝缘纳米颗粒层设于基板上且覆盖薄膜晶体管层；有机聚合物层层叠设置于绝缘纳米颗粒层远离薄膜晶体管层的一侧，且覆盖绝缘纳米颗粒层。本申请通过在所述薄膜晶体管层上形成层叠设置的绝缘纳米颗粒层和有机聚合物层，有利于提升整个阵列基板的致密性能，有效阻隔外界的水氧入侵，并有利于提高显示面板的使用寿命。
以上对本申请实施例所提供的一种显示面板、阵列基板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其包括：
    基板；
    薄膜晶体管层，设于所述基板上；
    绝缘纳米颗粒层，设于所述基板上且覆盖所述薄膜晶体管层；以及
    有机聚合物层，层叠设置于所述绝缘纳米颗粒层远离所述薄膜晶体管层的一侧，且覆盖所述绝缘纳米颗粒层。
  2. 根据权利要求1所述的阵列基板，其中，
    所述绝缘纳米颗粒层与所述有机聚合物层之间形成有化学键。
  3. 根据权利要求2所述的阵列基板，其中，
    所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒，所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
  4. 根据权利要求1所述的阵列基板，其还包括：
    一无机层，设于所述薄膜晶体管层背离所述绝缘纳米颗粒层的一侧。
  5. 根据权利要求4所述的阵列基板，其中，
    所述绝缘纳米颗粒层与所述无机层所用材料相同。
  6. 根据权利要求5所述的阵列基板，其中，
    所述绝缘纳米颗粒层和所述无机层所用材料均为SiO 2，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层中的SiO 2形成硅氧键。
  7. 根据权利要求5所述的阵列基板，其中，
    所述绝缘纳米颗粒层与所述无机层所用材料均为氧化硅或者沸石。
  8. 根据权利要求5所述的阵列基板，其中，
    所述绝缘纳米颗粒层的纳米颗粒尺寸为20nm-80nm。
  9. 一种阵列基板的制备方法，其包括如下步骤：
    提供一基板；
    形成一薄膜晶体管层于所述基板上；
    提供一混合溶液，获取以下组分：绝缘纳米颗粒、有机聚合物以及溶剂；
    涂布所述混合溶液于所述基板和所述薄膜晶体管层上，形成未固化的混合膜层；
    对所述未固化的混合膜层进行加热退火处理，形成固化的绝缘纳米颗粒层以及有机聚合物层，所述绝缘纳米颗粒层设于所述基板上且覆盖所述薄膜晶体管层，所述有机聚合物层层叠设置于所述绝缘纳米颗粒层远离所述薄膜晶体管层的一侧，且覆盖所述绝缘纳米颗粒层。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，对所述未固化的混合膜层进行加热退火处理的步骤包括：加热所述未固化的混合膜层至熔融状态，并冷却所述熔融状态的混合膜层以形成层状相分离保护层，所述层状相分离保护层包括绝缘纳米颗粒层以及有机聚合物层。
  11. 根据权利要求10所述的阵列基板的制备方法，其中，所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒；
    所述冷却所述熔融状态的混合膜层以形成层状相分离保护层的步骤包括：在所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
  12. 根据权利要求9所述的阵列基板的制备方法，其中，
    在提供一混合溶液的步骤中，按照体积比为（0.9-1.1）:（0.9-1.1）:（0.7-1.2）获取所述绝缘纳米颗粒、所述有机聚合物以及所述溶剂。
  13. 一种显示面板，其包括：
    如权利要求1所述的阵列基板；以及
    彩膜基板，与所述阵列基板相对设置。
  14. 根据权利要求13所述的显示面板，其中，
    所述绝缘纳米颗粒层与所述有机聚合物层之间形成有化学键。
  15. 根据权利要求14所述的显示面板，其中，
    所述有机聚合物层所用材料为聚苯乙烯衍生物，所述聚苯乙烯衍生物包括聚苯乙烯主链结构以及连接于所述聚苯乙烯主链结构的一羧基结构，所述绝缘纳米颗粒层为氧化物纳米颗粒，所述羧基结构与所述氧化物纳米颗粒之间形成氢键。
  16. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括：
    一无机层，设于所述薄膜晶体管层背离所述绝缘纳米颗粒层的一侧。
  17. 根据权利要求16所述的显示面板，其中，
    所述绝缘纳米颗粒层与所述无机层所用材料相同。
  18. 根据权利要求17所述的显示面板，其中，
    所述绝缘纳米颗粒层和所述无机层所用材料均为SiO 2，所述绝缘纳米颗粒层中的SiO 2纳米颗粒与所述无机层中的SiO 2形成硅氧键。
  19. 根据权利要求18所述的显示面板，其中，
    所述绝缘纳米颗粒层与所述无机层所用材料均为氧化硅或者沸石。
  20. 根据权利要求17所述的显示面板，其中，
    所述绝缘纳米颗粒层的纳米颗粒尺寸为20nm-80nm。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110699668A (zh) * 2019-10-16 2020-01-17 湖北大学 带复合涂层体及其制备方法和应用、太阳能电池
CN111129349A (zh) * 2019-12-26 2020-05-08 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
US20200295294A1 (en) * 2019-03-12 2020-09-17 Samsung Display Co., Ltd. Display device
CN111785684A (zh) * 2020-06-19 2020-10-16 安徽熙泰智能科技有限公司 一种适用于Micro OLED显示器的一体化薄膜结构的制备方法
CN112002794A (zh) * 2020-08-13 2020-11-27 Tcl华星光电技术有限公司 封装材料、其制备方法以及电子设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020003403A1 (en) * 2000-04-25 2002-01-10 Ghosh Amalkumar P. Thin film encapsulation of organic light emitting diode devices
KR102100767B1 (ko) * 2013-11-26 2020-04-21 엘지디스플레이 주식회사 유기발광 표시장치 및 그 제조방법
CN104979492B (zh) * 2015-05-28 2017-11-28 京东方科技集团股份有限公司 封装薄膜及其制作方法、发光器件、显示面板和显示装置
US10651421B2 (en) * 2018-08-03 2020-05-12 Wuhan China Star Optoelectronics Semiconductor Display Technology Co. Ltd. Display panel and encapsulation component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200295294A1 (en) * 2019-03-12 2020-09-17 Samsung Display Co., Ltd. Display device
CN110699668A (zh) * 2019-10-16 2020-01-17 湖北大学 带复合涂层体及其制备方法和应用、太阳能电池
CN111129349A (zh) * 2019-12-26 2020-05-08 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111785684A (zh) * 2020-06-19 2020-10-16 安徽熙泰智能科技有限公司 一种适用于Micro OLED显示器的一体化薄膜结构的制备方法
CN112002794A (zh) * 2020-08-13 2020-11-27 Tcl华星光电技术有限公司 封装材料、其制备方法以及电子设备

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