WO2022141680A1 - 显示面板和显示装置 - Google Patents
显示面板和显示装置 Download PDFInfo
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- WO2022141680A1 WO2022141680A1 PCT/CN2021/072695 CN2021072695W WO2022141680A1 WO 2022141680 A1 WO2022141680 A1 WO 2022141680A1 CN 2021072695 W CN2021072695 W CN 2021072695W WO 2022141680 A1 WO2022141680 A1 WO 2022141680A1
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- transistor
- gate
- line
- base substrate
- display panel
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/302—Details of OLEDs of OLED structures
Definitions
- At least one embodiment of the present disclosure relates to a display panel and a display device.
- AMOLED Active-Matrix Organic Light-Emitting Diode
- At least one embodiment of the present disclosure relates to a display panel and a display device.
- At least one embodiment of the present disclosure provides a display panel, including: a base substrate; and a pixel unit, located on the base substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the A light-emitting element, the pixel circuit includes a drive transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a second electrode of the drive transistor, and a second electrode of the threshold compensation transistor is connected to a second electrode of the drive transistor.
- the threshold compensation transistor includes a first channel and a second channel, and the first channel and the second channel are connected through a conductive connection;
- the orthographic projection of the base substrate and the orthographic projection of the conductive connection portion on the base substrate at least partially overlap; the orthographic projection of the first conductive structure on the base substrate and the blocking
- the orthographic projection of the block on the base substrate at least partially overlaps; the area of the orthographic projection of the portion of the block that overlaps with the first conductive structure on the base substrate is larger than that of the block The area of the orthographic projection of the portion overlapping the conductive connection portion on the base substrate.
- the material of the first conductive structure is the same as the material of the conductive connection.
- the material of the first conductive structure includes a conductive material obtained by doping a semiconductor material.
- the display panel further includes a connecting line, and the first conductive structure is connected to the gate of the driving transistor through the connecting line.
- the material of the first conductive structure is different from the material of the connection line.
- the connecting line is in contact with the gate of the driving transistor and the first conductive structure, respectively.
- the first conductive structure, the connection line, and the gate of the driving transistor constitute a gate signal portion of the driving transistor.
- the pixel circuit further includes a first reset transistor, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, and the first conductive structure is multiplexed is the second pole of the first reset transistor.
- the display panel further includes a first reset control signal line and a first initialization signal line, the gate of the first reset transistor is connected to the first reset control signal line, the The first electrode of the first reset transistor is connected to the first initialization signal line, and the orthographic projection of the first electrode of the first reset transistor on the base substrate is the same as that of the stopper on the base substrate The orthographic projections of , at least partially overlap.
- the display panel further includes a data line configured to provide a data signal to the pixel circuit and a second conductive structure, the data line and the second conductive structure
- the orthographic projection of the stopper on the base substrate at least partially overlaps the orthographic projection of the second conductive structure on the base substrate.
- the area of the orthographic projection of the portion of the stopper overlapping the second conductive structure on the base substrate is larger than that of the stopper and the conductive connection The area of the orthographic projection of the overlapping portion on the base substrate.
- the area of the orthographic projection of the portion of the stopper overlapping the first conductive structure on the base substrate is larger than that of the stopper and the second conductive structure.
- the area of the orthographic projection of the overlapping portion of the conductive structures on the base substrate is larger than that of the stopper and the second conductive structure.
- the orthographic projection of the stopper on the base substrate at least partially overlaps the orthographic projection of the data line on the base substrate.
- the display panel further includes a gate line, the gate of the threshold compensation transistor is connected to the gate line, and the pixel circuit further includes a data writing transistor, the data writing transistor The first pole of the data writing transistor is connected to the data line, the second pole of the data writing transistor is connected to the first pole of the driving transistor, the gate of the data writing transistor is connected to the gate line, and the The second conductive structure is multiplexed as the first electrode of the data writing transistor.
- the display panel further includes a first connection electrode, and the data line is connected to the second conductive structure through the first connection electrode.
- the data line, the first connection electrode, and the second conductive structure constitute a data signal portion.
- the pixel unit includes a first pixel unit, a second pixel unit, and a third pixel unit, and the first pixel unit and the second pixel unit are in a first direction. adjacent, the first pixel unit and the third pixel unit are adjacent in a second direction, and the first direction intersects with the second direction;
- the data line includes a first data line and a second data line and a third data line, the first data line is configured to provide a first data signal to the pixel circuit of the first pixel unit;
- the second data line is configured to provide a first data signal to the pixel circuit of the second pixel unit the pixel circuit provides a second data signal,
- the third data line is configured to provide a third data signal to the pixel circuit of the third pixel unit, the third data line is located on the first data line and the second data line;
- the orthographic projection of the stopper on the base substrate at least partially overlaps the orthographic projection of the third data line on the base substrate.
- the stopper is located between the first data line and the second data line.
- the stopper in a direction perpendicular to the base substrate, is located between the second conductive structure and the third data line.
- the orthographic projection of the second conductive structure on the base substrate at least partially overlaps the orthographic projection of the third data line on the base substrate.
- the display panel further includes a connecting element, the light emitting element is connected to the pixel circuit through the connecting element, the connecting element includes a shielding portion, and the data line includes two phase an adjacent data line, the shielding portion is located between the two adjacent data lines, the orthographic projection of the connecting line on the base substrate and the orthographic projection of the shielding portion on the base substrate are at least Partially overlapping.
- connection element further includes a second connection electrode
- the pixel circuit is connected to the second connection electrode
- the second connection electrode is connected to the shielding part
- the The shielding portion is connected to the light emitting element.
- the pixel unit further includes a fourth pixel unit, the fourth pixel unit is adjacent to the second pixel unit in the second direction, the fourth pixel unit The unit is adjacent to the third pixel unit in the first direction, and the data line further includes a fourth data line configured to provide the pixel circuit of the fourth pixel unit with a fourth data line.
- the orthographic projection of the stopper on the base substrate at least partially overlaps the orthographic projection of the fourth data line on the base substrate.
- the stopper has a first edge that overlaps the fourth data line, and a space between the first edge and the fourth data line The included angle is greater than zero and less than 90°.
- the stopper has a second edge, the second edge overlaps the third data line, and a space between the second edge and the third data line
- the included angle is greater than zero and less than 90°.
- the fourth data line is located between the third data line and the second data line.
- the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit constitute a repeating unit.
- the stopper includes a first portion, a second portion, and a third portion, the first portion extending in a first direction, the second portion extending in a second direction, the The third part extends along the first direction, the first part and the third part are connected by the second part, and the first part and the second part form an inverted T-shaped structure.
- the first portion, the second portion, and the third portion are located on the same layer and have a unitary structure.
- the pixel circuit further includes a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode of the storage capacitor is connected to the first electrode of the drive transistor. connected to a power cord.
- the display panel further includes a second reset control signal line and a second initialization signal line
- the pixel circuit further includes a second reset transistor
- the gate of the second reset transistor is connected to the second reset transistor.
- the second reset control signal line is connected
- the first electrode of the second reset transistor is connected to the second initialization signal line
- the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element.
- the display panel further includes an emission control signal line
- the pixel circuit further includes a first emission control transistor and a second emission control transistor
- the gate of the first emission control transistor is connected to the the light-emitting control signal line is connected
- the first pole of the first light-emitting control transistor is connected to the first power supply terminal
- the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor
- the gates of the second light-emitting control transistors are connected to the light-emitting control signal lines
- the first electrodes of the second light-emitting control transistors are connected to the second electrodes of the driving transistors
- the second electrodes of the second light-emitting control transistors are connected to The first poles of the light-emitting elements are connected.
- At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
- a display panel comprising: a base substrate; and a pixel unit, located on the base substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive a the light-emitting element, the pixel circuit is closer to the base substrate than the light-emitting element, the pixel circuit comprises a driving transistor; a data line is configured to provide a data signal to the pixel circuit; a connecting element, the light-emitting element The element is connected with the pixel circuit through the connecting element, the connecting element includes a shielding part; and a connecting line is connected with the gate of the driving transistor; the data line includes two adjacent data lines, the shielding The shielding portion is located between the two adjacent data lines, and the orthographic projection of the connecting line on the base substrate at least partially overlaps the orthographic projection of the shielding portion on the base substrate.
- the orthographic projection of the shielding portion on the base substrate is greater than the orthographic projection of the connection line on the base substrate.
- the orthographic projection of the gate of the driving transistor on the base substrate partially overlaps the orthographic projection of the shielding portion on the base substrate, the shielding The area of the overlapping portion of the portion and the gate of the driving transistor is smaller than that of the gate of the driving transistor.
- the two adjacent data lines are arranged in a first direction, and the data lines extend in a second direction.
- the size of the gate of the driving transistor in the first direction is larger than the size of the shielding portion in the first direction; the shielding portion is in the first direction.
- the size in the two directions is larger than the size of the gate of the driving transistor in the second direction.
- connection line is in contact with the gate of the drive transistor.
- the data line and the shielding portion are located at the same layer, and the extending direction of the shielding portion is the same as the extending direction of the data line.
- the display panel further includes a first conductive structure, the connection line is connected to the first conductive structure, and the orthographic projection of the shielding portion on the base substrate is the same as the first conductive structure. Orthographic projections of the first conductive structures on the base substrate at least partially overlap.
- the pixel circuit further includes a first reset transistor, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, and the first conductive structure is multiplexed is the second pole of the first reset transistor.
- the display panel further includes a first reset control signal line and a first initialization signal line, the gate of the first reset transistor is connected to the first reset control signal line, the The first pole of the first reset transistor is connected to the first initialization signal line.
- the first reset transistor includes a first channel and a second channel, and the first channel and the second channel of the first reset transistor are connected by a conductive connection,
- the orthographic projection of the shielding portion on the base substrate partially overlaps the orthographic projection of the conductive connection portion of the first reset transistor on the base substrate.
- the display panel further includes a second initialization signal line, wherein the first initialization signal line and the second initialization signal line are respectively located opposite to the gate of the driving transistor On both sides, the orthographic projection of the shielding portion on the base substrate partially overlaps the orthographic projection of the second initialization signal line on the base substrate.
- the display panel further includes a first power supply line and a stopper, wherein the first power supply line is configured to provide a first power supply voltage to the pixel circuit, and the stopper is connected to the pixel circuit.
- the first power line is electrically connected, and the orthographic projection of the first conductive structure on the base substrate at least partially overlaps the orthographic projection of the stopper on the base substrate.
- the display panel further includes a second conductive structure
- the data line is connected to the second conductive structure
- the orthographic projection of the stopper on the base substrate is the same as the second conductive structure. Orthographic projections of the second conductive structures on the base substrate at least partially overlap.
- the display panel further includes a gate line, the gate line and the data line intersect with each other and are insulated from each other, the gate line is configured to provide a scan signal to the pixel circuit, so
- the pixel circuit further includes a threshold compensation transistor, the first pole of the threshold compensation transistor is connected to the second pole of the driving transistor, and the second pole of the threshold compensation transistor is connected to the gate of the driving transistor; the The gate of the threshold compensation transistor is connected to the gate line; the gate of the driving transistor is connected to the second pole of the threshold compensation transistor through the connection line, and the threshold compensation transistor includes a first channel and a second electrode The first channel and the second channel are connected through a conductive connection part; the orthographic projection of the stopper on the base substrate and the conductive connection part of the threshold compensation transistor are in the same position.
- the orthographic projections on the base substrate at least partially overlap.
- the area of the orthographic projection of the portion of the stopper overlapping the first conductive structure on the base substrate is greater than the threshold compensation of the stopper The area of the orthographic projection of the overlapping portion of the conductive connection portions of the transistor on the base substrate.
- the material of the first conductive structure is different from the material of the connection line.
- the pixel unit includes two adjacent pixel units located in the same column, and the two adjacent data lines are respectively connected to the two pixel units.
- the display panel further includes a second reset control signal line
- the pixel circuit further includes a second reset transistor
- the gate of the second reset transistor is connected to the second reset control signal
- the first electrode of the second reset transistor is connected to the second initialization signal line
- the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element.
- the pixel circuit further includes a first power supply terminal and a storage capacitor, a first electrode of the storage capacitor is connected to a gate of the driving transistor, and a second electrode of the storage capacitor is connected to the gate of the driving transistor.
- the pole is connected to the first power supply terminal.
- the pixel circuit further includes a data writing transistor, a gate of the data writing transistor is connected to the gate line, and a first electrode of the data writing transistor is connected to the gate line.
- the data lines are connected to each other, and the second pole of the data writing transistor is connected to the first pole of the driving transistor.
- the display panel further includes an emission control signal line
- the pixel circuit further includes a first emission control transistor and a second emission control transistor
- the gate of the first emission control transistor is connected to the the light-emitting control signal line is connected
- the first pole of the first light-emitting control transistor is connected to the first power supply terminal
- the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor
- the gate of the second light-emitting control transistor is connected to the light-emitting control signal line
- the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor
- the second electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor.
- the pole is connected to the first pole of the light-emitting element.
- the data line has a first portion and a second portion, and the spacing between the first portions of the two adjacent data lines is greater than the second portion of the two adjacent data lines The spacing between the parts, the shielding part is located between the second parts of the two adjacent data lines.
- the second portions of the two adjacent data lines are respectively close to the first light-emitting control transistor and the second light-emitting control transistor, and the storage capacitor is located at the two adjacent data lines. between the first portions of adjacent data lines.
- connection element further includes a connection electrode, the connection electrode is connected to the pixel circuit, and the light-emitting element is connected to the connection electrode through the shielding portion.
- At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
- 1 is a schematic diagram of a 7T1C pixel circuit
- FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1;
- FIG. 3 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure
- FIG. 4 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure
- FIG. 5 is a schematic diagram of forming an active layer, a source electrode and a drain electrode of a thin film transistor in a display panel according to an embodiment of the present disclosure
- FIG. 6 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure
- FIG. 7 is a schematic plan view of a display panel after forming a second conductive pattern layer according to an embodiment of the present disclosure
- FIG. 8 is a schematic plan view of a via hole formed in at least one of a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer in a display panel according to an embodiment of the present disclosure
- FIG. 9 is a schematic plan view of a display panel provided by an embodiment of the present disclosure after via holes are formed in at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer;
- FIG. 10 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure.
- FIG. 11 is a plan view after forming a third conductive pattern layer in a display panel according to an embodiment of the disclosure.
- FIG. 12 is a schematic plan view of a passivation layer in a display panel and a via hole formed in a first planarization layer according to an embodiment of the present disclosure
- FIG. 13 is a schematic plan view of a passivation layer in a display panel and a via hole formed in the first planarization layer according to an embodiment of the present disclosure
- FIG. 14 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure.
- FIG. 15 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to an embodiment of the disclosure.
- 16A is a plan view of a fourth conductive pattern layer in a display panel according to another embodiment of the present disclosure.
- 16B is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to another embodiment of the present disclosure
- FIG. 17 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to another embodiment of the present disclosure.
- FIG. 18 is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure (a cross-sectional view along line AB of FIG. 17 );
- 19 is a partial plan view of a display panel according to an embodiment of the disclosure.
- FIG. 20 is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure (a cross-sectional view along line CD in FIG. 19 );
- FIG. 21 is a pixel circuit diagram of a repeating unit of a display panel according to an embodiment of the disclosure.
- the Dual Data solution can achieve 120Hz driving under the premise of ensuring the display effect.
- FIG. 1 is a schematic diagram of a 7T1C pixel circuit.
- FIG. 2 is an operation timing diagram of the pixel circuit shown in FIG. 1 .
- the pixel circuit shown in FIG. 1 may be a pixel circuit of a low temperature polysilicon (Low Temperature Poly-silicon, LTPS) AMOLED common in the related art.
- LTPS Low Temperature Poly-silicon
- FIG. 1 shows a pixel circuit of a pixel unit of a display panel.
- the pixel unit 101 includes a pixel circuit 10 and a light-emitting element 20 .
- the pixel circuit 10 includes six switching transistors ( T2 - T7 ), one driving transistor T1 and one storage capacitor Cst.
- the six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
- the light-emitting element 20 includes a first electrode 201 and a second electrode 202 and a light-emitting functional layer between the first electrode 201 and the second electrode 202 .
- the first pole 201 is an anode
- the second pole 202 is a cathode.
- the threshold compensation transistor T3 and the first reset transistor T6 are double-gate TFTs to reduce leakage.
- the display panel includes a gate line GT, a data line DT, a first power supply terminal VDD, a second power supply terminal VSS, a light emission control signal line EML, an initialization signal line INT, a first reset control signal line RT1, a second power supply terminal The reset control signal line RT2 and the like.
- the first power supply terminal VDD is configured to provide a constant first voltage signal ELVDD to the pixel unit 101
- the second power supply terminal VSS is configured to provide a constant second voltage signal ELVSS to the pixel unit 101
- the first voltage signal ELVDD is greater than the first voltage signal ELVDD.
- Two voltage signals ELVSS Two voltage signals ELVSS.
- the gate line GT is configured to provide a scan signal SCAN to the pixel unit 101
- the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 101
- the light emission control signal line EML is configured to provide light emission control to the pixel unit 101 signal EM
- the first reset control signal line RT1 is configured to provide a reset control signal RESET to the pixel unit 101
- the second reset control signal line RT1 is configured to provide a scan signal SCAN to the pixel unit 101
- the initialization signal line INT is configured to provide the pixel unit 101 with a scan signal SCAN.
- the pixel unit 101 provides the initialization signal Vinit.
- the initialization signal Vinit is a constant voltage signal, and its magnitude may be between, but not limited to, the first voltage signal ELVDD and the second voltage signal ELVSS, for example, the initialization signal Vinit may be less than or equal to the second voltage signal ELVSS .
- the initialization signal line INT includes a first initialization signal line INT1 and a second initialization signal line INT2.
- the first initialization signal line INT1 is configured to supply the initialization signal Vinit1 to the pixel unit 101
- the second initialization signal line INT1 is configured to supply the initialization signal Vinit2 to the pixel unit 101 .
- the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and both are Vinit.
- the driving transistor T1 is electrically connected to the light-emitting element 20 and outputs a driving current to drive the light-emitting element 20 under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, the second voltage signal ELVSS and other signals. glow.
- the light-emitting element 20 is an organic light-emitting diode (OLED), and the light-emitting element 20 emits red light, green light, blue light, or white light and the like under the driving of the corresponding pixel circuit 10.
- one pixel includes a plurality of pixel units.
- One pixel may include a plurality of pixel units that emit light of different colors.
- one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
- the number of pixel units included in a pixel and the light output of each pixel unit can be determined as required.
- the gate T20 of the data writing transistor T2 is connected to the gate line GT
- the first pole T21 of the data writing transistor T2 is connected to the data line DT
- the second pole T22 of the data writing transistor T2 is connected to the data line DT.
- the first pole T11 of the driving transistor T1 is connected.
- the pixel circuit 10 further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, and the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1
- the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
- the display panel further includes an emission control signal line EML
- the pixel circuit 10 further includes a first emission control transistor T4 and a second emission control transistor T5, and the gate T40 of the first emission control transistor T4 is connected to the emission control transistor T4.
- the signal line EML is connected, the first electrode T41 of the first light-emitting control transistor T4 is connected to the first power supply terminal VDD, the second electrode T42 of the first light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1; the second light-emitting control transistor T4 is connected to the first electrode T11 of the driving transistor T1;
- the gate T50 of the transistor T5 is connected to the light-emitting control signal line EML, the first electrode T51 of the second light-emitting control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is connected to the light-emitting element.
- the first pole 201 of 20 is connected.
- the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1
- the second reset transistor T7 is connected to the first electrode 201 of the light-emitting element 20 , and is configured to reset the first pole 201 of the light-emitting element 20 .
- the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6.
- the second initialization signal line INT2 is connected to the first electrode 201 of the light emitting element 20 through the second reset transistor T7.
- first initialization signal line INT1 and the second initialization signal line INT2 are connected to receive the same initialization signal, but not limited thereto, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are also can be isolated from each other and configured to input signals separately.
- the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1
- the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1
- the second reset transistor T6 is connected to the gate T10 of the driving transistor T1.
- the first electrode T71 of the transistor T7 is connected to the second initialization signal line INT2
- the second electrode T72 of the second reset transistor T7 is connected to the first electrode 201 of the light emitting element 20 .
- the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RT1
- the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RT2.
- the first power supply terminal VDD is configured to provide a first voltage signal ELVDD to the pixel circuit 10; the pixel circuit further includes a storage capacitor Cst, and the first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1 , the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD.
- the display panel further includes a second power supply terminal VSS, and the second power supply terminal VSS is connected to the second pole 201 of the light-emitting element 20 .
- the driving method of the pixel unit includes a first reset phase t1, data writing and threshold compensation, and a second reset phase t2 and light-emitting phase t3.
- the reset control signal RESET is at a low level
- the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode 201 (eg, the anode) of the light-emitting element 20 is reset.
- the first electrode 201 eg, the anode
- the storage capacitor is used to hold the voltage signal, so that the potential of the signal holding terminal can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form
- the driving current drives the light-emitting element 20 to emit light.
- the light emission control signal EM is set as the off voltage
- the reset control signal RESET is set as the on voltage
- the scan signal SCAN is set as the off voltage.
- the light emission control signal EM is set as the off voltage
- the reset control signal RESET is set as the off voltage
- the scan signal SCAN is set as the on voltage.
- the light-emitting control signal EM is set as the turn-on voltage
- the reset control signal RESET is set as the turn-off voltage
- the scan signal SCAN is set as the turn-off voltage.
- the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals, for example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.
- the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor
- the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor.
- the turn-on voltage is a low voltage (eg, 0V)
- the turn-off voltage is a high voltage (eg, 5V)
- the turn-on voltage is a high voltage (eg, 5V)
- the turn-off voltage is high.
- the voltage is a low voltage (eg, 0V).
- the driving waveforms shown in FIG. 2 are all described by taking a P-type transistor as an example.
- the turn-on voltage is a low voltage (eg, 0V)
- the turn-off voltage is a high voltage (eg, 5V), but not limited thereto.
- the first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the drive transistor T1 and is stored by the storage capacitor Cst, resets the drive transistor T1 and erases the data stored in the last (last frame) light emission .
- the light emission control signal EM is the off voltage
- the reset control signal RESET is the off voltage
- the scan signal SCAN is the on voltage.
- the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state
- the second reset transistor T7 is in the conducting state
- the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the light-emitting element 20
- the first electrode 201 to reset the light-emitting element 20 .
- the first light-emitting control transistor T4, the second light-emitting control transistor T5, and the first reset transistor T6 are in an off state.
- the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and transmits the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN Write data voltage VDATA.
- the threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1.
- the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and adjusts the driving transistor according to the scan signal SCAN.
- the gate voltage of T1 performs threshold voltage compensation. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.
- the light-emitting control signal EM is the turn-on voltage
- the reset control signal RESET is the turn-off voltage
- the scan signal SCAN is the turn-off voltage.
- the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
- the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
- the first voltage signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is kept as VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1 and the
- the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light according to the light emission control signal EM.
- the luminous current I satisfies the following saturation current formula:
- ⁇ n is the channel mobility of the driving transistor
- Cox is the channel capacitance per unit area of the driving transistor T1
- W and L are the channel width and channel length of the driving transistor T1, respectively
- Vgs is the gate and source of the driving transistor T1 The voltage difference between the poles (that is, the first pole of the driving transistor T1 in this embodiment).
- the pixel circuit of the present invention compensates the threshold voltage of the driving transistor T1 very well.
- the ratio of the duration of the light-emitting stage t3 to the display period of one frame can be adjusted.
- the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the display time period of one frame.
- adjusting the ratio of the duration of the light-emitting phase t3 to the display duration of one frame is achieved by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.
- the embodiment of the present disclosure is not limited to the specific pixel circuit shown in FIG. 1 , and other pixel circuits that can realize compensation for the driving transistor may be used. Based on the description and teaching of the present disclosure, other arrangements that can be easily conceived by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.
- FIG. 3 is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure.
- 4 is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure.
- 5 is a schematic diagram of forming an active layer, a source electrode and a drain electrode of a thin film transistor in a display panel according to an embodiment of the present disclosure.
- 6 is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure.
- 7 is a schematic plan view of a display panel after forming a second conductive pattern layer according to an embodiment of the present disclosure.
- FIG. 8 is a schematic plan view of a via hole formed in at least one of a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer in a display panel provided by an embodiment of the present disclosure.
- 9 is a schematic plan view of a display panel provided by an embodiment of the present disclosure after via holes are formed in at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.
- 10 is a plan view of a third conductive pattern layer in a display panel according to an embodiment of the disclosure.
- FIG. 11 is a plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the disclosure.
- FIG. 12 is a schematic plan view of a passivation layer in a display panel and a via hole formed in a first planarization layer according to an embodiment of the present disclosure.
- 13 is a schematic plan view of a passivation layer in a display panel and via holes formed in a first planarization layer according to an embodiment of the present disclosure.
- 14 is a plan view of a fourth conductive pattern layer in a display panel according to an embodiment of the disclosure.
- FIG. 15 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to an embodiment of the disclosure.
- 16A is a plan view of a fourth conductive pattern layer in a display panel according to another embodiment of the present disclosure.
- FIG. 17 is a schematic plan view of a display panel after forming a fourth conductive pattern layer according to another embodiment of the present disclosure.
- FIG. 18 is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure (a cross-sectional view taken along line AB in FIG. 17 ).
- FIG. 19 is a partial plan view of a display panel according to an embodiment of the disclosure.
- FIG. 20 is a partial cross-sectional view of a display panel according to an embodiment of the present disclosure (a cross-sectional view taken along line CD in FIG. 19 ).
- FIG. 21 is a pixel circuit diagram of a repeating unit of a display panel according to an embodiment of the disclosure.
- FIG. 19 illustrate a first direction X and a second direction Y, the second direction Y intersecting the first direction X.
- the first direction X is perpendicular to the second direction Y as an example.
- the first direction X is the row direction of the pixel unit
- the second direction Y is the column direction of the pixel unit.
- Both the first direction X and the second direction Y are directions parallel to the base substrate BS.
- the first direction X is perpendicular to the second direction Y.
- 17 and 19 illustrate the third direction Z, which is a direction perpendicular to the base substrate BS.
- the third direction Z is perpendicular to the first direction X and is perpendicular to the second direction Y.
- the insulating layer is shown in the form of via holes, the insulating layer itself is treated with transparency, and the first conductive pattern layer, the second conductive pattern layer, the third The conductive pattern layer and the fourth conductive pattern layer are translucent.
- FIG. 3 shows the semiconductor pattern SCP
- FIG. 4 shows the first conductive pattern layer LY1, for example, a first gate insulating layer (the first gate insulating layer GI1, Refer to Figure 18).
- a semiconductor pattern SCP and subsequent various components are formed on a base substrate.
- the first conductive pattern layer LY1 includes a first reset control signal line RT1, a gate line GT, a first electrode Ca of the storage capacitor Cst (gate T10 of the driving transistor T1), a light emission control signal line EML, a first electrode Ca of the storage capacitor Cst (the gate T10 of the driving transistor T1), Two reset control signal lines RT2.
- the semiconductor pattern SCP is doped with the first conductive pattern layer LY1 as a mask, so that the area of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 retains semiconductor characteristics, forming the active layer ACT (see FIG. 5 ), while the semiconductor pattern SCP is The regions of the pattern SCP that are not covered by the first conductive pattern layer LY1 are conductorized to form the source and drain electrodes of the thin film transistor. 5 shows the active layer ACT formed after the semiconductor pattern SCP is partially conductorized.
- the gate line GT of the current stage is connected to the reset control signal line of the next stage.
- the gate line GT and the second reset control signal line RT2 may be electrically connected to input the same signal at the same time.
- the first reset control signal line RT1 , the gate line GT, the light emission control signal line EML and the second reset control signal line RT2 all extend in the first direction X.
- the semiconductor pattern layer SCP is subjected to conducting treatment using the first conductive pattern layer LY1 as a mask.
- the pattern layer SCP is heavily doped, so that the part of the semiconductor pattern layer SCP that is not covered by the first conductive pattern layer LY1 is conductive, forming the source region (the first electrode T11) and the drain region (the first electrode T11) of the driving transistor T1.
- Diode T12 the source region (first electrode T21) and the drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and the drain region ( The second electrode T32), the source region (the first electrode T41) and the drain region (the second electrode T42) of the first light emission control transistor T4, the source region (the first electrode T51) of the second light emission control transistor T5 and the The drain region (the second electrode T52), the source region (the first electrode T61) and the drain region (the second electrode T62) of the first reset transistor T6, and the source region (the first electrode) of the second reset transistor T7 T71) and the drain region (the second electrode T72).
- the part of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retains semiconductor characteristics, forming the channel region T13 of the driving transistor T1, the channel region T23 of the data writing transistor T2, the channel region T33 of the threshold compensation transistor T3, The channel region T43 of the first light emission control transistor T4, the channel region T53 of the second light emission control transistor T5, the channel region T63 of the first reset transistor T6, and the channel region T73 of the second reset transistor T7.
- the channel region of each transistor constitutes the active layer ACT (refer to FIG. 5 ).
- the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are integrally formed; the first electrode T51 of the second light-emitting control transistor T5 and the first electrode T51 of the driving transistor T1
- the diode T12 and the first electrode T31 of the threshold compensation transistor T3 are integrally formed; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2, and the second electrode T42 of the first light-emitting control transistor T4 are integrally formed;
- the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.
- the channel region (active layer) of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polysilicon (eg, low temperature polysilicon) or metal oxide semiconductor material (eg IGZO, AZO, etc.).
- the transistors are all P-type low temperature polysilicon (LTPS) thin film transistors.
- the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal-oxide-semiconductor thin-film transistors, that is, the channel material of the transistors is a metal-oxide-semiconductor material (such as IGZO , AZO, etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
- the transistors employed in the embodiments of the present disclosure may include various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
- the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
- a part of the light emission control signal line EML serves as the gate T40 of the first light emission control transistor T4
- a part of the light emission control signal line EML serves as the gate T50 of the second light emission control transistor T5
- the first reset transistor The gate T60 of T6 is part of the first reset control signal line RT1
- the gate T70 of the second reset transistor T7 is part of the second reset control signal line RT2
- the gate T20 of the data writing transistor T2 is the gate line GT Part of the gate T30 of the threshold compensation transistor T3 is part of the gate line GT.
- the threshold compensation transistor T3 is a dual-gate transistor, and the threshold compensation transistor T3 includes a first channel T331 and a second channel T332, and the first channel T331 and the second channel T332 pass through the first conductive connection part CP1 connected.
- the first reset transistor T6 is a double-gate transistor, the first reset transistor T6 includes a first channel T631 and a second channel T632, and the first channel T631 and the second channel T632 are connected through a second conductive connection connected to CP2.
- FIG. 6 shows the second conductive pattern layer LY2.
- a second gate insulating layer (the second gate insulating layer GI2 , see FIG. 18 ) is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1 .
- the second conductive pattern layer LY2 includes a stopper BK, a first initialization signal line INT1, a second initialization signal line INT2, and a second pole Cb of the storage capacitor Cst.
- the first initialization signal line INT1 extends along the first direction X
- the second initialization signal line INT2 extends along the first direction X.
- the first initialization signal line INT1 and the second initialization signal line INT2 are arranged along the second direction Y. As shown in FIG. 6 , the first initialization signal line INT1 and the second initialization signal line INT2 are located on both sides of the second pole Cb of the storage capacitor Cst, and the first initialization signal line INT1 and the second initialization signal line INT2 are located on the side of the stopper BK. On both sides, the second pole Cb of the storage capacitor Cst and the stopper BK are arranged between the first initialization signal line INT1 and the second initialization signal line INT2. As shown in FIG.
- the first initialization signal line INT1 , the stopper BK, the second pole Cb of the storage capacitor Cst, and the second initialization signal line INT2 are sequentially arranged along the second direction Y.
- the block BK is electrically connected to the first power line VDD1 so that the first power line VDD1 provides a constant voltage to the block BK.
- the orthographic projection of the stopper BK on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion CP1 on the base substrate. That is, the stopper BK is configured to block the first conductive connection portion CP1 between the two channels of the threshold compensation transistor T3, and the stopper BK forms a capacitance (stabilizing capacitance) with the first conductive connection portion CP1 to avoid the threshold compensation transistor T3 generates leakage current to avoid affecting the display effect. As shown in FIG. 7 , in plan view, the stopper BK and the first conductive connection portion CP1 partially overlap.
- the first initialization signal line INT1 and the second conductive connection portion CP2 partially overlap, and a capacitance (stable capacitance) is formed between the first initialization signal line INT1 and the second conductive connection portion CP2 to The leakage current of the first reset transistor T6 is avoided, and the display effect is avoided.
- element A and element B partially overlap, which may mean that a part of element A overlaps with element B, a part of element B overlaps with element A, or a part of element A overlaps with element B Some overlap.
- Element A and Element B are two different elements.
- the gate line GT extends along the first direction X
- the first reset control signal line RT1 extends along the first direction X
- the stopper BK is located between the gate line GT and the first reset control signal line RT1.
- the position of the stopper BK in the second direction Y is defined.
- the stopper BK includes a first portion BKa, a second portion BKb and a third portion BKc, the first portion BKa extends along the first direction X, the second portion BKb extends along the second direction Y, and the third portion BKb extends along the second direction Y.
- the part BKc extends along the first direction X, the first part BKa and the third part BKc are connected by the second part BKb, and the first part BKa and the second part BKb form an inverted T-shaped structure.
- the third portion BKc has a T-shaped structure.
- the first part BKa, the second part BKb and the third part BKc are located in the same layer and have an integral structure. The function of each part of the stopper of the shape shown in FIGS. 6 and 7 will be described later.
- the display panel includes a first conductive structure CDT1 , the first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1 , and the orthographic projection of the first conductive structure CDT1 on the substrate is the same as
- the orthographic projection of the blocking block BK on the base substrate at least partially overlaps, so that the blocking block BK shields the gate signal part PT1 of the driving transistor (including the gate T10 of the driving transistor T1 and the first conductive structure CDT1 ) and the parasitics of the data line Capacitance to reduce coupling effects and reduce longitudinal crosstalk.
- the orthographic projection of the first conductive structure CDT1 on the base substrate at least partially overlaps the orthographic projection of the third portion BKc of the stopper BK on the base substrate.
- the material of the first conductive structure CDT1 is the same as the material of the first conductive connection portion CP1.
- the first conductive structure CDT1 and the first conductive connection portion CP1 can be fabricated from the same film layer through the same process.
- the material of the first conductive structure CDT1 includes a conductive material obtained by doping a semiconductor material.
- the material of the first conductive structure CDT1 includes, but is not limited to, a conductive material obtained by doping polysilicon.
- the first conductive structure CDT1 is multiplexed as the second pole T62 of the first reset transistor T6 , then the second pole T62 of the first reset transistor T6 is on the base substrate.
- the orthographic projection at least partially overlaps the orthographic projection of the stopper BK on the base substrate.
- the first conductive structure CDT1 is used as an example of the second electrode T62 of the first reset transistor T6 for description.
- the first pole T61 of the first reset transistor T6 partially overlaps with the stopper BK, that is, the first pole T61 of the first reset transistor T6 is lining the The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the stopper BK on the base substrate. This arrangement can increase the area of the stopper and make it better shield.
- the data line DT has a first part P01 and a second part P02 , and the spacing SP1 between the first parts P01 of two adjacent data lines DT is larger than the second part of the two adjacent data lines DT
- the shielding portions CEs are located between the second portions P02 of the two adjacent data lines DT.
- the shielding portions CEs are also located between the first portions P01 of the two adjacent data lines DT.
- the second part P02 of the two adjacent data lines DT is close to the first light emission control transistor T4 and the second light emission control transistor T5 respectively, and the storage capacitor Cst is located in the first part of the two adjacent data lines DT Between P01.
- the second portion P02 of the two adjacent data lines DT may also be referred to as a narrowing portion. As shown in FIG. 16B , the two adjacent data lines DT are narrowed at the first light emission control transistor T4 and the second light emission control transistor T5 , does not narrow at the storage capacitor Cst.
- the orthographic projection of the shielding portion CEs on the base substrate at least partially overlaps with the orthographic projection of the first conductive structure CDT1 on the base substrate.
- the orthographic projection of the shielding portion CEs on the base substrate partially overlaps the orthographic projection of the second conductive connection portion CP2 of the first reset transistor T6 on the base substrate.
- the orthographic projection of the shielding portion CEs in the first pixel unit 101 a on the base substrate is the same as the second projection of the first reset transistor T6 in the third pixel unit 101 c
- the orthographic portion of the conductive connection portion CP2 on the base substrate overlaps.
- the orthographic projection of the shielding portion CEs in one pixel unit 101 on the base substrate is on the substrate with the second conductive connection portion CP2 of the first reset transistor T6 in the pixel unit located in the same column as the pixel unit in the next row.
- the orthographic portions of the substrates overlap.
- the block BK overlaps with the first conductive connection portion CP1 of the threshold compensation transistor T3 of the second pixel unit 101 b to form a stable capacitance to reduce leakage current. .
- the area A1 of the orthographic projection of the portion of the stopper BK overlapping the first conductive structure CDT1 (the second pole T62 of the first reset transistor T6 ) on the base substrate is larger than that of the stopper BK and the first electrode T62 .
- the area A0 of the orthographic projection of the overlapping portion of a conductive connection portion CP1 on the base substrate is larger than that of the orthographic projection of the overlapping portion of the stopper BK and the first conductive connection portion CP1 on the base substrate Area A0.
- the third conductive pattern layer LY3 includes a power supply connection line VDD0, a connection electrode CEa, a connection electrode CEb, a connection electrode CEc, a connection electrode CEd (second connection electrode CEd), and a connection electrode CEe (first connection electrode CEe) ).
- An interlayer insulating layer (interlayer insulating layer ILD, see FIG. 18 ) is provided between the third conductive pattern layer LY3 and the second conductive pattern layer LY2 .
- the power supply connection line VDD0 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through the via hole H2, and the power supply connection line VDD0 is electrically connected to the second pole Cb of the storage capacitor Cst through the via holes H3 and H30.
- the power connection line VDD0 is electrically connected to the conductive block BK through the via hole H0.
- One end of the connection electrode CEa is electrically connected to the first initialization signal line INT1 through the via hole H12, and the other end of the connection electrode CEa is connected to the first electrode T61 of the first reset transistor T6 through the via hole H11, so that the The first pole T61 is electrically connected to the first initialization signal line INT1.
- One end of the connecting electrode CEb is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole H22, and the other end of the connecting electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (that is, the first electrode of the storage capacitor Cst) through the via hole H21.
- electrode Ca is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (ie, the first electrode Ca of the storage capacitor Cst).
- connection electrode CEc is electrically connected to the second initialization signal line INT2 through the via hole H32, and the other end of the connection electrode CEc is connected to the first electrode T71 of the second reset transistor T7 through the via hole H31, thereby making the second reset transistor T7
- the first pole T71 is electrically connected to the second initialization signal line INT2.
- the connection electrode CEd is electrically connected to the second electrode T52 of the second light-emitting control transistor T5 through the via hole H40.
- the connection electrode CEd can be used to connect to the connection electrode CEf to be formed later, so as to be electrically connected to the first electrode 201 (refer to FIG. 17 ) of the light-emitting element 20 .
- the connection electrode CEe is electrically connected to the first electrode T21 of the data writing transistor T2 through the via hole H5.
- the connection electrode CEe is used for connection with the data line.
- FIG. 14 shows the fourth conductive pattern layer LY4.
- the fourth conductive pattern layer LY4 includes a data line DT, a connection electrode CEf, and a first power supply line VDD1.
- a passivation layer (passivation layer PVX, see FIG. 18 ) and a first planarization layer (first planarization layer PLN1 , see FIG. 18 ) are provided between the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 .
- the first power supply line VDD1 is connected to the power supply connection line VDD0 through the via hole H6 penetrating the passivation layer and the first planarization layer
- the connection electrode CEf is connected to the connection electrode CEd through the via hole H7 penetrating the passivation layer and the first planarization layer.
- the data line DT is connected to the connection electrode CEe through the via hole H8 penetrating the passivation layer and the first planarization layer, and is further electrically connected to the first electrode T21 of the data writing transistor T2.
- the connection electrode CEf (third connection electrode CEf) and the connection electrode CEd (second connection electrode CEd) constitute the connection element CE0.
- the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0.
- the pixel circuit 10 is connected to the connection electrode CEd (the second connection electrode CEd), the connection electrode CEd (the second connection electrode CEd) is connected to the connection electrode CEf (the third connection electrode CEf), and the connection electrode CEf (the third connection electrode CEf) ) is connected to the light-emitting element 20.
- FIG. 14 shows the first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4.
- Fig. 14 also shows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d.
- the data line DT extends along the second direction Y, and the first data line DT1 , the third data line DT3 , the fourth data line DT4 and the second data line DT2 are arranged along the first direction X .
- the fourth data line DT4 is located between the third data line DT3 and the second data line DT2.
- the first pixel unit 101a and the second pixel unit 101b are located in the same row and in adjacent columns, and the third pixel unit 101c and the fourth pixel unit 101d are located in the same row and in adjacent columns.
- the first pixel unit 101a and the third pixel unit 101c are located in the same column and in adjacent rows, and the second pixel unit 101b and the fourth pixel unit 101d are located in the same column and in adjacent rows.
- the data line DT and the gate line GT cross each other and are insulated from each other.
- the first power supply line VDD1 is configured to supply the first voltage signal ELVDD to the pixel circuit 10 .
- the first power line VDD1 is electrically connected to the stopper BK to provide a constant voltage to the stopper BK.
- the first power supply line VDD1 is connected to the first power supply terminal VDD, and the second pole Cb of the storage capacitor Cst is connected to the first power supply line VDD1.
- the second pole Cb of the storage capacitor Cst is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1.
- FIG. 15 shows a plan view of the structure after the fourth conductive pattern layer LY4 is formed.
- the first pole T41 of the first light emission control transistor T4 is connected to the first power supply terminal VDD through the power supply connection line VDD0 and the first power supply line VDD1 (refer to FIGS. 10 and 15 ).
- the display panel includes the second conductive structure CDT2 , and the orthographic projection of the block BK on the base substrate at least partially overlaps the orthographic projection of the second conductive structure CDT2 on the base substrate , so as to shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid abnormal display caused by coupling.
- the blocking block BK overlaps with the first conductive connection portion CP1 of the threshold compensation transistor T3 of the second pixel unit 101b, and overlaps with the second conductive connection portion of the first pixel unit 101a.
- the structure CDT2 overlaps.
- the material of the second conductive structure CDT2 is the same as that of the first conductive structure CDT1.
- the first electrode T21 of the data writing transistor T2 is multiplexed into the second conductive structure CDT2 .
- the first electrode T21 of the data writing transistor T2 is used as the second conductive structure CDT2 as an example for description, but it is not limited thereto.
- the data line DT, the connection electrode CEe, and the second conductive structure CDT2 constitute the data signal portion PT2.
- the data line DT, the connection electrode CEe and the second conductive structure CDT2 constitute the same node.
- the potentials on the data line DT, the connection electrode CEe and the second conductive structure CDT2 are the same or substantially the same. That is, the potential at each position on the data signal portion PT2 is the same or substantially the same. Therefore, the blocking block BK overlaps with the second conductive structure CDT2, which can shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid abnormal display caused by coupling .
- the area A2 of the orthographic projection of the portion of the stopper BK overlapping the second conductive structure CDT2 (the first pole T21 of the data writing transistor T2 ) on the base substrate is larger than that of the stopper BK and the first conductive structure.
- the data line DT is connected to the connection electrode CEe through the via hole H8, and further connected to the second conductive structure CDT2.
- the area A1 of the orthographic projection of the portion of the stopper BK that overlaps the first conductive structure CDT1 on the base substrate is larger than the area A1 of the portion of the stopper BK that overlaps the second conductive structure CDT2 on the base substrate.
- area A1 is larger than area A2
- area A2 is larger than area A0. That is, the area A1 , the area A2 , and the area A0 decrease sequentially, but the embodiment of the present disclosure is not limited thereto.
- the stopper BK is located in the second conductive structure CDT2 (the first pole T21 of the data writing transistor T2 ). ) and the third data line DT3.
- the orthographic projection of the stopper BK on the base substrate partially overlaps the orthographic projection of the third data line DT3 on the base substrate, so that the stopper BK shields the first data line DT1 on the first data line DT1 Interference between the data signal and the third data signal on the third data line DT3 avoids display abnormality caused by coupling.
- the orthographic projection of the first portion BKa of the stopper BK on the base substrate partially overlaps the orthographic projection of the third data line DT3 on the base substrate, so that the first portion BKa of the stopper BK is shielded. Interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3 avoids display abnormality caused by coupling.
- one stopper BK corresponds to two pixel units in the same row. As shown in FIG. 15, in plan view, the stopper BK is located between the first data line DT1 and the second data line DT2.
- the orthographic projection of the first electrode T21 of the data writing transistor T2 on the base substrate at least partially overlaps the orthographic projection of the third data line DT3 on the base substrate.
- the stopper BK extends leftward into the first pixel unit 101a adjacent to the second pixel unit 101b such that the stopper BK has a portion located between the first data line DT1 and the third data line DT3 , so as to shield the interference between the first data signal on the first data line DT1 and the third data signal on the third data line DT3, and avoid abnormal display caused by coupling.
- the first data line DT1 and the third data line DT3 are two adjacent data lines.
- two adjacent elements C means that the two elements C are adjacent to each other, and no element C is disposed therebetween, but it does not exclude that there is also an element C between the two adjacent elements C.
- Elements other than element C are provided.
- the 120Hz driving scheme adopts the time-sharing writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and then written into the pixel unit.
- the interference between the data signals will affect the accurate writing of the data signal. Affect the display effect; the design of the block BK extending to the left to shield can improve this problem very well.
- the gate T10 of the driving transistor T1 is in a floating state during the light-emitting phase and is held by the storage capacitor Cst. Due to the parasitic capacitance between the gate and the data line, the transition of the data signal will be coupled to the driving The gate signal portion (the first node N1 ) of the transistor cannot be restored to the initial state, so that vertical crosstalk occurs.
- the blocking block BK extends to the right, overlaps with the first conductive structure CDT1 of the first pixel unit 101 a (the second pole T62 of the first reset transistor T6 ), and covers the driving transistor of the first pixel unit 101 a
- the signal on the gate T10 of T1 shields the parasitic capacitance of the gate T10 of the driving transistor T1 (the gate signal portion PT1 of the driving transistor) and the data line, thereby reducing the coupling effect and reducing the vertical crosstalk.
- the length of the connection electrode CEf in the second direction Y in the display panel is adjusted. As shown in FIGS. 16A and 16B , the length of the connection electrode CEf in the second direction Y is increased.
- the connection electrodes CEf shown in FIGS. 16A and 16B may be referred to as shield portions CEs.
- the shield portion CEs and the connection electrode CEd (second connection electrode CEd) constitute the connection element CE0.
- the shielding portion CEs can replace the connecting electrode CEf, and no additional process is required.
- the other end of the connecting electrode CEb is electrically connected to the gate T10 of the driving transistor T1 (ie, the first electrode Ca of the storage capacitor Cst) through the via hole H21, and one end of the connecting electrode CEb is electrically connected to the gate electrode T10 of the driving transistor T1 through the via hole H22.
- the second electrode T62 of the first reset transistor T6 is electrically connected, and the connection electrode CEb may also be referred to as a connection line CL.
- the gate T10 of the driving transistor T1 is connected to the second electrode T32 of the threshold compensation transistor T3 through the connection line CL.
- the first conductive structure CDT1 is connected to the gate T10 of the driving transistor T1 through the connection line CL.
- the gate T10 of the driving transistor T1 is connected to the first conductive structure CDT1 through the wiring CL.
- the material of the first conductive structure CDT1 is different from the material of the connection line CL.
- the material of the connection line CL includes metal.
- connection line CL is in contact with the gate T10 of the driving transistor T1.
- the connection line CL is in contact with the first conductive structure CDT1. That is, both ends of the connection line CL are in contact with the gate electrode T10 of the driving transistor T1 and the first conductive structure CDT1, respectively.
- the first conductive structure CDT1 , the connection line CL and the gate T10 of the driving transistor T1 constitute the gate signal portion PT1 of the driving transistor T1 . Therefore, the overlapping of the blocking block BK with the first conductive structure CDT1 can shield the parasitic capacitance of the gate signal portion of the driving transistor and the data line, and reduce the vertical crosstalk.
- the first conductive structure CDT1, the connection line CL and the gate T10 of the driving transistor T1 constitute the same node.
- the potentials on the first conductive structure CDT1, the connection line CL and the gate T10 of the driving transistor T1 are the same or substantially the same. That is, the potential at each position on the gate signal portion PT1 is the same or substantially the same.
- the shielding portions CEs extend in the second direction Y.
- the extending direction of the shielding portions CEs is the same as the extending direction of the data line DT.
- the light-emitting element 20 is connected to the pixel circuit 10 through the connection element CE0.
- the extending manner of a component refers to the general trend or trend of the component, and not necessarily all positions of the component extend along the extending direction.
- the data lines DT and the shielding portions CEs are located on the same layer, and both the data lines DT and the shielding portions CEs are located on the fourth conductive pattern layer LY4 .
- the data line DT includes two adjacent data lines DT, the shielding portion CEs is located between the two adjacent data lines DT, the orthographic projection of the shielding portion CEs on the base substrate BS and the positive projection of the connecting line CL on the base substrate BS.
- the projections overlap at least partially.
- two adjacent data lines DT are arranged in the first direction X, and the data lines DT extend in the second direction.
- the data line DT includes a first data line DT1 and a third data line DT3, the first data line DT1 and the third data line DT3 are adjacent, and in the first direction X, the shielding portion CEs between the first data line DT1 and the third data line DT3.
- the fact that part A and part B are adjacent means that part A and part B do not have part A or part B between them.
- the shielding portion CEs extends along the second direction and is inserted between two adjacent data lines DT, and the shielding effect is more obvious at a position where the adjacent data lines are closer.
- the embodiments of the present disclosure are described by taking an example that the data lines DT and the shielding portions CEs are located on the same layer. In other embodiments, the data lines DT and the shielding portions CEs are located on the same layer or may be located on different layers.
- the orthographic projection of the shielding portion CEs on the base substrate BS and the orthographic projection of the connection line CL on the base substrate BS at least partially overlap, so that the shielding portion CEs shields the gate signal portion of the driving transistor and the Parasitic capacitance between data lines, alleviating longitudinal crosstalk problems.
- the 120Hz driving scheme adopts the time-sharing writing method, that is, the data signal is first stored in the storage capacitor, and then the scanning signal is turned on and then written into the pixel unit.
- the interference between the data signals will affect the accurate writing of the data signal. affect the display effect.
- the shielding portions CEs are located between two adjacent data lines DT, and the orthographic projection of the connection line CL on the base substrate BS at least partially intersects the orthographic projection of the shielding portions CEs on the base substrate BS Stacking can reduce the coupling effect and improve this problem. It should be noted that the shielding portion CEs is located between two adjacent data lines DT, which is the setting position of the described shielding portion CEs.
- the shielding portion CEs is located between two adjacent data lines DT, but every two adjacent data lines DT
- the shielding portions CEs are not necessarily provided between the lines DT.
- the first data line DT1 and the third data line DT3 are adjacent to each other, the shielding portion CEs is located between the first data line DT1 and the third data line DT3, and the fourth data line DT4 and the second data line DT4
- the line DT2 is adjacent, and the shielding portion CEs is located between the fourth data line DT4 and the second data line DT2.
- the shielding portion CEs is not provided therebetween.
- the orthographic projection of the shielding portion CEs on the base substrate BS is larger than the orthographic projection of the connection line CL on the base substrate BS.
- the orthographic projection of the shielding portions CEs on the base substrate BS overlaps the orthographic projection of the connection line CL on the base substrate BS.
- the shield portions CEs cover the connection lines CL.
- the main surface of the base substrate BS is a surface for producing the respective components, and the respective components are provided on the main surface of the base substrate BS.
- the orthographic projection of the gate T10 of the driving transistor T1 on the base substrate BS partially overlaps the orthographic projection of the shielding portion CEs on the base substrate BS, and the shielding portion CEs and the driving transistor
- the area of the overlapping portion of the gate electrode T10 of T1 is smaller than that of the gate electrode T10 of the driving transistor T1.
- the size of the gate T10 of the driving transistor T1 in the first direction X is larger than the size of the shielding portion CEs in the first direction X; the size of the shielding portion CEs in the second direction Y is larger than that of the driving transistor The dimension of the gate of T1 in the second direction Y.
- the gate T10 of the driving transistor T1 protrudes from the shielding portions CEs from both sides in the first direction X, respectively.
- the orthographic projections of the shielding portions CEs on the base substrate BS overlap with the orthographic projections of the gate lines GT on the base substrate BS.
- the orthographic projection of the gate line GT on the base substrate BS partially overlaps the orthographic projection of the shielding portions CEs on the base substrate BS.
- the pixel unit includes two adjacent pixel units located in the same column, and the two adjacent data lines DT are respectively connected to the two pixel units.
- FIG. 16A shows the positions of the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c, and the fourth pixel unit 101d.
- FIG. 16A shows the first data line DT1, the second data line DT2, the third data line DT3, and the fourth data line DT4. 16A and 17, the first data line DT1 is connected to the first pixel unit 101a, the second data line DT2 is connected to the second pixel unit 101b, the third data line DT3 is connected to the third pixel unit 101c, and the fourth data line DT4 is connected to the fourth pixel unit 101d.
- the first data line DT1 is configured to provide a first data signal to the pixel circuit of the first pixel unit 101a.
- the second data line DT2 is configured to provide a second data signal to the pixel circuit of the second pixel unit 101b.
- the third data line DT3 is configured to supply a fourth data signal to the pixel circuit of the third pixel unit 101c.
- the fourth data line DT4 is configured to supply a fourth data signal to the pixel circuit of the fourth pixel unit 101d.
- the orthographic projection of the stopper BK on the base substrate partially overlaps the orthographic projection of the fourth data line DT4 on the base substrate.
- the block BK has a first edge E1 , the first edge E1 and the The fourth data lines DT4 overlap, and the included angle ⁇ 1 between the first edge E1 and the fourth data line DT4 is greater than zero and less than 90°.
- the included angle ⁇ 1 between the first edge E1 and the extending direction of the fourth data line DT4 is greater than zero and less than 90°.
- the extending direction of the fourth data line DT4 is the second direction Y.
- the first edge E1 is inclined with respect to the fourth data line DT4.
- the block BK has a second edge E2 , and the second edge E2 is the same as the second edge E2 .
- the third data lines DT3 overlap, and the included angle ⁇ 2 between the second edge E2 and the third data line DT3 is greater than zero and less than 90°.
- the included angle ⁇ 2 between the second edge E2 and the extending direction of the third data line DT3 is greater than zero and less than 90°.
- the extending direction of the third data line DT3 is the second direction Y.
- the second edge E2 is inclined with respect to the third data line DT3.
- This arrangement is beneficial to reduce the overlapping area of the third data line DT3 and the block BK, reduce parasitic capacitance, and avoid affecting the data writing speed of the third pixel unit.
- the first pixel unit 101a, the second pixel unit 101b, the third pixel unit 101c and the fourth pixel unit 101d constitute one repeating unit RP.
- a plurality of repeating units RP can form an array.
- the repeating unit RP is one smallest repeating unit of the display array.
- the first reset transistor T6 and the second reset transistor T7 are connected to the same reset control signal line RT to be inputted with the same reset control signal at the same time, but the implementation of the present disclosure The example is not limited to this.
- the first reset transistor T6 and the second reset transistor T7 may also be connected to the first reset control signal line and the second reset control signal line, respectively.
- the first reset control signal line and the second reset control signal line are insulated from each other to be input signals, respectively.
- signals are input to the first reset transistor T6 and the second reset transistor T7 at different times.
- the first reset transistor T6 is input with the reset control signal RESET in the first reset phase t1
- the second reset transistor T7 is input with the reset control signal RESET.
- T7 is input with the scan signal SCAN during data writing and threshold compensation and the second reset phase t2.
- the gate line GT of the present stage is connected to the reset control signal line of the next stage.
- the gate line GT and the second reset control signal line RT2 may be electrically connected to input the same signal at the same time.
- the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 through the connection line CL.
- the second electrode T62 of the first reset transistor T6 is integrally formed with the second electrode T32 of the threshold compensation transistor T3, so that the second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
- the orthographic projection of the shielding portions CEs on the base substrate BS at least partially overlaps the orthographic projection of the second pole T62 of the first reset transistor T6 on the base substrate BS.
- the orthographic projection of the shielding portion CEs on the base substrate BS is at the same level as the second electrode T32 of the threshold compensation transistor T3.
- the orthographic projections on the base substrate BS at least partially overlap.
- the orthographic projection of the shielding portion CEs on the base substrate BS does not overlap with the orthographic projection of the stopper BK on the base substrate BS, so that the shielding portion CEs is in the second direction Y The upper end position of .
- the first initialization signal line INT1 and the second initialization signal line INT2 are respectively provided on opposite sides of the gate T10 of the driving transistor T1, and the orthographic projection of the shielding portion CEs on the base substrate BS It overlaps with the orthographic portion of the second initialization signal line INT2 on the base substrate BS.
- the orthographic projection of the shielding portion CEs on the base substrate BS partially overlaps the orthographic projection of the second conductive connection portion CP2 of the pixel unit in the next row on the base substrate BS, so that the second conductive connection portion A capacitor is formed between the CP2 and the shielding portion CEs, and the capacitor acts as a stabilizing capacitor to reduce the leakage current of the first reset transistor T6.
- the shielding portion CEs does not overlap the orthographic projection of the first initialization signal line INT1 on the base substrate BS.
- the first reset control signal line RT1 and the second reset control signal line RT2 are respectively disposed on opposite sides of the gate T10 of the driving transistor T1 , and referring to FIG. 17 , the second reset control signal line RT2 is on the substrate
- the orthographic projection on the substrate BS and the orthographic projection of the shielding portions CEs on the base substrate BS do not overlap. Thereby, the lower end position of the shielding portion CEs in the second direction Y is defined.
- the orthographic projection of the first reset control signal line RT1 on the base substrate BS and the orthographic projection of the shielding portions CEs on the base substrate BS do not overlap.
- the first reset control signal line extends along the first direction X
- the second reset control signal line extends along the first direction X.
- each connection electrode CEf is connected to one light-emitting element, that is, each connection electrode CEf corresponds to one pixel unit 101 .
- each shielding portion CEs is connected to one light-emitting element, that is, each shielding portion CEs corresponds to one pixel unit 101 .
- the orthographic projection of the first gate T601 and the second gate T602 of the first reset transistor T6 on the base substrate BS is the same as the first channel T631 and the second channel T632 of the first reset transistor T6
- the orthographic projections on the base substrate BS overlap, respectively.
- the first power supply line VDD1 is connected to the second pole Cb of the storage capacitor Cst through the power supply connection line VDD0 .
- the threshold compensation transistor T3 is a double-gate transistor, and the intermediate node (the first conductive connection portion CP1 ) of the threshold compensation transistor T3 will be disturbed by the transition of the scan signal, and the voltage increases at the moment when the scan signal is turned off, and the driving transistor T1 The gate leakage will increase, which will lead to flicker (Flicker) problem.
- the orthographic projection of the stopper BK on the base substrate BS at least partially overlaps the orthographic projection of the first conductive connection portion CP1 on the base substrate BS .
- a stable capacitance is formed between the block BK and the first conductive connection portion CP1. Increasing the parasitic capacitance between the intermediate node of the threshold compensation transistor T3 and the first voltage signal ELVDD can reduce the amount of disturbance and improve the leakage problem.
- a pixel circuit is formed on a base substrate to form the display panel shown in FIG. 15 or FIG. 17 , and on the basis of the display panel shown in FIG. 15 or FIG. 17 , light-emitting elements are formed to obtain a display panel capable of displaying, thereby , the pixel circuit is closer to the base substrate than the light-emitting element. As shown in FIG. 20 , the pixel circuit 10 is closer to the base substrate BS than the light-emitting element 20 is.
- FIG. 18 is a cross-sectional view taken along line AB in FIG. 17 .
- FIG. 19 shows the first pole 201 of the light emitting element 20 .
- 17 is a cross-sectional view of a display panel according to an embodiment of the disclosure.
- the film layer on the first pole 201 of the light-emitting element is omitted.
- the layers above the first pole 201 of the light-emitting element 20 can be referred to in cross-sectional views.
- the arrangement position and shape of the first pole 201 of the light-emitting element are not limited to those shown in FIG. 19 , and those skilled in the art can adjust the arrangement position and shape of the first pole 201 of the light-emitting element as required.
- the buffer layer BL is located on the base substrate BS
- the isolation layer BR is located on the buffer layer BL
- the channel region, source and drain of the transistor are located on the isolation layer BR
- the channel region, the source and the drain of the transistor are located on the isolation layer BR.
- a first gate insulating layer GI1 is formed on the source and drain electrodes, the first conductive pattern layer LY1 is located on the first gate insulating layer GI1, the second gate insulating layer GI2 is located on the first conductive pattern layer LY1, and the second conductive pattern layer LY2 is located on the second gate insulating layer GI2, the interlayer insulating layer ILD is located on the second conductive pattern layer LY2, the third conductive pattern layer LY3 is located on the interlayer insulating layer ILD, and the passivation layer PVX is located on the first conductive pattern layer LY,
- the first planarization layer PLN1 is located on the passivation layer PVX, and the fourth conductive pattern layer LY4 is located on the first planarization layer PLN1.
- the second planarization layer PLN2 is located on the fourth conductive pattern layer LY4, the first pole 201 of the light emitting element 20 is located on the second planarization layer PLN2, the pixel definition layer PDL and the spacer PS are located on the second planarization layer
- the pixel defining layer PDL has an opening OPN, and the opening OPN is configured to define a light-emitting area (light-emitting area, effective light-emitting area) of the pixel unit.
- the spacer PS is configured to support the fine metal mask when the light emitting functional layer 203 is formed.
- the opening OPN is the light emitting area of the pixel unit.
- the light emitting functional layer 203 is located on the first pole 201 of the light emitting element 20
- the second pole 202 of the light emitting element 20 is located on the light emitting functional layer 203
- the encapsulation layer CPS is disposed on the light emitting element 20 .
- the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
- the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers
- the second encapsulation layer CPS2 is an organic material layer.
- the first electrode 201 is the anode of the light-emitting element 20
- the second electrode 202 is the cathode of the light-emitting element 20, but it is not limited thereto.
- the first electrode 201 of the light emitting element 20 is connected to the shielding portion CEs (connection electrode CEf) through a via hole H9 penetrating the second planarization layer PLN2.
- the light emitting element 20 includes an organic light emitting diode.
- the light-emitting functional layer 203 is located between the second pole 202 and the first pole 201 .
- the second electrode 202 is located on the side of the first electrode 201 away from the base substrate BS.
- the light-emitting functional layer 203 includes at least a light-emitting layer, and may also include a hole transport layer, a hole injection layer, and at least one of the electron transport layer and the electron injection layer. one.
- the second electrode Cb of the storage capacitor has an opening OPN1 , and the setting of the opening OPN1 facilitates the connection between the connecting electrode CEb and the gate T10 of the driving transistor T1 .
- the transistors in the pixel circuits of the embodiments of the present disclosure are all thin film transistors.
- the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, and the fourth conductive pattern layer LY4 are all made of metal materials.
- the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto.
- the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are formed of materials such as titanium, aluminum, etc., but are not limited thereto.
- the third conductive pattern layer LY3 and the fourth conductive pattern layer LY4 are structures formed by three sub-layers of Ti/AL/Ti, respectively, but not limited thereto.
- a glass substrate or a polyimide substrate can be used as the base substrate, but it is not limited thereto, and can be selected as required.
- the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, the spacer PS All are made of insulating material.
- the materials of the first pole 201 and the second pole 202 of the light-emitting element can be selected as required.
- the first electrode 201 may be at least one of transparent conductive metal oxide and silver, but not limited thereto.
- the transparent conductive metal oxide includes, but is not limited to, indium tin oxide (ITO).
- ITO indium tin oxide
- the first pole 201 may adopt a structure in which three sub-layers of ITO-Ag-ITO are provided.
- the second pole 202 may be a low work function metal, at least one of magnesium and silver may be used, but not limited thereto.
- the stopper BK of the structure shown in FIG. 6 may not be provided, and of course, the shielding portion CEs shown in FIG. 16A may not be provided.
- the stopper BK is not provided, or a stopper of other shape or structure is provided.
- shields CEs are not provided, but connection electrodes CEf as shown in FIG. 14 are provided.
- the display panel provided by the embodiments of the present disclosure can be fabricated according to the structure of the display panel.
- a feasible manufacturing method is listed below. It should be noted that the manufacturing method of the display panel provided by the embodiments of the present disclosure is not limited to the following method.
- the manufacturing method will be described with reference to the preceding figures.
- the manufacturing method of the display panel provided by the embodiment of the present disclosure includes the following steps.
- Step S1 forming a buffer layer BL on the base substrate.
- Step S2 forming an isolation layer BR on the buffer layer BL.
- Step S3 forming a semiconductor pattern SCP on the isolation layer BR.
- Step S4 forming a first gate insulating layer GI1 on the semiconductor pattern SCP.
- Step S5 forming a first conductive film on the first gate insulating layer GI1 , and patterning the first conductive film to form a first conductive pattern layer LY1 .
- Step S6 using the first conductive pattern layer LY1 as a mask to dope the semiconductor pattern SCP to form an active layer ACT, a source electrode and a drain electrode of the transistor.
- Step S7 forming a second gate insulating layer GI2.
- Step S8 forming a second conductive film on the second gate insulating layer GI2, and patterning the second conductive film to form a second conductive pattern layer LY2.
- Step S9 forming an interlayer insulating layer ILD on the second conductive pattern layer LY2.
- Step S10 forming a via hole in at least one of the first gate insulating layer GI1 , the second gate insulating layer GI2 and the interlayer insulating layer ILD (refer to FIG. 8 ).
- Step S11 forming a third conductive film on the interlayer insulating layer ILD, and patterning the third conductive film to form a third conductive pattern layer LY3 .
- the components in the third conductive pattern layer LY3 are connected to the components in the second conductive pattern layer LY2 and the source and drain electrodes of the transistors through via holes, respectively.
- Step S12 forming a passivation layer PVX and a first planarization layer PLN1.
- Step S13 forming via holes in the passivation layer PVX and the first planarization layer PLN1 (refer to FIG. 12 ).
- Step S14 forming a fourth conductive film on the first planarization layer PLN1 , and patterning the fourth conductive film to form a fourth conductive pattern layer LY4 .
- Features in the fourth conductive pattern layer LY4 may be connected to features in the third conductive pattern layer LY3 through vias in the passivation layer PVX and the first planarization layer PLN1.
- Step S15 forming the first pole 201 of the light emitting element 20 on the fourth conductive pattern layer LY4.
- Step S16 forming a pixel definition layer PDL and a spacer PS.
- Step S17 forming the light-emitting functional layer 203 of the light-emitting element 20 .
- Step S18 forming the second pole 202 of the light-emitting element 20 .
- Step S19 forming a packaging layer CPS.
- At least one embodiment of the present disclosure further provides a display device including any one of the above-mentioned display panels.
- the display device includes an OLED or a high frame rate driven product including an OLED.
- the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which contain the above-mentioned display panel.
- the above description takes a 7T1C pixel circuit as an example, and embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
- the pixel circuit of the display panel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
- elements located in the same layer may be processed by the same patterning process from the same film layer.
- elements located on the same layer may be located on a surface of the same element remote from the base substrate.
- the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
- the lithography process refers to the process of film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
- Corresponding patterning processes may be selected according to the structures formed in the embodiments of the present disclosure.
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Abstract
一种显示面板和显示装置。显示面板包括:衬底基板(BS);像素单元(101),位于衬底基板(BS)上,包括像素电路(10)和发光元件(20),像素电路(10)被配置为驱动发光元件(20),像素电路(10)比发光元件(20)更靠近衬底基板(BS),像素电路(10)包括驱动晶体管(T1);数据线(DT),被配置为向像素电路(10)提供数据信号;连接元件(CE0),发光元件(20)通过连接元件(CE0)与像素电路(10)相连,连接元件(CE0)包括屏蔽部(CEs);以及连接线(CL),与驱动晶体管(T1)的栅极(T10)相连;数据线(DT)包括两条相邻数据线(DT),屏蔽部(CEs)位于两条相邻数据线(DT)之间,连接线(CL)在衬底基板(BS)上的正投影与屏蔽部(CEs)在衬底基板(BS)上的正投影至少部分交叠。
Description
相关申请的交叉引用
出于所有目的,本专利申请要求于2020年12月28日递交的PCT专利申请第PCT/CN2020/140199号的优先权,在此全文引用上述PCT专利申请公开的内容以作为本公开的实施例的一部分。
本公开至少一实施例涉及一种显示面板和显示装置。
随着显示技术的不断发展,有源矩阵型有机发光二极管(Active-Matrix Organic Light-Emitting Diode,AMOLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经在手机、平板电脑、数码相机等显示装置上得到越来越多地应用。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
一方面,本公开的至少一实施例提供一种显示面板,包括:衬底基板;像素单元,位于所述衬底基板上,包括像素电路和发光元件,所述像素电路被配置为驱动所述发光元件,所述像素电路包括驱动晶体管和阈值补偿晶体管,所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连,所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极相连;第一电源线,被配置为向所述像素电路提供第一电源电压;挡块,与所述第一电源线电连接;以及第一导电结构,所述第一导电结构与所述驱动晶体管的栅极相连,其中,所述阈值补偿晶体管包括第一沟道和第二沟道,所述第一沟道和所述第二沟道通过导电连接部相连;所述挡块在所述衬底基板上的正投影与所述导电连接部在所述衬底基板上的正投影至少部分交叠;所述第一导电结构在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠;所述挡块的与所述第一导电结构交叠的部分在所述衬底基板上的正投影的面积大于所述挡块的与所述导电连接部交叠的部分在所述衬底基板上的正投影的面积。
例如,在本公开的一些实施例中,所述第一导电结构的材料与所述导电连接部的材料相同。
例如,在本公开的一些实施例中,所述第一导电结构的材料包括半导体材料经掺杂而得的导电材料。
例如,在本公开的一些实施例中,显示面板还包括连接线,所述第一导电结构通过所述连接线与所述驱动晶体管的栅极相连。
例如,在本公开的一些实施例中,所述第一导电结构的材料与所述连接线的材料不同。
例如,在本公开的一些实施例中,所述连接线与所述驱动晶体管的栅极和所述第一导电结构分别接触。
例如,在本公开的一些实施例中,所述第一导电结构、所述连接线和所述驱动晶体管的栅极构成所述驱动晶体管的栅信号部。
例如,在本公开的一些实施例中,所述像素电路还包括第一复位晶体管,所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连,所述第一导电结构复用为所述第一复位晶体管的第二极。
例如,在本公开的一些实施例中,显示面板还包括第一复位控制信号线和第一初始化信号线,所述第一复位晶体管的栅极与所述第一复位控制信号线相连,所述第一复位晶体管的第一极与所述第一初始化信号线相连,所述第一复位晶体管的第一极在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,显示面板还包括数据线和第二导电结构,所述数据线被配置为向所述像素电路提供数据信号,所述数据线与所述第二导电结构相连,所述挡块在所述衬底基板上的正投影与所述第二导电结构在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述挡块的与所述第二导电结构交叠的部分在所述衬底基板上的正投影的面积大于所述挡块的与所述导电连接部交叠的部分在所述衬底基板上的正投影的面积。
例如,在本公开的一些实施例中,所述挡块的与所述第一导电结构交叠的部分在所述衬底基板上的正投影的面积大于所述挡块的与所述第二导电结构交叠的部分在所述衬底基板上的正投影的面积。
例如,在本公开的一些实施例中,所述挡块在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,显示面板还包括栅线,所述阈值补偿晶体管的栅极与所述栅线相连,所述像素电路还包括数据写入晶体管,所述数据写入晶体管的第一极与所述数据线相连,所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连,所述数据写入晶体管的栅极与所述栅线相连,所述第二导电结构复用为所述数据写入晶体管的第一极。
例如,在本公开的一些实施例中,显示面板还包括第一连接电极,所述数据线通过所述第一连接电极与所述第二导电结构相连。
例如,在本公开的一些实施例中,所述数据线、所述第一连接电极和所述第二导电结构构成数据信号部。
例如,在本公开的一些实施例中,所述像素单元包括第一像素单元、第二像素单元和第三像素单元,所述第一像素单元和所述第二像素单元在第一方向上相邻,所述第一像素单元和所述第三像素单元在第二方向上相邻,所述第一方向与所述第二方向相交;所述数据线包括第一数据线、第二数据线和第三数据线,所述第一数据线被配置为向所述第一像 素单元的所述像素电路提供第一数据信号;所述第二数据线被配置为向所述第二像素单元的所述像素电路提供第二数据信号,所述第三数据线被配置为向所述第三像素单元的所述像素电路提供第三数据信号,所述第三数据线位于所述第一数据线和所述第二数据线之间;所述挡块在所述衬底基板上的正投影与所述第三数据线在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述挡块位于所述第一数据线和所述第二数据线之间。
例如,在本公开的一些实施例中,在垂直于所述衬底基板的方向上,所述挡块位于所述第二导电结构和所述第三数据线之间。
例如,在本公开的一些实施例中,所述第二导电结构在所述衬底基板上的正投影与所述第三数据线在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,显示面板还包括连接元件,所述发光元件通过所述连接元件与所述像素电路相连,所述连接元件包括屏蔽部,所述数据线包括两条相邻数据线,所述屏蔽部位于所述两条相邻数据线之间,所述连接线在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述连接元件还包括第二连接电极,所述像素电路与所述第二连接电极相连,所述第二连接电极与所述屏蔽部相连,所述屏蔽部与所述发光元件相连。
例如,在本公开的一些实施例中,所述像素单元还包括第四像素单元,所述第四像素单元与所述第二像素单元在所述第二方向上相邻,所述第四像素单元与所述第三像素单元在所述第一方向上相邻,所述数据线还包括第四数据线,所述第四数据线被配置为向第四像素单元的所述像素电路提供第四数据信号,所述挡块在所述衬底基板上的正投影与所述第四数据线在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述挡块具有第一边缘,所述第一边缘与所述第四数据线交叠,所述第一边缘与所述第四数据线之间的夹角大于零并且小于90°。
例如,在本公开的一些实施例中,所述挡块具有第二边缘,所述第二边缘与所述第三数据线交叠,所述第二边缘与所述第三数据线之间的夹角大于零并且小于90°。
例如,在本公开的一些实施例中,所述第四数据线位于所述第三数据线和所述第二数据线之间。
例如,在本公开的一些实施例中,所述第一像素单元、所述第二像素单元、所述第三像素单元和所述第四像素单元构成重复单元。
例如,在本公开的一些实施例中,所述挡块包括第一部分、第二部分和第三部分,所述第一部分沿第一方向延伸,所述第二部分沿第二方向延伸,所述第三部分沿所述第一方向延伸,所述第一部分和所述第三部分通过所述第二部分相连,所述第一部分和所述第二部分构成倒T形结构。
例如,在本公开的一些实施例中,所述第一部分、所述第二部分和所述第三部分位于 同一层,且为一体结构。
例如,在本公开的一些实施例中,所述像素电路还包括存储电容,所述存储电容的第一极与所述驱动晶体管的栅极相连,所述存储电容的第二极与所述第一电源线相连。
例如,在本公开的一些实施例中,显示面板还包括第二复位控制信号线和第二初始化信号线,所述像素电路还包括第二复位晶体管,所述第二复位晶体管的栅极与所述第二复位控制信号线相连,所述第二复位晶体管的第一极与所述第二初始化信号线相连,所述第二复位晶体管的第二极与所述发光元件的第一极相连。
例如,在本公开的一些实施例中,显示面板还包括发光控制信号线,所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管,所述第一发光控制晶体管的栅极与所述发光控制信号线相连,所述第一发光控制晶体管的第一极与第一电源端相连,所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连;所述第二发光控制晶体管的栅极与所述发光控制信号线相连,所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连,所述第二发光控制晶体管的第二极与所述发光元件的第一极相连。
本公开的至少一实施例还提供一种显示装置,包括上述任一显示面板。
另一方面,本公开的至少一实施例提供一种显示面板,包括:衬底基板;像素单元,位于所述衬底基板上,包括像素电路和发光元件,所述像素电路被配置为驱动所述发光元件,所述像素电路比所述发光元件更靠近所述衬底基板,所述像素电路包括驱动晶体管;数据线,被配置为向所述像素电路提供数据信号;连接元件,所述发光元件通过所述连接元件与所述像素电路相连,所述连接元件包括屏蔽部;以及连接线,与所述驱动晶体管的栅极相连;所述数据线包括两条相邻数据线,所述屏蔽部位于所述两条相邻数据线之间,所述连接线在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述屏蔽部在所述衬底基板上的正投影大于所述连接线在所述衬底基板上的正投影。
例如,在本公开的一些实施例中,所述驱动晶体管的栅极在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影部分交叠,所述屏蔽部与所述驱动晶体管的栅极的交叠部分的面积小于所述驱动晶体管的栅极的面积。
例如,在本公开的一些实施例中,所述两条相邻数据线沿第一方向排列,所述数据线沿第二方向延伸。
例如,在本公开的一些实施例中,所述驱动晶体管的栅极在所述第一方向上的尺寸大于所述屏蔽部在所述第一方向上的尺寸;所述屏蔽部在所述第二方向上的尺寸大于所述驱动晶体管的栅极在所述第二方向上的尺寸。
例如,在本公开的一些实施例中,所述连接线与所述驱动晶体管的栅极接触。
例如,在本公开的一些实施例中,所述数据线与所述屏蔽部位于同一层,所述屏蔽部的延伸方向与所述数据线的延伸方向相同。
例如,在本公开的一些实施例中,显示面板还包括第一导电结构,所述连接线与所述 第一导电结构相连,所述屏蔽部在所述衬底基板上的正投影与所述第一导电结构在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述像素电路还包括第一复位晶体管,所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连,所述第一导电结构复用为所述第一复位晶体管的第二极。
例如,在本公开的一些实施例中,显示面板还包括第一复位控制信号线和第一初始化信号线,所述第一复位晶体管的栅极与所述第一复位控制信号线相连,所述第一复位晶体管的第一极与所述第一初始化信号线相连。
例如,在本公开的一些实施例中,所述第一复位晶体管包括第一沟道和第二沟道,所述第一复位晶体管的第一沟道和第二沟道通过导电连接部相连,所述屏蔽部在所述衬底基板的上的正投影与所述第一复位晶体管的所述导电连接部在所述衬底基板的上的正投影部分交叠。
例如,在本公开的一些实施例中,显示面板还包括第二初始化信号线,其中,所述第一初始化信号线和所述第二初始化信号线分设在所述驱动晶体管的栅极的相对的两侧,所述屏蔽部在所述衬底基板上的正投影与所述第二初始化信号线在所述衬底基板上的正投影部分交叠。
例如,在本公开的一些实施例中,显示面板还包括第一电源线和挡块,其中,所述第一电源线被配置为向所述像素电路提供第一电源电压,所述挡块与所述第一电源线电连接,所述第一导电结构在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,显示面板还包括第二导电结构,所述数据线与所述第二导电结构相连,所述挡块在所述衬底基板上的正投影与所述第二导电结构在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,显示面板还包括栅线,所述栅线与所述数据线相互交叉且彼此绝缘,所述栅线被配置为向所述像素电路提供扫描信号,所述像素电路还包括阈值补偿晶体管,所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连,所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极相连;所述阈值补偿晶体管的栅极与所述栅线相连;所述驱动晶体管的栅极通过所述连接线与所述阈值补偿晶体管的第二极相连,所述阈值补偿晶体管包括第一沟道和第二沟道,所述第一沟道和所述第二沟道通过导电连接部相连;所述挡块在所述衬底基板上的正投影与所述阈值补偿晶体管的所述导电连接部在所述衬底基板上的正投影至少部分交叠。
例如,在本公开的一些实施例中,所述挡块的与所述第一导电结构交叠的部分在所述衬底基板上的正投影的面积大于所述挡块的与所述阈值补偿晶体管的所述导电连接部交叠的部分在所述衬底基板上的正投影的面积。
例如,在本公开的一些实施例中,所述第一导电结构的材料与所述连接线的材料不同。
例如,在本公开的一些实施例中,所述像素单元包括位于同一列且相邻的两个像素单 元,所述两条相邻的数据线分别与所述两个像素单元相连。
例如,在本公开的一些实施例中,显示面板还包括第二复位控制信号线,所述像素电路还包括第二复位晶体管,所述第二复位晶体管的栅极与所述第二复位控制信号线相连,所述第二复位晶体管的第一极与所述第二初始化信号线相连,所述第二复位晶体管的第二极与所述发光元件的第一极相连。
例如,在本公开的一些实施例中,所述像素电路还包括第一电源端和存储电容,所述存储电容的第一极与所述驱动晶体管的栅极相连,所述存储电容的第二极与所述第一电源端相连。
例如,在本公开的一些实施例中,所述像素电路还包括数据写入晶体管,所述数据写入晶体管的栅极与所述栅线相连,所述数据写入晶体管的第一极与所述数据线相连,所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
例如,在本公开的一些实施例中,显示面板还包括发光控制信号线,所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管,所述第一发光控制晶体管的栅极与所述发光控制信号线相连,所述第一发光控制晶体管的第一极与所述第一电源端相连,所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连;所述第二发光控制晶体管的栅极与所述发光控制信号线相连,所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连,所述第二发光控制晶体管的第二极与所述发光元件的第一极相连。
例如,在本公开的一些实施例中,所述数据线具有第一部分和第二部分,所述两条相邻数据线的第一部分之间的间距大于所述两条相邻数据线的第二部分之间的间距,所述屏蔽部位于所述两条相邻数据线的第二部分之间。
例如,在本公开的一些实施例中,所述两条相邻数据线的第二部分分别靠近所述第一发光控制晶体管和所述第二发光控制晶体管,所述存储电容位于所述两条相邻数据线的第一部分之间。
例如,在本公开的一些实施例中,所述连接元件还包括连接电极,所述连接电极与所述像素电路相连,所述发光元件通过所述屏蔽部与所述连接电极相连。
本公开至少一实施例还提供一种显示装置,包括上述任一显示面板。
为了更清楚地说明本公开实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本公开的一些实施例,而非对本公开的限制。
图1为一种7T1C的像素电路的示意图;
图2为图1所示的像素电路的工作时序图;
图3为本公开一实施例提供的一种显示面板中的半导体图形的平面图;
图4为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图;
图5为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源层、源极和漏极的示意图;
图6为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图;
图7为本公开一实施例提供的一种显示面板中形成第二导电图案层后的平面示意图;
图8为本公开一实施例提供的一种显示面板中在第一栅绝缘层、第二栅绝缘层和层间绝缘层至少之一中形成的过孔的平面示意图;
图9为本公开一实施例提供的一种显示面板中在第一栅绝缘层、第二栅绝缘层和层间绝缘层至少之一中形成过孔后的平面示意图;
图10为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图;
图11为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面图;
图12为本公开一实施例提供的一种显示面板中的钝化层和第一平坦化层中形成的过孔的平面示意图;
图13为本公开一实施例提供的一种显示面板中的钝化层和第一平坦化层中形成过孔后的平面示意图;
图14为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图;
图15为本公开一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图;
图16A为本公开另一实施例提供的一种显示面板中的第四导电图案层的平面图;
图16B为本公开另一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图;
图17为本公开另一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图;
图18为本公开一实施例提供的一种显示面板的局部剖视图(图17的沿AB线的剖视图);
图19为本公开一实施例提供的一种显示面板的局部平面图;
图20为本公开一实施例提供的一种显示面板的局部剖视图(图19的沿CD线的剖视图);以及
图21为本公开一实施例提供的一种显示面板的一个重复单元的像素电路图。
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者 物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
目前市场有较大的高帧频AMOLED显示面板的需求,例如,双数据(Dual Data)方案可以在保证显示效果的前提下实现120Hz的驱动。
图1为一种7T1C的像素电路的示意图。图2为图1所示的像素电路的工作时序图。图1所示的像素电路可为相关技术中常见的低温多晶硅(Low Temperature Poly-silicon,LTPS)AMOLED的像素电路。
图1示出了显示面板的一个像素单元的像素电路,如图1所示,像素单元101包括像素电路10和发光元件20。像素电路10包括六个开关晶体管(T2-T7)、一个驱动晶体管T1和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、以及第二复位晶体管T7。发光元件20包括第一极201和第二极202以及位于第一极201和第二极202之间的发光功能层。例如,第一极201为阳极,第二极202为阴极。通常,阈值补偿晶体管T3、第一复位晶体管T6采用双栅TFT的方式降低漏电。
如图1所示,显示面板包括栅线GT、数据线DT、第一电源端VDD、第二电源端VSS、发光控制信号线EML、初始化信号线INT、第一复位控制信号线RT1、第二复位控制信号线RT2等。第一电源端VDD被配置为向像素单元101提供恒定的第一电压信号ELVDD、第二电源端VSS被配置为向像素单元101提供恒定的第二电压信号ELVSS,并且第一电压信号ELVDD大于第二电压信号ELVSS。栅线GT被配置为向像素单元101提供扫描信号SCAN、数据线DT被配置为向像素单元101提供数据信号DATA(数据电压VDATA)、发光控制信号线EML被配置为向像素单元101提供发光控制信号EM,第一复位控制信号线RT1被配置为向像素单元101提供复位控制信号RESET,第二复位控制信号线RT1被配置为向像素单元101提供扫描信号SCAN,初始化信号线INT被配置为向像素单元101提供初始化信号Vinit。例如,初始化信号Vinit为恒定的电压信号,其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间,但不限于此,例如,初始化信号Vinit可小于或等于第二电压信号ELVSS。例如,初始化信号线INT包括第一初始化信号线INT1和第二初始化信号线INT2。例如,第一初始化信号线INT1被配置为向像素单元101提供初始化信号Vinit1,第二初始化信号线INT1被配置为向像素单元101提供初始化信号Vinit2。例如,在一些实施例中,第一初始化信号Vinit1和第二初始化信号Vinit2相等,均为Vinit。
如图1所示,驱动晶体管T1与发光元件20电连接,并在扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
例如,发光元件20为有机发光二极管(OLED),发光元件20在其对应的像素电路 10的驱动下发出红光、绿光、蓝光,或者白光等。例如,一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如,一个像素包括出射红光的像素单元,出射绿光的像素单元和出射蓝光的像素单元,但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
例如,如图1所示,数据写入晶体管T2的栅极T20与栅线GT相连,数据写入晶体管T2的第一极T21与数据线DT相连,数据写入晶体管T2的第二极T22与驱动晶体管T1的第一极T11相连。
例如,如图1所示,像素电路10还包括阈值补偿晶体管T3,阈值补偿晶体管T3的栅极T30与栅线GT相连,阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12相连,阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如,如图1所示,显示面板还包括发光控制信号线EML,像素电路10还包括第一发光控制晶体管T4和第二发光控制晶体管T5,第一发光控制晶体管T4的栅极T40与发光控制信号线EML相连,第一发光控制晶体管T4的第一极T41与第一电源端VDD相连,第一发光控制晶体管T4的第二极T42与驱动晶体管T1的第一极T11相连;第二发光控制晶体管T5的栅极T50与发光控制信号线EML相连,第二发光控制晶体管T5的第一极T51与驱动晶体管T1的第二极T12相连,第二发光控制晶体管T5的第二极T52与发光元件20的第一极201相连。
如图1所示,第一复位晶体管T6与驱动晶体管T1的栅极T10相连,并被配置为对驱动晶体管T1的栅极进行复位,第二复位晶体管T7与发光元件20的第一极201相连,并被配置为对发光元件20的第一极201进行复位。第一初始化信号线INT1通过第一复位晶体管T6与驱动晶体管T1的栅极相连。第二初始化信号线INT2通过第二复位晶体管T7与发光元件20的第一极201相连。例如,第一初始化信号线INT1和第二初始化信号线INT2相连,以被输入相同的初始化信号,但不限于此,在一些实施例中,第一初始化信号线INT1和第二初始化信号线INT2也可以彼此绝缘,并被配置为分别输入信号。
例如,如图1所示,第一复位晶体管T6的第一极T61与第一初始化信号线INT1相连,第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10相连,第二复位晶体管T7的第一极T71与第二初始化信号线INT2相连,第二复位晶体管T7的第二极T72与发光元件20的第一极201相连。例如,如图1所示,第一复位晶体管T6的栅极T60与第一复位控制信号线RT1相连,第二复位晶体管T7的栅极T70与第二复位控制信号线RT2相连。
如图1所示,第一电源端VDD被配置为向像素电路10提供第一电压信号ELVDD;像素电路还包括存储电容Cst,存储电容Cst的第一极Ca与驱动晶体管T1的栅极T10相连,存储电容Cst的第二极Cb与第一电源端VDD相连。
例如,如图1所示,显示面板还包括第二电源端VSS,第二电源端VSS与发光元件20的第二极201相连。
如图2所示,一帧显示时间段,像素单元的驱动方法包括第一复位阶段t1、数据写入 及阈值补偿和第二复位阶段t2和发光阶段t3,复位控制信号RESET为低电平时,给驱动晶体管T1的栅极复位,扫描信号SCAN为低电平时,给发光元件20的第一极201(例如,阳极)复位。例如,如图1所示,扫描信号SCAN为低电平时,数据电压VDATA写入,同时获取驱动晶体管T1的阈值电压Vth,并将含有数据线上数据信息的数据电压VDADA存储在电容Cst内;发光控制信号线EML为低电平时,发光元件20发光,第一节点N1(驱动晶体管的栅信号部)的电压保持(发光元件20的发光稳定性)靠存储电容Cst维持。在像素电路10的驱动过程中,在发光阶段,存储电容用以保持电压信号,使其信号保持端的电位得以保持恒定,在驱动晶体管的栅极和源极之间形成电压,从而控制驱动晶体管形成驱动电流,进而驱动发光元件20发光。
如图2所示,在复位阶段t1,设置发光控制信号EM为关闭电压,设置复位控制信号RESET为开启电压,设置扫描信号SCAN为关闭电压。
如图2所示,在数据写入及阈值补偿阶段和第二复位阶段t2,设置发光控制信号EM为关闭电压,设置复位控制信号RESET为关闭电压,设置扫描信号SCAN为开启电压。
如图2所示,在发光阶段t3,设置发光控制信号EM为开启电压,设置复位控制信号RESET为关闭电压,设置扫描信号SCAN为关闭电压。
如图2所示,第一电压信号ELVDD和第二电压信号ELVSS均为恒定的电压信号,例如,初始化信号Vinit介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如,本公开实施例中的开启电压是指能使相应晶体管的第一极和第二极导通的电压,关闭电压是指能使相应晶体管的第一极和第二极断开的电压。当晶体管为P型晶体管时,开启电压为低电压(例如,0V),关闭电压为高电压(例如,5V);当晶体管为N型晶体管时,开启电压为高电压(例如,5V),关闭电压为低电压(例如,0V)。图2所示的驱动波形均以P型晶体管为例进行说明。例如,开启电压为低电压(例如,0V),关闭电压为高电压(例如,5V),但不限于此。
请一并参阅图1和图2,在第一复位阶段t1,发光控制信号EM为关闭电压,复位控制信号RESET为开启电压,扫描信号SCAN为关闭电压。此时,第一复位晶体管T6处于导通状态,而第二复位晶体管T7、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将第一初始化信号(初始化电压Vinit)Vinit1传输到驱动晶体管T1的栅极并被存储电容Cst存储,将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2,发光控制信号EM为关闭电压,复位控制信号RESET为关闭电压,扫描信号SCAN为开启电压。此时,数据写入晶体管T2和阈值补偿晶体管T3处于导通状态,第二复位晶体管T7处于导通状态,第二复位晶体管T7将第二初始化信号(初始化电压Vinit)Vinit2传输到发光元件20的第一电极201,以将发光元件20复位。而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6处于关闭状态。此时,数据写入晶体管T2将数据电压VDATA传输到驱动晶体管T1的第一极,即,数据写入晶体管T2接收扫描信号SCAN和数据电压VDATA并根据 扫描信号SCAN向驱动晶体管T1的第一极写入数据电压VDATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构,由此可对于驱动晶体管T1的栅极进行充电。充电完成之后,驱动晶体管T1的栅极电压为VDATA+Vth,其中,VDATA为数据电压,Vth为驱动晶体管T1的阈值电压,即,阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段,存储电容Cst两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3,发光控制信号EM为开启电压,复位控制信号RESET为关闭电压,扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态,而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电压信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极,驱动晶体管T1的栅极电压保持为VDATA+Vth,发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20,发光元件20发光。即,第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM,并根据发光控制信号EM控制发光元件20发光。发光电流I满足如下饱和电流公式:
K(Vgs-Vth)
2=K(VDATA+Vth-ELVDD-Vth)
2=K(VDATA-ELVDD)
2
其中,
μ
n为驱动晶体管的沟道迁移率,Cox为驱动晶体管T1单位面积的沟道电容,W和L分别为驱动晶体管T1的沟道宽度和沟道长度,Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此,本像素电路非常好的补偿了驱动晶体管T1的阈值电压。
例如,发光阶段t3的时长占一帧显示时间段的比例可被调节。这样,可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如,通过控制显示面板中的扫描驱动电路或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如,本公开实施例不限于图1所示出的具体像素电路,可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导,本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式,都属于本公开的保护范围之内。
以下结合图3至图21对本公开的实施例提供的显示面板进行说明。图3为本公开一实施例提供的一种显示面板中的半导体图形的平面图。图4为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图。图5为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源层、源极和漏极的示意图。图6为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图。图7为本公开一实施例提供的一种显示面板中形成第二导电图案层后的平面示意图。图8为本公开一实施例提供的一种显示面板中在第一栅绝缘 层、第二栅绝缘层和层间绝缘层至少之一中形成的过孔的平面示意图。图9为本公开一实施例提供的一种显示面板中在第一栅绝缘层、第二栅绝缘层和层间绝缘层至少之一中形成过孔后的平面示意图。图10为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图。图11为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面图。图12为本公开一实施例提供的一种显示面板中的钝化层和第一平坦化层中形成的过孔的平面示意图。图13为本公开一实施例提供的一种显示面板中的钝化层和第一平坦化层中形成过孔后的平面示意图。图14为本公开一实施例提供的一种显示面板中的第四导电图案层的平面图。图15为本公开一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图。图16A为本公开另一实施例提供的一种显示面板中的第四导电图案层的平面图。图17为本公开另一实施例提供的一种显示面板中形成第四导电图案层后的平面示意图。图18为本公开一实施例提供的一种显示面板的局部剖视图(图17的沿AB线的剖视图)。图19为本公开一实施例提供的一种显示面板的局部平面图。图20为本公开一实施例提供的一种显示面板的局部剖视图(图19的沿CD线的剖视图)。图21为本公开一实施例提供的一种显示面板的一个重复单元的像素电路图。
图5至图17以及图19示出了第一方向X和第二方向Y,第二方向Y与第一方向X相交。例如,本公开的实施例以第一方向X与第二方向Y垂直为例。例如,第一方向X为像素单元的行方向,第二方向Y为像素单元的列方向。第一方向X和第二方向Y均为平行于衬底基板BS的方向。例如,第一方向X垂直于第二方向Y。图17和图19示出了第三方向Z,第三方向Z为垂直于衬底基板BS的方向。第三方向Z垂直于第一方向X,并且垂直于第二方向Y。
在本公开的实施例中,为了图示清晰,平面图中,绝缘层以过孔的形式示出,绝缘层本身采用了透明化处理,并且第一导电图案层、第二导电图案层、第三导电图案层、第四导电图案层做了半透明处理。
图3示出了半导体图形SCP,图4示出了第一导电图案层LY1,例如,第一导电图案层LY1和半导体图形SCP之间设置有第一栅绝缘层(第一栅绝缘层GI1,参照图18)。例如,在衬底基板上形成半导体图形SCP以及后续各种部件。如图4所示,第一导电图案层LY1包括第一复位控制信号线RT1、栅线GT、存储电容Cst的第一极Ca(驱动晶体管T1的栅极T10)、发光控制信号线EML、第二复位控制信号线RT2。以第一导电图案层LY1为掩模版对半导体图形SCP进行掺杂,使得半导体图形SCP的被第一导电图案层LY1覆盖的区域保留半导体特性,形成有源层ACT(参见图5),而半导体图形SCP的未被第一导电图案层LY1覆盖的区域被导体化,形成薄膜晶体管的源极和漏极。如5示出了半导体图形SCP被部分导体化之后形成的有源层ACT。例如,在本公开的实施例中,本级的栅线GT与下一级的复位控制信号线相连。例如,栅线GT和第二复位控制信号线RT2可以电连接以在同一时间输入相同的信号。
如图4和图5所示,第一复位控制信号线RT1、栅线GT、发光控制信号线EML和第二复位控制信号线RT2均沿第一方向X延伸。
例如,如图5所示,在显示面板的制作过程中,采用自对准工艺,以第一导电图案层LY1为掩模对半导体图案层SCP进行导体化处理,例如,采用离子注入工艺对半导体图案层SCP进行重掺杂,从而使得半导体图案层SCP的未被第一导电图案层LY1覆盖的部分被导体化,形成驱动晶体管T1的源极区(第一极T11)和漏极区(第二极T12)、数据写入晶体管T2的源极区(第一极T21)和漏极区(第二极T22)、阈值补偿晶体管T3的源极区(第一极T31)和漏极区(第二极T32)、第一发光控制晶体管T4的源极区(第一极T41)和漏极区(第二极T42)、第二发光控制晶体管T5的源极区(第一极T51)和漏极区(第二极T52)、第一复位晶体管T6的源极区(第一极T61)和漏极区(第二极T62)、以及第二复位晶体管T7的源极区(第一极T71)和漏极区(第二极T72)。半导体图案层SCP的被第一导电图案层L1覆盖的部分保留半导体特性,形成驱动晶体管T1的沟道区T13、数据写入晶体管T2的沟道区T23、阈值补偿晶体管T3的沟道区T33、第一发光控制晶体管T4的沟道区T43、第二发光控制晶体管T5的沟道区T53、第一复位晶体管T6的沟道区T63、以及第二复位晶体管T7的沟道区T73。各晶体管的沟道区构成有源层ACT(参考图5)。
例如,如图5所示,第二复位晶体管T7的第二极T72和第二发光控制晶体管T5的第二极T52一体形成;第二发光控制晶体管T5的第一极T51、驱动晶体管T1的第二极T12和阈值补偿晶体管T3的第一极T31一体形成;驱动晶体管T1的第一极T11、数据写入晶体管T2的第二极T22、第一发光控制晶体管T4的第二极T42一体形成;阈值补偿晶体管T3的第二极T32和第一复位晶体管T6的第二极T62一体形成。
例如,本公开实施例采用的晶体管的沟道区(有源层)可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个实施例中,该晶体管均为P型低温多晶硅(LTPS)薄膜晶体管。在另一个实施例中,与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管,即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等),金属氧化物半导体薄膜晶体管具有较低的漏电流,可以有助于降低驱动晶体管T1的栅极漏电流。
例如,本公开实施例采用的晶体管可以包括多种结构,如顶栅型、底栅型或者双栅结构。在一些实施例中,与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管,可以有助于降低驱动晶体管T1的栅极漏电流。
例如,如图5所示,发光控制信号线EML的一部分作为第一发光控制晶体管T4的栅极T40,发光控制信号线EML的一部分作为第二发光控制晶体管T5的栅极T50,第一复位晶体管T6的栅极T60为第一复位控制信号线RT1的一部分,第二复位晶体管T7的栅极T70为第二复位控制信号线RT2的一部分,数据写入晶体管T2的栅极T20为栅线GT的一部分,阈值补偿晶体管T3的栅极T30为栅线GT的一部分。
如图5所示,阈值补偿晶体管T3为双栅晶体管,阈值补偿晶体管T3包括第一沟道T331和第二沟道T332,第一沟道T331和第二沟道T332通过第一导电连接部CP1相连。如图5所示,第一复位晶体管T6为双栅晶体管,第一复位晶体管T6包括第一沟道T631 和第二沟道T632,第一沟道T631和第二沟道T632通过第二导电连接部CP2相连。
图6示出了第二导电图案层LY2。例如,第二导电图案层LY2和第一导电图案层LY1之间设置有第二栅绝缘层(第二栅绝缘层GI2,参照图18)。第二导电图案层LY2包括挡块BK、第一初始化信号线INT1、第二初始化信号线INT2和存储电容Cst的第二极Cb。例如,参考图6,第一初始化信号线INT1沿第一方向X延伸,第二初始化信号线INT2沿第一方向X延伸。第一初始化信号线INT1和第二初始化信号线INT2沿第二方向Y排列。如图6所示,第一初始化信号线INT1和第二初始化信号线INT2位于存储电容Cst的第二极Cb的两侧,第一初始化信号线INT1和第二初始化信号线INT2位于挡块BK的两侧,第一初始化信号线INT1和第二初始化信号线INT2之间设有存储电容Cst的第二极Cb和挡块BK。如图6所示,第一初始化信号线INT1、挡块BK、存储电容Cst的第二极Cb和第二初始化信号线INT2沿第二方向Y依次排列。挡块BK与第一电源线VDD1电连接,以使第一电源线VDD1为挡块BK提供恒定的电压。
如图7所示,挡块BK在衬底基板上的正投影与第一导电连接部CP1在衬底基板上的正投影至少部分交叠。即,挡块BK被配置为遮挡阈值补偿晶体管T3的两个沟道之间的第一导电连接部CP1,挡块BK与第一导电连接部CP1形成电容(稳定电容),以避免阈值补偿晶体管T3产生漏电流,避免影响显示效果。如图7所示,在平面图中,挡块BK和第一导电连接部CP1部分交叠。
如图7所示,在平面图中,第一初始化信号线INT1和第二导电连接部CP2部分交叠,第一初始化信号线INT1和第二导电连接部CP2之间形成电容(稳定电容),以避免第一复位晶体管T6产生漏电流,避免影响显示效果。
例如,在本公开的实施例中,元件A和元件B部分交叠,可指元件A的一部分与元件B交叠,元件B的一部分与元件A交叠,或者元件A的一部分与元件B的一部分交叠。元件A和元件B为两个不同的元件。
如图7所示,栅线GT沿第一方向X延伸,第一复位控制信号线RT1沿第一方向X延伸,挡块BK位于栅线GT和第一复位控制信号线RT1之间。从而,挡块BK在第二方向Y上的位置得以限定。
如图6和图7所示,挡块BK包括第一部分BKa、第二部分BKb和第三部分BKc,第一部分BKa沿第一方向X延伸,第二部分BKb沿第二方向Y延伸,第三部分BKc沿第一方向X延伸,第一部分BKa和第三部分BKc通过第二部分BKb相连,第一部分BKa和第二部分BKb构成倒T形结构。例如,第三部分BKc呈T字形结构。例如,如图6所示,第一部分BKa、第二部分BKb和第三部分BKc位于同一层,且为一体结构。将在后续介绍图6和图7所示形状的挡块的各个部分的作用。
如图5、图7和图15所示,显示面板包括第一导电结构CDT1,第一导电结构CDT1与驱动晶体管T1的栅极T10相连,第一导电结构CDT1在衬底基板上的正投影与挡块BK在衬底基板上的正投影至少部分交叠,以使得挡块BK屏蔽驱动晶体管的栅信号部PT1(包括驱动晶体管T1的栅极T10和第一导电结构CDT1)与数据线的寄生电容,降低耦 合影响,减轻纵向串扰。参考图15和图6,第一导电结构CDT1在衬底基板上的正投影与挡块BK的第三部分BKc在衬底基板上的正投影至少部分交叠。
例如,第一导电结构CDT1的材料与第一导电连接部CP1的材料相同。例如,第一导电结构CDT1与第一导电连接部CP1可由同一膜层经同一工艺制作而成。
例如,第一导电结构CDT1的材料包括半导体材料经掺杂而得的导电材料。例如,第一导电结构CDT1的材料包括多晶硅经掺杂而得的导电材料,但不限于此。
例如,如图5、图7和图15所示,第一导电结构CDT1复用为第一复位晶体管T6的第二极T62,则第一复位晶体管T6的第二极T62在衬底基板上的正投影与挡块BK在衬底基板上的正投影至少部分交叠。在本公开的实施例中,以第一导电结构CDT1作为第一复位晶体管T6的第二极T62为例进行说明。
例如,如图5、图7和图15所示,在平面图中,第一复位晶体管T6的第一极T61与挡块BK部分交叠,即,第一复位晶体管T6的第一极T61在衬底基板上的正投影与挡块BK在衬底基板上的正投影至少部分交叠。这种设置可以增大挡块的面积,使其更好的起到屏蔽作用。
例如,参考图16A和图16B,数据线DT具有第一部分P01和第二部分P02,两条相邻数据线DT的第一部分P01之间的间距SP1大于两条相邻数据线DT的第二部分P02之间的间距SP2,屏蔽部CEs位于两条相邻数据线DT的第二部分P02之间。如图16A和图16B所示,屏蔽部CEs也位于两条相邻数据线DT的第一部分P01之间。
例如,如图16B所示,两条相邻数据线DT的第二部分P02分别靠近第一发光控制晶体管T4和第二发光控制晶体管T5,存储电容Cst位于两条相邻数据线DT的第一部分P01之间。
两条相邻数据线DT的第二部分P02也可称作缩窄部,如图16B所示,两条相邻数据线DT在第一发光控制晶体管T4和第二发光控制晶体管T5处缩窄,不在存储电容Cst处缩窄。
参考图17,为了更好地起到屏蔽作用,屏蔽部CEs在衬底基板上的正投影与第一导电结构CDT1在衬底基板上的正投影至少部分交叠。
参考图5和图17,屏蔽部CEs在衬底基板的上的正投影与第一复位晶体管T6的第二导电连接部CP2在衬底基板的上的正投影部分交叠。例如,参考图5、图14、图15和图17,第一像素单元101a中的屏蔽部CEs在衬底基板的上的正投影与第三像素单元101c中的第一复位晶体管T6的第二导电连接部CP2在衬底基板的上的正投影部分交叠。即,一个像素单元101中的屏蔽部CEs在衬底基板的上的正投影与下一行与该像素单元位于同一列的像素单元中的第一复位晶体管T6的第二导电连接部CP2在衬底基板的上的正投影部分交叠。
参考图14至图16A,以图15左上角的挡块BK为例,挡块BK与第二像素单元101b的阈值补偿晶体管T3的第一导电连接部CP1交叠,以形成稳定电容减少漏电流。
如图7所示,挡块BK的与第一导电结构CDT1(第一复位晶体管T6的第二极T62) 交叠的部分在衬底基板上的正投影的面积A1大于挡块BK的与第一导电连接部CP1交叠的部分在衬底基板上的正投影的面积A0。即,挡块BK与第一导电结构CDT1的交叠部分在衬底基板上的正投影的面积A1大于挡块BK与第一导电连接部CP1的交叠部分在衬底基板上的正投影的面积A0。
如图10所示,第三导电图案层LY3包括电源连接线VDD0、连接电极CEa、连接电极CEb、连接电极CEc、连接电极CEd(第二连接电极CEd)和连接电极CEe(第一连接电极CEe)。第三导电图案层LY3和第二导电图案层LY2之间设有层间绝缘层(层间绝缘层ILD,参照图18)。
参考图9至图11,电源连接线VDD0通过过孔H2与第一发光控制晶体管T4的第一极T41电连接,电源连接线VDD0通过过孔H3和H30与存储电容Cst的第二极Cb电连接,电源连接线VDD0通过过孔H0与导电块BK电连接。连接电极CEa的一端通过过孔H12与第一初始化信号线INT1电连接,连接电极CEa的另一端通过过孔H11与第一复位晶体管T6的第一极T61相连,进而使得第一复位晶体管T6的第一极T61与第一初始化信号线INT1电连接。连接电极CEb的一端通过过孔H22与第一复位晶体管T6的第二极T62电连接,连接电极CEb的另一端通过过孔H21与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接,从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接。连接电极CEc的一端通过过孔H32与第二初始化信号线INT2电连接,连接电极CEc的另一端通过过孔H31与第二复位晶体管T7的第一极T71相连,进而使得第二复位晶体管T7的第一极T71与第二初始化信号线INT2电连接。连接电极CEd通过过孔H40与第二发光控制晶体管T5的第二极T52电连接。连接电极CEd可用来与后续形成的连接电极CEf相连,进而与发光元件20的第一电极201(参照图17)电连接。连接电极CEe通过过孔H5与数据写入晶体管T2的第一极T21电连接。连接电极CEe用于与数据线相连。
图14示出了第四导电图案层LY4。第四导电图案层LY4包括数据线DT、连接电极CEf和第一电源线VDD1。第三导电图案层LY3与第四导电图案层LY4之间设有钝化层(钝化层PVX,参照图18)和第一平坦化层(第一平坦化层PLN1,参照图18)。第一电源线VDD1通过贯穿钝化层和第一平坦化层的过孔H6与电源连接线VDD0相连,连接电极CEf通过贯穿钝化层和第一平坦化层的过孔H7与连接电极CEd相连。数据线DT通过贯穿钝化层和第一平坦化层的过孔H8与连接电极CEe相连,进而与数据写入晶体管T2的第一极T21电连接。例如,连接电极CEf(第三连接电极CEf)和连接电极CEd(第二连接电极CEd)构成连接元件CE0。例如,发光元件20通过连接元件CE0与像素电路10相连。例如,像素电路10与连接电极CEd(第二连接电极CEd)相连,连接电极CEd(第二连接电极CEd)与连接电极CEf(第三连接电极CEf)相连,连接电极CEf(第三连接电极CEf)与发光元件20相连。
图14示出了第一数据线DT1、第二数据线DT2、第三数据线DT3和第四数据线DT4。图14还示出了第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素 单元101d的位置。
如图14图16A和图16B所示,数据线DT沿第二方向Y延伸,第一数据线DT1、第三数据线DT3、第四数据线DT4和第二数据线DT2沿第一方向X排列。第四数据线DT4位于第三数据线DT3和第二数据线DT2之间。第一像素单元101a和第二像素单元101b位于同一行并位于相邻列,第三像素单元101c和第四像素单元101d位于同一行并位于相邻列。第一像素单元101a和第三像素单元101c位于同一列并位于相邻行,第二像素单元101b和第四像素单元101d位于同一列并位于相邻行。如图15所示,数据线DT与栅线GT相互交叉且彼此绝缘。
例如,第一电源线VDD1被配置为向像素电路10提供第一电压信号ELVDD。第一电源线VDD1与挡块BK电连接以为挡块BK提供恒定的电压。第一电源线VDD1连接至第一电源端VDD,存储电容Cst的第二极Cb与第一电源线VDD1相连。例如,存储电容Cst的第二极Cb通过电源连接线VDD0以及第一电源线VDD1与第一电源端VDD相连。图15示出了形成第四导电图案层LY4后的结构的平面图。
例如,第一发光控制晶体管T4的第一极T41通过电源连接线VDD0、第一电源线VDD1(参考图10和图15)与第一电源端VDD相连。
如图5、图7和图15所示,显示面板包括第二导电结构CDT2,挡块BK在衬底基板上的正投影与第二导电结构CDT2在衬底基板上的正投影至少部分交叠,以屏蔽第一数据线DT1上的第一数据信号和第三数据线DT3上的第三数据信号之间的干扰,避免耦合导致的显示异常。例如,在第一像素单元101a和第二像素单元101b中,挡块BK与第二像素单元101b的阈值补偿晶体管T3的第一导电连接部CP1交叠,与第一像素单元101a的第二导电结构CDT2交叠。例如,第二导电结构CDT2与第一导电结构CDT1的材料相同。
如图5、图7和图15所示,数据写入晶体管T2的第一极T21复用为第二导电结构CDT2。在本公开的实施例中,以数据写入晶体管T2的第一极T21用作第二导电结构CDT2为例进行说明,但不限于此。
如图15所示,数据线DT、连接电极CEe和第二导电结构CDT2构成数据信号部PT2。例如,数据线DT、连接电极CEe和第二导电结构CDT2构成同一个节点。例如,数据线DT、连接电极CEe和第二导电结构CDT2上的电位相同或基本相同。即,数据信号部PT2上各位置处的电位相同或基本相同。从而,挡块BK与第二导电结构CDT2交叠,可以屏蔽第一数据线DT1上的第一数据信号和第三数据线DT3上的第三数据信号之间的干扰,避免耦合导致的显示异常。
参考图7,挡块BK的与第二导电结构CDT2(数据写入晶体管T2的第一极T21)交叠的部分在衬底基板上的正投影的面积A2大于挡块BK的与第一导电连接部CP1交叠的部分在衬底基板上的正投影的面积A0。例如,数据线DT通过过孔H8与连接电极CEe相连,进而与第二导电结构CDT2相连。
参考图7,挡块BK的与第一导电结构CDT1交叠的部分在衬底基板上的正投影的面积A1大于挡块BK的与第二导电结构CDT2交叠的部分在衬底基板上的正投影的面积 A2。例如,面积A1大于面积A2,面积A2大于面积A0。即,面积A1、面积A2、以及面积A0依次减小,但本公开的实施例不限于此。
参考图13至图15,根据显示面板的各层制作顺序,可以得知,在垂直于衬底基板的方向上,挡块BK位于第二导电结构CDT2(数据写入晶体管T2的第一极T21)和第三数据线DT3之间。
如图15所示,挡块BK在衬底基板上的正投影与第三数据线DT3在衬底基板上的正投影部分交叠,以使得挡块BK屏蔽第一数据线DT1上的第一数据信号和第三数据线DT3上的第三数据信号之间的干扰,避免耦合导致的显示异常。参考图15和图6,挡块BK的第一部分BKa在衬底基板上的正投影与第三数据线DT3在衬底基板上的正投影部分交叠,以使得挡块BK的第一部分BKa屏蔽第一数据线DT1上的第一数据信号和第三数据线DT3上的第三数据信号之间的干扰,避免耦合导致的显示异常。
如图15所示,在平面图中,一个挡块BK对应同一行中的两个像素单元。如图15所示,在平面图中,挡块BK位于第一数据线DT1和第二数据线DT2之间。
如图5、图7和图15所示,数据写入晶体管T2的第一极T21在衬底基板上的正投影与第三数据线DT3在衬底基板上的正投影至少部分交叠。
参考图14至图16B,挡块BK向左延伸进入与第二像素单元101b相邻的第一像素单元101a,使得挡块BK具有位于第一数据线DT1和第三数据线DT3之间的部分,以屏蔽第一数据线DT1上的第一数据信号和第三数据线DT3上的第三数据信号之间的干扰,避免耦合导致的显示异常。第一数据线DT1和第三数据线DT3为两条相邻的数据线。
例如,在本公开的实施例中,两个相邻的元件C是指该两个元件C彼此相邻,且其间不设置有元件C,但不排除在两个相邻的元件C之间还设置有除了元件C之外的其他元件。
例如,采用120Hz的驱动方案采用分时写入方式,即数据信号先存储到存储电容中,然后扫描信号开启再写入像素单元中,数据信号之间的干扰会影响数据信号的准确写入,影响显示效果;挡块BK向左延伸起到屏蔽作用的设计可以很好的改善这一问题。
通常技术中,驱动晶体管T1的栅极T10在发光阶段处于浮置(Floating)状态,被存储电容Cst保持,由于栅极与数据线之间的寄生电容的存在,数据信号跳变会耦合到驱动晶体管的栅信号部(第一节点N1)且无法恢复到初始状态,从而出现纵向串扰。
参考图14至图16B,挡块BK向右延伸,与第一像素单元101a的第一导电结构CDT1(第一复位晶体管T6的第二极T62)交叠,覆盖第一像素单元101a的驱动晶体管T1的栅极T10上的信号,屏蔽驱动晶体管T1的栅极T10(驱动晶体管的栅信号部PT1)与数据线的寄生电容,降低耦合影响,减轻纵向串扰。
在另一实施例中,调整了显示面板中的连接电极CEf在第二方向Y上的长度,如图16A和图16B所示,增加连接电极CEf在第二方向Y上的长度。图16A和图16B所示的连接电极CEf可称作屏蔽部CEs。屏蔽部CEs和连接电极CEd(第二连接电极CEd)构成连接元件CE0。屏蔽部CEs可替换连接电极CEf,无需额外的工艺制作。
参考图10和图11,连接电极CEb的另一端通过过孔H21与驱动晶体管T1的栅极T10(也即存储电容Cst的第一极Ca)电连接,连接电极CEb的一端通过过孔H22与第一复位晶体管T6的第二极T62电连接,连接电极CEb也可称作连接线CL。如图11所示,驱动晶体管T1的栅极T10通过连接线CL与阈值补偿晶体管T3的第二极T32相连。
例如,参考图10和图11,第一导电结构CDT1通过连接线CL与驱动晶体管T1的栅极T10相连。换句话说,驱动晶体管T1的栅极T10通过接线CL与第一导电结构CDT1相连。例如,第一导电结构CDT1的材料与连接线CL的材料不同。例如,连接线CL的材料包括金属。
例如,如图11和图18所示,连接线CL与驱动晶体管T1的栅极T10接触。例如,如图11和图18所示,连接线CL与第一导电结构CDT1接触。即,连接线CL的两端与驱动晶体管T1的栅极T10和第一导电结构CDT1分别接触。
例如,如图11所示,第一导电结构CDT1、连接线CL和驱动晶体管T1的栅极T10构成驱动晶体管T1的栅信号部PT1。从而,挡块BK与第一导电结构CDT1交叠可以屏蔽驱动晶体管的栅信号部与数据线的寄生电容,降低纵向串扰。例如,例如,第一导电结构CDT1、连接线CL和驱动晶体管T1的栅极T10构成同一个节点。例如,第一导电结构CDT1、连接线CL和驱动晶体管T1的栅极T10上的电位相同或基本相同。即,栅信号部PT1上各位置处的电位相同或基本相同。
参考图16A、图16B和图17,屏蔽部CEs沿第二方向Y延伸。例如,屏蔽部CEs的延伸方向与数据线DT的延伸方向相同。如图20所示,发光元件20通过连接元件CE0与像素电路10相连。在本公开的实施例中,一个部件的延伸方式是指该部件的大体的走向或趋势,并不一定该部件的所有位置都是沿着该延伸方向延伸的。
参考图16A、图16B和图17,数据线DT与屏蔽部CEs位于同一层,数据线DT与屏蔽部CEs均位于第四导电图案层LY4。数据线DT包括两条相邻数据线DT,屏蔽部CEs位于两条相邻数据线DT之间,屏蔽部CEs在衬底基板BS上的正投影与连接线CL在衬底基板BS上的正投影至少部分交叠。例如,两条相邻数据线DT沿第一方向X排列,数据线DT沿第二方向延伸。参考图16A、图16B和图17,数据线DT包括第一数据线DT1和第三数据线DT3,第一数据线DT1和第三数据线DT3相邻,在第一方向X上,屏蔽部CEs位于第一数据线DT1和第三数据线DT3之间。在本公开的实施例中,部件A和部件B相邻是指部件A和部件B之间不具有部件A,也不具有部件B。屏蔽部CEs沿第二方向延伸,穿插在两条相邻数据线DT之间,在相邻数据线距离较近的位置,屏蔽效果更明显。本公开的实施例以数据线DT与屏蔽部CEs位于同一层为例进行说明,在其他的实施例中,数据线DT与屏蔽部CEs位于同一层也可以位于不同的层。
在本公开的实施例中,屏蔽部CEs在衬底基板BS上的正投影与连接线CL在衬底基板BS上的正投影至少部分交叠,使得屏蔽部CEs屏蔽驱动晶体管的栅信号部与数据线之间的寄生电容,减轻纵向串扰问题。
例如,采用120Hz的驱动方案采用分时写入方式,即数据信号先存储到存储电容中, 然后扫描信号开启再写入像素单元中,数据信号之间的干扰会影响数据信号的准确写入,影响显示效果。在本公开的实施例中,屏蔽部CEs位于两条相邻数据线DT之间,连接线CL在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影至少部分交叠,可以很好的减少耦合影响,改善这一问题。需要说明的是,屏蔽部CEs位于两条相邻数据线DT之间,是描述的屏蔽部CEs的设置位置,屏蔽部CEs位于两条相邻数据线DT之间,但每两条相邻数据线DT之间并一定都设有屏蔽部CEs。如图16A和图17所示,第一数据线DT1和第三数据线DT3相邻,屏蔽部CEs位于第一数据线DT1和第三数据线DT3之间,第四数据线DT4和第二数据线DT2相邻,屏蔽部CEs位于第四数据线DT4和第二数据线DT2之间,虽然第三数据线DT3和第四数据线DT4相邻,但其间并没有设置屏蔽部CEs。
例如,如图17所示,为了最大限度的减轻纵向串扰,屏蔽部CEs在衬底基板BS上的正投影大于连接线CL在衬底基板BS上的正投影。例如,屏蔽部CEs在衬底基板BS上的正投影覆盖连接线CL在衬底基板BS上的正投影。例如,在平面图中,屏蔽部CEs覆盖连接线CL。如图17和图18所示,衬底基板BS的主表面为用于制作各个部件的表面,各部件设置在衬底基板BS的主表面上。
例如,为了较大程度地减轻纵向串扰,驱动晶体管T1的栅极T10在衬底基板BS上的正投影与屏蔽部CEs在衬底基板BS上的正投影部分交叠,屏蔽部CEs与驱动晶体管T1的栅极T10的交叠部分的面积小于驱动晶体管T1的栅极T10的面积。
例如,如图17所示,驱动晶体管T1的栅极T10在第一方向X上的尺寸大于屏蔽部CEs在第一方向X上的尺寸;屏蔽部CEs在第二方向Y上的尺寸大于驱动晶体管T1的栅极在第二方向Y上的尺寸。
例如,如图17所示,驱动晶体管T1的栅极T10在第一方向X上从两侧分别超出屏蔽部CEs。
例如,如图17所示,屏蔽部CEs在衬底基板BS上的正投影与栅线GT在衬底基板BS上的正投影交叠。
例如,如图17所示,栅线GT在衬底基板BS的上的正投影与屏蔽部CEs在衬底基板BS的上的正投影部分交叠。
例如,像素单元包括位于同一列且相邻的两个像素单元,两条相邻的数据线DT分别与两个像素单元相连。图16A示出了第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d的位置。图16A示出了第一数据线DT1、第二数据线DT2、第三数据线DT3和第四数据线DT4。参考图16A和图17,第一数据线DT1与第一像素单元101a相连,第二数据线DT2与第二像素单元101b相连,第三数据线DT3与第三像素单元101c相连,第四数据线DT4与第四像素单元101d相连。第一数据线DT1被配置为向第一像素单元101a的像素电路提供第一数据信号。第二数据线DT2被配置为向第二像素单元101b的像素电路提供第二数据信号。第三数据线DT3被配置为向第三像素单元101c的像素电路提供第四数据信号。第四数据线DT4被配置为向第四像素单元101d的像 素电路提供第四数据信号。
例如,参照图15,挡块BK在衬底基板上的正投影与第四数据线DT4在衬底基板上的正投影部分交叠。
例如,参照图6、图9、图11和图15,以位于第一像素单元101a和第二像素单元101b内的挡块BK为例,挡块BK具有第一边缘E1,第一边缘E1与第四数据线DT4交叠,第一边缘E1与第四数据线DT4之间的夹角θ1大于零并且小于90°。或者说,第一边缘E1与第四数据线DT4的延伸方向之间的夹角θ1大于零并且小于90°。第四数据线DT4的延伸方向为第二方向Y。换句话说,第一边缘E1相对于第四数据线DT4倾斜。这种设置方式利于减小第四数据线DT4与挡块BK的交叠面积,减小寄生电容,避免影响第四像素单元的数据写入速度。
例如,参照图6、图9、图11和图15,以位于第一像素单元101a和第二像素单元101b内的挡块BK为例,挡块BK具有第二边缘E2,第二边缘E2与第三数据线DT3交叠,第二边缘E2与第三数据线DT3之间的夹角θ2大于零并且小于90°。或者说,第二边缘E2与第三数据线DT3的延伸方向之间的夹角θ2大于零并且小于90°。第三数据线DT3的延伸方向为第二方向Y。换句话说,第二边缘E2相对于第三数据线DT3倾斜。这种设置方式利于减小第三数据线DT3与挡块BK的交叠面积,减小寄生电容,避免影响第三像素单元的数据写入速度。
参考图14、图16A和图21,第一像素单元101a、第二像素单元101b、第三像素单元101c和第四像素单元101d构成一个重复单元RP。多个重复单元RP可构成阵列。重复单元RP为显示阵列的一个最小重复单元。
在图21中,在同一个像素单元中,第一复位晶体管T6和第二复位晶体管T7连接至同一条复位控制信号线RT,以在相同时刻被输入相同的复位控制信号,但本公开的实施例不限于此。
在其他的实施例中,如图1所示,在同一个像素单元中,也可以第一复位晶体管T6和第二复位晶体管T7分别连接至第一复位控制信号线和第二复位控制信号线,第一复位控制信号线和第二复位控制信号线彼此绝缘以被分别输入信号。此情况下,第一复位晶体管T6和第二复位晶体管T7在不同的时刻被输入信号,如前所述,第一复位晶体管T6在第一复位阶段t1被输入复位控制信号RESET,第二复位晶体管T7在数据写入及阈值补偿和第二复位阶段t2被输入扫描信号SCAN。例如,本级的栅线GT与下一级的复位控制信号线相连。例如,栅线GT和第二复位控制信号线RT2可以电连接以在同一时间输入相同的信号。
例如,如图17所示,第一复位晶体管T6的第二极T62通过连接线CL与驱动晶体管T1的栅极T10相连。如前所述,第一复位晶体管T6的第二极T62与阈值补偿晶体管T3的第二极T32一体形成,从而,阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如,如图17所示,屏蔽部CEs在衬底基板BS的上的正投影与第一复位晶体管T6 的第二极T62在衬底基板BS的上的正投影至少部分交叠。同样,因第一复位晶体管T6的第二极T62与阈值补偿晶体管T3的第二极T32一体形成,屏蔽部CEs在衬底基板BS的上的正投影与阈值补偿晶体管T3的第二极T32在衬底基板BS的上的正投影至少部分交叠。
例如,如图17所示,屏蔽部CEs在衬底基板BS的上的正投影与挡块BK在衬底基板BS的上的正投影不交叠,从而,屏蔽部CEs在第二方向Y上的上端位置得以限定。
例如,参考图9和图17,第一初始化信号线INT1和第二初始化信号线INT2分设在驱动晶体管T1的栅极T10的相对的两侧,屏蔽部CEs在衬底基板BS的上的正投影与第二初始化信号线INT2在衬底基板BS的上的正投影部分交叠。
进一步例如,屏蔽部CEs在衬底基板BS的上的正投影与下一行的像素单元的第二导电连接部CP2在衬底基板BS的上的正投影部分交叠,从而,第二导电连接部CP2与屏蔽部CEs之间形成电容,该电容作为稳定电容,起到减少第一复位晶体管T6的漏电流的作用。
例如,参考图15和图17,屏蔽部CEs与第一初始化信号线INT1在衬底基板BS的上的正投影不交叠。
例如,参考图15,第一复位控制信号线RT1和第二复位控制信号线RT2分设在驱动晶体管T1的栅极T10的相对的两侧,参考图17,第二复位控制信号线RT2在衬底基板BS的上的正投影和屏蔽部CEs在衬底基板BS的上的正投影不交叠。从而,屏蔽部CEs在第二方向Y上的下端位置得以限定。
例如,参考图15和图17,第一复位控制信号线RT1在衬底基板BS的上的正投影和屏蔽部CEs在衬底基板BS的上的正投影不交叠。
例如,参考图15,第一复位控制信号线沿第一方向X延伸,第二复位控制信号线沿第一方向X延伸。
在图14中,每个连接电极CEf与一个发光元件相连,即,每个连接电极CEf对应一个像素单元101。在图16A中,每个屏蔽部CEs与一个发光元件相连,即,每个屏蔽部CEs对应一个像素单元101。
例如,参考图5,第一复位晶体管T6的第一栅极T601和第二栅极T602在衬底基板BS上的正投影与第一复位晶体管T6的第一沟道T631和第二沟道T632在衬底基板BS上的正投影分别交叠。
例如,如图11和图13所示,第一电源线VDD1通过电源连接线VDD0与存储电容Cst的第二极Cb相连。
通常技术中,阈值补偿晶体管T3为双栅晶体管,阈值补偿晶体管T3的中间节点(第一导电连接部CP1)会受到扫描信号的跳变扰动,在扫描信号关断瞬间电压增高,向驱动晶体管T1的栅极漏电加剧,会导致闪烁(Flicker)问题。
例如,参考图13和图15,为了减轻阈值补偿晶体管T3的漏电,挡块BK在衬底基板BS上的正投影与第一导电连接部CP1在衬底基板BS上的正投影至少部分交叠。挡块 BK与第一导电连接部CP1之间形成稳定电容。增加阈值补偿晶体管T3的中间节点与第一电压信号ELVDD的寄生电容,可以降低扰动量,改善漏电问题。
在衬底基板上形成像素电路,形成图15或图17所示的显示面板,在图15或图17所示的显示面板的基础上,再形成发光元件,得到可以进行显示的显示面板,从而,像素电路比发光元件更靠近衬底基板。如图20所示,像素电路10比发光元件20更靠近所述衬底基板BS。
例如,图18为图17中沿AB线的剖视图。图19示出了发光元件20的第一极201。图17为本公开一实施例提供的显示面板的剖视图。图19中省略了发光元件的第一极201之上的膜层。发光元件20的第一极201以上的各层可参照截面图。当然,发光元件的第一极201的设置位置和形状不限于图19所示,本领域技术人员可以根据需要调整发光元件的第一极201的设置位置和形状。
参考图18和图20,缓冲层BL位于衬底基板BS上,隔离层BR位于缓冲层BL上,晶体管的沟道区、源极和漏极位于隔离层BR上,在晶体管的沟道区、源极和漏极上形成第一栅绝缘层GI1,第一导电图案层LY1位于第一栅绝缘层GI1上,第二栅绝缘层GI2位于第一导电图案层LY1上,第二导电图案层LY2位于第二栅绝缘层GI2上,层间绝缘层ILD位于第二导电图案层LY2上,第三导电图案层LY3位于层间绝缘层ILD上,钝化层PVX位于第一导电图案层LY上,第一平坦化层PLN1位于钝化层PVX上,第四导电图案层LY4位于第一平坦化层PLN1上。
参考图20,第二平坦化层PLN2位于第四导电图案层LY4上,发光元件20的第一极201位于第二平坦化层PLN2上,像素定义层PDL以及隔垫物PS位于第二平坦化层PLN2上,像素定义层PDL具有开口OPN,开口OPN被配置为限定像素单元的发光面积(出光区域,有效发光面积)。隔垫物PS被配置为在形成发光功能层203时支撑精细金属掩膜。
例如,开口OPN为像素单元的出光区域。发光功能层203位于发光元件20的第一极201之上,发光元件20的第二极202位于发光功能层203上,光元件20上设置封装层CPS。封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如,第一封装层CPS1和第三封装层CPS3为无机材料层,第二封装层CPS2为有机材料层。例如,第一极201为发光元件20的阳极,第二电极202为发光元件20的阴极,但不限于此。
如图19和图20所示,发光元件20的第一极201通过贯穿第二平坦化层PLN2的过孔H9与屏蔽部CEs(连接电极CEf)相连。
例如,发光元件20包括有机发光二极管。发光功能层203位于第二极202和第一极201之间。第二极202位于第一极201的远离衬底基板BS的一侧,发光功能层203至少包括发光层,还可以包括空穴传输层、空穴注入层,电子传输层、电子注入层至少之一。
如图6和图18所示,存储电容的第二极Cb具有开口OPN1,开口OPN1的设置利于连接电极CEb与驱动晶体管T1的栅极T10相连。
例如,本公开的实施例的像素电路中的晶体管均为薄膜晶体管。例如,第一导电图案层LY1、第二导电图案层LY2、第三导电图案层LY3、第四导电图案层LY4均采用金属材料制作。例如,第一导电图案层LY1和第二导电图案层LY2采用镍、铝等金属材料形成,但不限于此。例如,第三导电图案层LY3和第四导电图案层LY4采用钛、铝等材料形成,但不限于此。例如,第三导电图案层LY3和第四导电图案层LY4分别为Ti/AL/Ti三个子层形成的结构,但不限于此。例如,衬底基板可以采用玻璃基板或聚酰亚胺基板,但不限于此,可根据需要进行选择。例如,第一栅绝缘层GI1、第二栅绝缘层GI2、层间绝缘层ILD、钝化层PVX、第一平坦化层PLN1、第二平坦化层PLN2、像素定义层PDL、隔垫物PS均采用绝缘材料制作。发光元件的第一极201和第二极202的材料可根据需要进行选取。一些实施例中,第一极201可采用透明导电金属氧化物和银至少之一,但不限于此。例如,透明导电金属氧化物包括氧化铟锡(ITO),但不限于此。例如,第一极201可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中,第二极202可以为低功函的金属,可采用镁和银至少之一,但不限于此。
在本公开的实施例提供的显示面板中,也可以不设置如图6所示的结构的挡块BK,当然,也可以不设置如图16A所示的屏蔽部CEs。例如,在一些实施例中,不设置挡块BK,或者设置其他形状或结构的挡块。例如,在一些实施例中,不设置屏蔽部CEs,而是设置如图14所示的连接电极CEf。
本公开的实施例提供的显示面板,可以根据显示面板的结构来进行制作。以下列举一种可行的制作方法,需要说明的是,本公开的实施例提供的显示面板的制作方法不限于下述方法。
结合之前的附图对制作方法进行描述。本公开的实施例提供的显示面板的制作方法,包括如下步骤。
步骤S1、在衬底基板上形成缓冲层BL。
步骤S2、在缓冲层BL上形成隔离层BR。
步骤S3、在隔离层BR上形成半导体图形SCP。
步骤S4、在半导体图形SCP上形成第一栅绝缘层GI1。
步骤S5、在第一栅绝缘层GI1上形成第一导电薄膜,对第一导电薄膜进行构图形成第一导电图案层LY1。
步骤S6、以第一导电图案层LY1为掩模版对半导体图形SCP进行掺杂,形成晶体管的有源层ACT、源极和漏极。
步骤S7、形成第二栅绝缘层GI2。
步骤S8、在第二栅绝缘层GI2上形成第二导电薄膜,对第二导电薄膜进行构图形成第二导电图案层LY2。
步骤S9、在第二导电图案层LY2上形成层间绝缘层ILD。
步骤S10、在第一栅绝缘层GI1、第二栅绝缘层GI2和层间绝缘层ILD至少之一中形成过孔(参照图8)。
步骤S11、在层间绝缘层ILD上形成第三导电薄膜,对第三导电薄膜进行构图形成第三导电图案层LY3。第三导电图案层LY3中的部件分别通过过孔与第二导电图案层LY2中的部件以及晶体管的源极和漏极相连。
步骤S12、形成钝化层PVX和第一平坦化层PLN1。
步骤S13、在钝化层PVX和第一平坦化层PLN1中形成过孔(参照图12)。
步骤S14、在第一平坦化层PLN1上形成第四导电薄膜,对第四导电薄膜进行构图形成第四导电图案层LY4。第四导电图案层LY4中的部件可通过钝化层PVX和第一平坦化层PLN1中的过孔与第三导电图案层LY3中的部件相连。
步骤S15、在第四导电图案层LY4上形成发光元件20的第一极201。
步骤S16、形成像素定义层PDL和隔垫物PS。
步骤S17、形成发光元件20的发光功能层203。
步骤S18、形成发光元件20的第二极202。
步骤S19、形成封装层CPS。
本公开至少一实施例还提供一种显示装置,包括上述任一项显示面板。例如,显示装置包括OLED或包括OLED的高帧频驱动的产品。例如,显示装置包括含有上述显示面板的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
以上以7T1C的像素电路为例进行说明,本公开的实施例包括但不限于此。需要说明的是,本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如,在另外的一些实施例中,显示面板的像素电路还可以为包括其他数量的晶体管的结构,如7T2C结构、6T1C结构、6T2C结构或者9T2C结构,本公开实施例对此不作限定。
在本公开的实施例中,位于同一层的元件可由同一膜层经同一构图工艺行程。例如,位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是,为了清晰起见,在用于描述本公开的实施例的附图中,层或区域的厚度被放大。可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
在本公开的实施例中,构图或构图工艺可只包括光刻工艺,或包括光刻工艺以及刻蚀步骤,或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程,利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下,本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (26)
- 一种显示面板,包括:衬底基板;像素单元,位于所述衬底基板上,包括像素电路和发光元件,所述像素电路被配置为驱动所述发光元件,所述像素电路比所述发光元件更靠近所述衬底基板,所述像素电路包括驱动晶体管;数据线,被配置为向所述像素电路提供数据信号;连接元件,所述发光元件通过所述连接元件与所述像素电路相连,所述连接元件包括屏蔽部;以及连接线,与所述驱动晶体管的栅极相连,其中,所述数据线包括两条相邻数据线,所述屏蔽部位于所述两条相邻数据线之间,所述连接线在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影至少部分交叠。
- 根据权利要求1所述的显示面板,其中,所述屏蔽部在所述衬底基板上的正投影大于所述连接线在所述衬底基板上的正投影。
- 根据权利要求1或2所述的显示面板,其中,所述驱动晶体管的栅极在所述衬底基板上的正投影与所述屏蔽部在所述衬底基板上的正投影部分交叠,所述屏蔽部与所述驱动晶体管的栅极的交叠部分的面积小于所述驱动晶体管的栅极的面积。
- 根据权利要求1-3任一项所述的显示面板,其中,所述两条相邻数据线沿第一方向排列,所述数据线沿第二方向延伸。
- 根据权利要求4所述的显示面板,其中,所述驱动晶体管的栅极在所述第一方向上的尺寸大于所述屏蔽部在所述第一方向上的尺寸;所述屏蔽部在所述第二方向上的尺寸大于所述驱动晶体管的栅极在所述第二方向上的尺寸。
- 根据权利要求1-5任一项所述的显示面板,其中,所述连接线与所述驱动晶体管的栅极接触。
- 根据权利要求1-6任一项所述的显示面板,其中,所述数据线与所述屏蔽部位于同一层,所述屏蔽部的延伸方向与所述数据线的延伸方向相同。
- 根据权利要求1-7任一项所述的显示面板,还包括第一导电结构,其中,所述连接线与所述第一导电结构相连,所述屏蔽部在所述衬底基板上的正投影与所述第一导电结构在所述衬底基板上的正投影至少部分交叠。
- 根据权利要求8所述的显示面板,其中,所述像素电路还包括第一复位晶体管,所述第一复位晶体管的第二极与所述驱动晶体管的栅极相连,所述第一导电结构复用为所述第一复位晶体管的第二极。
- 根据权利要求9所述的显示面板,还包括第一复位控制信号线和第一初始化信号 线,其中,所述第一复位晶体管的栅极与所述第一复位控制信号线相连,所述第一复位晶体管的第一极与所述第一初始化信号线相连。
- 根据权利要求9或10所述的显示面板,其中,所述第一复位晶体管包括第一沟道和第二沟道,所述第一复位晶体管的第一沟道和第二沟道通过导电连接部相连,所述屏蔽部在所述衬底基板的上的正投影与所述第一复位晶体管的所述导电连接部在所述衬底基板的上的正投影部分交叠。
- 根据权利要求10或11所述的显示面板,还包括第二初始化信号线,其中,所述第一初始化信号线和所述第二初始化信号线分设在所述驱动晶体管的栅极的相对的两侧,所述屏蔽部在所述衬底基板上的正投影与所述第二初始化信号线在所述衬底基板上的正投影部分交叠。
- 根据权利要求1-12任一项所述的显示面板,还包括第一电源线和挡块,其中,所述第一电源线被配置为向所述像素电路提供第一电源电压,所述挡块与所述第一电源线电连接,所述第一导电结构在所述衬底基板上的正投影与所述挡块在所述衬底基板上的正投影至少部分交叠。
- 根据权利要求13所述的显示面板,还包括第二导电结构,其中,所述数据线与所述第二导电结构相连,所述挡块在所述衬底基板上的正投影与所述第二导电结构在所述衬底基板上的正投影至少部分交叠。
- 根据权利要求13或14所述的显示面板,还包括栅线,其中,所述栅线与所述数据线相互交叉且彼此绝缘,所述栅线被配置为向所述像素电路提供扫描信号,所述像素电路还包括阈值补偿晶体管,所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极相连,所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极相连;所述阈值补偿晶体管的栅极与所述栅线相连;所述驱动晶体管的栅极通过所述连接线与所述阈值补偿晶体管的第二极相连,所述阈值补偿晶体管包括第一沟道和第二沟道,所述第一沟道和所述第二沟道通过导电连接部相连;所述挡块在所述衬底基板上的正投影与所述阈值补偿晶体管的所述导电连接部在所述衬底基板上的正投影至少部分交叠。
- 根据权利要求15所述的显示面板,其中,所述挡块的与所述第一导电结构交叠的部分在所述衬底基板上的正投影的面积大于所述挡块的与所述阈值补偿晶体管的所述导电连接部交叠的部分在所述衬底基板上的正投影的面积。
- 根据权利要求13-16任一项所述的显示面板,其中,所述第一导电结构的材料与所述连接线的材料不同。
- 根据权利要求1-17任一项所述的显示面板,其中,所述像素单元包括位于同一列且相邻的两个像素单元,所述两条相邻的数据线分别与所述两个像素单元相连。
- 根据权利要求12-17任一项所述的显示面板,还包括第二复位控制信号线,其中,所述像素电路还包括第二复位晶体管,所述第二复位晶体管的栅极与所述第二复位控制信 号线相连,所述第二复位晶体管的第一极与所述第二初始化信号线相连,所述第二复位晶体管的第二极与所述发光元件的第一极相连。
- 根据权利要求1-19任一项所述的显示面板,其中,所述像素电路还包括第一电源端和存储电容,所述存储电容的第一极与所述驱动晶体管的栅极相连,所述存储电容的第二极与所述第一电源端相连。
- 根据权利要求20所述的显示面板,其中,所述像素电路还包括数据写入晶体管,所述数据写入晶体管的栅极与所述栅线相连,所述数据写入晶体管的第一极与所述数据线相连,所述数据写入晶体管的第二极与所述驱动晶体管的第一极相连。
- 根据权利要求20或21所述的显示面板,还包括发光控制信号线,其中,所述像素电路还包括第一发光控制晶体管和第二发光控制晶体管,所述第一发光控制晶体管的栅极与所述发光控制信号线相连,所述第一发光控制晶体管的第一极与所述第一电源端相连,所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极相连;所述第二发光控制晶体管的栅极与所述发光控制信号线相连,所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极相连,所述第二发光控制晶体管的第二极与所述发光元件的第一极相连。
- 根据权利要求22所述的显示面板,其中,所述数据线具有第一部分和第二部分,所述两条相邻数据线的第一部分之间的间距大于所述两条相邻数据线的第二部分之间的间距,所述屏蔽部位于所述两条相邻数据线的第二部分之间。
- 根据权利要求23所述的显示面板,其中,所述两条相邻数据线的第二部分分别靠近所述第一发光控制晶体管和所述第二发光控制晶体管,所述存储电容位于所述两条相邻数据线的第一部分之间。
- 根据权利要求1-24任一项所述的显示面板,其中,所述连接元件还包括连接电极,所述连接电极与所述像素电路相连,所述发光元件通过所述屏蔽部与所述连接电极相连。
- 一种显示装置,包括根据权利要求1-25任一项所述的显示面板。
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