WO2022127468A1 - 供电电路、驱动芯片以及显示装置 - Google Patents
供电电路、驱动芯片以及显示装置 Download PDFInfo
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- WO2022127468A1 WO2022127468A1 PCT/CN2021/130736 CN2021130736W WO2022127468A1 WO 2022127468 A1 WO2022127468 A1 WO 2022127468A1 CN 2021130736 W CN2021130736 W CN 2021130736W WO 2022127468 A1 WO2022127468 A1 WO 2022127468A1
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- type field
- power supply
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- 230000005669 field effect Effects 0.000 claims description 145
- 238000010586 diagram Methods 0.000 description 5
- -1 MOS metal oxide Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/345—Current stabilisation; Maintaining constant current
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
Definitions
- the present application relates to the technical field of integrated circuits, and in particular, to a power supply circuit, a driving chip and a display device.
- LED Light Emitting Diode, light emitting diode
- the constant current source generating circuit is divided into three parts, wherein the first part is the reference current generating circuit 101 , the second part is the current mirror circuit 102 , and the third part is the current output circuit 103 .
- the specific working principle of the constant current generating circuit is as follows: firstly, the reference current generating circuit 101 uses the built-in reference voltage Vref and the external resistance Rext to generate the reference current I 0 , and then the reference current I 0 is generated by the current mirror circuit 102 (the ratio of the number of MOS metal oxide semiconductor devices) is M:N) to obtain the current I 1 by mirroring the current; finally, the current output circuit 103 (the ratio of the number of MOS devices is J:K) generates and drives the output constant current source Iout.
- the second and third parts are to adapt to the LED common anode structure and meet the multi-channel driving capability requirements.
- the purpose of the embodiments of the present application is to provide a power supply circuit, a driving chip and a display device.
- the embodiment of the present application provides a power supply circuit, including:
- a reference current generating circuit configured to generate a reference current
- a driving circuit connected to the reference current generating circuit, configured to generate a mirror current with an adjustable mirror ratio according to the reference current, and output a bias voltage and a gate driving voltage;
- a channel current output circuit connected to the driving circuit, is configured to receive the bias voltage and the gate driving voltage, and generate a channel current with an adjustable mirror ratio according to the mirror current.
- the reference current generating circuit includes:
- the reverse input terminal is configured to input the reference voltage
- the first end is grounded, and the second end is connected to the forward input end of the first amplifier
- a plurality of groups of first P-type field effect transistors the source is connected to the power supply, the gate is connected to the output end of the first amplifier respectively, the drain is connected to the second end of the resistor, and the reference current is output to the resistor;
- the first switch is connected to the plurality of groups of first P-type field effect transistors, and is configured to independently control whether the first P-type field effect transistors of each group are turned on or off.
- the number of groups of the first P-type field effect transistors is four.
- the drive circuit includes:
- the second P-type field effect transistor the source is connected to the power supply, the gate is connected to the gates of the plurality of groups of the first P-type field effect transistor, and the drain is configured to output the mirror current;
- the inverting input terminal is configured to input a reference voltage
- the output terminal is configured to provide the gate driving voltage
- the first N-type field effect transistor the gate is connected to the output terminal of the second amplifier, the source is grounded, and the drain is connected to the drain of the second P-type field effect transistor and the forward input terminal of the second amplifier , configured to provide the same bias voltage as the reference voltage.
- the channel current output circuit includes:
- the forward input terminal is connected to the drain of the first N-type field effect transistor
- the third N-type field effect transistor the gate is connected to the output terminal of the third amplifier; the source is connected to the reverse input terminal of the third amplifier, and the drain is configured to output the channel current;
- the drains are respectively connected to the reverse input terminals of the third amplifier; the gates are respectively connected to the output terminals of the second amplifier; the sources are grounded;
- the second switch is connected to a plurality of groups of the second N-type field effect transistors, and is configured to independently control the conduction of each group of the second N-type field effect transistors.
- the number of groups of the second N-type field effect transistors is four.
- the drive circuit further includes:
- a drive buffer is connected to the output terminal of the second amplifier and the gates of the plurality of second N-type field effect transistors, and is configured to increase the gate drive voltage.
- the drive buffer includes two inverters connected in series.
- the first switch includes a plurality of first sub-switches, which independently control whether the plurality of groups of the first P-type field effect transistors are turned on or not;
- the second switch includes a plurality of second sub-switches, which independently control whether the plurality of groups of the second N-type field effect transistors are turned on or off.
- a plurality of the first sub-switches are connected to a plurality of groups of the first P-type field effect transistors in a one-to-one correspondence;
- the plurality of second sub-switches are connected to the plurality of groups of the second N-type field effect transistors in one-to-one correspondence.
- the number ratio between the multiple groups of first P-type field effect transistors is the same as the number ratio between the multiple groups of second N-type field effect transistors.
- the adjustment ratio of the number of conduction of the plurality of groups of first P-type field effect transistors is the same as the adjustment ratio of the number of conduction of the plurality of groups of second N-type field effect transistors.
- the switch control signals of the first switch and the second switch are the same.
- the embodiment of the present application also provides a driving chip, including the above-mentioned power supply circuit.
- the embodiment of the present application also provides a display device, including:
- the LED display panel is of common cathode or common anode structure
- a driver chip is connected to the LED display panel, and the driver chip includes the above-mentioned power supply circuit, wherein there are multiple channel current output circuits; if the LED display panel has a common cathode structure, the multiple channel current output circuits respectively connecting the anodes of the plurality of light emitting diodes of the LED display panel;
- the plurality of channel current output circuits are respectively connected to the cathodes of the plurality of light emitting diodes of the LED display panel.
- FIG. 1 is a schematic structural diagram of a power supply circuit provided in the background technology
- FIG. 2 is a schematic diagram of the principle of a current mirror provided by an embodiment of the present application.
- FIG. 3 is a schematic diagram of a power supply circuit provided by an embodiment of the present application.
- 101-reference current generating circuit 101-reference current generating circuit; 102-current mirror circuit; 103-current output circuit; 301-reference current generating circuit; 302-drive circuit; 303-channel current output circuit.
- FIG. 2 is a schematic diagram of the principle of a current mirror provided by an embodiment of the present application.
- N-type field effect transistor (NOMS) NM0 and N-type field effect transistor NM1 have the same gate voltage Vg1, assuming that the gate voltage Vg2 of N-type field effect transistor NM2, N-type field effect transistor NM0,
- the drain voltages of N-type field effect transistor NM1 and N-type field effect transistor NM2 are Vd0, Vd1 and Vd2 respectively, then if the gate voltage Vg1 of N-type field effect transistor NM1 is equal to the gate voltage Vg2 of N-type field effect transistor NM2 , and the drain voltage Vd1 of the N-type field effect transistor NM1 is equal to the drain voltage Vd2 of the N-type field effect transistor NM2, then the two devices of the N-type field effect transistor NM1 and the N-type field effect transistor NM2 are in the same bias condition Then, the current I1 of the branch where the N-type field effect
- FIG. 3 is a schematic diagram of a power supply circuit provided by an embodiment of the present application.
- the power supply circuit includes: a reference current generating circuit 301 , a driving circuit 302 and a channel current output circuit 303 .
- the reference current generating circuit 301 is configured to generate the reference current I0.
- the reference current generating circuit 301 includes: a first amplifier OP0, a resistor REXT, multiple groups of first P-type field effect transistors PM0, and a first switch K0;
- the reverse input terminal of the first amplifier OP0 is configured to input the reference voltage VREF
- the output terminal is connected to the gates of multiple groups of first P-type field effect transistors PM0, and is configured to provide the gate voltage VGATEP
- the forward input terminal is connected to the first resistor REXT.
- the first end of the resistor REXT is grounded, and the second end is connected to the forward input end of the first amplifier OP0 and the drains of the plurality of groups of first P-type field effect transistors PM0.
- the sources of the plurality of first P-type field effect transistors PM0 are connected to the power supply, the gates are respectively connected to the output terminals of the first amplifier OP0, the drains are connected to the second terminal of the resistor REXT, and the reference current I0 is output to the resistor REXT.
- the reference voltage VREF can be generated by a bandgap reference voltage source inside the chip, and a negative feedback structure is formed by using the first amplifier OP0, multiple groups of first P-type field effect transistors PM0 and an external resistor REXT to obtain the reference current I0.
- I0 represents the reference current
- Vref represents the reference voltage
- Rext represents the resistance
- the first switch K0 is connected to a plurality of groups of the first P-type field effect transistors PM0, and is configured to independently control whether the first P-type field effect transistors PM0 of each group are turned on or off.
- the multiple groups of first P-type field effect transistors PM0 may be four groups (PM0:1, PM0:2, PM0:3, PM0:4), for example, four groups of first P-type field effect transistors PM0
- the number ratio can be M:M:2M:4M; the gate of each group of the first P-type field effect transistor PM0 is connected to the output end of the first amplifier OP0, the source is connected to the power supply, and the drain is connected to the resistor REXT and the first amplifier.
- OP0 is connected to the first terminal. It can be understood that the above is only an implementation example and should not be regarded as a limitation. In practical applications, the number of groups of the first P-type field effect transistor PM0 can be flexibly set according to requirements.
- the first switch K0 may include a plurality of first sub-switches (K0:1, K0:2, K0:3, K0:4), which are connected to a plurality of groups of first P-type field effect transistors PM0 in one-to-one correspondence, and are configured to individually control each Whether the first P-type field effect transistor PM0 of the group is turned on or not.
- each first sub-switch can have two states, which is connected to a high level to be turned on, and connected to a low level to be disconnected.
- K0:1 is configured to control the conduction of the first group of first P-type field effect transistors PM0:1, and K0:2 is configured to control the second group of first P-type field effect transistors PM0:2 Whether it is turned on or not
- K0:3 is configured to control the conduction of the third group of the first P-type field effect transistor PM0:3, and K0:4 is configured to control the fourth group of the first P-type field effect transistor PM0:4 of conduction or not.
- the conduction of K0:1, K0:2, K0:3, and K0:4 can be independently controlled, thereby controlling the conduction number of the first P-type field effect transistor PM0.
- the driving circuit 302 is connected to the reference current generating circuit 301, and is configured to generate a mirror current I1 with an adjustable mirror ratio according to the reference current I0, and output a bias voltage and a gate driving voltage;
- the driving circuit 302 includes: a second P-type field effect transistor PM1 , a second amplifier OP1 and a first N-type field effect transistor NM1 .
- the gate of the second P-type field effect transistor PM1 is connected to the gates of the plurality of groups of the first P-type field effect transistor PM0, the source is connected to the power supply, and the drain is configured to output a mirror current I1.
- the second P-type field effect transistor PM1 and multiple groups of the first P-type field effect transistor PM0 form a current mirror.
- the current of the MOS device is proportional to the size of the device.
- the current ratio is determined by The number of MOS devices is determined, and the required current ratio can be obtained by adjusting the number of MOS devices. Therefore, by controlling the first switch K0, the number of the first P-type field effect transistors PM0 that are turned on can be adjusted, thereby controlling the magnitude of the mirror current I1.
- the reverse input terminal of the second amplifier OP1 is configured to input the reference voltage VCRES, the output terminal is configured to provide the gate driving voltage VGATE, and the forward input terminal is connected to the drain of the first N-type field effect transistor NM0.
- the gate of the first N-type field effect transistor NM0 is connected to the output terminal of the second amplifier OP1, the source is grounded, and the drain is connected to the drain of the second P-type field effect transistor PM1 and the forward input terminal of the second amplifier OP1 , configured to provide the same bias voltage as the reference voltage VCRES.
- a negative feedback loop formed by the second P-type field effect transistor PM1, the first N-type field effect transistor NM0 and the second amplifier OP1 can set the drain voltage of the first N-type field effect transistor NM0 (i.e. bias voltage). Since the negative feedback system is in steady state, the voltages of the two input terminals of the second amplifier OP1 are the same (there is only a slight difference, depending on the open-loop gain of the loop), so the drain voltage of the first N-type field effect transistor NM0 is equal to that of the second amplifier OP1.
- the channel current output circuit 303 is connected to the driving circuit 302, and is configured to receive the bias voltage and the gate driving voltage, and generate a channel current Iout with an adjustable mirror ratio according to the mirror current I0.
- the channel current output circuit includes: a third amplifier DRIVER_OP, a third N-type field effect transistor NM2 , a plurality of groups of second N-type field effect transistors NM1 and a second switch K1 .
- the forward input terminal of the third amplifier DRIVER_OP is connected to the drain of the first N-type field effect transistor NM0, so the voltage input to the forward input terminal of the third amplifier DRIVER_OP is equal to the reference voltage VCRES.
- the gate of the third N-type field effect transistor NM2 is connected to the output terminal of the third amplifier DRIVER_OP; the source is connected to the drains of the second N-type field effect transistors NM1 and the inverting input terminal of the third amplifier DRIVER_OP , the drain is configured to output the channel current.
- the voltage input to the inverting input terminal of the third amplifier DRIVER_OP is also equal to the reference voltage VCRES.
- bias voltages are provided for the plurality of groups of second N-type field effect transistors NM1, and the bias voltages are also equal to the reference voltage VCRES.
- the drains of the plurality of groups of second N-type field effect transistors NM1 are respectively connected to the reverse input terminals of the third amplifier DRIVER_OP; the gates are respectively connected to the output terminals of the second amplifier OP1; and the sources are grounded.
- the second switch K1 is connected to a plurality of groups of the second N-type field effect transistors NM1, and is configured to independently control the conduction of each group of the second N-type field effect transistors NM1.
- the second N-type field effect transistor NM1 may have 4 groups (NM1:1, NM1:2, NM1:3, NM1:4), and the number ratio of each group of MOS transistors is K :K:2K:4K.
- Each group of second N-type field effect transistors NM1 is connected to the inverting input terminal of the third amplifier DRIVER_OP and the source of the third N-type field effect transistor NM2, so as to provide the same bias voltage for each group of N-type field effect transistors NM1.
- DRIVER_OP the third amplifier
- the third N-type field effect transistor NM2 so as to provide the same bias voltage for each group of N-type field effect transistors NM1.
- the second switch K1 may include a plurality of second sub-switches (K1:1, K1:2, K1:3, K1:4), which are connected to a plurality of groups of the second N-type field effect transistors NM1 in a one-to-one correspondence, and are configured to be individually Control whether the second N-type field effect transistor NM1 of each group is turned on or not.
- each second sub-switch can have two states, which is connected to a high level to be turned on, and connected to a low level to be disconnected.
- K1:1 controls the conduction of the first group of second N-type field effect transistors NM1:1
- K1:2 controls the conduction of the second group of second N-type field effect transistors NM1:2 and No
- K1:3 controls the conduction of the third group of the second N-type field effect transistors NM1:3
- K1:4 controls the conduction of the fourth group of the second N-type field effect transistors NM1:4.
- the drive circuit 302 further includes a drive buffer buffer, which is connected to the output end of the second amplifier OP1 and the gates of the plurality of groups of second N-type field effect transistors NM1, and is configured to increase By increasing the gate driving voltage and increasing the driving capability of the later stage, the buffer can be an inverter with a gradually increasing device size of several stages or a circuit with a similar structure, such as two inverters connected in series.
- a drive buffer buffer which is connected to the output end of the second amplifier OP1 and the gates of the plurality of groups of second N-type field effect transistors NM1, and is configured to increase
- the buffer can be an inverter with a gradually increasing device size of several stages or a circuit with a similar structure, such as two inverters connected in series.
- the number ratio between the multiple groups of first P-type field effect transistors and the number ratio between the multiple groups of second N-type field effect transistors may be the same.
- the number ratio of multiple groups of first P-type field effect transistors PM0 is M:M:2M:4M
- the number ratio of multiple groups of second N-type field effect transistors NN1 is K:K:2K:4K, it can be The number ratio is considered to be the same.
- the adjustment ratio of the number of conduction of the plurality of groups of first P-type field effect transistors is the same as the adjustment ratio of the number of conduction of the plurality of groups of second N-type field effect transistors.
- the number of the first P-type field effect transistors PM0 being turned on can be controlled by the first switch K0.
- the number of the first P-type field effect transistor PM0 to be turned on can be M, 2M, 3M, 4M, 5M, 6M, 7M, and 8M.
- the number of the second N-type field effect transistors NN1 turned on can be controlled by the second switch K1.
- the number K, 2K, 3K, 4K, 5K, 6K, 7K, 8K of the second N-type field effect transistor NN1 turned on. Therefore, the number of the first P-type field effect transistor PM0 being turned on is M.
- the number of the second N-type field effect transistor NN1 turned on is K, and the number of the first P-type field effect transistor PM0 turned on is 2M, the number of the second N-type field effect transistor NN1 turned on is 2K, with By analogy, it can be considered that the adjustment ratio of the number of conduction is the same.
- the switch control signals of the first switch and the second switch may be the same, so that the conduction number of the plurality of groups of first P-type field effect transistors is adjusted in proportion to the conduction of the plurality of groups of second N-type field effect transistors.
- the adjustment ratio of the number of passes is the same, that is, the values of control R1 and R2 are equal.
- the switch control signal can be configured to control the first switch K0 and the second switch K1.
- the switch control signals are the same, that is, the control signals of K0:1 and K1:1 are the same, the control signals of K0:2 and K1:2 are the same, K0: 3
- the control signals of K1:3 are the same, and the control signals of K0:4 and K1:4 are the same, so that the ratio of the number of the first P-type field effect transistors PM0 in the multiple groups to the number of the second N-type field effect transistors in the multiple groups is NN1.
- both R1 and R2 can be represented by R, and compared to cancel.
- the precise output current Iout can be obtained.
- a comparator and a logic circuit can be set to automatically determine whether the VGATE voltage is too high or too low, so as to output a corresponding switch control signal to control the first switch K0 and the second switch K1.
- the accuracy of the current mirror in a larger current range is guaranteed, and the power consumption of the chip is reduced at the same time.
- the table below shows the R value for different on-states of the switch.
- Idis represents the quiescent current of the entire chip
- Idis_ana represents the quiescent current of other analog modules
- I0 and I1 represent the two branch currents in the power supply circuit respectively
- L represents the number of output constant current channels
- ICH represents the analog circuit in the constant current source channel.
- Quiescent Current In general, N/M>1, and K/J>1. Therefore, it is I1 that varies greatly in the quiescent current of the chip.
- the power supply circuit provided in the embodiment of the present application can be applied to a driver chip, and the driver chip can be a driver chip of an LED (Light Emitting Diode, light-emitting diode) display panel.
- the driver chip can be a driver chip of an LED (Light Emitting Diode, light-emitting diode) display panel.
- An embodiment of the present application further provides a display device, the display device may include an LED display panel and a driving chip, and the LED display panel may be a common cathode or a common anode structure.
- the driver chip is connected to the LED display panel, and the driver chip may include the power supply circuit provided in the embodiment of the present application, wherein there are multiple channel current output circuits; the common anode means that the anodes of the multiple light-emitting diodes in the same row are connected together (For example, +5V), the output terminals IOUT of the current output circuits of the multiple channels are respectively connected to the cathodes of the multiple light-emitting diodes, and different levels of the cathodes control different brightness.
- the common anode means that the anodes of the multiple light-emitting diodes in the same row are connected together (For example, +5V), the output terminals IOUT of the current output circuits of the multiple channels are respectively connected to the cathodes of the multiple light-emitting diodes, and different levels of the cathodes control different brightness.
- Common cathode means that the cathodes of multiple light-emitting diodes in the same row are connected together (for example, grounded), and the output terminals IOUT of the current output circuits of multiple channels are respectively connected to the anodes of multiple light-emitting diodes. Different anode levels control different brightness. .
- Each functional module in each embodiment of the present application may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.
- the connection mentioned in the text can be a direct connection or an indirect connection.
- the mirror ratio is adjustable, the current accuracy can be improved, and when a large channel current is required, the mirror current can still be small, thereby reducing power consumption.
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Abstract
Description
Claims (15)
- 一种供电电路,其特征在于,包括:基准电流产生电路,配置成产生基准电流;驱动电路,连接所述基准电流产生电路,配置成根据所述基准电流,产生镜像比例可调的镜像电流,并输出偏置电压以及栅极驱动电压;通道电流输出电路,连接所述驱动电路,配置成接收所述偏置电压以及栅极驱动电压,并根据所述镜像电流,产生镜像比例可调的通道电流。
- 根据权利要求1所述的供电电路,其特征在于,所述基准电流产生电路包括:第一放大器,反向输入端配置成输入基准电压;电阻,第一端接地,第二端连接所述第一放大器的正向输入端;多组第一P型场效应管,源极接电源,栅极分别连接所述第一放大器的输出端,漏极连接所述电阻的第二端,向所述电阻输出所述基准电流;第一开关,连接所述多组第一P型场效应管,配置成独立控制每组的第一P型场效应管的导通与否。
- 根据权利要求2所述的供电电路,其特征在于,所述第一P型场效应管的组数为四组。
- 根据权利要求2或3所述的供电电路,其特征在于,所述驱动电路包括:第二P型场效应管,源极接电源,栅极连接所述多组第一P型场效应管的栅极,漏极配置成输出所述镜像电流;第二放大器,反向输入端配置成输入参考电压,输出端配置成提供所述栅极驱动电压;第一N型场效应管,栅极连接所述第二放大器的输出端,源极接地,漏极连接所述第二P型场效应管的漏极以及所述第二放大器的正向输入端,配置成提供与所述参考电压相同的所述偏置电压。
- 根据权利要求4所述的供电电路,其特征在于,所述通道电流输出电路包括:第三放大器,正向输入端连接所述第一N型场效应管的漏极;第三N型场效应管,栅极连接所述第三放大器的输出端;源极连接所述第三放大器的反向输入端,漏极配置成输出所述通道电流;多组第二N型场效应管,漏极分别连接所述第三放大器的反向输入端;栅极分别连接所述第二放大器的输出端;源极接地;第二开关,连接多组所述第二N型场效应管,配置成独立控制每组的第二N型场效应管的导通与否。
- 根据权利要求5所述的供电电路,其特征在于,所述第二N型场效应管的组数为四组。
- 根据权利要求5所述的供电电路,其特征在于,所述驱动电路还包括:驱动缓冲器,连接所述第二放大器的输出端和所述多组第二N型场效应管的栅极,配置成增大所述栅极驱动电压。
- 根据权利要求7所述的供电电路,其特征在于,所述驱动缓冲器包括两个串联的反相器。
- 根据权利要求5所述的供电电路,其特征在于,所述第一开关包括多个第一子开关,分别独立控制多组所述第一P型场效应管的导通与否;第二开关包括多个第二子开关,分别独立控制多组所述第二N型场效应管的导通与否。
- 根据权利要求9所述的供电电路,其特征在于,多个所述第一子开关与多组所述第一P型场效应管一一对应连接;多个所述第二子开关与多组所述第二N型场效应管一一对应连接。
- 根据权利要求5所述的供电电路,其特征在于,所述多组第一P型场效应管之间的个数比与所述多组第二N型场效应管之间的个数比相同。
- 根据权利要求11所述的供电电路,所述多组第一P型场效应管的导通个数调整比例与所述多组第二N型场效应管的导通个数调整比例相同。
- 根据权利要求12所述的供电电路,其特征在于,所述第一开关和第二开关的开关控制信号相同。
- 一种驱动芯片,其特征在于,包括如权利要求1至13任一项所述的供电电路。
- 一种显示装置,其特征在于,包括:LED显示面板,所述LED显示面板为共阴极或共阳极结构;驱动芯片,连接所述LED显示面板,所述驱动芯片包括权利要求1至13任一项所述的供电电路,其中,所述通道电流输出电路存在多个;若所述LED显示面板为共阴极结构,多个所述通道电流输出电路分别连接所述LED显示面板的多个发光二极管的阳极;若所述LED显示面板为共阳极结构,多个所述通道电流输出电路分别连接所述LED显示面板的多个发光二极管的阴极。
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JP2023524873A JP2023553251A (ja) | 2020-12-17 | 2021-11-15 | 給電回路、駆動用チップおよび表示装置 |
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CN116248136A (zh) * | 2023-03-02 | 2023-06-09 | 苏州纳芯微电子股份有限公司 | 发送器电路及具有其的总线收发器 |
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CN112423436A (zh) * | 2020-12-17 | 2021-02-26 | 北京集创北方科技股份有限公司 | 供电电路以及显示装置 |
CN113098483B (zh) * | 2021-03-26 | 2022-04-08 | 上海芯问科技有限公司 | 一种高速全差分升压转换电路 |
CN113672026B (zh) * | 2021-08-17 | 2022-11-29 | 晟合微电子(肇庆)有限公司 | Mipi的偏置电路、mipi模块及显示设备 |
CN114461006B (zh) * | 2022-01-17 | 2023-06-13 | 深圳市诚芯微科技股份有限公司 | 一种基准电压及倍压电路 |
CN117059020B (zh) * | 2023-09-14 | 2024-02-27 | 广东保伦电子股份有限公司 | 一种低转折电压的led显示屏驱动电路及led显示屏 |
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KR20230038261A (ko) | 2023-03-17 |
JP2023553251A (ja) | 2023-12-21 |
US20230402000A1 (en) | 2023-12-14 |
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CN112423436A (zh) | 2021-02-26 |
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