WO2022116283A1 - 面板驱动电路和显示面板 - Google Patents

面板驱动电路和显示面板 Download PDF

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Publication number
WO2022116283A1
WO2022116283A1 PCT/CN2020/137427 CN2020137427W WO2022116283A1 WO 2022116283 A1 WO2022116283 A1 WO 2022116283A1 CN 2020137427 W CN2020137427 W CN 2020137427W WO 2022116283 A1 WO2022116283 A1 WO 2022116283A1
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WIPO (PCT)
Prior art keywords
transistor
data signal
drive
driving
emitting diode
Prior art date
Application number
PCT/CN2020/137427
Other languages
English (en)
French (fr)
Inventor
李艳
Original Assignee
Tcl华星光电技术有限公司
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Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/255,481 priority Critical patent/US11705054B2/en
Publication of WO2022116283A1 publication Critical patent/WO2022116283A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element
    • G09G2300/089—Pixel comprising a non-linear two-terminal element in series with each display pixel element, the series comprising also other elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0633—Adjustment of display parameters for control of overall brightness by amplitude modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the present application belongs to the field of display technology, and in particular relates to a panel driving circuit and a display panel.
  • Mini Light Emitting Diode is a liquid crystal display (Liquid Crystal Display, LCD) backlight technology, through the introduction of packaging, size reduction and mass transfer technology, improve the ability of backlight area control, reduce the optical distance of the backlight, and then achieve ultra-thin, power saving, flexible, high dynamic contrast ( High-Dynamic Range, HDR) backlight technology.
  • the mini LED backlight is arranged in a high-density matrix, which can better achieve finer regional dimming, and has better power consumption performance than traditional backlights.
  • FIG. 1 is a schematic diagram of a circuit structure of a panel driving circuit of a mini LED in the related art.
  • the panel driving circuit of the mini LED includes a scan control transistor T2, a storage capacitor Cs, a driving transistor T1 and a light emitting diode.
  • the gate of the scan control transistor T2 is connected to the scan signal SCAN
  • the source of the scan control transistor T2 is connected to the data signal DATA
  • the drain of the scan control transistor T2 is connected to one end of the storage capacitor and the gate of the drive transistor T1 respectively
  • the drive The drain of the transistor T1 is connected to the cathode of the light emitting diode LED
  • the anode of the light emitting diode LED is connected to the power supply voltage input terminal
  • the other end of the storage capacitor Cs is connected to the ground terminal of the source of the driving transistor T1.
  • the scan function When the scan signal is at a high level, the scan function is enabled, and after that, the data signal jumps to a high level, and the scan control transistor T2 is turned on, so that the drive transistor T1 is turned on, then the light-emitting diode LED has current flowing, and the light-emitting diode LED glow.
  • Embodiments of the present application provide a panel driving circuit and a display panel, which can better increase the number of gray levels, thereby improving image quality.
  • Embodiments of the present application provide a panel drive circuit, including:
  • a driving circuit and a light-emitting diode the driving circuit is connected with the light-emitting diode;
  • the driving circuit includes a plurality of superimposed driving modules, and selects a corresponding number of driving modules according to a preset grayscale;
  • Each of the drive modules includes a scan control transistor, a switch transistor and a drive transistor, the scan control transistor in each of the drive modules is connected to the drive transistor through the switch transistor, and the scan control transistor in each of the drive modules The first ends of the transistors are respectively connected to the scan signal ends, and the light emitting diodes are sequentially connected to the drive transistors in each drive module.
  • the second end of the scan transistor in each of the driving modules is connected to the first end of the switching transistor, and the third end of the scan transistor in each of the driving modules is respectively connected to different data signal ends,
  • the second end of the switching transistor in each of the driving modules is respectively connected to the third end of the corresponding driving transistor, and the third end of the switching transistor in each of the driving modules is connected to the ground terminal;
  • the first end of the drive transistor in each of the drive modules is respectively connected to different chip select signal ends
  • the second end of the drive transistor in the latter drive module is connected with the third end of the drive transistor in the former drive module
  • the second end of the drive transistor in the drive module that is closest to the light-emitting diode is connected to the cathode of the light-emitting diode
  • the anode of the light-emitting diode is connected to the power supply voltage input end
  • the chip input through the chip selection signal end The gate signal gates the corresponding drive transistor to adjust the current through the light emitting diode.
  • the drive circuit further includes a storage capacitor, the second end of the scan control transistor in each of the drive modules is further connected to one end of the storage capacitor, and the other end of the storage capacitor is connected to the ground terminal. .
  • the storage capacitor is used to store the gray-scale voltage input from the data signal terminal.
  • the switching transistor is a MOS transistor.
  • the scan control transistor, the MOS transistor and the driving transistor are thin film transistors.
  • first end is a gate
  • second end is a drain
  • third end is a source
  • the ratio of the channel width to the channel length of each of the MOS transistors is different.
  • the ratio of the channel width to the channel length of each of the MOS transistors is a different integer multiple of the ratio of the channel width to the channel length of the MOS transistor closest to the position of the light emitting diode.
  • the MOS transistor connected to the target data signal terminal is turned on.
  • the target data signal terminal is one or more different data signal terminals.
  • the chip selection signal terminal is relatively independent of the data signal terminal and divides gray scales according to different gray scales.
  • the embodiments of the present application provide a display panel, including the panel driving circuit provided by the embodiments of the present application.
  • the driving circuit includes a plurality of superimposed driving modules, and a corresponding number of driving modules are selected according to a preset gray scale, and each driving module includes a scanning control transistor, a switching transistor and a driving module.
  • Transistors different currents can be combined by turning on different switching transistors and gating one or more driving transistors, so that the current passing through the light-emitting diode can be adjusted, which is convenient to improve the level of brightness, so the embodiment of the present application can be better to increase the number of gray levels, thereby improving the image quality.
  • FIG. 1 is a schematic diagram of a circuit structure of a panel driving circuit of a mini light-emitting diode in the related art.
  • FIG. 2 is a schematic diagram of a circuit structure of a panel driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of voltage waveforms of voltage-type signals in a timing diagram provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • Embodiments of the present application provide a panel drive circuit, including:
  • a driving circuit and a light-emitting diode the driving circuit is connected with the light-emitting diode;
  • the driving circuit includes a plurality of superimposed driving modules, and selects a corresponding number of driving modules according to a preset grayscale;
  • Each of the drive modules includes a scan control transistor, a switch transistor and a drive transistor, the scan control transistor in each of the drive modules is connected to the drive transistor through the switch transistor, and the scan control transistor in each of the drive modules The first ends of the transistors are respectively connected to the scan signal ends, and the light emitting diodes are sequentially connected to the drive transistors in each drive module.
  • the second end of the scan transistor in each of the driving modules is connected to the first end of the switching transistor, and the third end of the scan transistor in each of the driving modules is respectively connected to different data a signal terminal, the second terminal of the switching transistor in each of the driving modules is respectively connected with the third terminal of the corresponding driving transistor, and the third terminal of the switching transistor in each of the driving modules is connected to the ground terminal;
  • the first end of the drive transistor in each of the drive modules is respectively connected to different chip select signal ends
  • the second end of the drive transistor in the latter drive module is connected with the third end of the drive transistor in the former drive module
  • the second end of the drive transistor in the drive module that is closest to the light-emitting diode is connected to the cathode of the light-emitting diode
  • the anode of the light-emitting diode is connected to the power supply voltage input end
  • the chip input through the chip selection signal end The gate signal gates the corresponding drive transistor to adjust the current through the light emitting diode.
  • the drive circuit further includes a storage capacitor, the second end of the scan control transistor in each of the drive modules is further connected to one end of the storage capacitor, and the other end of the storage capacitor is connected to the other end of the storage capacitor. the ground terminal.
  • the storage capacitor is used to store the gray-scale voltage input from the data signal terminal.
  • the switching transistor is a MOS transistor.
  • the scan control transistor, the MOS transistor and the driving transistor are thin film transistors.
  • the first end is a gate
  • the second end is a drain
  • the third end is a source
  • the ratio of the channel width to the channel length of each of the MOS transistors is different.
  • the ratio of the channel width to the channel length of each of the MOS transistors is a different integer multiple of the ratio of the channel width to the channel length of the MOS transistor closest to the position of the light emitting diode.
  • the MOS transistor connected to the target data signal terminal when the data signal input to the target data signal terminal is high level and the data signals input to other data signal terminals are low level, the MOS transistor connected to the target data signal terminal is turned on.
  • the target data signal terminal is one or more different data signal terminals.
  • the chip selection signal terminal is relatively independent of the data signal terminal and divides the gray scales according to different gray scales.
  • the driving circuit is an integrated MOS chip.
  • the plurality of driving modules and storage capacitors are all arranged inside the integrated MOS chip.
  • Embodiments of the present application further provide a display panel, including the above-mentioned panel driving circuit.
  • FIG. 2 is a schematic diagram of a circuit structure of a panel driving circuit provided by an embodiment of the present application.
  • the panel driving circuit includes a driving circuit 100 and a light emitting diode LED, and the driving circuit 100 is connected with the light emitting diode LED.
  • the driving circuit 100 includes a plurality of superimposed driving modules, and the driving circuit 100 selects a corresponding number of driving modules according to a preset gray level. For example, the driving circuit 100 may select one driving module according to a preset gray level. , the driving circuit 100 may select four driving modules according to a preset gray level, for another example, the driving circuit 100 may select six driving modules according to a preset gray level, and so on. When the preset gray scales are different, the number of driving modules corresponding to the gates is also different.
  • the driving circuit 100 includes four driving modules as an example for description, and the four driving modules are a driving module 101 , a driving module 102 , a driving module 103 and a driving module 104 .
  • the number of drive modules can be adjusted accordingly according to specific requirements, for example, the number of drive modules is one, or the number of drive modules is six, or the number of drive modules is ten, etc. For example, there is no limit to the number of drive modules.
  • each drive module includes a scan control transistor, a switch transistor and a drive transistor, the scan control transistor in each drive module is connected to the drive transistor through the switch transistor, and the first scan control transistor in each drive module is The terminals are respectively connected to the scanning signal terminal Scan, and the light emitting diode LED is connected to the driving transistor in each driving module in turn.
  • the drive module 101 includes a scan control transistor T1, a switch transistor M1 and a drive transistor Q1, the scan control transistor T1 is connected to the drive transistor Q1 through the switch transistor M1, and the drive module 102 includes a scan control transistor T2, a switch transistor M2 and a drive transistor Q2,
  • the scan control transistor T2 is connected to the drive transistor Q2 through the switch transistor M2
  • the drive module 103 includes a scan control transistor T3, a switch transistor M3 and a drive transistor Q3, the scan control transistor T3 is connected to the drive transistor Q3 through the switch transistor M3, and the drive module 104 includes a scan control transistor T3.
  • the control transistor T4, the switch transistor M4 and the drive transistor Q4, the scan control transistor T4 is connected to the drive transistor Q4 through the switch transistor M4, and so on.
  • the driving circuit 100 by arranging the driving circuit 100 and the light-emitting diode LED, the driving circuit 100 includes a plurality of superimposed driving modules, and selects a corresponding number of driving modules according to a preset gray scale, and each driving module includes a scan control transistor, a switch, and a switch. Transistor and driving transistor; different currents can be combined by turning on different switching transistors and gating one or more driving transistors, so that the current passing through the light-emitting diode LED can be adjusted, which is convenient to improve the level of brightness, so this application implements For example, the number of gray levels can be better increased, thereby improving the image quality.
  • the second end of the scan transistor in each drive module is connected to the first end of the switch transistor, and the third end of the scan transistor in each drive module is respectively connected to different data signal ends,
  • the second terminals of the switch transistors in each driving module are respectively connected to the third terminals of the corresponding driving transistors, and the third terminals of the switching transistors in each driving module are connected to the ground terminal GND.
  • the first terminal of the driving transistor in each driving module is respectively connected to different chip select signal terminals
  • the second terminal of the driving transistor in the latter driving module is connected to the third terminal of the driving transistor in the previous driving module
  • the light-emitting The second terminal of the driving transistor in the driving module with the diode LED closest to the position is connected to the cathode of the light emitting diode LED, and the anode of the light emitting diode LED is connected to the power supply voltage input terminal VDD.
  • the chip select signal input through the chip select signal terminal selects the corresponding driving transistor to adjust the current passing through the light emitting diode LED.
  • the drive transistor connected to the chip select signal terminal is turned on.
  • the chip select signal input from multiple chip select signal terminals is high level, then The drive transistors connected to these chip select signal terminals are gated.
  • the drive circuit 100 further includes a storage capacitor Cst, the second end of the scan control transistor in each drive module is further connected to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to ground. terminal GND.
  • the storage capacitor Cst can store the gray-scale voltage input from the data signal terminal, and the current through the light-emitting diode LED depends on the gray-scale voltage, that is, the current of the light-emitting diode LED can be adjusted accordingly according to the gray-scale voltage stored in the storage capacitor Cst.
  • To further increase the adjustment level of the current that is, to further improve the brightness level, further increase the number of gray levels, and further improve the image quality.
  • the driving circuit 100 may be an integrated MOS chip, and the integrated MOS chip includes a plurality of superimposed driving modules and storage capacitors Cst.
  • the plurality of driving modules and the storage capacitors Cst are all arranged inside the integrated MOS chip MOS IC.
  • the switching transistor may be a MOS transistor.
  • MOS tube Using MOS tube, its conductivity is controllable.
  • the first terminal may be the gate
  • the second terminal may be the drain
  • the third terminal may be the source.
  • the gate of the scan control transistor in each drive module is respectively connected to the scan signal terminal Scan
  • the source of the scan control transistor in each drive module is respectively connected to different data signal terminals
  • the drain of the MOS transistor in each drive module is respectively It is connected to the source of the corresponding driving transistor
  • the source of the MOS transistor in each driving module is connected to the ground terminal GND.
  • the gates of the drive transistors in each drive module are respectively connected to different chip select signal terminals, the drain of the latter drive transistor is connected to the source of the former drive transistor, and the drain of the drive transistor closest to the position of the light-emitting diode LED It is connected with the cathode of the light-emitting diode LED, and the anode of the light-emitting diode LED is connected with the power supply voltage input terminal VDD.
  • the former and the latter refer to the distance from the position of the light-emitting diode LED. The closer the position of the driving transistor and the light-emitting diode LED is, the more forward, otherwise, the more backward.
  • the gate of the scan control transistor T1, the gate of the scan control transistor T2, the gate of the scan control transistor T3 and the gate of the scan control transistor T4 are all connected to the scan signal terminal.
  • Scan the source of the scan control transistor T1 is connected to the data signal terminal D1
  • the source of the scan control transistor T2 is connected to the data signal terminal D2
  • the source of the scan control transistor T3 is connected to the data signal terminal D3
  • the source of the scan control transistor T4 is connected to the data
  • the drain of the scanning control transistor T1 is respectively connected with one end of the storage capacitor Cst and the gate of the MOS transistor M1
  • the drain of the scanning control transistor T2 is respectively connected with one end of the storage capacitor Cst and the gate of the MOS transistor M2
  • the drain of the scan control transistor T3 is respectively connected to one end of the storage capacitor Cst and the gate of the MOS transistor M3, the drain of the scan control transistor T4 is respectively connected to one end of the storage capacitor Cst
  • the drain of the MOS transistor M1 is connected to the source of the driving transistor Q1, the source of the MOS transistor M1 is connected to the ground terminal GND, the drain of the MOS transistor M2 is connected to the source of the driving transistor Q2, and the source of the MOS transistor M2 is connected to the ground terminal GND, the drain of the MOS transistor M3 is connected to the source of the driving transistor Q3, the source of the MOS transistor M3 is connected to the ground terminal GND, the drain of the MOS transistor M4 is connected to the source of the driving transistor Q4, and the source of the MOS transistor M4 is connected Ground terminal GND.
  • the ground terminal GND provides a DC low voltage.
  • the gate of the driving transistor Q1 is connected to the chip selection signal terminal O1
  • the drain of the driving transistor Q1 is connected to the cathode of the light emitting diode LED
  • the driving transistor Q1 is the driving transistor closest to the position of the light emitting diode LED.
  • the anode of the light emitting diode LED is connected to the power supply voltage input terminal VDD, and the input voltage of the power supply voltage input terminal VDD is a high DC voltage.
  • the gate of the driving transistor Q2 is connected to the chip selection signal terminal O2, the drain of the driving transistor Q2 is connected to the source of the driving transistor Q1, the gate of the driving transistor Q3 is connected to the chip selection signal terminal O3, and the drain of the driving transistor Q3 is connected to the driving transistor.
  • the source of Q2 is connected, the gate of the driving transistor Q4 is connected to the chip selection signal terminal O4, and the drain of the driving transistor Q4 is connected to the source of the driving transistor Q3.
  • FIG. 3 is a schematic diagram of voltage waveforms of voltage-type signals in a timing diagram provided by an embodiment of the present application. From FIG. 3, it can be seen that the scan signal terminal Scan, the data signal terminal D1, the chip select signal terminal O1, the data signal terminal Signal terminal D2, chip selection signal terminal O2, data signal terminal D3, chip selection signal terminal O3, data signal terminal D4, chip selection signal terminal O4, power supply voltage input terminal VDD and ground terminal GND input voltage waveform.
  • the front end sends the required voltage of these voltage signals to the back end according to the image information.
  • the brightness of the light-emitting diode LED depends on the magnitude of the current passing through the light-emitting diode LED.
  • the brightness of the light-emitting diode LED increases, and vice versa, when the current passing through the light-emitting diode LED decreases. If it is small, the brightness of the light-emitting diode LED is weakened.
  • the embodiment of the present application utilizes four MOS transistors, that is, the combination of the MOS transistor M1, the MOS transistor M2, the MOS transistor M3, and the MOS transistor M4 to generate different currents. Specifically, different numbers of MOS transistors are turned on.
  • One or more driving transistors connected to the MOS transistors are selected through the chip selection signal terminal, so as to adjust the current passing through the light emitting diode (LED) to different degrees.
  • the driving transistor Q1 when the driving transistor Q1 is gated, the current passing through the light-emitting diode LED is I, and when the driving transistor Q1 and the driving transistor Q2 are gated, the current passing through the light-emitting diode LED is 3I, etc.
  • the number of gated driving transistors is different, The current passing through the light-emitting diode LED is also different, and correspondingly, the brightness of the light-emitting diode LED is also different, so the brightness of the light-emitting diode LED can be adjusted in detail.
  • Every dot ie, a pixel seen on the screen of the display panel. It is composed of three sub-pixels of red, green and blue (RGB).
  • the different brightness levels displayed by each sub-pixel are grayscales.
  • a 6bit display panel where 6bit means that each sub-pixel can display 2 to the 6th power of different levels of brightness.
  • the clearer the grayscale the more realistic the displayed picture.
  • the 8bit display panel can display 2 to the 8th power of brightness levels, that is, 256 brightness levels, which are called 256 grayscales. It can be seen from this that the more brightness levels, the greater the gray scale.
  • the grayscale value of an image is represented by how many bits of binary numbers, that is, the grayscale resolution, usually in bits, such as 8bit and 12bit.
  • the chip select signal terminal increases the number of gated drive transistors to increase the current through the light-emitting diode LED, and the chip select signal terminal reduces the number of gated drive transistors to reduce the Current through the light-emitting diode LED.
  • the current state is to gate the driving transistor Q1 and the driving transistor Q2, in order to increase the current through the light-emitting diode LED, the driving transistor Q1, the driving transistor Q2 and the driving transistor Q3 are gated, that is, by increasing the number of gated driving transistors , to increase the current through the light-emitting diode LED.
  • either the drive transistor Q1 or the drive transistor Q2 is gated, ie by reducing the number of gated drive transistors to reduce the current through the light emitting diode LED.
  • the storage capacitor Cst can store the gray-scale voltage input from the data signal terminal, for example, the storage capacitor Cst stores the input voltage from the data signal terminal D1, the data signal terminal D2, the data signal terminal D3, and the data signal terminal D4 respectively.
  • Grayscale voltage The current passing through the light-emitting diode LED depends on the gray-scale voltage. For example, when the gray-scale voltage input by the data signal terminal D1 is at a high level, the scan control transistor T1 is turned on, and the MOS transistor M1 is also turned on accordingly. When the data signal D1 is input When the gray-scale voltage is low, the scan control transistor T1 is turned off, and the MOS transistor M1 is also turned off accordingly.
  • the data signal terminal D1, data signal terminal D2, data signal terminal D3, and data signal terminal D4 input
  • the high and low levels of the gray-scale voltage determine the number of MOS transistors that are turned on, and then through the gating of the chip select signal at the chip select signal terminal, different sizes of current can be combined, thus determining the current through the light-emitting diode LED.
  • each of the scan control transistors, the MOS transistors and the drive transistors may be thin film transistors.
  • Such as scan control transistor T1, scan control transistor T2, scan control transistor T3, scan control transistor T4, MOS transistor M1, MOS transistor M2, MOS transistor M3, MOS transistor M4, drive transistor Q1, drive transistor Q2, drive transistor Q3 and drive The transistors Q4 are all thin film transistors.
  • Thin film transistors play an important role in the performance of display panels.
  • different MOS tubes different MOS tubes have different channel width/channel length designs. W is used to represent the channel width, and L is used to represent the channel length, that is, different MOS tubes have different W/L designs. When the W/L ratio is relatively large, the current passing through the light-emitting diode LED is relatively large, and when the W/L ratio is relatively small, the current passing through the light-emitting diode LED is relatively small.
  • the ratio of the channel width to the channel length of each MOS transistor may be different.
  • W1 is used to represent the channel width of the MOS transistor M1
  • L1 is used to represent the channel length of the MOS transistor M1
  • the ratio of the channel width to the channel length of the MOS transistor M1 is W1/L1
  • the channel width, L2 represents the channel length of the MOS transistor M2, then the ratio of the channel width to the channel length of the MOS transistor M2 is W2/L2
  • W3 represents the channel width of the MOS transistor M3, and L3 represents the MOS transistor
  • the channel length of M3, then the ratio of the channel width to the channel length of the MOS transistor M3 is W3/L3
  • W4 represents the channel width of the MOS transistor M4, and L4 represents the channel length of the MOS transistor M4, then the MOS transistor The ratio of the channel width to the channel length of M4 is W4/L4, and so on.
  • the ratio of the channel width to the channel length of the MOS transistor M1 is W1/ L1
  • the ratio of the channel width to the channel length of the MOS transistor M2 is W2/ L2
  • the ratio of the channel width to the channel length of the MOS transistor M3 is W3/
  • the ratios W4/L4 of the channel width to the channel length of the L3 and MOS transistors M4 are different, the corresponding currents passing through the light-emitting diode LED are also different.
  • the ratio W2/L2 of the channel width to the channel length of the MOS transistor M2 is greater than the ratio W1/L1 of the channel width to the channel length of the MOS transistor M1
  • the MOS transistor M1 when the MOS transistor M1 is turned on, the light emitting diode LED
  • the MOS tube M2 when the MOS tube M2 is turned on, the current passing through the light-emitting diode LED is denoted as I2, then I2 is greater than I.
  • the ratio of the channel width to the channel length of the MOS transistor in each driving module may also be set to be equal.
  • different currents can also be combined to improve the brightness level of the light-emitting diode (LED), thereby improving the gray level, which is beneficial to improve the bit number of gray level resolution.
  • the ratio of the channel width to the channel length of each MOS transistor may be a different integer multiple of the ratio of the channel width to the channel length of the MOS transistor closest to the position of the light emitting diode LED .
  • the MOS tube closest to the position of the light-emitting diode LED is the MOS tube M1.
  • the ratio of the channel width to the channel length of the MOS tube M3 W3/ L3 3W/ L
  • the ratio of the channel width to the channel length of the MOS tube M4 W4/ L4 4W/ L, and so on.
  • DH is used to represent a high level
  • DL is used to represent a low level.
  • the scan control transistor T1 is turned on
  • the MOS transistor M1 is turned on
  • the chip select signal input from the chip select signal terminal O1 is DH
  • the driving transistor Q1 is turned on, and the current through the light-emitting diode LED is I.
  • the scan control transistor T1 is turned on, and the MOS transistor M1 is turned on.
  • the scan control transistor T2 is turned on, and the MOS transistor M2 is turned on.
  • the data signal input from the data signal terminal D1 is DH
  • the data signal input from the data signal terminal D2 is DH
  • the data signal input from the data signal terminal D3 is DH
  • the data signal input from the data signal terminal D4 is DH
  • scan the The control transistor T1 is turned on, the MOS tube M1 is turned on, the scan control transistor T2 is turned on, the MOS tube M2 is turned on, the scan control transistor T3 is turned on, the MOS tube M3 is turned on, the scan control transistor T4 is turned on, and the MOS tube M4 is turned on
  • the scan control transistor T2 is turned on, and the MOS transistor M2 is turned on.
  • the current passing through the light emitting diode LED can increase accordingly. That is, when W/L increases, the current passing through the light-emitting diode LED increases accordingly.
  • the current passing through the light-emitting diode LED is I
  • I2 is greater than I.
  • I3 is greater than I
  • I3 is greater than I2.
  • the current passing through the light emitting diode LED can be reduced by turning on other MOS transistors with a smaller ratio of the channel width to the channel length.
  • the MOS transistor M3 in the current state, the MOS transistor M3 is turned on, and the driving transistor Q3 is turned on.
  • the MOS transistor M3 is turned off, so that the driving transistor Q3 is in a non-gated state, and then the MOS transistor is turned on.
  • M1 turns on the driving transistor Q1, or turns on the MOS transistor M2, and turns on the driving transistor Q2, so that the current passing through the light emitting diode LED can be reduced, and so on.
  • the MOS tube M3 is turned on, the driving transistor Q3 is turned on, the MOS tube M4 is turned on, and the driving transistor Q4 is turned on.
  • the MOS tube M4 is turned off to make the driving
  • the transistor Q3 is in a non-gated state, and then the MOS transistor M1 is turned on to turn on the driving transistor Q1, or the MOS transistor M2 is turned on to turn on the driving transistor Q2, so that the current through the light-emitting diode LED can be reduced, and so on.
  • which MOS transistors to be turned on and which driving transistors to be gated can be selected correspondingly according to specific current regulation requirements, and the embodiment of the present application does not limit the selection method.
  • the MOS transistor connected to the target data signal terminal when the data signal input to the target data signal terminal is high level and the data signals input to other data signal terminals are low level, the MOS transistor connected to the target data signal terminal can be turned on.
  • the MOS transistor M1 connected to the data signal terminal D1 when the data signal input from the data signal terminal D1 is at a high level and the data signals input from other data signal terminals are at a low level, the MOS transistor M1 connected to the data signal terminal D1 is turned on.
  • the MOS transistor M2 connected to the data signal terminal D2 is turned on.
  • the MOS transistor M3 connected to the data signal terminal D3 is turned on.
  • the MOS transistor M4 connected to the data signal terminal D4 is turned on.
  • the target data signal terminal may be one or more different data signal terminals.
  • the target data signal terminal is a data signal terminal
  • the target data signal terminal is the data signal terminal D1
  • the MOS transistor M1 is turned on.
  • the target data signal terminal is the data signal terminal D3
  • the MOS transistor M3 is turned on.
  • the target data signal terminals are two data signal terminals
  • the MOS transistor M1 and the MOS transistor M2 are turned on. If the target data signal terminals are the data signal terminal D2 and the data signal terminal D3, the MOS transistor M2 and the MOS transistor M3 are turned on.
  • the target data signal terminals are three data signals, if the target data signal terminals are the data signal terminal D1, the data signal terminal D2 and the data signal terminal D3, the MOS transistor M1, the MOS transistor M2 and the MOS transistor M3 are turned on.
  • the target data signal terminal is four data signals
  • the target data signal is the data signal terminal D1, the data signal terminal D2, the data signal terminal D3 and the data signal terminal D4, then the MOS transistor M1, MOS transistor M2, MOS transistor M3 and The MOS tube M4 is turned on, and so on.
  • the chip select signal terminal may divide the gray scales relatively independently from the data signal terminal according to different gray scales.
  • the chip selection signal terminal O1, the chip selection signal terminal O2, the chip selection signal terminal O3, and the chip selection signal terminal O4 can be based on different gray scales and the data signal terminal D1, data signal terminal D2, data signal terminal D3, and data signal terminal D4. Relatively independent segmentation of grayscale, after segmentation of grayscale, the grayscale is improved, which helps to increase the number of bits of grayscale resolution.
  • FIG. 4 is a schematic structural diagram of the display panel provided by the embodiment of the present application.
  • the display panel 200 includes the panel driving circuit 201 provided by the embodiment of the present application.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

一种面板驱动电路和显示面板，面板驱动电路包括：驱动电路（100）和发光二极管（LED），驱动电路（100）与发光二极管（LED）连接。其中，驱动电路（100）包括多个叠加的驱动模块（101,102,103,104），根据预设灰阶选通对应数量的驱动模块（101,102,103,104）；每个驱动模块（101,102,103,104）包括扫描控制晶体管（T1,T2,T3,T4）、开关晶体管（M1,M2,M3,M4）和驱动晶体管（Q1,Q2,Q3,Q4），每个驱动模块（101,102,103,104）中的扫描控制晶体管（T1,T2,T3,T4）通过开关晶体管（M1,M2,M3,M4）与驱动晶体管（Q1,Q2,Q3,Q4）连接，每个驱动模块（101,102,103,104）中的扫描控制晶体管（T1,T2,T3,T4）的第一端分别连接扫描信号端（Scan），发光二极管（LED）与每个驱动模块（101,102,103,104）中的驱动晶体管（Q1,Q2,Q3,Q4）依次连接。选通对应数量的驱动模块（101,102,103,104），能够组合出多种不同的通过发光二极管（LED）的电流，从而提高灰阶。

Description

面板驱动电路和显示面板 技术领域
本申请属于显示技术领域，尤其涉及一种面板驱动电路和显示面板。
 背景技术
迷你发光二极管（Mini LED OE）属于液晶显示器（Liquid Crystal Display，LCD）背光技术，通过封装、尺寸微缩与巨量转移技术的导入，提高背光源区域控制的能力、减少背光的光学距离，进而实现超薄、省电、可挠、高动态对比(High-Dynamic Range，HDR)的背光技术。迷你发光二极管背光通过高密度矩阵式排列，可以更好实现较为精细的区域调光，并且功耗表现较传统背光更好。
请参阅图1，图1为相关技术中迷你发光二极管的面板驱动电路的电路结构示意图，图1中，该迷你发光二极管的面板驱动电路包括扫描控制晶体管T2、存储电容Cs、驱动晶体管T1和发光二极管LED，扫描控制晶体管T2的栅极连接扫描信号SCAN，扫描控制晶体管T2的源极连接数据信号DATA，扫描控制晶体管T2的漏极分别与存储电容的一端和驱动晶体管T1的栅极连接，驱动晶体管T1的漏极与发光二极管LED的阴极连接，发光二极管LED的阳极连接电源电压输入端，存储电容Cs的另一端和驱动晶体管T1的源极连接接地端。
当扫描信号为高电平时，使能扫描功能，此后，数据信号跳变到高电平，打开扫描控制晶体管T2，从而使驱动晶体管T1导通，则发光二极管LED有电流流过，发光二极管LED发光。
然而，随着市场需求及对发光二极管规格的提升，该方案受限于LED灯的特性等因素，导致显示面板显示亮度不能调节，无法更好的提高灰阶数，从而影响图像的质量。
 技术问题
本申请实施例提供一种面板驱动电路和显示面板，可以更好的提高灰阶数，从而提升图像质量。
 技术解决方案
本申请实施例提供一种面板驱动电路，包括：
驱动电路和发光二极管，所述驱动电路与所述发光二极管连接；其中，
所述驱动电路包括多个叠加的驱动模块，根据预设灰阶选通对应数量的驱动模块；
每个所述驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管，每个所述驱动模块中的扫描控制晶体管通过所述开关晶体管与所述驱动晶体管连接，每个所述驱动模块中的扫描控制晶体管的第一端分别连接扫描信号端，所述发光二极管与所述每个驱动模块中的驱动晶体管依次连接。
进一步地，每个所述驱动模块中的扫描晶体管的第二端与所述开关晶体管的第一端连接，每个所述驱动模块中的扫描晶体管的第三端分别连接不同的数据信号端，每个所述驱动模块中的开关晶体管的第二端分别与对应驱动晶体管的第三端连接，每个所述驱动模块中的开关晶体管的第三端连接接地端；
每个所述驱动模块中的驱动晶体管的第一端分别连接不同的片选信号端，后一个驱动模块中的驱动晶体管的第二端与前一个驱动模块中的驱动晶体管的第三端连接，与所述发光二极管位置最接近的驱动模块中的驱动晶体管的第二端与所述发光二极管的阴极连接，所述发光二极管的阳极连接电源电压输入端，通过所述片选信号端输入的片选信号选通对应的驱动晶体管以调节通过所述发光二极管的电流。
进一步地，所述驱动电路还包括存储电容，每个所述驱动模块中的扫描控制晶体管的第二端还分别与所述存储电容的一端连接，所述存储电容的另一端连接所述接地端。
进一步地，所述存储电容用于存储所述数据信号端输入的灰阶电压。
进一步地，所述开关晶体管为MOS管。
进一步地，所述扫描控制晶体管、MOS管和驱动晶体管为薄膜晶体管。
进一步地，所述第一端为栅极，所述第二端为漏极，所述第三端为源极。
进一步地，每个所述MOS管的沟道宽度与沟道长度的比值不同。
进一步地，每个所述MOS管的沟道宽度与沟道长度的比值为与所述发光二极管的位置最接近的MOS管的沟道宽度与沟道长度的比值的不同整数倍。
进一步地，当目标数据信号端输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与所述目标数据信号端连接的MOS管导通。
进一步地，所述目标数据信号端为一个或多个不同的数据信号端。
进一步地，所述片选信号端根据不同的灰阶与所述数据信号端相对独立的切分灰阶。
本申请实施例提供了一种显示面板，包括本申请实施例提供的所述面板驱动电路。
 有益效果
本申请实施例中，通过设置驱动电路和发光二极管，驱动电路包括多个叠加的驱动模块，根据预设灰阶选通对应数量的驱动模块，每个驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管；通过导通不同的开关晶体管及选通一个或多个驱动晶体管可以组合出不同的电流，从而可以对通过发光二极管的电流进行调节，便于提升亮度的层级，因此本申请实施例可以更好的提高灰阶数，进而提升图像质量。
 附图说明
图1为相关技术中迷你发光二极管的面板驱动电路的电路结构示意图。
图2为本申请实施例提供的面板驱动电路的电路结构示意图。
图3为本申请实施例提供的一个时序图中电压类信号的电压波形示意图。
图4为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种面板驱动电路，包括：
驱动电路和发光二极管，所述驱动电路与所述发光二极管连接；其中，
所述驱动电路包括多个叠加的驱动模块，根据预设灰阶选通对应数量的驱动模块；
每个所述驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管，每个所述驱动模块中的扫描控制晶体管通过所述开关晶体管与所述驱动晶体管连接，每个所述驱动模块中的扫描控制晶体管的第一端分别连接扫描信号端，所述发光二极管与所述每个驱动模块中的驱动晶体管依次连接。
本申请实施例中，每个所述驱动模块中的扫描晶体管的第二端与所述开关晶体管的第一端连接，每个所述驱动模块中的扫描晶体管的第三端分别连接不同的数据信号端，每个所述驱动模块中的开关晶体管的第二端分别与对应驱动晶体管的第三端连接，每个所述驱动模块中的开关晶体管的第三端连接接地端；
每个所述驱动模块中的驱动晶体管的第一端分别连接不同的片选信号端，后一个驱动模块中的驱动晶体管的第二端与前一个驱动模块中的驱动晶体管的第三端连接，与所述发光二极管位置最接近的驱动模块中的驱动晶体管的第二端与所述发光二极管的阴极连接，所述发光二极管的阳极连接电源电压输入端，通过所述片选信号端输入的片选信号选通对应的驱动晶体管以调节通过所述发光二极管的电流。
本申请实施例中，所述驱动电路还包括存储电容，每个所述驱动模块中的扫描控制晶体管的第二端还分别与所述存储电容的一端连接，所述存储电容的另一端连接所述接地端。
本申请实施例中，所述存储电容用于存储所述数据信号端输入的灰阶电压。
本申请实施例中，所述开关晶体管为MOS管。
本申请实施例中，所述扫描控制晶体管、MOS管和驱动晶体管为薄膜晶体管。
本申请实施例中，所述第一端为栅极，所述第二端为漏极，所述第三端为源极。
本申请实施例中，每个所述MOS管的沟道宽度与沟道长度的比值不同。
本申请实施例中，每个所述MOS管的沟道宽度与沟道长度的比值为与所述发光二极管的位置最接近的MOS管的沟道宽度与沟道长度的比值的不同整数倍。
本申请实施例中，当目标数据信号端输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与所述目标数据信号端连接的MOS管导通。
本申请实施例中，所述目标数据信号端为一个或多个不同的数据信号端。
本申请实施例中，所述片选信号端根据不同的灰阶与所述数据信号端相对独立的切分灰阶。
本申请实施例中，所述驱动电路是一种集成化的MOS芯片。
本申请实施例中，所述多个驱动模块和存储电容均设置在所述集成化的MOS芯片的内部。
本申请实施例还提供一种显示面板，包括如上所述的面板驱动电路。
请参阅图2，图2为本申请实施例提供的面板驱动电路的电路结构示意图。该面板驱动电路包括驱动电路100和发光二极管LED，驱动电路100与发光二极管LED连接。
其中，驱动电路100包括多个叠加的驱动模块，该驱动电路100根据预设灰阶选通对应数量的驱动模块，比如，该驱动电路100可以根据预设灰阶选通一个驱动模块，再如，该驱动电路100可以根据预设灰阶选通四个驱动模块，又如，该驱动电路100可以根据预设灰阶选通六个驱动模块，等等。当预设灰阶不同时，对应选通的驱动模块的数量也是不同的。
图1中以驱动电路100包括四个驱动模块为例进行说明，该四个驱动模块为驱动模块101、驱动模块102、驱动模块103和驱动模块104。实际应用中，可以根据具体需求相应调整驱动模块的数量，例如，驱动模块的数量为一个，或者，驱动模块的数量为六个，或者，驱动模块的数量为十个，等等，本申请实施例对驱动模块的数量不做限制。
本申请实施例中，每个驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管，每个驱动模块中的扫描控制晶体管通过开关晶体管与驱动晶体管连接，每个驱动模块中的扫描控制晶体管的第一端分别连接扫描信号端Scan，发光二极管LED与每个驱动模块中的驱动晶体管依次连接。
比如，驱动模块101包括扫描控制晶体管T1、开关晶体管M1和驱动晶体管Q1，扫描控制晶体管T1通过开关晶体管M1与驱动晶体管Q1连接，驱动模块102包括扫描控制晶体管T2、开关晶体管M2和驱动晶体管Q2，扫描控制晶体管T2通过开关晶体管M2与驱动晶体管Q2连接，驱动模块103包括扫描控制晶体管T3、开关晶体管M3和驱动晶体管Q3，扫描控制晶体管T3通过开关晶体管M3与驱动晶体管Q3连接，驱动模块104包括扫描控制晶体管T4、开关晶体管M4和驱动晶体管Q4，扫描控制晶体管T4通过开关晶体管M4与驱动晶体管Q4连接，等等。
本申请实施例中，通过设置驱动电路100和发光二极管LED，驱动电路100包括多个叠加的驱动模块，根据预设灰阶选通对应数量的驱动模块，每个驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管；通过导通不同的开关晶体管及选通一个或多个驱动晶体管可以组合出不同的电流，从而可以对通过发光二极管LED的电流进行调节，便于提升亮度的层级，因此本申请实施例可以更好的提高灰阶数，进而提升图像质量。
比如，在一种实施方式中，每个驱动模块中的扫描晶体管的第二端与开关晶体管的第一端连接，每个驱动模块中的扫描晶体管的第三端分别连接不同的数据信号端，每个驱动模块中的开关晶体管的第二端分别与对应驱动晶体管的第三端连接，每个驱动模块中的开关晶体管的第三端连接接地端GND。
每个驱动模块中的驱动晶体管的第一端分别连接不同的片选信号端，后一个驱动模块中的驱动晶体管的第二端与前一个驱动模块中的驱动晶体管的第三端连接，与发光二极管LED位置最接近的驱动模块中的驱动晶体管的第二端与发光二极管LED的阴极连接，发光二极管LED的阳极连接电源电压输入端VDD。
通过片选信号端输入的片选信号选通对应的驱动晶体管以调节通过发光二极管LED的电流。当有一个片选信号端输入的片选信号为高电平时，则选通与该片选信号端连接的驱动晶体管，当有多个片选信号端输入的片选信号为高电平时，则选通与这些片选信号端连接的驱动晶体管。通过选通不同数量的驱动晶体管，可以组合出的不同电流，从而可以对通过发光二极管LED的电流进行多层次调节，提升亮度的层级，这样可以进一步提高灰阶数，进而进一步提升图像质量。
比如，在一种实施方式中，该驱动电路100还包括存储电容Cst，每个驱动模块中的扫描控制晶体管的第二端还分别与存储电容Cst的一端连接，存储电容Cst的另一端连接接地端GND。存储电容Cst可以存储数据信号端输入的灰阶电压，通过发光二极管LED的电流取决于灰阶电压，即可以根据存储电容Cst中存储的灰阶电压，相应调节发光二极管LED的电流，这样可以更进一步增加电流的调节层次，即更进一步提升亮度层次，更进一步提高灰阶数，更进一步提升图像质量。
比如，在一种实施方式中，驱动电路100可以是一种集成化的MOS芯片，该集成化的MOS芯片中包括多个叠加的驱动模块和存储电容Cst。该多个驱动模块和存储电容Cst均设置在集成MOS芯片MOS IC的内部。通过对驱动电路100进行集成化，可以大大减少零散元器件的数量，将元器件进行集成后，可以减少外界电信号的干扰，电路设计方面也有了很大提升，从而可以提高运行速度，提高性能。
比如，在一种实施方式中，开关晶体管可以为MOS管。采用MOS管，其导电性可控。
比如，在一种实施方式中，第一端可以为栅极，第二端可以为漏极，第三端可以为源极。
例如，每个驱动模块中扫描控制晶体管的栅极分别连接扫描信号端Scan，每个驱动模块中扫描控制晶体管的源极分别连接不同的数据信号端，每个驱动模块中MOS管的漏极分别与对应驱动晶体管的源极连接，每个驱动模块中MOS管的源极连接接地端GND。
每个驱动模块中驱动晶体管的栅极分别连接不同的片选信号端，后一个驱动晶体管的漏极与前一个驱动晶体管的源极连接，与发光二极管LED的位置最接近的驱动晶体管的漏极与发光二极管LED的阴极连接，发光二极管LED的阳极连接电源电压输入端VDD。其中，前一个、后一个指的是距离发光二极管LED的位置的远近，驱动晶体管与发光二极管LED的位置越接近，则越靠前，否则越靠后。
以图1中的四个驱动模块为例，其中，扫描控制晶体管T1的栅极、扫描控制晶体管T2的栅极、扫描控制晶体管T3的栅极和扫描控制晶体管T4的栅极均连接扫描信号端Scan，扫描控制晶体管T1的源极连接数据信号端D1，扫描控制晶体管T2的源极连接数据信号端D2，扫描控制晶体管T3的源极连接数据信号端D3，扫描控制晶体管T4的源极连接数据信号端D4，扫描控制晶体管T1的漏极分别与存储电容Cst的一端和MOS管M1的栅极连接，扫描控制晶体管T2的漏极分别与存储电容Cst的一端和MOS管M2的栅极连接，扫描控制晶体管T3的漏极分别与存储电容Cst的一端和MOS管M3的栅极连接，扫描控制晶体管T4的漏极分别与存储电容Cst的一端和MOS管M4的栅极连接，存储电容Cst的另一端连接接地端GND。
MOS管M1的漏极与驱动晶体管Q1的源极连接，MOS管M1的源极连接接地端GND，MOS管M2的漏极与驱动晶体管Q2的源极连接，MOS管M2的源极连接接地端GND，MOS管M3的漏极与驱动晶体管Q3的源极连接，MOS管M3的源极连接接地端GND，MOS管M4的漏极与驱动晶体管Q4的源极连接，MOS管M4的源极连接接地端GND。其中，接地端GND提供直流低电压。
驱动晶体管Q1的栅极连接片选信号端O1，驱动晶体管Q1的漏极连接发光二极管LED的阴极，驱动晶体管Q1是与发光二极管LED的位置最接近的驱动晶体管。发光二极管LED的阳极连接电源电压输入端VDD，电源电压输入端VDD输入的电压为直流高电压。驱动晶体管Q2的栅极连接片选信号端O2，驱动晶体管Q2的漏极与驱动晶体管Q1的源极连接，驱动晶体管Q3的栅极连接片选信号端O3，驱动晶体管Q3的漏极与驱动晶体管Q2的源极连接，驱动晶体管Q4的栅极连接片选信号端O4，驱动晶体管Q4的漏极与驱动晶体管Q3的源极连接。
需要说明的是，扫描信号端Scan、数据信号端D1、数据信号端D2、数据信号端D3、数据信号端D4、电源电压输入端VDD和接地端GND可以为显示面板提供电压类信号。请参阅图3，图3为本申请实施例提供的一个时序图中电压类信号的电压波形示意图，从图3中可以看出扫描信号端Scan、数据信号端D1、片选信号端O1、数据信号端D2、片选信号端O2、数据信号端D3、片选信号端O3、数据信号端D4、片选信号端O4、电源电压输入端VDD和接地端GND输入的电压波形。一般是前端根据图像信息给后端发送这些电压类信号的需求电压。
可以理解的是，发光二极管LED的亮度取决于通过发光二极管LED的电流的大小，当通过发光二极管LED的电流增大时，则发光二极管LED的亮度增强，反之，当通过发光二极管LED的电流减小时，则发光二极管LED的亮度减弱。
比如，本申请实施例利用四个MOS管，即MOS管M1、MOS管M2、MOS管M3和MOS管M4的组合可以组合出不同的电流，具体是通过导通不同数量的MOS管。比如，导通MOS管M1，导通MOS管M2，MOS管M3，MOS管M4，导通MOS管M1和MOS管M2，导通MOS管M1和MOS管M3，导通MOS管M1和MOS管M4，导通MOS管M2和MOS管M3，导通MOS管M2和MOS管M4，导通MOS管M3和MOS管M4，导通MOS管M1、MOS管M2和MOS管M3，导通MOS管M1、MOS管M2和MOS管M4，导通MOS管M1、MOS管M3和MOS管M4，或者导通MOS管M2、MOS管M3和MOS管M4，这样可以组合出多种不同的电流。
通过片选信号端选通一个或多个与MOS管连接的驱动晶体管，以对通过发光二极管LED的电流进行不同程度的调节。比如，选通驱动晶体管Q1时，通过发光二极管LED的电流为I，选通驱动晶体管Q1和驱动晶体管Q2时，通过发光二极管LED的电流为3I，等等，选通的驱动晶体管的数量不同，通过发光二极管LED的电流也不同，相应的，发光二极管LED的亮度也不同，因此可以细部调整发光二极管LED的亮度。
在显示面板的屏幕上看到的每一个点（即为一个像素）。它是由红、绿、蓝（RGB）三个子像素组成。每一个子像素显现出来的不同亮度级别就是灰阶。要实现画面色彩的变化，就必须对RGB三个子像素分别作出不同的明暗度的控制，以调配处不同的色彩。比如6bit显示面板，其中，6bit表示每个子像素可以显示2的6次方个不同级别的亮度。灰阶越分明，显示的画面也就越逼真。而8bit显示面板能显示2的8次方个亮度层次，即256个亮度层次，称之为256灰阶。由此可知，亮度层次越多，则灰阶越大。
本申请实施例通过导通不同的MOS管，并通过选通相应的驱动晶体管，可以组合出多种不同的通过发光二极管LED的电流，提高发光二极管LED的亮度层次，从而提高灰阶。灰阶越高，显示的色彩越丰富，画面也越细腻，更易表现丰富的细节。
需要说明的是，图像的灰度值以多少位的二进制数来表示，也就是灰阶分辨率，通常以 bit为单位，如 8bit、12bit。灰阶分辨率是衡量图像质量的重要指标。比如，如果图像以8 bit存储一个像素点，即灰阶分辨率是8bit，则表示图像有28=256种颜色，即灰阶级数为256，能表示的灰度值为0~255；如果以12bit存储一个像素点，即灰阶分辨率是12bit，则表示图像由212=4096种颜色，即灰阶级数为4096，能表示的灰度值为0~4095。
图像的灰阶分辨率越高，图像中存储的颜色数量越多，灰阶层次越丰富，包含更多的灰阶信息，图像的质量越好。反之，则图像质量越差，会出现假轮廓（原始图像中没有的轮廓）的现象。因此本申请实施例中，当提高灰阶时，也有利于提供灰阶分辨率的bit数。
需要说明的是，在其它实施例中，可以采用更多的驱动模块，这样可以组合出更多层级的电流。
由此可知，本申请实施例中，通过导通不同驱动模块中的MOS管，并通过片选信号选通一个或多个驱动晶体管可以组合出不同的电流，从而可以对通过发光二极管LED的电流进行不同程度的调节，便于提升亮度的层级，因此本申请实施例可以更进一步提高灰阶数，进而更进一步提升图像质量。
比如，在一种实施方式中，片选信号端通过增加选通的驱动晶体管的数量，以增大通过发光二极管LED的电流，片选信号端通过减少选通的驱动晶体管的数量，以减小通过发光二极管LED的电流。例如，当前状态为选通驱动晶体管Q1和驱动晶体管Q2，为了增大通过发光二极管LED的电流，则选通驱动晶体管Q1、驱动晶体管Q2和驱动晶体管Q3，即通过增加选通的驱动晶体管的数量，以增大通过发光二极管LED的电流。为了减小通过发光二极管LED的电流，则选通驱动晶体管Q1或选通驱动晶体管Q2，即通过减少选通的驱动晶体管的数量，以减小通过发光二极管LED的电流。
比如，在一种实施方式中，存储电容Cst可以存储数据信号端输入的灰阶电压，如存储电容Cst存储数据信号端D1、数据信号端D2、数据信号端D3、数据信号端D4分别输入的灰阶电压。通过发光二极管LED的电流取决于灰阶电压，如，当数据信号端D1输入的灰阶电压为高电平时，则扫描控制晶体管T1导通，MOS管M1也相应导通，当数据信号D1输入的灰阶电压为低电平时，则扫描控制晶体管T1断开，MOS管M1也相应断开，由此可知，数据信号端D1、数据信号端D2、数据信号端D3、数据信号端D4输入的灰阶电压的高低电平决定了MOS管导通的数量，进而通过片选信号端的片选信号的选通，可以组合出不同大小的电流，因此决定了通过发光二极管LED的电流大小。
比如，在一种实施方式中，每个扫描控制晶体管、MOS管和驱动晶体管可以为薄膜晶体管。如扫描控制晶体管T1、扫描控制晶体管T2、扫描控制晶体管T3、扫描控制晶体管T4、MOS管M1、MOS管M2、MOS管M3、MOS管M4、驱动晶体管Q1、驱动晶体管Q2、驱动晶体管Q3和驱动晶体管Q4均为薄膜晶体管。薄膜晶体管对显示面板的工作性能具有重要的作用。对于MOS管，不同MOS管有具有不同的沟道宽度/沟道长度设计，用W表示沟道宽度，用L表示沟道长度，即不同MOS管有不同的W/L设计。当W/L比较大时，则通过发光二极管LED的电流比较大，当W/L比较小时，则通过发光二极管LED的电流比较小。
比如，在一种实施方式中，每个MOS管的沟道宽度与沟道长度的比值可以不同。例如，用W1表示MOS管M1的沟道宽度，用L1表示MOS管M1的沟道长度，则MOS管M1的沟道宽度与沟道长度的比值为W1/ L1；用W2表示MOS管M2的沟道宽度，用L2表示MOS管M2的沟道长度，则MOS管M2的沟道宽度与沟道长度的比值为W2/ L2；用W3表示MOS管M3的沟道宽度，用L3表示MOS管M3的沟道长度，则MOS管M3的沟道宽度与沟道长度的比值为W3/ L3；用W4表示MOS管M4的沟道宽度，用L4表示MOS管M4的沟道长度，则MOS管M4的沟道宽度与沟道长度的比值为W4/ L4，等等。
当MOS管M1的沟道宽度与沟道长度的比值W1/ L1、MOS管M2的沟道宽度与沟道长度的比值W2/ L2、MOS管M3的沟道宽度与沟道长度的比值W3/ L3、MOS管M4的沟道宽度与沟道长度的比值W4/ L4不同时，则分别对应的通过发光二极管LED的电流也是不同的。如，MOS管M2的沟道宽度与沟道长度的比值W2/ L2大于MOS管M1的沟道宽度与沟道长度的比值W1/ L1时，将MOS管M1导通时，通过发光二极管LED的电流记作I，将MOS管M2导通时，通过发光二极管LED的电流记作I2，则I2大于I。
需要说明的是，在其它实施方式中，也可以将每个驱动模块中MOS管的沟道宽度与沟道长度的比值设置为相等。通过导通不同数量的MOS管，以及选通相应的驱动晶体管，也可以组合出不同的电流，提升发光二极管LED的亮度层次，进而提高灰阶，有利于提高灰阶分辨率的bit数。
比如，在一种实施方式中，每个MOS管的沟道宽度与沟道长度的比值可以为与发光二极管LED的位置最接近的MOS管的沟道宽度与沟道长度的比值的不同整数倍。例如，与发光二极管LED的位置最接近的MOS管是MOS管M1，MOS管M1的沟道宽度与沟道长度的比值W1/ L1= W/ L，MOS管M2的沟道宽度与沟道长度的比值W2/ L2= 2W/ L，MOS管M3的沟道宽度与沟道长度的比值W3/ L3= 3W/ L，MOS管M4的沟道宽度与沟道长度的比值W4/ L4= 4W/ L，等等。
比如，本申请实施例中，用DH表示高电平，用DL表示低电平，当数据信号端D1输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，即当数据信号端D1输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T1导通，MOS管M1导通，片选信号端O1输入的片选信号为DH，驱动晶体管Q1导通，通过发光二极管LED的电流为I。
当数据信号端D2输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，即当数据信号端D2输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T2导通，MOS管M2导通，片选信号端O2输入的片选信号为DH，驱动晶体管Q2导通，通过发光二极管LED的电流为I2，I2=2I。
当数据信号端D3输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，即当数据信号端D3输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T3导通，MOS管M3导通，片选信号端O3输入的片选信号为DH，驱动晶体管Q3导通，通过发光二极管LED的电流为I3，I3=3I。
当数据信号端D4输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，即当数据信号端D4输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T4导通，MOS管M4导通，片选信号端O4输入的片选信号为DH，驱动晶体管Q4导通，通过发光二极管LED的电流为I4，I4=4I。
比如，当数据信号端D1输入的数据信号为DH，数据信号端D2输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T1导通，MOS管M1导通，扫描控制晶体管T2导通，MOS管M2导通，相应的，驱动晶体管Q1和驱动晶体管Q2导通，通过发光二极管LED的电流为I+I2=3I。
再比如，当数据信号端D1输入的数据信号为DH，数据信号端D2输入的数据信号为DH，数据信号端D3输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T1导通，MOS管M1导通，扫描控制晶体管T2导通，MOS管M2导通，扫描控制晶体管T3导通，MOS管M3导通，相应的，驱动晶体管Q1、驱动晶体管Q2和驱动晶体管Q3导通，通过发光二极管LED的电流为I+I2+I3=6I。
又比如，当数据信号端D1输入的数据信号为DH，数据信号端D2输入的数据信号为DH，数据信号端D3输入的数据信号为DH，数据信号端D4输入的数据信号为DH时，扫描控制晶体管T1导通，MOS管M1导通，扫描控制晶体管T2导通，MOS管M2导通，扫描控制晶体管T3导通，MOS管M3导通，扫描控制晶体管T4导通，MOS管M4导通，相应的，驱动晶体管Q1、驱动晶体管Q2、驱动晶体管Q3和驱动晶体管Q4导通，通过发光二极管LED的电流为I+I2+I3+I4=10I。
比如，当数据信号端D2输入的数据信号为DH，数据信号端D3输入的数据信号为DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T2导通，MOS管M2导通，扫描控制晶体管T3导通，MOS管M3导通，相应的，驱动晶体管Q2和驱动晶体管Q3导通，通过发光二极管LED的电流为I2+I3=5I。比如，当数据信号端D2输入的数据信号为DH，数据信号端D3输入的数据信号为DH，数据信号端D4为输入的数据信号DH，其它数据信号端输入的数据信号为DL时，扫描控制晶体管T2导通，MOS管M2导通，扫描控制晶体管T3导通，MOS管M3导通，扫描控制晶体管T4导通，MOS管M4导通，相应的，驱动晶体管Q2、驱动晶体管Q3和驱动晶体管Q4导通，通过发光二极管LED的电流为I2+I3+ I4=9I，等等。
由此可知，通过导通不同数量的MOS管以及选通相应的驱动晶体管，可以组合出不同的电流，扩大通过发光二极管LED的电流调节范围，提升发光二极管LED的亮度层次，进而提高灰阶，有利于提高灰阶分辨率的bit数。
比如，在一种实施方式中，MOS管的沟道宽度与沟道长度的比值增大时，通过发光二极管LED的电流可以随之增大。即当W/L增大时，通过发光二极管LED的电流随之增大。如，MOS管M1的沟道宽度与沟道长度的比值W1/L1=W/L时，通过发光二极管LED的电流为I，MOS管M2的沟道宽度与沟道长度的比值W2/L2=2W/L时，通过发光二极管LED的电流为I2=2I，I2大于I。
再如，MOS管M3的沟道宽度与沟道长度的比值W3/L3=3W/L时，通过发光二极管LED的电流为I3=3I，I3大于I，且I3大于I2。由此可知，当MOS管的沟道宽度与沟道长度的比值增大时，通过发光二极管LED的电流也会增大，通过设置不同沟道宽度与沟道长度比值的MOS管，是为了进一步扩大电流的调节范围，从而进一步提升亮度层次，进一步提高灰阶，以进一步提高灰阶分辨率的bit数。
比如，在一种可能的实施方式中，可以通过导通其它沟道宽度与沟道长度的比值小的MOS管，来减小通过发光二极管LED的电流。例如，当前状态下为导通MOS管M3，选通驱动晶体管Q3，为了减小通过发光二极管LED的电流，则断开MOS管M3，使驱动晶体管Q3处于未选通状态，然后导通MOS管M1，选通驱动晶体管Q1，或者导通MOS管M2，选通驱动晶体管Q2，这样就可以减小通过发光二极管LED的电流，等等。
再例如，当前状态下为导通MOS管M3，选通驱动晶体管Q3，导通MOS管M4，选通驱动晶体管Q4，为了减小通过发光二极管LED的电流，则断开MOS管M4，使驱动晶体管Q3处于未选通状态，然后导通MOS管M1，选通驱动晶体管Q1，或者导通MOS管M2，选通驱动晶体管Q2，这样就可以减小通过发光二极管LED的电流，等等。在实际应用中，可以根据具体的电流调节需求，相应选择导通哪些MOS管及选通哪些驱动晶体管，本申请实施例对选择方式不做限制。
比如，在一种实施方式中，当目标数据信号端输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与该目标数据信号端连接的MOS管可以导通。例如，当数据信号端D1输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与该数据信号端D1连接的MOS管M1导通。当数据信号端D2输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与该数据信号端D2连接的MOS管M2导通。
当数据信号端D3输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与该数据信号端D3连接的MOS管M3导通。当数据信号端D4输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与该数据信号端D4连接的MOS管M4导通。当进行电流组合时，可以根据需要选通的驱动晶体管，确定出哪些MOS管是需要导通的，与这些需要导通的MOS管连接的数据信号为高电平时，则这些MOS管就可以导通。不需要导通的MOS管，与其连接的数据信号端输入的数据信号可以为低电平。
比如，在一种实施方式中，目标数据信号端可以为一个或多个不同的数据信号端。例如，当目标数据信号端为一个数据信号端时，若目标数据信号端为数据信号端D1，当该数据信号端D1输入的数据信号为高电平时，则MOS管M1导通。若目标数据信号端为数据信号端D3，当该数据信号端D3输入的数据信号为高电平时，则MOS管M3导通。
当目标数据信号端为两个数据信号端时，若目标数据信号端为数据信号端D1和数据信号端D2，则MOS管M1和MOS管M2导通。若目标数据信号端为数据信号端D2和数据信号端D3，则MOS管M2和MOS管M3导通。
当目标数据信号端为三个数据信号时，若目标数据信号端为数据信号端D1、数据信号端D2和数据信号端D3，则MOS管M1、MOS管M2和MOS管M3导通。
当目标数据信号端为四个数据信号时，若目标数据信号为数据信号端D1、数据信号端D2、数据信号端D3和数据信号端D4，则MOS管M1、MOS管M2、MOS管M3和MOS管M4导通，等等。
比如，在一种实施方式中，片选信号端可以根据不同的灰阶与数据信号端相对独立的切分灰阶。如片选信号端O1、片选信号端O2、片选信号端O3、片选信号端O4可以根据不同的灰阶与数据信号端D1、数据信号端D2、数据信号端D3、数据信号端D4相对独立的切分灰阶，切分灰阶后，灰阶得到提升，这样有助于提高灰阶分辨率的bit数。
本申请实施例还提供一种显示面板，请参阅图4，图4为本申请实施例提供的显示面板的结构示意图。该显示面板200包括本申请实施例提供的面板驱动电路201。
需要说明的是，本申请实施例以上各实施例之间可以相互结合，共同作用以通过组合不同的电流，提升发光二极管LED的亮度层次，从而提高灰阶，进而有助于提高灰阶分辨率的bit数，在此不再一一举例说明。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备（可以是个人计算机，服务器，或者网络设备等）执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器（Read-Only Memory ，ROM）、随机存取存储器（Random Access Memory，RAM）、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (15)

  1. 一种面板驱动电路，其中，包括：
    驱动电路和发光二极管，所述驱动电路与所述发光二极管连接；其中，
    所述驱动电路包括多个叠加的驱动模块，根据预设灰阶选通对应数量的驱动模块；
    每个所述驱动模块包括扫描控制晶体管、开关晶体管和驱动晶体管，每个所述驱动模块中的扫描控制晶体管通过所述开关晶体管与所述驱动晶体管连接，每个所述驱动模块中的扫描控制晶体管的第一端分别连接扫描信号端，所述发光二极管与所述每个驱动模块中的驱动晶体管依次连接。
  2. 根据权利要求1所述的面板驱动电路，其中，每个所述驱动模块中的扫描晶体管的第二端与所述开关晶体管的第一端连接，每个所述驱动模块中的扫描晶体管的第三端分别连接不同的数据信号端，每个所述驱动模块中的开关晶体管的第二端分别与对应驱动晶体管的第三端连接，每个所述驱动模块中的开关晶体管的第三端连接接地端；
    每个所述驱动模块中的驱动晶体管的第一端分别连接不同的片选信号端，后一个驱动模块中的驱动晶体管的第二端与前一个驱动模块中的驱动晶体管的第三端连接，与所述发光二极管位置最接近的驱动模块中的驱动晶体管的第二端与所述发光二极管的阴极连接，所述发光二极管的阳极连接电源电压输入端，通过所述片选信号端输入的片选信号选通对应的驱动晶体管以调节通过所述发光二极管的电流。
  3. 根据权利要求2所述的面板驱动电路，其中，所述驱动电路还包括存储电容，每个所述驱动模块中的扫描控制晶体管的第二端还分别与所述存储电容的一端连接，所述存储电容的另一端连接所述接地端。
  4. 根据权利要求3所述的面板驱动电路，其中，所述存储电容用于存储所述数据信号端输入的灰阶电压。
  5. 根据权利要求2所述的面板驱动电路，其中，所述开关晶体管为MOS管。
  6. 根据权利要求5所述的面板驱动电路，其中，所述扫描控制晶体管、MOS管和驱动晶体管为薄膜晶体管。
  7. 根据权利要求5所述的面板驱动电路，其中，所述第一端为栅极，所述第二端为漏极，所述第三端为源极。
  8. 根据权利要求5所述的面板驱动电路，其中，每个所述MOS管的沟道宽度与沟道长度的比值不同。
  9. 根据权利要求8所述的面板驱动电路，其中，每个所述MOS管的沟道宽度与沟道长度的比值为与所述发光二极管的位置最接近的MOS管的沟道宽度与沟道长度的比值的不同整数倍。
  10. 根据权利要求5所述的面板驱动电路，其中，当目标数据信号端输入的数据信号为高电平，其它数据信号端输入的数据信号为低电平时，与所述目标数据信号端连接的MOS管导通。
  11. 根据权利要求10所述的面板驱动电路，其中，所述目标数据信号端为一个或多个不同的数据信号端。
  12. 根据权利要求10所述的面板驱动电路，其中，所述片选信号端根据不同的灰阶与所述数据信号端相对独立的切分灰阶。
  13. 根据权利要求3所述的面板驱动电路，其中，所述驱动电路是一种集成化的MOS芯片。
  14. 根据权利要求13所述的面板驱动电路，所述多个驱动模块和存储电容均设置在所述集成化的MOS芯片的内部。
  15. 一种显示面板，其中，包括如权利要求1至14中任一项所述的面板驱动电路。
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