WO2022100410A1 - 一种沟槽功率器件与源极电容集成及其制造方法 - Google Patents

一种沟槽功率器件与源极电容集成及其制造方法 Download PDF

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Publication number
WO2022100410A1
WO2022100410A1 PCT/CN2021/125673 CN2021125673W WO2022100410A1 WO 2022100410 A1 WO2022100410 A1 WO 2022100410A1 CN 2021125673 W CN2021125673 W CN 2021125673W WO 2022100410 A1 WO2022100410 A1 WO 2022100410A1
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trench
pattern
contact hole
power device
source
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PCT/CN2021/125673
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English (en)
French (fr)
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赵毅
石亮
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重庆万国半导体科技有限公司
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Priority to EP21890937.2A priority Critical patent/EP4246562A4/en
Publication of WO2022100410A1 publication Critical patent/WO2022100410A1/zh
Priority to US18/316,245 priority patent/US20230282636A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the invention relates to the field of power device semiconductor manufacturing, in particular to a trench power device and source capacitor integration and a manufacturing method thereof.
  • Trench power devices are widely used in the field of power management due to their advantages of low on-resistance and high integration.
  • the source end is usually connected in series with capacitive elements to achieve filtering and rectification purposes.
  • a common practice is to solder capacitors on a printed circuit board and connect them to power devices through printed circuit board wires.
  • the Chinese invention patent with publication number CN102255527B provides a new type of microwave intermodulation current circuit.
  • the microstrip rectifier circuit is printed on a single-layer double-sided printed circuit board, and the bottom surface is a ground plate; the microwave source is input and connected to a DC blocking capacitor.
  • the diode rectifier microstrip circuit part is connected between the DC blocking capacitor and the parallel grounding capacitor I; the output end is branched into two channels: one channel is output to the DC load I through the low-pass filter circuit, and the other channel enters the recovery branch through the band-pass filter circuit
  • the rectifying part of the recovery branch is connected between the band-pass filter circuit and the parallel grounding capacitor II; the recovery branch is output to the DC load II.
  • the intermodulation difference frequency recovery branch is used to solve the problem of low frequency energy loss caused by intermodulation and other factors, effectively solve the drawbacks of the traditional rectifier circuit in the intermodulation effect, and improve the conversion efficiency of radio frequency energy to direct current.
  • the printed circuit board usually sets aside a large area for external capacitors, which increases the cost and is not conducive to the miniaturization and integration of electronic equipment.
  • the purpose of the present invention is to provide a manufacturing method for integrating a trench power device and a source capacitor.
  • a manufacturing method for integrating a trench power device and a source capacitor comprising the following steps:
  • the step A specifically includes the following steps:
  • Step S1 chemical vapor deposition of an epitaxial layer on the upper surface of the silicon substrate; the epitaxial layer is doped with trivalent elements and pentavalent elements;
  • Step S2 depositing a mask on the upper surface of the epitaxial layer, the composition of the mask is silicon dioxide, and the preparation method of the mask includes a low temperature chemical vapor deposition method or a high temperature furnace tube method;
  • Step S3 spin-coating photoresist on the upper surface of the mask, and exposing the photolithography machine to define a trench pattern, and the trench pattern sequentially includes the lower plate trench pattern of the integrated capacitor, the cell gate trench pattern, and the interconnection gate. Pole trench pattern to form a circuit pattern on the mask;
  • the critical dimension of the lower plate trench pattern of the integrated capacitor is larger than the critical dimension of the interconnect gate trench pattern and larger than the critical dimension of the cell gate trench pattern;
  • Step S4 after the circuit pattern is formed on the mask, the circuit pattern is transferred to the silicon substrate by dry etching, and the photoresist and the mask are removed by wet etching;
  • the depth of the bottom plate trench of the integrated capacitor obtained by etching is greater than the depth of the interconnect gate trench and greater than the depth of the cell gate trench;
  • Step S5 growing a sacrificial oxide layer on the sidewall of the trench by a high temperature furnace tube thermal oxidation method
  • Step S6 removing the sacrificial oxide layer by wet etching, and then growing the gate oxide layer by a high temperature furnace tube thermal oxidation method;
  • Step S7 depositing a layer of polysilicon on the surface of the trench and the silicon substrate by a low pressure chemical vapor deposition method, and doping with a pentavalent element or a trivalent element, when the doping element is a pentavalent element, doping is performed during the deposition process , when the doping element is a trivalent element, it is doped by ion implantation after the gate is formed;
  • Step S8 removing the polysilicon above the notch at the upper end of the trench by chemical mechanical polishing or dry etching;
  • Step S9 growing a silicon dioxide-silicon nitride-silicon dioxide composite thin film on the top surface of the gate oxide layer/polysilicon by a high-temperature furnace tube thermal oxidation method;
  • step S10 a layer of intrinsic polysilicon is deposited on the upper surface of the silicon dioxide-silicon nitride-silicon dioxide composite thin film by a low pressure chemical vapor deposition method, and ion implantation is used to dope impurities, and the ion implanted impurities include five. valence element or trivalent element;
  • Step S11 using photolithography to define the ESD diode area circuit diagram pattern and the integrated capacitor upper plate area circuit diagram pattern; the ESD diode area circuit diagram pattern is located above the cell gate trench and the interconnect gate trench, so The circuit diagram pattern of the upper plate area of the integrated capacitor is located above the groove of the lower plate of the integrated capacitor;
  • Step S12 using dry etching to transfer the circuit diagram pattern of the ESD area and the circuit diagram pattern of the upper plate area of the integrated capacitor to the silicon substrate, and remove excess silicon dioxide-silicon nitride-silicon dioxide composite thin film and photoresist;
  • Step S13 forming a transistor body region by ion implantation, and activating doping elements in the tube body region by high-temperature thermal annealing, and the ion implanted impurities include trivalent elements or pentavalent elements;
  • step S14 the source region of the transistor cell, the ESD diode region and the upper plate region of the integrated capacitor are simultaneously defined by photolithography, and the above regions are simultaneously doped with trivalent element or pentavalent element impurities by ion implantation, and then removed.
  • the photoresist is removed and the doping element is activated by high temperature thermal annealing, and finally the cell structure is obtained;
  • the source region of the transistor cell is located on both sides of the gate of the cell, a plurality of the ESD diode regions are arranged at intervals inside the ESD region, and the upper plate region of the integrated capacitor is located in the oxide layer disposed above the groove of the lower plate.
  • the upper surface of the silicon-silicon nitride-silicon dioxide composite film is located on both sides of the gate of the cell, a plurality of the ESD diode regions are arranged at intervals inside the ESD region, and the upper plate region of the integrated capacitor is located in the oxide layer disposed above the groove of the lower plate.
  • the trivalent element includes boron element
  • the pentavalent element includes arsenic and phosphorus.
  • the polarity of the ion implanted element in the step S14 should be opposite to the polarity of the doping element in the step S10 to form a PN junction diode in the ESD region.
  • the thickness of the sacrificial oxide layer in the step S5 is 10-100 nm; the thickness of the gate oxide layer in the step S6 is 10-100 nm; the thickness of the polysilicon in the step S7 is 500 nm ⁇ 1000 nm; the thickness of the silicon dioxide-silicon nitride-silicon dioxide composite thin film in the step S9 is 100-2000 nm.
  • the step B specifically includes the following steps:
  • Step S15 forming a silicon dioxide interlayer dielectric layer by chemical vapor deposition method, and the interlayer dielectric layer can be doped with boron and phosphorus impurities to improve the fluidity of the film and the adsorption of foreign impurities;
  • Step S16 define the source trench contact hole pattern, the interconnect gate contact hole pattern, the contact hole pattern at both ends of the ESD diode, and the contact hole pattern of the lower plate of the integrated capacitor on the upper surface of the silicon dioxide interlayer dielectric layer by the photolithography method. Hole pattern and upper plate contact hole pattern;
  • the two source trench contact hole pattern segments are located above the source regions of the two transistor cells, the interconnected gate contact hole pattern is located above the interconnected gate trenches, and both ends of the two ESD diodes are in contact with each other.
  • the hole patterns are respectively located above both ends of the ESD diode region, the contact hole pattern of the lower plate of the integrated capacitor is located above the side of the lower plate trench of the integrated capacitor close to the cell gate trench, and the upper plate contact hole
  • the graphic is above the upper plate area of the integrated capacitor;
  • Step S17 dry etching the silicon dioxide interlayer dielectric layer to connect the source trench contact hole, the interconnect gate contact hole, the contact holes at both ends of the ESD diode, the lower plate contact hole and the upper plate contact hole of the integrated capacitor.
  • the pattern is transferred to the silicon substrate;
  • Step S18 using ion implantation to dope high-concentration impurity elements to the bottom of the contact holes, and rapid thermal annealing to activate the impurities to make ohmic contacts of all the contact holes;
  • Step S19 depositing titanium metal at the bottom of the source trench contact hole, the interconnect gate contact hole, the contact holes at both ends of the ESD diode, the lower plate contact hole and the upper plate contact hole of the integrated capacitor by a physical chemical vapor deposition method , and use titanium nitride as the bonding layer to form silicide through rapid thermal degradation, and deposit metal tungsten, remove metal tungsten outside the contact hole by dry etching, and form a tungsten plug in the contact hole.
  • the polarity of the impurity element implanted in this ion implantation in the step S18 should be the same as the polarity of the element implanted into the transistor body region in the thirteenth step.
  • the step C specifically includes the following steps: step S20, depositing metal aluminum copper on the tungsten plug by magnetron sputtering, and then using photolithography and dry etching to form circuit links;
  • the tungsten plugs in the side of the interconnected gate contact hole and the contact holes at both ends of the ESD diode far away from the source trench contact holes are connected by metal aluminum copper, and the source trench contact holes and the contact holes at both ends of the ESD diode are close to each other.
  • One side of the trench contact hole in the source region and the tungsten plug in the contact hole of the lower plate of the integrated capacitor are connected by metal aluminum copper.
  • the capacitor is connected to the trench power device.
  • the step D specifically includes the following steps: step S21, depositing a passivation layer, the passivation layer comprising silicon nitride or silicon dioxide; etching the pad area through a photolithography method and a dry etching method , the subsequent packaging can be performed by wire bonding on the pad, and the entire process is completed. In particular, if no integrated capacitor is required, wire bonding packaging can still be performed through the source pad.
  • a trench power device and source capacitor are integrated, and the trench power device and source capacitor are integrated, and the trench power device and source capacitor are integrated according to the manufacturing method of the trench power device and source capacitor integration.
  • the present invention has the following beneficial effects:
  • Trench power devices with integrated capacitors can reduce the use of external capacitors, thereby reducing the use area of printed circuit boards, and achieving the purpose of reducing costs and miniaturizing equipment.
  • step S6 is a schematic process flow diagram of step S6 of a trench power device and a source capacitor integration and a manufacturing method thereof according to Embodiments 1-3 of the present invention
  • step S9 of a trench power device and a source capacitor integration and a manufacturing method thereof according to Embodiments 1-3 of the present invention is a schematic process flow diagram of step S9 of a trench power device and a source capacitor integration and a manufacturing method thereof according to Embodiments 1-3 of the present invention.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • Step S1 the epitaxial layer 2 is grown on the silicon substrate 1 by chemical vapor deposition.
  • a trivalent element boron
  • a trivalent element can be selected to be doped to prepare a P-type device or a pentavalent element (arsenic, phosphorus) to prepare an N-type device.
  • a trivalent element boron
  • the thickness of the epitaxial layer 2 can vary in the order of microns according to different operating voltages.
  • Step S2 as shown in FIG. 2 , a silicon dioxide film is deposited on the silicon substrate as a mask 3 required for trench etching.
  • the mask 3 is prepared by a low temperature chemical vapor deposition method or a high temperature furnace tube method. In this embodiment, it is prepared by a low temperature chemical vapor deposition method.
  • Step S3 spin-coating the photoresist on the mask, and define the groove pattern on the mask on the photoresist by exposure by a photolithography machine.
  • this method needs to define three kinds of trenches at the same time, one is the cell gate trench 4, which has the smallest critical dimension and is used to form the gate of the cell transistor; the other is the interconnect gate trench 5, which is The size is slightly larger, which is used to realize the gate interconnection of the cell transistor; the third is the lower plate groove 6 of the integrated capacitor, which has the largest size and is used to form the lower plate of the integrated capacitor.
  • Step S4 as shown in FIG. 4, after the circuit pattern is formed on the mask, the circuit pattern is transferred to the silicon substrate by dry etching, and the photoresist and the mask 3 are removed by wet etching. Due to the characteristics of dry etching, the interconnect gate trenches 5 with larger critical dimensions and the lower plate trenches 6 of the integrated capacitor are etched deeper, and the cell gate trenches 4 are etched shallowly.
  • Step S5 as shown in FIG. 5 , a sacrificial oxide layer 7 is grown on the trench sidewall by using a high temperature furnace tube thermal oxidation method with a thickness of 10 nanometers for repairing and rounding the silicon lattice damage of the trench sidewall.
  • Step S6 as shown in FIG. 6 , the sacrificial oxide layer 7 is removed by wet etching, and then the gate oxide layer 8 is grown by using a high temperature furnace tube thermal oxidation method. Depending on the application, the gate oxide thickness is 10 nm.
  • Step S7 as shown in FIG. 7 , a low-pressure chemical vapor deposition method is used to deposit a layer of polysilicon 9 on the surface of the trench and the silicon substrate, the thickness of which is 500 nanometers.
  • pentavalent elements are doped during deposition or trivalent elements are doped by ion implantation after gate formation.
  • Step S8 as shown in FIG. 8 , chemical mechanical polishing or dry etching is used to remove polysilicon outside the trenches.
  • Step S9 as shown in FIG. 9 , a silicon dioxide-silicon nitride-silicon dioxide composite film 10 is grown on the surface of the silicon substrate by using a high-temperature furnace tube thermal oxidation method, which is used as an insulation isolation for electrostatic protection diodes (ESD). layer, which is also the dielectric layer of the integrated capacitor.
  • ESD electrostatic protection diodes
  • the thicknesses of silicon dioxide and silicon nitride are tunable in the range of 100 nanometers.
  • Step S10 a low pressure chemical vapor deposition method is used to deposit a layer of intrinsic polysilicon 11 on the surface of the silicon dioxide-silicon nitride-silicon dioxide composite thin film 10 , and ion implantation is used for doping.
  • the impurity of ion implantation is a pentavalent element (arsenic).
  • Step S11 as shown in FIG. 11 , the ESD region pattern 12 and the integrated capacitor upper plate region pattern 13 are defined by using a photolithography method.
  • Step S12 as shown in FIG. 12, the ESD area pattern 12 and the integrated capacitor upper plate area pattern 13 circuit pattern are transferred to the silicon substrate by dry etching, and then the unnecessary silicon dioxide-nitride is removed together Silicon-silicon dioxide composite film 11 and photoresist.
  • Step S13 as shown in FIG. 13 , the transistor body region 14 is formed by ion implantation, and then the doping elements in the body region are activated by high temperature thermal annealing.
  • the impurity implanted by ion is a trivalent element (boron).
  • step S14 the source region 15 of the transistor cell, the ESD diode region 16 and the upper plate region 17 of the integrated capacitor are simultaneously defined by the photolithography method, and the above 15, 16, 17 are simultaneously treated by the ion implantation method.
  • the regions are doped, followed by removal of the photoresist and activation of the dopant element by high temperature thermal annealing.
  • the polarity of the elements in this ion implantation is opposite to the polarity of the doping elements in step 10, so as to form a PN junction diode in the ESD region and obtain the cell structure as shown in Figure 15.
  • the subsequent methods are mainly for the purpose of making device isolation Interconnect with metal.
  • Step S15 as shown in FIG. 16 , a silicon dioxide interlayer dielectric layer 18 is formed by chemical vapor deposition.
  • the interlayer dielectric layer can be doped with boron and phosphorus impurities to improve the fluidity of the film and the adsorption of foreign impurities
  • Step S16 as shown in FIG. 17, the source trench contact hole 19, the interconnection gate contact hole 20, the contact holes 21 at both ends of the ESD diode, the lower plate contact hole 22 and the upper plate contact hole 22 of the integrated capacitor are simultaneously defined by the photolithography method. Plate contact hole 23 .
  • Step S17 as shown in FIG. 18 , the interlayer dielectric layer of silicon dioxide is dry-etched, and all the patterns of the contact holes 19-23 are transferred to the silicon substrate.
  • Step S18 ion implantation is used to dope high-concentration impurities to the bottom of the contact holes, and rapid thermal annealing activates the impurities to form ohmic contacts 24 of all the contact holes.
  • the polarity of the elements implanted this time is the same as the polarity of the elements implanted into the body region of the transistor in step S13.
  • step S19 metal titanium and titanium nitride are deposited as the bonding layer 25 by means of physical chemical vapor deposition, and silicide is formed by rapid thermal degradation. Then, metal tungsten is deposited on the silicon substrate, and the metal tungsten outside the contact hole is removed by dry etching, and finally a tungsten plug is formed in the contact hole.
  • Step S20 depositing metal aluminum copper 26 by magnetron sputtering, and then using photolithography and dry etching to form circuit links to ensure that ESD and integrated capacitors are connected to the trench power device.
  • Step S21 deposit a passivation layer (silicon nitride or silicon dioxide), and use photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • a passivation layer silicon nitride or silicon dioxide
  • Photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • Packaging so far the entire process is completed. In particular, if no integrated capacitor is required, wire bonding packaging can still be performed through the source pad.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • Step S1 the epitaxial layer 2 is grown on the silicon substrate 1 by chemical vapor deposition.
  • a trivalent element boron
  • a pentavalent element arsenic, phosphorus
  • a pentavalent element is selected to prepare the N-type device. type device.
  • the thickness of the epitaxial layer 2 can vary in the order of microns according to different operating voltages.
  • Step S2 as shown in FIG. 2 , a silicon dioxide film is deposited on the silicon substrate as a mask 3 required for trench etching.
  • the mask 3 is prepared by a low temperature chemical vapor deposition or a high temperature furnace tube method. In this embodiment, the high temperature furnace tube method is used.
  • Step S3 spin-coating the photoresist on the mask, and define the groove pattern on the mask on the photoresist by exposure by a photolithography machine.
  • this method needs to define three kinds of trenches at the same time, one is the cell gate trench 4, which has the smallest critical dimension and is used to form the gate of the cell transistor; the other is the interconnect gate trench 5, which is The size is slightly larger, which is used to realize the gate interconnection of the cell transistor; the third is the lower plate groove 6 of the integrated capacitor, which has the largest size and is used to form the lower plate of the integrated capacitor.
  • Step S4 as shown in FIG. 4, after the circuit pattern is formed on the mask, the circuit pattern is transferred to the silicon substrate by dry etching, and the photoresist and the mask 3 are removed by wet etching. Due to the characteristics of dry etching, the interconnect gate trenches 5 with larger critical dimensions and the lower plate trenches 6 of the integrated capacitor are etched deeper, and the cell gate trenches 4 are etched shallowly.
  • Step S5 as shown in FIG. 5 , a sacrificial oxide layer 7 is grown on the trench sidewall with a thickness of 50 nanometers by using a high temperature furnace tube thermal oxidation method for repairing and rounding the silicon lattice damage of the trench sidewall.
  • Step S6 as shown in FIG. 6 , the sacrificial oxide layer 7 is removed by wet etching, and then the gate oxide layer 8 is grown by using a high temperature furnace tube thermal oxidation method.
  • the gate oxide thickness can be 50 nm.
  • Step S7 as shown in FIG. 7 , a low-pressure chemical vapor deposition method is used to deposit a layer of polysilicon 9 on the surface of the trench and the silicon substrate, the thickness of which is 800 nanometers.
  • pentavalent elements are doped during deposition or trivalent elements are doped by ion implantation after gate formation.
  • Step S8 as shown in FIG. 8 , chemical mechanical polishing or dry etching is used to remove polysilicon outside the trenches.
  • Step S9 as shown in FIG. 9 , a silicon dioxide-silicon nitride-silicon dioxide composite film 10 is grown on the surface of the silicon substrate by using a high-temperature furnace tube thermal oxidation method, which is used as an insulation isolation for electrostatic protection diodes (ESD). layer, which is also the dielectric layer of the integrated capacitor.
  • ESD electrostatic protection diodes
  • the thickness of silicon dioxide and silicon nitride is 1000 nanometers.
  • Step S10 a low pressure chemical vapor deposition method is used to deposit a layer of intrinsic polysilicon 11 on the surface of the silicon dioxide-silicon nitride-silicon dioxide composite thin film 10 , and ion implantation is used for doping.
  • the impurity implanted by ion is a trivalent element (boron).
  • Step S11 as shown in FIG. 11 , the ESD region pattern 12 and the integrated capacitor upper plate region pattern 13 are defined by using a photolithography method.
  • Step S12 as shown in FIG. 12, the ESD area pattern 12 and the integrated capacitor upper plate area pattern 13 circuit pattern are transferred to the silicon substrate by dry etching, and then the unnecessary silicon dioxide-nitride is removed together Silicon-silicon dioxide composite film 11 and photoresist.
  • Step S13 as shown in FIG. 13 , the transistor body region 14 is formed by ion implantation, and then the doping elements in the body region are activated by high temperature thermal annealing.
  • the impurity of ion implantation is a pentavalent element (phosphorus).
  • step S14 the source region 15 of the transistor cell, the ESD diode region 16 and the upper plate region 17 of the integrated capacitor are simultaneously defined by the photolithography method, and the above 15, 16, 17 are simultaneously treated by the ion implantation method.
  • the regions are doped, followed by removal of the photoresist and activation of the dopant element by high temperature thermal annealing.
  • the polarity of the elements in this ion implantation is opposite to the polarity of the doping elements in step 10, so as to form a PN junction diode in the ESD region and obtain the cell structure as shown in Figure 15.
  • the subsequent methods are mainly for the purpose of making device isolation Interconnect with metal.
  • Step S15 as shown in FIG. 16 , a silicon dioxide interlayer dielectric layer 18 is formed by chemical vapor deposition.
  • the interlayer dielectric layer can be doped with boron and phosphorus impurities to improve the fluidity of the film and the adsorption of foreign impurities
  • Step S16 as shown in FIG. 17, the source trench contact hole 19, the interconnection gate contact hole 20, the contact holes 21 at both ends of the ESD diode, the lower plate contact hole 22 and the upper plate contact hole 22 of the integrated capacitor are simultaneously defined by the photolithography method. Plate contact hole 23 .
  • Step S17 as shown in FIG. 18 , the interlayer dielectric layer of silicon dioxide is dry-etched, and all the patterns of the contact holes 19-23 are transferred to the silicon substrate.
  • Step S18 ion implantation is used to dope high-concentration impurities to the bottom of the contact holes, and rapid thermal annealing activates the impurities to form ohmic contacts 24 of all the contact holes.
  • the polarity of the elements implanted this time is the same as the polarity of the elements implanted into the body region of the transistor in step S13.
  • step S19 metal titanium and titanium nitride are deposited as the bonding layer 25 by means of physical chemical vapor deposition, and silicide is formed by rapid thermal degradation. Then, metal tungsten is deposited on the silicon substrate, and the metal tungsten outside the contact hole is removed by dry etching, and finally a tungsten plug is formed in the contact hole.
  • Step S20 depositing metal aluminum copper 26 by magnetron sputtering, and then using photolithography and dry etching to form circuit links to ensure that ESD and integrated capacitors are connected to the trench power device.
  • Step S21 deposit a passivation layer (silicon nitride or silicon dioxide), and use photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • a passivation layer silicon nitride or silicon dioxide
  • Photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • Packaging so far the entire process is completed. In particular, if no integrated capacitor is required, wire bonding packaging can still be performed through the source pad.
  • a trench power device is integrated with a source capacitor and a manufacturing method thereof, comprising the following steps:
  • Step S1 the epitaxial layer 2 is grown on the silicon substrate 1 by chemical vapor deposition.
  • a trivalent element boron
  • a pentavalent element arsenic, phosphorus
  • a pentavalent element phosphorus
  • the thickness of the epitaxial layer 2 can vary in the order of microns according to different operating voltages.
  • Step S2 as shown in FIG. 2 , a silicon dioxide film is deposited on the silicon substrate as a mask 3 required for trench etching.
  • the mask 3 is prepared by a low temperature chemical vapor deposition method or a high temperature furnace tube method, and is prepared by a low temperature chemical vapor deposition method in this embodiment.
  • Step S3 spin-coating the photoresist on the mask, and define the groove pattern on the mask on the photoresist by exposure by a photolithography machine.
  • this method needs to define three kinds of trenches at the same time, one is the cell gate trench 4, which has the smallest critical dimension and is used to form the gate of the cell transistor; the other is the interconnect gate trench 5, which is The size is slightly larger, which is used to realize the gate interconnection of the cell transistor; the third is the lower plate groove 6 of the integrated capacitor, which has the largest size and is used to form the lower plate of the integrated capacitor.
  • Step S4 as shown in FIG. 4, after the circuit pattern is formed on the mask, the circuit pattern is transferred to the silicon substrate by dry etching, and the photoresist and the mask 3 are removed by wet etching. Due to the characteristics of dry etching, the interconnect gate trenches 5 with larger critical dimensions and the lower plate trenches 6 of the integrated capacitor are etched deeper, and the cell gate trenches 4 are etched shallowly.
  • Step S5 as shown in FIG. 5 , a sacrificial oxide layer 7 is grown on the trench sidewall with a thickness of about 100 nanometers by using a high temperature furnace tube thermal oxidation method for repairing and rounding the silicon lattice damage of the trench sidewall.
  • Step S6 as shown in FIG. 6 , the sacrificial oxide layer 7 is removed by wet etching, and then the gate oxide layer 8 is grown by using a high temperature furnace tube thermal oxidation method. Depending on the application, the gate oxide thickness is 100 nm.
  • Step S7 as shown in FIG. 7 , a low-pressure chemical vapor deposition method is used to deposit a layer of polysilicon 9 on the surface of the trench and the silicon substrate, the thickness of which is 1000 nanometers.
  • pentavalent elements are doped during deposition or trivalent elements are doped by ion implantation after gate formation.
  • Step S8 as shown in FIG. 8 , chemical mechanical polishing or dry etching is used to remove polysilicon outside the trenches.
  • Step S9 as shown in FIG. 9 , a silicon dioxide-silicon nitride-silicon dioxide composite film 10 is grown on the surface of the silicon substrate by using a high-temperature furnace tube thermal oxidation method, which is used as an insulation isolation for electrostatic protection diodes (ESD). layer, which is also the dielectric layer of the integrated capacitor.
  • ESD electrostatic protection diodes
  • the thickness of silicon dioxide and silicon nitride is 2000 nanometers.
  • Step S10 a low pressure chemical vapor deposition method is used to deposit a layer of intrinsic polysilicon 11 on the surface of the silicon dioxide-silicon nitride-silicon dioxide composite thin film 10 , and ion implantation is used for doping.
  • the impurity for ion implantation is a pentavalent element (phosphorus).
  • Step S11 as shown in FIG. 11 , the ESD region pattern 12 and the integrated capacitor upper plate region pattern 13 are defined by using a photolithography method.
  • Step S12 as shown in FIG. 12, the ESD area pattern 12 and the integrated capacitor upper plate area pattern 13 circuit pattern are transferred to the silicon substrate by dry etching, and then the unnecessary silicon dioxide-nitride is removed together Silicon-silicon dioxide composite film 11 and photoresist.
  • Step S13 as shown in FIG. 13 , the transistor body region 14 is formed by ion implantation, and then the doping elements in the body region are activated by high temperature thermal annealing.
  • the impurity for ion implantation is a trivalent element (boron).
  • step S14 the source region 15 of the transistor cell, the ESD diode region 16 and the upper plate region 17 of the integrated capacitor are simultaneously defined by the photolithography method, and the above 15, 16, 17 are simultaneously treated by the ion implantation method.
  • the region is doped, followed by removal of the photoresist and activation of the dopant element by high temperature thermal annealing.
  • the polarity of the elements of this ion implantation is opposite to the polarity of the doping elements in step 10, so as to form a PN junction diode in the ESD region to obtain the cell structure as shown in Figure 15.
  • the subsequent method is mainly for the purpose of making device isolation Interconnect with metal.
  • Step S15 as shown in FIG. 16 , a silicon dioxide interlayer dielectric layer 18 is formed by chemical vapor deposition.
  • the interlayer dielectric layer can be doped with boron and phosphorus impurities to improve the fluidity of the film and the adsorption of foreign impurities
  • Step S16 as shown in FIG. 17, the source trench contact hole 19, the interconnection gate contact hole 20, the contact holes 21 at both ends of the ESD diode, the lower plate contact hole 22 and the upper plate contact hole 22 of the integrated capacitor are simultaneously defined by the photolithography method. Plate contact hole 23 .
  • step S17 as shown in FIG. 18, the interlayer dielectric layer of silicon dioxide is dry-etched, and all the patterns of the contact holes 19-23 are transferred to the silicon substrate.
  • Step S18 ion implantation is used to dope high-concentration impurities to the bottom of the contact holes, and rapid thermal annealing activates the impurities to form ohmic contacts 24 of all the contact holes.
  • the polarity of the elements implanted this time is the same as the polarity of the elements implanted into the body region of the transistor in step S13.
  • step S19 metal titanium and titanium nitride are deposited as the bonding layer 25 by means of physical chemical vapor deposition, and silicide is formed by rapid thermal degradation. Then, metal tungsten is deposited on the silicon substrate, and the metal tungsten outside the contact hole is removed by dry etching, and finally a tungsten plug is formed in the contact hole.
  • Step S20 depositing metal aluminum copper 26 by magnetron sputtering, and then using photolithography and dry etching to form circuit links to ensure that ESD and integrated capacitors are connected to the trench power device.
  • Step S21 deposit a passivation layer (silicon nitride or silicon dioxide), and use photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • a passivation layer silicon nitride or silicon dioxide
  • Photolithography and dry etching to etch the pad area, and the subsequent steps can be performed by wiring on the pad.
  • Packaging so far the entire process is completed. In particular, if no integrated capacitor is required, wire bonding packaging can still be performed through the source pad.

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Abstract

本发明公开了一种沟槽功率器件与源极电容集成及其制造方法，涉及功率器件半导体制造领域，包括如下步骤：A、元胞结构的制备；B、沟槽功率器件的制备；所述沟槽功率器件包括接触孔、钨栓；C、ESD、集成电路接入沟槽功率器件；D、淀积钝化层，蚀刻焊盘区域，打线封装。本发明在沟槽功率器件制造的同时集成源极电容的制造。由于没有增加掩模版，成本可控。集成电容的沟槽功率器件可以减少外接电容的使用，从而减小印刷电路板的使用面积，达到降低成本和设备小型化的目的。

Description

一种沟槽功率器件与源极电容集成及其制造方法 技术领域
本发明涉及功率器件半导体制造领域，尤其涉及一种沟槽功率器件与源极电容集成及其制造方法。
背景技术
沟槽功率器件因具有低导通电阻，高集成度等优点，而被广泛应用于电源管理领域。在具体应用电路设计时，其源端通常会串联电容元件以实现滤波整流等目的。通常的做法是在印刷电路板上焊接电容，通过印刷电路板导线与功率器件相连。
公开号为CN102255527B的中国发明专利提供了一种新型的微波互调整流电路，将微带整流电路印刷在单层双面印刷电路板上，底面均为接地板；微波源输入并与隔直电容相连；二极管整流微带电路部分连接在隔直电容与并联接地电容I之间；输出端分支两路：一路经低通滤波电路输出至直流负载I，另一路经带通滤波电路进入回收支路；回收支路整流部分连接在带通滤波电路和并联接地电容II之间；回收支路输出至直流负载II。利用互调差频回收支路解决因互调等因素引起的低频能量损失的问题，有效地解决传统整流电路在互调效应上的弊端，提高射频能量到直流电的转换效率。
但是印刷电路板通常会留出较大面积用于外接电容，增加了成本也不利于电子设备小型化和集成化。
发明内容
为解决现有技术中的缺陷，本发明的目的在于提供一种沟槽功率器件与源极电容集成的制造方法。
本发明的目的是通过以下技术方案实现的：一种沟槽功率器件与源极电容集成的制造方法，包括如下步骤：
A、元胞结构的制备；
B、接触孔、钨栓的制备；
C、ESD、集成电路接入沟槽功率器件；
D、淀积钝化层，蚀刻焊盘区域，打线封装。
优选地，所述步骤A具体包括如下步骤：
步骤S1、在硅衬底上表面化学气相沉积外延层；所述外延层掺杂三价元素、五价元素；
步骤S2、在外延层上表面沉积掩膜，所述掩膜的成分为二氧化硅，所述掩膜的制备方法包括低温化学气相沉积法或高温炉管法；
步骤S3、在掩膜上表面旋涂光刻胶，光刻机曝光定义沟槽图形，所述沟槽图形依次包括集成电容的下极板沟槽图形、元胞栅极沟槽图形、互联栅极沟槽图形，在掩膜上形成电路图形；
所述集成电容的下极板沟槽图形的关键尺寸大于互联栅极沟槽图形的关键尺寸大于元胞栅极沟槽图形的关键尺寸；
步骤S4、在掩膜上形成电路图形后，利用干法蚀刻将电路图形转移到硅衬底上，并通过湿法刻蚀，去除光刻胶和掩膜；
蚀刻得到的集成电容的下极板沟槽的深度大于互联栅极沟槽的深度大于元胞栅极沟槽的深度；
步骤S5、通过高温炉管热氧化法在沟槽侧壁生长一层牺牲氧化层；
步骤S6、通过湿法刻蚀法去除牺牲氧化层，然后通过高温炉管热氧化法生长栅极氧化层；
步骤S7、通过低压化学气相沉积方法在沟槽和硅衬底表面沉积一层多晶硅，并掺杂五价元素或三价元素，当掺杂元素为五价元素时，在沉积过程中进行掺杂，当掺杂元素为三价元素时，在栅极形成后通过离子注入进行掺杂；
步骤S8、通过化学机械研磨或干法蚀刻去除沟槽上端槽口上方多晶硅；
步骤S9、通过高温炉管热氧化法在栅极氧化层/多晶硅上表面生长二氧化硅-氮化硅-二氧化硅复合型薄膜；
步骤S10、通过低压化学气相沉积法在二氧化硅-氮化硅-二氧化硅复合型薄膜上表面沉积一层本征多晶硅，并利用离子注入进行掺杂杂质，所述离子注入的杂质包括五价元素或三价元素；
步骤S11、利用光刻法定义出ESD二极管区域电路图图案和集成电容上极板区域电路图图案；所述ESD二极管区域电路图图案位于元胞栅极沟槽和互联栅极沟槽之间的上方，所述集成电容上极板区域电路图图案位于集成电容的下极板沟槽上方；
步骤S12、利用干法蚀刻将ESD区域电路图图案和集成电容上极板区域电路图图案转移到硅衬底上，去除多余二氧化硅-氮化硅-二氧化硅复合型薄膜和光刻胶；
步骤S13、通过离子注入形成晶体管体区，用高温热退火对管体区掺杂元素进行激活，所述离子注入的杂质包括三价元素或五价元素；
步骤S14、通过光刻方法同时定义出晶体管元胞源极区域、ESD二极管区域和集成电容上极板区域，并通过离子注入方法同时对上述区域掺杂三价元素或五价元素杂质，随后去除掉光刻胶并通过高温热退火进行掺杂元素激活，最终得到元胞结构；
所述晶体管元胞源极区域位于元胞栅极两侧，若干所述ESD二极管区域间隔设置于于ESD区域内部，所述集成电容上极板区域位于设置于下极板沟槽上方的二氧化硅-氮化硅-二氧化硅复合型薄膜的上表面。
优选地，所述步骤S1、S7、S10、S13、S14中所述三价元素包括硼元素，所述五价元素包括砷、磷。
优选地，所述步骤S14中离子注入的元素极性应与步骤S10中的掺杂元素极性相反，在ESD区域形成PN结二极管。
优选地，所述步骤S5中所述牺牲氧化层的厚度为10～100nm；所述步骤S6中所述栅极氧化层的厚度为10～100nm；所述步骤S7中所述多晶硅的厚度为500～1000nm；所述步骤S9中所述二氧化硅-氮化硅-二氧化硅复合型薄膜的厚度为100～2000nm。
优选地，所述步骤B具体包括如下步骤：
步骤S15、通过化学气相淀积方法形成二氧化硅层间介质层，层间介质层可以进行硼磷杂质的掺杂，以提高薄膜流动性与外来杂质的吸附性；
步骤S16、通过光刻方法在二氧化硅层间介质层上表面同时定义出源区沟槽接触孔图形、互联栅极接触孔图形、ESD二极管的两端接触孔图形、集成电容下极板接触孔图形和上极板接触孔图形；
两个所述源区沟槽接触孔图形分部位于两个晶体管元胞源极区域上方，所述互联栅极接触孔图形位于互联栅极沟槽上方，两个所述ESD二极管的两端接触孔图形分别位于ESD二极管区域两端的上方，所述集成电容下极板接触孔图形位于集成电容的下极板沟槽靠近元胞栅极沟槽的一侧的上方，所述上极板接触孔图形位于集成电容上极板区域的上方；
步骤S17、通过干法蚀刻二氧化硅层间介质层，将源区沟槽接触孔、互联栅极接触孔、ESD二极管的两端接触孔、集成电容下极板接触孔和上极板接触孔的图形转移到硅衬底上；
步骤S18、利用离子注入掺杂高浓度杂质元素到接触孔的底部，快速热退火激活杂质以制作得到全部接触孔的欧姆接触；
步骤S19、通过物理化学气相沉积方法在源区沟槽接触孔、互联栅极接触孔、ESD二极管的两端接触孔、集成电容下极板接触孔和上极板接触孔的底部淀积金属钛，并以氮化钛作为粘结层，通过快速热退化形成硅化物，并淀积金属钨，通过干法刻蚀方法去除掉接触孔以外的金属钨，在接触孔里形成钨栓。
优选地，所述步骤S18中本次离子注入的杂质元素极性应与第13步晶体管体区注入元素极性相同。
优选地，所述步骤C具体包括如下步骤：步骤S20、在钨栓上方通过磁控溅射法淀积金属铝铜，随后利用光刻方法与干法蚀刻形成电路链接；
其中互联栅极接触孔和ESD二极管的两端接触孔远离源区沟槽接触孔的一侧内的钨栓通过金属铝铜相连接，源区沟槽接触孔、ESD二极管的两端接触孔靠近源区沟槽接触孔的一侧以及集成电容下极板接触孔内的钨栓通过金属铝铜相连接，上极板接触孔内的钨栓上方沉积有所述金属铝铜，使ESD和集成电容接入沟槽功率器件中。
优选地，所述步骤D具体包括如下步骤：步骤S21、淀积钝化层，所述钝化层包括氮化硅或二氧化硅；通过光刻方法和干法蚀刻方法将焊盘区域蚀刻开，后续可通过在焊盘上打线进行封装，至此整个工艺流程完成。特别的，如不需要集成电容，仍可通过源极焊盘进行打线封装。
一种沟槽功率器件与源极电容集成，所述沟槽功率器件与源极电容集成根据所述的沟槽功率器件与源极电容集成的制造方法制备得到。
综上所述，与现有技术相比，本发明具有如下的有益效果：
(1)可以在沟槽功率器件制造的同时，集成源极电容的制造；
(2)由于没有增加掩模版，成本可控；
(3)集成电容的沟槽功率器件可以减少外接电容的使用，从而减小印刷电路板的使用面积，达到降低成本和设备小型化的目的。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S1的工艺流程示意图；
图2为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S2的工艺流程示意图；
图3为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S3的工艺流程示意图；
图4为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S4的工艺流程示意图；
图5为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S5的工艺流程示意图；
图6为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S6的工艺流程示意图；
图7为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S7的工艺流程示意图；
图8为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S8的工艺流程示意图；
图9为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S9的工艺流程示意图；
图10为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S10的工艺流程示意图；
图11为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S11的工艺流程示意图；
图12为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S12的工艺流程示意图；
图13为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S13的工艺流程示意图；
图14为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S14的工艺流程示意图；
图15为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S14的工艺流程示意图；
图16为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S15的工艺流程示意图；
图17为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S16的工艺流程示意图；
图18为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S17的工艺流程示意图；
图19为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S18的工艺流程示意图；
图20为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S19的工艺流程示意图；
图21为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S20的工艺流程示意图；
图22为本发明实施例1-3一种沟槽功率器件与源极电容集成及其制造方法的步骤S21的工艺流程示意图；
附图标记：
1、硅衬底；2、外延层；3、掩膜；4、元胞栅极；5、互联栅极沟槽；6、集成电容的下极板沟槽；7、牺牲氧化层；8、栅极氧化层；9、多晶硅；10、二氧化硅-氮化硅-二氧化硅复合型薄膜；11、本征多晶硅；12、ESD区域；13、集成电容上极板区域；14、晶体管体区；15、晶体管元胞源极区域；16、ESD二极管区域；17、集成电容上极板区域；18、二氧化硅层间介质层；19、源区沟槽接触孔；20、互联栅极接触孔；21、ESD二极管的两端接触孔；22、集成电容下极板接触孔；23、上极板接触孔；24、欧姆接触；25、粘结层；26、金属铝铜。
具体实施方式
以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进，这些都属于本发明的保护范围。在本文中所披露的范围的端点和任何值都不限于该精确的范围或值，这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说，各个范围的端点值之间、各个范围的端点值和单独的点值之间，以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围，这些数值范围应被视为在本文中具体公开，下面结合具体实施例对本发明进行详细说明：
实施例1
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、如图1所示，在硅衬底1上采取化学气相淀积的方式生长外延层2。根据器件极性的不同，可以选择掺杂三价元素(硼)以制备P型器件或五价元素(砷，磷)以制备N型器件，本实施例选择三价元素(硼)以制备P型器件。外延层2根据工作电压的不同，厚度可以有微米级的变化。
步骤S2、如图2所示，在硅衬底上沉积二氧化硅薄膜作为沟槽蚀刻所需的掩膜3。该掩膜3由低温化学气相沉积或者高温炉管方法制备，本实施例以低温化学气相沉积方法制备。
步骤S3、如图3所示，在掩膜上进行光刻胶旋涂，通过光刻机曝光将掩模版上沟槽图形定义在光刻胶上。特别的，此方法需同时定义三种沟槽，其一为元胞栅极沟槽4，其关键尺寸最小，用于形成元胞晶体管的栅极；其二为互联栅极沟槽5，其尺寸稍大，用于实现元胞晶体管的栅极互联；其三为集成电容的下极板沟槽6，其尺寸最大，用于形成集成电容的下极板。
步骤S4、如图4所示，在掩膜上形成电路图形后，利用干法蚀刻将电路图形转移到硅衬底上，并通过湿法刻蚀，将光刻胶和掩膜3去除掉。由于干法蚀刻的特性，关键尺寸较大的互联栅极沟槽5和集成电容的下极板沟槽6会蚀刻得较深，元胞栅极沟槽4会蚀刻得较浅。
步骤S5、如图5所示，利用高温炉管热氧化方法在沟槽侧壁生长一层牺牲氧化层7，其厚度为10纳米，用于沟槽侧壁硅晶格损伤修复和圆润。
步骤S6、如图6所示，通过湿法刻蚀，将牺牲氧化层7去除，然后利用高温炉管热氧化方法生长栅极氧化层8。根据应用不同，栅极氧化层厚度为10纳米。
步骤S7、如图7所示，采用低压化学气相沉积方法在沟槽和硅衬底表面沉积一层多晶硅9，其厚度为500纳米。根据功率器件极性的不同，在淀积的过程中掺杂五价元素或在栅极形成后进行离子注入掺杂三价元素。
步骤S8、如图8所示，利用化学机械研磨或干法蚀刻以去除沟槽以外的多晶硅。
步骤S9、如图9所示，利用高温炉管热氧化方法在硅衬底表面生长二氧化硅-氮化硅-二氧化硅复合型薄膜10，既用作静电保护二极管(ESD)的绝缘隔离层，也是集成电容的介质层。二氧化硅和氮化硅的厚度为100纳米范围内可调。
步骤S10、如图10所示，采用低压化学气相沉积方法在二氧化硅-氮化硅-二氧化硅复合型薄膜10表面沉积一层本征多晶硅11，并利用离子注入进行掺杂。根据功率器件极性的不同，离子注入的杂质为五价元素(砷)。
步骤S11、如图11所示，利用光刻方法定义出ESD区域图案12和集成电容上极板区域图案13。
步骤S12、如图12所示，利用干法蚀刻将ESD区域图案12和集成电容上极板区域图案13电路图形转移到硅衬底上，随后一并去除掉不需要的二氧化硅-氮化硅-二氧化硅复合型薄膜11和光刻胶。
步骤S13、如图13所示，利用离子注入形成晶体管体区14，然后用高温热退火对管体区掺杂元素进行激活。根据功率器件极性的不同，离子注入的杂质为三价元素(硼)。
步骤S14、如图14所示，利用光刻方法同时定义出晶体管元胞源极区域15，ESD二极管区域16和集成电容上极板区域17，并通过离子注入方法同时对上述15、16、17区域进行掺杂，随后去除掉光刻胶并通过高温热退火进行掺杂元素激活。特别的，本次离子注入的元素极性与步骤10中的掺杂元素极性相反，以便在ESD区域形成PN结二极管，得到如图15所示元胞结构，后续方法主要是为了制作器件隔绝与金属互连。
步骤S15、如图16所示，利用化学气相淀积形成二氧化硅层间介质层18。层间介质层可进行硼磷杂质的掺杂，以提高薄膜流动性与外来杂质的吸附性
步骤S16、如图17所示，利用光刻方法同时定义出源区沟槽接触孔19，互联栅极接触孔20，ESD二极管的两端接触孔21，集成电容下极板接触孔22和上极板接触孔23。
步骤S17、如图18，利用干法蚀刻二氧化硅层间介质层，将全部接触孔19-23图形转移到硅衬底上。
步骤S18、如图19所示，利用离子注入掺杂高浓度杂质到接触孔的底部，快速热退火激活杂质以制作全部接触孔的欧姆接触24。特别的，本次离子注入的元素极性与步骤S13步晶体管体区注入元素极性相同。
步骤S19、如图20所示，利用物理化学气相沉积方法淀积金属钛，以及氮化钛作为粘结层25，并利用快速热退化形成硅化物。随后在硅衬底上淀积金属钨，并通过干法刻蚀方法去除掉接触孔以外的金属钨，最终在接触孔里形成钨栓。
步骤S20、如图21所示，利用磁控溅射淀积金属铝铜26，随后利用光刻方法与干法蚀刻形成电路链接，确保ESD和集成电容接入沟槽功率器件中。
步骤S21、如图22所示，淀积钝化层(氮化硅或二氧化硅)，并用光刻方法和干法蚀刻方法将焊盘区域蚀刻开，后续可通过在焊盘上打线进行封装，至此整个工艺流程完成。特别的，如不需要集成电容，仍可通过源极焊盘进行打线封装。
实施例2
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、如图1所示，在硅衬底1上采取化学气相淀积的方式生长外延层2。根据器件极性的不同，可以选择掺杂三价元素(硼)以制备P型器件或五价元素(砷，磷)以制备N型器件，本实施例选择五价元素(砷)以制备N型器件。外延层2根据工作电压的不同，厚度可以有微米级的变化。
步骤S2、如图2所示，在硅衬底上沉积二氧化硅薄膜作为沟槽蚀刻所需的掩膜3。该掩膜3由低温化学气相沉积或者高温炉管方法制备，本实施例以高温炉管方法制备。
步骤S3、如图3所示，在掩膜上进行光刻胶旋涂，通过光刻机曝光将掩模版上沟槽图形定义在光刻胶上。特别的，此方法需同时定义三种沟槽，其一为元胞栅极沟槽4，其关键尺寸最小，用于形成元胞晶体管的栅极；其二为互联栅极沟槽5，其尺寸稍大，用于实现元胞晶体管的栅极互联；其三为集成电容的下极板沟槽6，其尺寸最大，用于形成集成电容的下极板。
步骤S4、如图4所示，在掩膜上形成电路图形后，利用干法蚀刻将电路图形转移到硅衬底上，并通过湿法刻蚀，将光刻胶和掩膜3去除掉。由于干法蚀刻的特性，关键尺寸较大的互联栅极沟槽5和集成电容的下极板沟槽6会蚀刻得较深，元胞栅极沟槽4会蚀刻得较浅。
步骤S5、如图5所示，利用高温炉管热氧化方法在沟槽侧壁生长一层牺牲氧化层7，其厚度为50纳米，用于沟槽侧壁硅晶格损伤修复和圆润。
步骤S6、如图6所示，通过湿法刻蚀，将牺牲氧化层7去除，然后利用高温炉管热氧化方法生长栅极氧化层8。根据应用不同，栅极氧化层厚度可为50纳米。
步骤S7、如图7所示，采用低压化学气相沉积方法在沟槽和硅衬底表面沉积一层多晶硅9，其厚度为800纳米。根据功率器件极性的不同，在淀积的过程中掺杂五价元素或在栅极形成后进行离子注入掺杂三价元素。
步骤S8、如图8所示，利用化学机械研磨或干法蚀刻以去除沟槽以外的多晶硅。
步骤S9、如图9所示，利用高温炉管热氧化方法在硅衬底表面生长二氧化硅-氮化硅-二氧化硅复合型薄膜10，既用作静电保护二极管(ESD)的绝缘隔离层，也是集成电容的介质层。二氧化硅和氮化硅的厚度为1000纳米。
步骤S10、如图10所示，采用低压化学气相沉积方法在二氧化硅-氮化硅-二氧化硅复合型薄膜10表面沉积一层本征多晶硅11，并利用离子注入进行掺杂。根据功率器件极性的不同，离子注入的杂质为三价元素(硼)。
步骤S11、如图11所示，利用光刻方法定义出ESD区域图案12和集成电容上极板区域图案13。
步骤S12、如图12所示，利用干法蚀刻将ESD区域图案12和集成电容上极板区域图案13电路图形转移到硅衬底上，随后一并去除掉不需要的二氧化硅-氮化硅-二氧化硅复合型薄膜11和光刻胶。
步骤S13、如图13所示，利用离子注入形成晶体管体区14，然后用高温热退火对管体区掺杂元素进行激活。根据功率器件极性的不同，离子注入的杂质为五价元素(磷)。
步骤S14、如图14所示，利用光刻方法同时定义出晶体管元胞源极区域15，ESD二极管区域16和集成电容上极板区域17，并通过离子注入方法同时对上述15、16、17区域进行掺杂，随后去除掉光刻胶并通过高温热退火进行掺杂元素激活。特别的，本次离子注入的元素极性与步骤10中的掺杂元素极性相反，以便在ESD区域形成PN结二极管，得到如图15所示元胞结构，后续方法主要是为了制作器件隔绝与金属互连。
步骤S15、如图16所示，利用化学气相淀积形成二氧化硅层间介质层18。层间介质层可进行硼磷杂质的掺杂，以提高薄膜流动性与外来杂质的吸附性
步骤S16、如图17所示，利用光刻方法同时定义出源区沟槽接触孔19，互联栅极接触孔20，ESD二极管的两端接触孔21，集成电容下极板接触孔22和上极板接触孔23。
步骤S17、如图18，利用干法蚀刻二氧化硅层间介质层，将全部接触孔19-23图形转移到硅衬底上。
步骤S18、如图19所示，利用离子注入掺杂高浓度杂质到接触孔的底部，快速热退火激活杂质以制作全部接触孔的欧姆接触24。特别的，本次离子注入的元素极性与步骤S13步晶体管体区注入元素极性相同。
步骤S19、如图20所示，利用物理化学气相沉积方法淀积金属钛，以及氮化钛作为粘结层25，并利用快速热退化形成硅化物。随后在硅衬底上淀积金属钨，并通过干法刻蚀方法去除掉接触孔以外的金属钨，最终在接触孔里形成钨栓。
步骤S20、如图21所示，利用磁控溅射淀积金属铝铜26，随后利用光刻方法与干法蚀刻形成电路链接，确保ESD和集成电容接入沟槽功率器件中。
步骤S21、如图22所示，淀积钝化层(氮化硅或二氧化硅)，并用光刻方法和干法蚀刻方法将焊盘区域蚀刻开，后续可通过在焊盘上打线进行封装，至此整个工艺流程完成。特别的，如不需要集成电容，仍可通过源极焊盘进行打线封装。
实施例3
一种沟槽功率器件与源极电容集成及其制造方法，包括如下步骤：
步骤S1、如图1所示，在硅衬底1上采取化学气相淀积的方式生长外延层2。根据器件极性的不同，可以选择掺杂三价元素(硼)以制备P型器件或五价元素(砷，磷)以制备N型器件，本实施例选择五价元素(磷)以制备N型器件。外延层2根据工作电压的不同，厚度可以有微米级的变化。
步骤S2、如图2所示，在硅衬底上沉积二氧化硅薄膜作为沟槽蚀刻所需的掩膜3。该掩膜3由低温化学气相沉积或者高温炉管方法制备，本实施例以低温化学气相沉积方法制备。
步骤S3、如图3所示，在掩膜上进行光刻胶旋涂，通过光刻机曝光将掩模版上沟槽图形定义在光刻胶上。特别的，此方法需同时定义三种沟槽，其一为元胞栅极沟槽4，其关键尺寸最小，用于形成元胞晶体管的栅极；其二为互联栅极沟槽5，其尺寸稍大，用于实现元胞晶体管的栅极互联；其三为集成电容的下极板沟槽6，其尺寸最大，用于形成集成电容的下极板。
步骤S4、如图4所示，在掩膜上形成电路图形后，利用干法蚀刻将电路图形转移到硅衬底上，并通过湿法刻蚀，将光刻胶和掩膜3去除掉。由于干法蚀刻的特性，关键尺寸较大的互联栅极沟槽5和集成电容的下极板沟槽6会蚀刻得较深，元胞栅极沟槽4会蚀刻得较浅。
步骤S5、如图5所示，利用高温炉管热氧化方法在沟槽侧壁生长一层牺牲氧化层7，其厚度约为100纳米，用于沟槽侧壁硅晶格损伤修复和圆润。
步骤S6、如图6所示，通过湿法刻蚀，将牺牲氧化层7去除，然后利用高温炉管热氧化方法生长栅极氧化层8。根据应用不同，栅极氧化层厚度为100纳米。
步骤S7、如图7所示，采用低压化学气相沉积方法在沟槽和硅衬底表面沉积一层多晶硅9，其厚度为1000纳米。根据功率器件极性的不同，在淀积的过程中掺杂五价元素或在栅极形成后进行离子注入掺杂三价元素。
步骤S8、如图8所示，利用化学机械研磨或干法蚀刻以去除沟槽以外的多晶硅。
步骤S9、如图9所示，利用高温炉管热氧化方法在硅衬底表面生长二氧化硅-氮化硅-二氧化硅复合型薄膜10，既用作静电保护二极管(ESD)的绝缘隔离层，也是集成电容的介质层。二氧化硅和氮化硅的厚度为2000纳米。
步骤S10、如图10所示，采用低压化学气相沉积方法在二氧化硅-氮化硅-二氧化硅复合型薄膜10表面沉积一层本征多晶硅11，并利用离子注入进行掺杂。根据功率器件极性的不同，离子注入的杂质是五价元素(磷)。
步骤S11、如图11所示，利用光刻方法定义出ESD区域图案12和集成电容上极板区域图案13。
步骤S12、如图12所示，利用干法蚀刻将ESD区域图案12和集成电容上极板区域图案13电路图形转移到硅衬底上，随后一并去除掉不需要的二氧化硅-氮化硅-二氧化硅复合型薄膜11和光刻胶。
步骤S13、如图13所示，利用离子注入形成晶体管体区14，然后用高温热退火对管体区掺杂元素进行激活。根据功率器件极性的不同，离子注入的杂质是三价元素(硼)。
步骤S14、如图14所示，利用光刻方法同时定义出晶体管元胞源极区域15，ESD二极管区域16和集成电容上极板区域17，并通过离子注入方法同时对上述15、16、17区域进行掺杂，随后去除掉光刻胶并通过高温热退火进行掺杂元素激活。特别的，本次离子注入的元素极性与步骤10中的掺杂元素极性相反，以便在ESD区域形成PN结二极管，得到如图15所示元胞结构，后续方法主要是为了制作器件隔绝与金属互连。
步骤S15、如图16所示，利用化学气相淀积形成二氧化硅层间介质层18。层间介质层可进行硼磷杂质的掺杂，以提高薄膜流动性与外来杂质的吸附性
步骤S16、如图17所示，利用光刻方法同时定义出源区沟槽接触孔19，互联栅极接触孔20，ESD二极管的两端接触孔21，集成电容下极板接触孔22和上极板接触孔23。
步骤S17、如图18，利用干法蚀刻二氧化硅层间介质层，将全部接触孔19-23图形转移到硅衬底上。
步骤S18、如图19所示，利用离子注入掺杂高浓度杂质到接触孔的底部，快速热退火激活杂质以制作全部接触孔的欧姆接触24。特别的，本次离子注入的元素极性与步骤S13步晶体管体区注入元素极性相同。
步骤S19、如图20所示，利用物理化学气相沉积方法淀积金属钛，以及氮化钛作为粘结层25，并利用快速热退化形成硅化物。随后在硅衬底上淀积金属钨，并通过干法刻蚀方法去除掉接触孔以外的金属钨，最终在接触孔里形成钨栓。
步骤S20、如图21所示，利用磁控溅射淀积金属铝铜26，随后利用光刻方法与干法蚀刻形成电路链接，确保ESD和集成电容接入沟槽功率器件中。
步骤S21、如图22所示，淀积钝化层(氮化硅或二氧化硅)，并用光刻方法和干法蚀刻方法将焊盘区域蚀刻开，后续可通过在焊盘上打线进行封装，至此整个工艺流程完成。特别的，如不需要集成电容，仍可通过源极焊盘进行打线封装。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变化或修改，这并不影响本发明的实质内容。在不冲突的情况下，本申请的实施例和实施例中的特征可以任意相互组合。

Claims (10)

  1. 一种沟槽功率器件与源极电容集成的制造方法，其特征在于，包括如下步骤：
    A、元胞结构的制备；
    B、接触孔、钨栓的制备；
    C、ESD、集成电路接入沟槽功率器件；
    D、淀积钝化层，蚀刻焊盘区域，打线封装。
  2. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤A具体包括如下步骤：
    步骤S1、在硅衬底上表面化学气相沉积外延层；所述外延层掺杂三价元素、五价元素；
    步骤S2、在外延层上表面沉积掩膜，所述掩膜的成分为二氧化硅，所述掩膜的制备方法包括低温化学气相沉积法或高温炉管法；
    步骤S3、在掩膜上表面旋涂光刻胶，光刻机曝光定义沟槽图形，所述沟槽图形依次包括集成电容的下极板沟槽图形、元胞栅极沟槽图形、互联栅极沟槽图形，在掩膜上形成电路图形；
    所述集成电容的下极板沟槽图形的关键尺寸大于互联栅极沟槽图形的关键尺寸大于元胞栅极沟槽图形的关键尺寸；
    步骤S4、在掩膜上形成电路图形后，利用干法蚀刻将电路图形转移到硅衬底上，并通过湿法刻蚀，去除光刻胶和掩膜；
    蚀刻得到的集成电容的下极板沟槽的深度大于互联栅极沟槽的深度大于元胞栅极沟槽的深度；
    步骤S5、通过高温炉管热氧化法在沟槽侧壁生长一层牺牲氧化层；
    步骤S6、通过湿法刻蚀法去除牺牲氧化层，然后通过高温炉管热氧化法生长栅极氧化层；
    步骤S7、通过低压化学气相沉积方法在沟槽和硅衬底表面沉积一层多晶硅，并掺杂五价元素或三价元素，当掺杂元素为五价元素时，在沉积过程中进行掺杂，当掺杂元素为三价元素时，在栅极形成后通过离子注入进行掺杂；
    步骤S8、通过化学机械研磨或干法蚀刻去除沟槽上端槽口上方多晶硅；
    步骤S9、通过高温炉管热氧化法在栅极氧化层/多晶硅上表面生长二氧化硅-氮化硅-二氧化硅复合型薄膜；
    步骤S10、通过低压化学气相沉积法在二氧化硅-氮化硅-二氧化硅复合型薄膜上表面沉积一层本征多晶硅，并利用离子注入进行掺杂杂质，所述离子注入的杂质包括五价元素或三价元素；
    步骤S11、利用光刻法定义出ESD二极管区域电路图图案和集成电容上极板区域电路图图案；所述ESD二极管区域电路图图案位于元胞栅极沟槽和互联栅极沟槽之间的上方，所述集成电容上极板区域电路图图案位于集成电容的下极板沟槽上方；
    步骤S12、利用干法蚀刻将ESD区域电路图图案和集成电容上极板区域电路图图案转移到硅衬底上，去除多余二氧化硅-氮化硅-二氧化硅复合型薄膜和光刻胶；
    步骤S13、通过离子注入形成晶体管体区，用高温热退火对管体区掺杂元素进行激活，所述离子注入的杂质包括三价元素或五价元素；
    步骤S14、通过光刻方法同时定义出晶体管元胞源极区域、ESD二极管区域和集成电容上极板区域，并通过离子注入方法同时对上述区域掺杂三价元素或五价元素杂质，随后去除掉光刻胶并通过高温热退火进行掺杂元素激活，最终得到元胞结构；
    所述晶体管元胞源极区域位于元胞栅极两侧，若干所述ESD二极管区域间隔设置于于ESD区域内部，所述集成电容上极板区域位于设置于下极板沟槽上方的二氧化硅-氮化硅-二氧化硅复合型薄膜的上表面。
  3. 根据权利要求2所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S1、S7、S10、S13、S14中所述三价元素包括硼元素，所述五价元素包括砷、磷。
  4. 根据权利要求2所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S14中离子注入的元素极性应与步骤S10中的掺杂元素极性相反，在ESD区域形成PN结二极管。
  5. 根据权利要求2所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S5中所述牺牲氧化层的厚度为10～100nm；所述步骤S6中所述栅极氧化层的厚度为10～100nm；所述步骤S7中所述多晶硅的厚度为500～1000nm；所述步骤S9中所述二氧化硅-氮化硅-二氧化硅复合型薄膜的厚度为100～2000nm。
  6. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤B具体包括如下步骤：
    步骤S15、通过化学气相淀积方法形成二氧化硅层间介质层；
    步骤S16、通过光刻方法在二氧化硅层间介质层上表面同时定义出源区沟槽接触孔图形、互联栅极接触孔图形、ESD二极管的两端接触孔图形、集成电容下极板接触孔图形和上极板接触孔图形；
    两个所述源区沟槽接触孔图形分部位于两个晶体管元胞源极区域上方，所述互联栅极接触孔图形位于互联栅极沟槽上方，两个所述ESD二极管的两端接触孔图形分别位于ESD二极管区域两端的上方，所述集成电容下极板接触孔图形位于集成电容的下极板沟槽靠近元胞栅极沟槽的一侧的上方，所述上极板接触孔图形位于集成电容上极板区域的上方；
    步骤S17、通过干法蚀刻二氧化硅层间介质层，将源区沟槽接触孔、互联栅极接触孔、ESD二极管的两端接触孔、集成电容下极板接触孔和上极板接触孔的图形转移到硅衬底上；
    步骤S18、利用离子注入掺杂高浓度杂质元素到接触孔的底部，快速热退火激活杂质以制作得到全部接触孔的欧姆接触；
    步骤S19、通过物理化学气相沉积方法在源区沟槽接触孔、互联栅极接触孔、ESD二极管的两端接触孔、集成电容下极板接触孔和上极板接触孔的底部淀积金属钛，并以氮化钛作为粘结层，通过快速热退化形成硅化物，并淀积金属钨，通过干法刻蚀方法去除掉接触孔以外的金属钨，在接触孔里形成钨栓。
  7. 根据权利要求6所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤S18中本次离子注入的杂质元素极性应与第13步晶体管体区注入元素极性相同。
  8. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤C具体包括如下步骤：步骤S20、在钨栓上方通过磁控溅射法淀积金属铝铜，随后利用光刻方法与干法蚀刻形成电路链接；
    其中互联栅极接触孔和ESD二极管的两端接触孔远离源区沟槽接触孔的一侧内的钨栓通过金属铝铜相连接，源区沟槽接触孔、ESD二极管的两端接触孔靠近源区沟槽接触孔的一侧以及集成电容下极板接触孔内的钨栓通过金属铝铜相连接，上极板接触孔内的钨栓上方沉积有所述金属铝铜，使ESD和集成电容接入沟槽功率器件中。
  9. 根据权利要求1所述的沟槽功率器件与源极电容集成的制造方法，其特征在于，所述步骤D具体包括如下步骤：步骤S21、淀积钝化层，所述钝化层包括氮化硅或二氧化硅；通过光刻方法和干法蚀刻方法将焊盘区域蚀刻开。
  10. 一种沟槽功率器件与源极电容集成，其特征在于，所述沟槽功率器件与源极电容集成根据权利要求1-9所述的沟槽功率器件与源极电容集成的制造方法制备得到。
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