WO2020233698A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2020233698A1
WO2020233698A1 PCT/CN2020/091762 CN2020091762W WO2020233698A1 WO 2020233698 A1 WO2020233698 A1 WO 2020233698A1 CN 2020091762 W CN2020091762 W CN 2020091762W WO 2020233698 A1 WO2020233698 A1 WO 2020233698A1
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Prior art keywords
light
pixel
sub
area
substrate
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PCT/CN2020/091762
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/264,056 priority Critical patent/US11895890B2/en
Publication of WO2020233698A1 publication Critical patent/WO2020233698A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8428—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • an embodiment of the present disclosure provides a display substrate, including: a first substrate and a plurality of pixel units disposed on the first substrate.
  • the multiple pixel units are arranged in multiple rows and multiple columns; one pixel unit of the multiple pixel units has a first effective light-emitting area, a second effective light-emitting area, and a third effective light-emitting area; the pixel unit Including: multiple light emitting devices.
  • the plurality of light-emitting devices includes a first light-emitting device, a second light-emitting device, and a third light-emitting device.
  • the first light-emitting device, the second light-emitting device, and the third light-emitting device respectively include the first effective light-emitting device.
  • the first effective light-emitting area and the second effective light-emitting area are arranged at intervals along a first direction, and the third effective light-emitting area and the first effective light-emitting area and the second effective light-emitting area are along a second direction And the minimum distance between the first effective light-emitting area and the second effective light-emitting area is smaller than the minimum distance between the third effective light-emitting area and the first effective light-emitting area and the second effective light-emitting area.
  • the first direction is parallel to the row direction of the plurality of pixel units
  • the second direction is parallel to the column direction of the plurality of pixel units.
  • the minimum distance between the first effective light-emitting area and the second effective light-emitting area is about 10-20 ⁇ m, and the third effective light-emitting area is different from the first effective light-emitting area and the second effective light-emitting area.
  • the minimum pitch of the effective light-emitting area is about 20-25 ⁇ m.
  • the third light emitting device is configured to emit green light; the first color light emitting device and the second color light emitting device are configured to emit red and blue light, respectively.
  • the first light-emitting device includes a first anode, a first light-emitting functional layer, and a first cathode
  • the second light-emitting device includes a second anode, a second light-emitting functional layer, and a second cathode
  • the third light emitting device includes a third anode, a third light emitting functional layer, and a third cathode.
  • the pixel unit further includes a plurality of pixel drive circuits, the first anode, the second anode, and the third anode are respectively connected to a corresponding pixel drive circuit, and the pixel drive circuit is configured to drive the corresponding light emitting The device emits light.
  • the pixel driving circuit includes a storage capacitor; the orthographic projections of all the storage capacitors in the pixel unit on the first substrate are located in the third effective light-emitting area and the first effective light-emitting area and the second The effective light emitting area is between the orthographic projections on the first substrate.
  • the display substrate has a display area; the display area includes a plurality of pixel areas, and the area where each pixel unit is located is a pixel area.
  • the pixel area includes a first sub-area, a second sub-area, and a third sub-area that are sequentially arranged along a first direction.
  • the pixel driving circuit is provided in each sub-region.
  • the first anode is located in the first sub-region and the second sub-region and is connected to the pixel driving circuit provided in the second sub-region; the second anode is located at least in the third sub-region The third anode is located in the first sub-region, the second sub-region, and the third sub-region, and is connected to the pixel driving circuit provided in the third sub-region.
  • the pixel driving circuit in the first sub-region is connected.
  • the second anode further extends into the second sub-region.
  • the first anode is connected to the pixel driving circuit provided in the second sub-region through a first via hole, and the second anode drives the pixel provided in the third sub-region.
  • the circuit is connected through a second via, and the third anode is connected with the pixel driving circuit provided in the first sub-region through a third via; the first via, the second via and the The orthographic projection of the third via on the first substrate is located on the third effective light-emitting area and the orthographic projection of the first effective light-emitting area and the second effective light-emitting area on the first substrate between.
  • the geometric center of the orthographic projection of the first via, the second via, and the third via in the pixel unit on the first substrate is located along the On the same straight line in the first direction.
  • the display substrate further includes: a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines disposed on the first substrate, and a plurality of first data lines The wires, the plurality of second data lines, and the plurality of third data lines all extend along the second direction.
  • a first data line and a second data line are arranged between the first sub-region and the second sub-region, and the first data line is connected to a pixel driving circuit located in the first sub-region ,
  • the second data line is connected to the pixel driving circuit located in the second sub-region;
  • a third data line is arranged between the second sub-region and the third sub-region, and the third data The line is connected to the pixel driving circuit located in the third sub-region.
  • the display substrate further includes a plurality of first gate lines, a plurality of first voltage lines, and a plurality of second voltage lines.
  • the plurality of first gate lines all extend in the first direction
  • the plurality of first voltage lines and the plurality of second voltage lines all extend in the second direction.
  • the pixel driving circuit includes a first transistor, a driving transistor, and a storage capacitor.
  • the storage capacitor includes a first storage electrode and a second storage electrode.
  • the gate of the first transistor is connected to a first gate line corresponding to the pixel driving circuit; the first electrode of the first transistor located in the first sub-region is connected to the first data line, and is located The first electrode of the first transistor in the second sub-region is connected to the second data line, and the first electrode of the first transistor in the third sub-region is connected to the third data line ; The second electrode of the first transistor is connected to the gate of the driving transistor.
  • the first electrode of the driving transistor is connected to a first voltage line corresponding to the pixel driving circuit, and the second electrode of the driving transistor is connected to the first storage electrode; the The first storage electrode of the storage capacitor is connected to the third anode through the third via; the first storage electrode of the storage capacitor located in the second sub-region is connected to the first via through the first via. An anode connection, and the first storage electrode of the storage capacitor located in the third sub-area is connected to the second anode through the second via hole.
  • the first cathode, the second cathode, and the third cathode are connected to a second voltage line through at least one fourth via.
  • the second storage electrode is connected to the gate of the driving transistor; the orthographic projections of the first via, the second via, and the third via on the first substrate respectively correspond to it The orthographic projections of the storage capacitors on the first substrate overlap.
  • the driving transistor further includes an active pattern disposed on a side of the gate of the driving transistor close to the first substrate.
  • the first storage electrode and the first electrode and the second electrode of the driving transistor are arranged in the same layer; the second storage electrode and the active pattern of the driving transistor are arranged in the same layer.
  • the gate of the first transistor is served by the corresponding first gate line.
  • every two adjacent pixel units are a pixel group, and the two pixel units of each pixel group are a first pixel unit and a second pixel unit, respectively.
  • a second voltage line is provided between the first pixel unit and the second pixel unit in the pixel group; along the first direction, a first voltage line is provided between two adjacent pixel groups line.
  • the pixel driving circuit further includes a second transistor.
  • the display substrate further includes a plurality of second gate lines and a plurality of sensing signal lines; the plurality of second gate lines extend along the first direction, and the plurality of sensing signal lines extend along the second direction extend.
  • a sensing signal line is arranged between the first pixel unit and the second pixel unit in the pixel group.
  • the gate of the second transistor is connected to a corresponding second gate line; the first electrode of the second transistor is connected to a corresponding sensing signal line, and the second electrode of the second transistor is connected to the first A storage electrode connection.
  • the gate of the second transistor is served by a second gate line connected to it.
  • the orthographic projection of the third light-emitting device on the first substrate and the orthographic projection of the second transistor on the first substrate have an overlapping area.
  • the orthographic projection on the first substrate of the second light-emitting device in the first pixel unit of the pixel group is related to the second voltage line and the sensing signal
  • the orthographic projection of a line on the first substrate has an overlapping area;
  • the orthographic projection of the second light-emitting device located in the second pixel unit of the pixel group on the first substrate is
  • the orthographic projection of the first voltage line on the first substrate has an overlapping area.
  • the plurality of first data lines, the plurality of second data lines, the plurality of third data lines, the plurality of first voltage lines, and the plurality of second voltage lines It is arranged on the same layer as the multiple sensing signal lines.
  • the first effective light-emitting area and the second effective light-emitting area are symmetrically distributed with respect to a central axis of the third effective light-emitting area along the second direction.
  • a display device including the above-mentioned display substrate, and further including a color filter substrate.
  • the color filter substrate includes a second substrate and a color filter layer disposed on a side of the second substrate facing the first substrate.
  • the color film layer includes a plurality of first color filter units, a plurality of second color filter units, and a plurality of third color filter units; a black matrix is arranged between two adjacent filter units; each The first color filter unit and the corresponding one of the first light-emitting devices overlap the orthographic projection on the second substrate, and each second color filter unit and the corresponding one of the second light-emitting devices are on the second substrate.
  • the orthographic projections on the second substrate overlap, and the orthographic projections of each third color filter unit and a corresponding third light-emitting device on the second substrate overlap.
  • FIG. 1A is a top structural view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 1B is a structural diagram of a display substrate provided by an embodiment of the disclosure.
  • FIG. 2A is a top structural diagram of a display device provided by an embodiment of the disclosure.
  • 2B is a structural diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 3 is a top structural view of a display device provided by related art
  • FIG. 4 is a cross-sectional structural diagram of a display device provided by the related art along the direction B-B' in FIG. 3;
  • 5A is a top structural view of a display substrate provided by an embodiment of the disclosure.
  • 5B is a top structural view of a pixel area of a display substrate provided by an embodiment of the disclosure.
  • 5C is a top structural view of a pixel area of another display substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a top structural view of another pixel area of a display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a top structural view of another pixel area of a display substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a top structural view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 9 is a top structural view of another display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a structural diagram of a pixel driving circuit of a display substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a top structural view of a first sub-region of a pixel region provided by an embodiment of the disclosure.
  • Figure 12 is a cross-sectional structural view of Figure 11 along the direction C-C';
  • Fig. 13 is a cross-sectional structural view of Fig. 11 along the direction D-D';
  • FIG. 14 is a top structural view of yet another display substrate provided by an embodiment of the disclosure.
  • FIG. 15 is a structural diagram of a pixel driving circuit of another display substrate provided by an embodiment of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • connection and its extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • the display device is, for example, a display panel, a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, and the like. As shown in FIGS. 1A and 1B, the display device includes a display substrate 1000.
  • the display substrate 1000 has a display area DA and a peripheral area S, and the peripheral area S is arranged around the display area DA for example.
  • the peripheral area S is used for wiring.
  • at least one driving circuit (such as a gate driving circuit, etc.) may also be provided.
  • the display substrate 1000 includes a first substrate 10, and a plurality of pixel units P disposed on the first substrate 10 and located in the display area DA, and the plurality of pixel units P are arranged in multiple rows and multiple columns. Arrangement.
  • One pixel unit P of the plurality of pixel units P includes a plurality of light emitting devices.
  • each pixel unit P includes a plurality of light emitting devices.
  • the pixel unit P has a first effective light-emitting area 1214, a second effective light-emitting area 1224, and a third effective light-emitting area 1234.
  • the plurality of light emitting devices includes a first light emitting device 121, a second light emitting device 122, and a third light emitting device 123.
  • the first light emitting device 121, the second light emitting device 122 and the third light emitting device 123 respectively include a first effective light emitting area 1214, The second effective light emitting area 1224 and the third effective light emitting area 1234.
  • the first light emitting device 121, the second light emitting device 122, and the third light emitting device 123 are used to emit light of three primary colors.
  • the three primary colors of light emitted by the first light emitting device 121, the second light emitting device 122, and the third light emitting device 123 are red light, green light, and blue light, respectively.
  • the light of the three primary colors emitted by the first light emitting device 121, the second light emitting device 122, and the third light emitting device 123 may also be cyan light, magenta light, and yellow light, respectively.
  • the first light emitting device 121 includes a first anode 1211, a first light emitting function layer 1212, and a first cathode 1213;
  • the second light emitting device 122 includes a second anode 1221, a second light emitting function
  • the third light-emitting device 123 includes a third anode 1231, a third light-emitting functional layer 1232, and a third cathode 1233.
  • the display substrate 1000 further includes a pixel defining layer 109.
  • the pixel defining layer 109 is in a grid shape, and each opening of the grid is an effective light-emitting area. That is, the three effective light-emitting areas located in the area where the pixel unit P is located are the first effective light-emitting area 1214, the second effective light-emitting area 1224, and the third effective light-emitting area 1234, respectively.
  • the first effective light-emitting area 1214 and the second effective light-emitting area 1224 are arranged at intervals along the first direction X, and the third effective light-emitting area 1234 and the first effective light-emitting area 1214 and the second effective light-emitting area 1224 are arranged along the first direction X.
  • the two directions are Y spaced apart, and the minimum distance between the first effective light emitting area 1214 and the second effective light emitting area 1224 is smaller than the minimum distance between the third effective light emitting area 1234 and the first effective light emitting area 1214 and the second effective light emitting area 1224, respectively.
  • the first direction X is parallel to the row direction of the plurality of pixel units P
  • the second direction Y is parallel to the column direction of the plurality of pixel units P.
  • the first cathode 1213, the second cathode 1223, and the third cathode 1233 in all the pixel units P form an integrated cathode layer.
  • the first anode 1211, the second anode 1221, and the third anode 1231 in all the pixel units P are arranged in the same layer, and the first anode 1211, the second anode 1221, and the third anode 1231 are located in the anode layer.
  • the first light-emitting functional layer 1212, the second light-emitting functional layer 1222, and the third light-emitting functional layer 1232 each include a light-emitting layer.
  • the first light-emitting functional layer 1212, the second light-emitting functional layer 1222, and the third light-emitting functional layer 1232 have different light-emitting colors, the first light-emitting functional layer 1212, the second light-emitting functional layer 1222, and the The materials of the light-emitting layers in the third light-emitting functional layer 1232 are different.
  • the first light-emitting functional layer 1212, the second light-emitting functional layer 1222, and the third light-emitting functional layer 1232 include not only the light-emitting layer, but also an electron transporting layer (ETL) and an electron injection layer ( Electron injection layer (EIL for short), hole transporting layer (HTL for short), and hole injection layer (HIL for short).
  • ETL electron transporting layer
  • EIL electron injection layer
  • HTL hole transporting layer
  • HIL hole injection layer
  • the hole transport layer and the hole injection layer are disposed between the first light-emitting layer and the first anode 1211, and the hole injection layer is closer to the first anode 1211 than the hole transport layer.
  • the second light-emitting functional layer 1222 and the third light-emitting functional layer 1232 are similar, and will not be repeated here.
  • the light-emitting layers in all light-emitting devices can be located on the same layer.
  • the electron transport layer in all light emitting devices can be located on the same layer, the electron injection layer in all light emitting devices can be located on the same layer, the hole transport layer in all light emitting devices can be located on the same layer, and the hole injection layer in all light emitting devices can be located on the same layer. Located on the same floor.
  • the light emitting layer is, for example, an organic light emitting layer, and based on this, the light emitting device is an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the light-emitting device is, for example, a top-emitting type light-emitting device.
  • the light emitted by the light-emitting device is emitted from a side away from the first substrate 10.
  • the anode layer is opaque, for example, a layered structure (ie, ITO/Ag/ITO) composed of a layer of ITO (Indium Tin Oxides), a layer of silver (Ag), and a layer of ITO (ie ITO/Ag/ITO), which emits light by reflection The part of the light emitted by the layer that is directed toward the anode layer, thereby improving the light output rate of the light-emitting device;
  • the cathode layer is transparent or semi-transparent, for example, a thin silver layer to transmit the light emitted by the light-emitting layer.
  • the display substrate 100 further includes a thin film encapsulation layer 150 located in the display area DA and disposed on the side of the light emitting device away from the first substrate 10.
  • the thin film encapsulation layer 150 includes a first inorganic encapsulation layer 151, an organic encapsulation layer 152, and a second inorganic encapsulation layer 153 that are stacked, and the organic encapsulation layer 152 is located between the first inorganic encapsulation layer 151 and the second inorganic encapsulation layer 153 .
  • the first effective light-emitting area 1214, the second effective light-emitting area 1224, and the third effective light-emitting area 1234 in the display substrate 1000 are sequentially and periodically arranged along the first direction X, and the first The distance between the effective light-emitting area 1214 and the second effective light-emitting area 1224 is equal to the distance between the second effective light-emitting area 1224 and the third effective light-emitting area 1234.
  • the display substrate 1000 when the display substrate 1000 is applied to a display device, and the display device further includes a color filter substrate 2000 disposed on the light-emitting side of the display substrate 1000, as shown in FIG.
  • the display substrate 1000 is The thickness of the retaining wall 160 is relatively thick (its thickness can reach 11.4 ⁇ m), so that the first light-emitting device 121, the second light-emitting device 122, and the third light-emitting device 123 are far away from the color film layer 210 in the color film substrate 2000 As a result, the light emitted by the first light emitting device 121, the second light emitting device 122, and the third light emitting device 123 has a longer path to reach the color film layer 210. Based on this, as shown in FIG. 4, taking three adjacent light-emitting devices as an example, part of the light (the straight dashed line in FIG.
  • emitted by the second light-emitting device 122 may hit the first color in the color film layer.
  • part of the light emitted by the first light-emitting device 121 may hit the second color filter unit 212, and part of the light emitted by the third light-emitting device 123 may hit To the second color filter unit 212.
  • the transmittance of other light except for its own color light is different. When a certain color filter unit has a higher transmittance for other colors of light, It will cause color mixing problems and affect the display quality of the display device.
  • the first effective light-emitting area 1214 and the second effective light-emitting area 1224 in the pixel unit P are arranged at intervals along the first direction X, and the third effective light-emitting area 1234 and the first effective light-emitting area 1234
  • the light emitting area 1214 and the second effective light emitting area 1224 are spaced along the second direction Y.
  • the minimum distance between the first effective light emitting area 1214 and the second effective light emitting area 1224 is smaller than the minimum distance between the third effective light emitting area 1234 and the first effective light emitting area 1214 and the second effective light emitting area 1224, respectively.
  • the filter unit of a certain color has a higher transmittance to light of other colors except its own color light
  • the luminous color and the filter unit ’s
  • the light-emitting device with the same color is used as the third light-emitting device 123, which can reduce the light of other colors from reaching the color filter unit.
  • the minimum distance between the first effective light-emitting area 1214 and the second effective light-emitting area 1224 is about 10-20 ⁇ m.
  • the minimum distance between the first effective light-emitting area 1214 and the second effective light-emitting area 1224 is 10 ⁇ m, 11 ⁇ m, 12 ⁇ m, 13 ⁇ m, 15 ⁇ m, 17 ⁇ m, 20 ⁇ m.
  • the minimum distance between the third effective light-emitting area 1234 and the first effective light-emitting area 1214 and the second effective light-emitting area 1224 along the second direction Y is about 20-25 ⁇ m.
  • the third effective light-emitting area 1234 and the first effective light-emitting area 1214 and the second The minimum distance between the two effective light-emitting areas 1224 is 20 ⁇ m, 21 ⁇ m, 22 ⁇ m, 23 ⁇ m, 24 ⁇ m, 25 ⁇ m.
  • the minimum distance between the first effective light emitting area 1214 and the second effective light emitting area 1224 is 10 ⁇ m
  • the minimum distance between the third effective light emitting area 1234 and the first effective light emitting area 1214 and the second effective light emitting area 1224 is about 20 ⁇ m. .
  • the third light emitting device 123 is configured to emit green light
  • the first light emitting device 121 and the second light emitting device 122 are configured to emit red and blue light, respectively.
  • the transmittance of the green filter unit of the color film layer 210 through other light except green light is relative to the transmittance of the red filter unit through other light except red light and the blue filter unit
  • the transmittance of other light except blue light is relatively high, so when red light and blue light hit the green filter unit, part of the red light and blue light will pass through the green filter unit.
  • the third light-emitting device 123 in the pixel unit P is configured to emit green light, and along the second direction Y, the third effective light-emitting area 1234 and the first effective light-emitting area 1214 are
  • the second effective light-emitting area 1224 has a relatively large interval, thereby reducing the red and blue light emitted by the first light-emitting device 121 and the second light-emitting device 122 from reaching the green filter unit, thereby improving the color mixing problem.
  • the pixel unit P further includes a plurality of pixel driving circuits 100.
  • the first anode 1211, the second anode 1221, and the third anode 1231 in the pixel unit P are respectively connected to a corresponding pixel driving circuit 100, and the pixel driving circuit 100 is configured to drive the corresponding light emitting device to emit light.
  • Each pixel driving circuit 100 includes, for example, a plurality of transistors and storage capacitors.
  • the pixel driving circuit 100 in FIG. 1B only illustrates one transistor, but in the embodiment of the present disclosure, the pixel driving circuit may include multiple transistors.
  • the display area DA includes a plurality of pixel areas P', and the area where each pixel unit P is located is a pixel area P'.
  • the pixel area P' includes a first sub-area 131, a second sub-area 132, and a third sub-area 133 arranged in sequence along the first direction X, the first sub-area 131, the second sub-area 132, and the The pixel driving circuit 100 is provided in each of the third sub-regions 133.
  • the first anode 1211 is located in the first sub-region 131 and the second sub-region 132 and is connected to the pixel driving circuit 100 disposed in the second sub-region 132.
  • the second anode 1221 is located at least in the third sub-region 133 and is connected to the pixel driving circuit 100 disposed in the third sub-region 133.
  • the third anode 1231 is located in the first sub-region 131, the second sub-region 132 and the third sub-region 133 and is connected to the pixel driving circuit 100 provided in the first sub-region 131.
  • the second anode 1221 also extends into the second sub-region 133.
  • the first effective light-emitting area 1214 and the second effective light-emitting area 1224 are symmetrically distributed with respect to the central axis of the third effective light-emitting area 1234 along the second direction Y.
  • the pixel units P of the display substrate 1000 can be more symmetrical, which is beneficial to the uniformity of light emission of the display substrate 1000.
  • the first anode 1211 is connected to the pixel driving circuit 100 disposed in the second sub-region 132 through the first via hole V1
  • the second anode 1221 is connected to the third
  • the pixel driving circuit 100 in the sub-region 133 is connected through a second via V2
  • the third anode 1231 is connected to the pixel driving circuit 100 disposed in the first sub-region 131 through a third via V3.
  • the orthographic projection of the first via hole V1, the second via hole V2, and the third via hole V3 on the first substrate 10 are located in the third effective light-emitting area 1234, the first effective light-emitting area 1214, and the second effective light-emitting area 1224 is between the orthographic projections on the first substrate 10.
  • the geometric centers of the orthographic projection of the first via V1, the second via V2, and the third via V3 on the first substrate 10 are on the same straight line along the first direction X.
  • the display substrate 1000 further includes a plurality of first data lines DL1, a plurality of second data lines DL2, and a plurality of third data lines DL3 disposed on the first substrate 10. And the plurality of first data lines DL1, the plurality of second data lines DL2, and the plurality of third data lines DL3 all extend along the second direction Y.
  • a first data line DL1 and a second data line DL2 are arranged between the first sub-region 131 and the second sub-region 132, and the first data line DL1 is connected to the pixel driving circuit 100 located in the first sub-region 131, The second data line DL2 is connected to the pixel driving circuit 100 located in the second sub-region 132.
  • a third data line DL3 is provided between the second sub-region 132 and the third sub-region 133, and the third data line DL3 is connected to the pixel driving circuit 100 located in the third sub-region 133.
  • the first data line DL1, the second data line DL2, and the third data line DL3 are respectively connected to the pixel driving circuit 100 in a corresponding subarea, and are respectively used to provide data signals to the pixel driving circuit 100 connected to each other, thereby controlling and
  • the light emitting device connected to each pixel driving circuit 100 has a light emission intensity.
  • the first data line DL1, the second data line DL2, and the third data line DL3 are also connected to, for example, a source driving chip.
  • the source driving chip is used to connect the first data line DL1, the second data line DL2, and the third The data line DL3 provides data signals.
  • the first data line DL1 connected to the pixel driving circuit 100 in the first sub-region 131 and the second data line connected to the pixel driving circuit 100 in the second sub-region 132 DL2 is disposed between the first sub-region 131 and the second sub-region 132
  • the third data line DL3 connected to the pixel driving circuit 100 in the third sub-region 133 is disposed between the second sub-region 132 and the third sub-region 133
  • it is convenient for the first data line DL1, the second data line DL2, and the third data line DL3 to be respectively connected to the corresponding pixel driving circuit 100, which facilitates wiring and avoids that there are many cross-line connections when the display substrate 1000 is made. The process is complicated.
  • the display substrate 1000 further includes a plurality of first gate lines GL1, a plurality of first voltage lines PL1, and a plurality of second voltage lines PL2 disposed on the first substrate 10.
  • the plurality of first gate lines GL1 all extend in the first direction X
  • the plurality of first voltage lines PL1 and the plurality of second voltage lines PL2 all extend in the second direction Y.
  • the first gate line GL1 is used to provide a first scan signal to the plurality of pixel driving circuits 100.
  • each first gate line GL1 corresponds to a row of pixel units P
  • the first gate line GL1 is used to provide a corresponding row of pixel units P.
  • the pixel driving circuit 100 in provides a first scan signal.
  • the first voltage line PL1 and the second voltage line PL2 are used to provide a first voltage and a second voltage to the plurality of pixel driving circuits 100, respectively.
  • every two adjacent pixel units P are a pixel group PG, and the two pixel units P of each pixel group PG are the first pixel units.
  • a second voltage line PL2 is provided between the first pixel unit P1 and the second pixel unit P2 in the pixel group PG.
  • a first voltage line PL1 is provided between two adjacent pixel groups PG.
  • each first voltage line PL1 is connected to a plurality of pixel driving circuits 100 of the second pixel unit P2 in one pixel group PG of two adjacent pixel groups PG, and is connected to the other pixel group PG A plurality of pixel driving circuits 100 of the first pixel unit P1 in P1 are connected. In this way, the number of first voltage lines PL1 in the display substrate 1000 can be reduced, thereby simplifying the production process.
  • the display substrate 1000 further includes a plurality of first auxiliary patterns AL1 disposed on the first substrate 10.
  • the plurality of first auxiliary patterns AL1 extend along the first direction X, and each first auxiliary pattern AL1
  • the pattern AL1 is connected to a first voltage line PL1.
  • One first auxiliary pattern AL1 is connected, and is connected to one first voltage line PL1 through the first auxiliary pattern AL1. In this way, it can avoid that there are many cross-line connections between the pixel driving circuit 100 and the first voltage line PL1, resulting in complicated processes.
  • the pixel driving circuit 100 includes a first transistor T1, a driving transistor Td, and a storage capacitor Cst.
  • the pixel driving circuit has a 2T1C (2 transistors and 1 capacitor) structure.
  • the driving transistor Td is used to drive the light emitting device to emit light, and generally, the width-to-length ratio of its channel is larger than that of the other transistors.
  • the storage capacitor Cst includes a first storage electrode C1 and a second storage electrode C2. As shown in FIG. 8, the opposing portion of the first storage electrode C1 and the second storage electrode C2 forms a storage capacitor Cst.
  • the orthographic projection of all the storage capacitors Cst in the pixel unit P on the first substrate 10 is located in the third effective light-emitting area 1234 and the first effective light-emitting area 1214 and the second effective light-emitting area 1224 are on the first substrate. Between the orthographic projections on the bottom 10.
  • the gate of the first transistor T1 is connected to a first gate line GL1 corresponding to the pixel driving circuit 100.
  • the gate of the first transistor T1 is served by the corresponding first gate line GL1, which can simplify the production process.
  • the first electrode of the first transistor T1 located in the first sub-region 131 is connected to the first data line DL1
  • the first electrode of the first transistor T1 located in the second sub-region 132 is connected to the second data line DL2.
  • the first electrode of the first transistor T1 located in the third sub-region 133 is connected to the third data line DL3.
  • the second electrode of the first transistor T1 is connected to the gate of the driving transistor Td.
  • the first gate line GL1 inputs the first scan signal, and the first transistor T1 is turned on.
  • the data signal on the first data line DL1 is input to the gate of the driving transistor Td through the first transistor T1, the first voltage line PL1, the first light emitting device 121, and the second voltage line PL2 are connected, and the first voltage line PL1
  • the first voltage is provided, and the second voltage line PL2 provides the second voltage, so that the driving transistor Td outputs a driving current, so that the first light-emitting device 121 emits light under the action of the driving current.
  • the voltage signal on the first data line DL1 charges the storage capacitor Cst connected to the first transistor T1 that is turned on.
  • the electric energy stored in the storage capacitor Cst is used to drive the transistor Td. Keep it on to maintain the time required for one frame of screen display.
  • the active pattern 102 of the first transistor T1 is disposed on the side of the gate 104 close to the first substrate 10.
  • a gate insulating pattern 103 is provided between the active pattern 102 of the first transistor T1 and the gate 104 of the first transistor T1.
  • the pixel unit P also includes an interlayer dielectric layer 105.
  • the first electrode 1061 and the second electrode 1062 and the gate 104 of the first transistor T1 are located on both sides of the interlayer dielectric layer 105.
  • the first electrode 1061 and the second electrode 1062 of the first transistor T1 are in contact with the active pattern 102 through via holes penetrating the interlayer dielectric layer 105 respectively.
  • the interlayer dielectric layer 105 in all the pixel units P is an integral structure.
  • the pixel unit P further includes a buffer layer 101, the active pattern 102 of the first transistor T1 is located between the buffer layer 101 and the first substrate 10, and the buffer layer 101 is used to prevent Impurities in the first substrate 10 diffuse to the active pattern 102 of the first transistor T1, and affect the performance of the transistor.
  • the pixel unit P further includes a passivation layer 107 and a flattening layer 108.
  • the passivation layer 107 is disposed on the side of the first electrode 1061 and the second electrode 1062 of the first transistor T1 away from the first substrate 10.
  • the flattening layer 108 is provided between the passivation layer 107 and the first anode 1211.
  • the passivation layer 107 in all pixel units P is an integrated structure
  • the flat layer 108 in all pixel units P is an integrated structure.
  • the material of the buffer layer 101, the gate insulating pattern 103, the interlayer dielectric layer 105 and the passivation layer 107 is, for example, at least one of silicon oxide (SiOx) or silicon nitride (SiNx).
  • the material of the flat layer 108 is, for example, silicone.
  • the first pole of the driving transistor Td is connected to the first voltage line PL1 corresponding to the pixel driving circuit 100.
  • the first pole of the driving transistor Td may be directly connected to a corresponding first voltage line PL1, or may also be connected to a first voltage line PL1 through the first auxiliary pattern AL1.
  • the second electrode of the driving transistor Td is connected to the first storage electrode C1.
  • the second storage electrode C2 is connected to the gate of the driving transistor Td.
  • the first storage electrode C1 of the storage capacitor Cst located in the first sub-region 131 is connected to the third anode 1231 through the third via hole V3, and the storage capacitor Cst located in the second sub-region 132
  • the first storage electrode C1 is connected to the first anode 1211 through the first via hole V1
  • the first storage electrode C1 of the storage capacitor Cst in the third subregion 133 is connected to the second anode 1221 through the second via hole V2.
  • the first cathode 1213, the second cathode 1223, and the third cathode 1233 are connected to a second voltage line PL2 through at least one fourth via V4.
  • the first cathode 1213, the second cathode 1223, and the third cathode 1233 form an integrated cathode layer 1230, and the cathode layer 1230 is connected to a second voltage line PL2 through at least one fourth via V4 .
  • the active pattern 102 of the driving transistor Td is disposed on the side of the gate 104 of the driving transistor Td close to the first substrate 10.
  • a gate insulating pattern 103 is provided between the active pattern 102 of the driving transistor Td and the gate 104 of the driving transistor Td.
  • the first electrode 1061 and the second electrode 1062 of the driving transistor Td are in contact with the active pattern 102 through via holes penetrating the interlayer dielectric layer 105 respectively.
  • the first electrode 1061 is one of the source and drain of the transistor
  • the second electrode 1062 is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode 1061 and the first electrode of the transistor in the embodiment of the present disclosure
  • the second pole 1062 may be indistinguishable in structure.
  • the first storage electrode C1 and the first electrode 1061 and the second electrode 1062 of the driving transistor Td are arranged in the same layer, and are made of the same material. In this way, the first storage electrode C1 and the first electrode 1061 and the second electrode 1062 of the driving transistor Td can be made by the same process, which can simplify the production process and reduce the production cost.
  • the first electrode 1061 and the second electrode 1062 of the first transistor T1 can also be arranged in the same layer as the first electrode 1061 and the second electrode 1062 of the driving transistor Td.
  • the gate of the first transistor T1 and the gate of the driving transistor Td are arranged in the same layer.
  • the active pattern of the first transistor T1 and the active pattern of the driving transistor Td are arranged in the same layer.
  • the second storage electrode C2 and the active pattern 102 of the driving transistor Td are arranged in the same layer.
  • the active pattern 102 is made of indium gallium zinc oxide (IGZO), and the second storage electrode C2 is obtained by conducting indium gallium zinc oxide.
  • the indium gallium zinc oxide may be implanted by ion implantation.
  • Zinc is conductive, and the ions can be boron ions or phosphorus ions.
  • the second storage electrode C2 and the active pattern 102 of the driving transistor Td can be made by the same process, which can simplify the production process and reduce the production cost.
  • the pixel defining layer 109 is disposed on the side of the flat layer 108 away from the first substrate 10.
  • the edge portion of the third anode 1231 of the third light-emitting device 123 is disposed between the flat layer 108 and the pixel defining layer 109, and the third anode 1231 passes through the flat layer 108.
  • At least one third via V3 of the passivation layer 107 is connected to the first storage electrode C1.
  • the edge portion of the second anode 1231 in the second light emitting device 122 is also disposed between the flat layer 108 and the pixel defining layer 109.
  • the first via hole V1 is used to connect the first anode 1211 of the first light emitting device 121 to the first storage electrode C1 in the corresponding storage capacitor Cst
  • the second via hole V2 is used to connect the second anode 1221 of the second light emitting device 122 to the The first storage electrode C1 in the corresponding storage capacitor Cst
  • the third via hole V3 is used to connect the third anode 1231 of the third light emitting device 123 with the first storage electrode C1 in the corresponding storage capacitor Cst.
  • the area on the flat layer 108 where the first via V1, the second via V2, or the third via V3 is located is compared
  • the flatness of the area without via holes is poor, which will affect the production and display of the light emitting device.
  • the orthographic projection of all the storage capacitors Cst in the pixel unit P on the first substrate 10 is located in the third effective light-emitting area 1234 and the first effective light-emitting area 1214 and the second effective light-emitting area 1224 are located in the second Between the orthographic projections on a substrate 10, the first via hole V1 of the first storage electrode C1 in the first storage electrode C1 used to connect the first anode 1211 of each first light emitting device 121 and its corresponding storage capacitor Cst is used to connect the second The second anode 1221 of the light emitting device 122 and the second via hole V2 of the first storage electrode C1 in the corresponding storage capacitor Cst are used to connect the third anode 1231 of the third light emitting device 123 with the first storage in the corresponding storage capacitor Cst.
  • the pixel driving circuit 100 further includes a second transistor T2.
  • the display substrate 1000 further includes a plurality of second gate lines GL2 and a plurality of sensing signal lines SL, the plurality of second gate lines GL2 extending in the first direction X, and the plurality of sensing signal lines SL extending in the second direction.
  • the gate of the second transistor T2 is connected to a corresponding second gate line GL2, the first electrode of the second transistor T2 is connected to a corresponding sensing signal line SL, and the second transistor T2 The electrode is connected to the first storage electrode C1.
  • the pixel driving circuit has a 3T1C (3 transistors and 1 capacitor) structure. Taking the pixel driving circuit 100 corresponding to the first light-emitting device 121 as an example, the driving circuit structure diagram is shown in FIG. 15.
  • the sensing signal line SL is used to sense electrical signals in the pixel driving circuit 100. As shown in FIG. 15, during signal sensing, the first gate line GL1 inputs the first scan signal, and the first transistor T1 is turned on. At the same time, the second gate line GL2 inputs the second scan signal, and the second transistor T2 is turned on.
  • the data line DL1 provides a data signal to the first node G through the first transistor T1, and the sensing signal line SL senses the voltage transmitted to the second node S through the second transistor T2. When the voltage of the second node S is stable, it is compared The data signal and the voltage of the second node S can obtain the threshold voltage of the driving transistor Td. In this way, the threshold voltage of the driving transistor Td can be externally compensated, thereby avoiding the uneven display caused by the drift of the threshold voltage of the driving transistor Td due to material, process and other reasons.
  • a sensing signal line SL is provided between the first pixel unit P1 and the second pixel unit P2 in the pixel group PG.
  • the sensing signal line SL is connected to the pixel driving circuit 100 in the first pixel unit P1 and the pixel driving circuit 100 in the second pixel unit P2 in the corresponding pixel group PG.
  • the orthographic projection of the second light-emitting device 122 in the first pixel unit P1 of the pixel group PG on the first substrate 10 and the second voltage line PL2 And the orthographic projection of the sensing signal line SL on the first substrate 10 has an overlapping area.
  • the orthographic projection of the second light emitting device 122 in the second pixel unit P2 of the pixel group PG on the first substrate 10 and the orthographic projection of the first voltage line PL1 on the first substrate 10 have an overlapping area.
  • the display substrate 1000 further includes a plurality of second auxiliary patterns AL2 disposed on the first substrate 10.
  • the plurality of second auxiliary patterns AL2 extend along the first direction X, each The second auxiliary pattern AL2 is connected to one sensing signal line SL.
  • All the pixel driving circuits 100 in each pixel group PG are connected to one second auxiliary pattern AL2, and are connected to one sensing signal line SL through the second auxiliary pattern AL2. This can prevent the pixel driving circuit 100 and the sensing signal line SL from having more cross-line connections, resulting in complicated processes.
  • the gate of the second transistor T2 is served by the second gate line GL2 connected thereto. This can simplify the production process and save production costs.
  • the orthographic projection of the third light-emitting device 123 on the first substrate 10 and the orthographic projection of the second transistor T2 on the first substrate 10 have an overlapping area.
  • the first data lines DL1, the second data lines DL2, the third data lines DL3, the first voltage lines PL1, the second voltage lines PL2, and the The multiple sensing signal lines SL are arranged in the same layer and made of the same material. In this way, the same production process can be used, which can simplify the production process and save production costs.
  • the multiple first data lines DL1, multiple second data lines DL2, multiple third data lines DL3, multiple first voltage lines PL1, multiple second voltage lines PL2, and multiple sensing When the signal lines SL are arranged in the same layer, the first auxiliary pattern AL1 and the corresponding first voltage line PL1 are arranged in different layers, and are connected through vias; the second auxiliary pattern AL2 and the corresponding sensing signal line The SL is arranged on different layers and connected through vias. This can prevent the first auxiliary pattern AL1 from being short-circuited with the first data line DL1, the second data line DL2, and the third data line DL3, or the second auxiliary pattern AL2 and the first data line DL1, the second data line DL2, and the third data line DL2. The data line DL3 and the second voltage line PL2 are short-circuited.
  • a plurality of first data lines DL1, a plurality of second data lines DL2, a plurality of third data lines DL3, a plurality of first voltage lines PL1, a plurality of second voltage lines PL2, and a plurality of sensing signal lines SL The material includes at least one of copper element, aluminum element, silver element, copper alloy, aluminum alloy or silver alloy.
  • the display device further includes a color filter substrate 2000.
  • the color filter substrate 2000 includes a second substrate 20 and a color filter layer 210 disposed on the side of the second substrate 20 facing the first substrate 10.
  • the color film layer 210 includes a plurality of first color filter units 211, a plurality of second color filter units 212 and a plurality of third color filter units 213.
  • a black matrix 220 is arranged between two adjacent filter units.
  • the orthographic projection of each first color filter unit 211 and a corresponding first light emitting device 121 on the second substrate 20 overlaps, and each second color filter unit 212 and a corresponding second light emitting device 122 are in the first
  • the orthographic projections on the two substrates 20 overlap, and the orthographic projections of each third color filter unit 213 and a corresponding third light emitting device 123 on the second substrate 20 overlap.
  • the second substrate 20 is cover glass.
  • the black matrix 220 is provided with a buffer glue layer 230 facing the display substrate 1000 side, and the buffer glue layer 230 is provided with a post spacer (PS) 240 facing the display substrate 1000 side.
  • the isolation column 240 is used to prevent the display device from deforming when subjected to external pressure, which affects the display effect.
  • the buffer glue layer 230 can play a buffering role when the display device is subjected to external pressure.
  • the display device further includes a filler 3000 disposed between the display substrate 1000 and the color filter substrate 2000.
  • the filler 3000 is filled between the display substrate 1000 and the color filter substrate 2000.
  • the filler 3000 can relieve the external pressure of the display device, prevent the display device from being damaged by pressure, and can further isolate water and oxygen.
  • the above-mentioned display devices include televisions, mobile phones, display panels and the like.

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Abstract

一种显示基板，包括：第一衬底以及设置于该第一衬底上且呈多行和多列排布的多个像素单元。多个像素单元中的一个像素单元包括多个发光器件。多个发光器件包括第一发光器件、第二发光器件和第三发光器件。第一发光器件包括的第一有效发光区和第二发光器件包括的第二有效发光区沿第一方向间隔排布，第三发光器件包括的第三有效发光区与第一有效发光区和第二有效发光区沿第二方向间隔，且第一有效发光区和第二有效发光区的最小间距分别小于第三有效发光区与第一有效发光区和第二有效发光区的最小间距；第一方向与多个像素单元的行方向平行，第二方向与多个像素单元的列方向平行。

Description

显示基板和显示装置
本申请要求于2019年05月22日提交的、申请号为201910431419.5的中国专利申请的优先权和权益，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
主动矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示面板，因具有高对比度、可视角度广以及响应速度快等优点，有望取缔液晶显示面板，成为下一代显示器的主流选择。其中，顶发射结构的有机发光二极管显示面板具有较高的开口率，更加适用于高分辨率产品，适应市场潮流，得到广泛应用。
发明内容
一方面，本公开实施例提供一种显示基板，包括：第一衬底以及设置于所述第一衬底上的多个像素单元。所述多个像素单元呈多行和多列排布；所述多个像素单元中的一个像素单元，具有第一有效发光区、第二有效发光区和第三有效发光区；所述像素单元包括：多个发光器件。所述多个发光器件包括第一发光器件、第二发光器件和第三发光器件，所述第一发光器件、所述第二发光器件和所述第三发光器件分别包括所述第一有效发光区、所述第二有效发光区和所述第三有效发光区，且用于发出三基色的光。所述第一有效发光区和所述第二有效发光区沿第一方向间隔排布，所述第三有效发光区与所述第一有效发光区和所述第二有效发光区沿第二方向间隔，且所述第一有效发光区和所述第二有效发光区的最小间距分别小于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区的的最小间距；所述第一方向与所述多个像素单元的行方向平行，所述第二方向与所述多个像素单元的列方向平行。
在一些实施例中，所述第一有效发光区和所述第二有效发光区的最小间距约为10～20μm，所述第三有效发光区与所述第一有效发光区和所述第二有效发光区的最小间距约为20～25μm。
在一些实施例中，所述第三发光器件被配置为发出绿色光；所述第一颜色发光器件和所述第二颜色发光器件分别被配置为发出红色和蓝色 的光。
在一些实施例中，所述第一发光器件包括第一阳极、第一发光功能层和第一阴极，所述第二发光器件包括第二阳极、第二发光功能层和第二阴极，所述第三发光器件包括第三阳极、第三发光功能层和第三阴极。所述像素单元还包括多个像素驱动电路，所述第一阳极、所述第二阳极和所述第三阳极分别与对应的一个像素驱动电路连接，所述像素驱动电路配置为驱动对应的发光器件发光。所述像素驱动电路包括存储电容；所述像素单元中的所有存储电容在所述第一衬底上的正投影位于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区在所述第一衬底上的正投影之间。
在一些实施例中，所述显示基板具有显示区；所述显示区包括多个像素区，每个像素单元所在的区域为一个像素区。所述像素区包括沿第一方向依次排布的第一子区、第二子区和第三子区，所述第一子区、所述第二子区和所述第三子区中的每个子区中均设置有所述像素驱动电路。所述第一阳极位于所述第一子区和所述第二子区中并与设置于所述第二子区中的像素驱动电路连接；所述第二阳极至少位于所述第三子区中且与设置于所述第三子区中的像素驱动电路连接；所述第三阳极位于所述第一子区、所述第二子区和所述第三子区中，且与设置于所述第一子区中的像素驱动电路连接。
在一些实施例中，所述第二阳极还延伸至所述第二子区中。
在一些实施例中，所述第一阳极与设置于所述第二子区中的像素驱动电路通过第一过孔连接，所述第二阳极与设置于所述第三子区中的像素驱动电路通过第二过孔连接，所述第三阳极与设置于所述第一子区中的像素驱动电路通过第三过孔连接；所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影位于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区在所述第一衬底上的正投影之间。
在一些实施例中，所述像素单元中的所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影的几何中心处于沿所述第一方向的同一直线上。
在一些实施例中，所述显示基板还包括：设置于所述第一衬底上的多条第一数据线、多条第二数据线和多条第三数据线，且多条第一数据线、多条第二数据线和多条第三数据线均沿所述第二方向延伸。所述第一子区和所述第二子区之间设置有一条第一数据线和一条第二数据线， 且所述第一数据线与位于所述第一子区中的像素驱动电路连接，所述第二数据线与位于所述第二子区中的像素驱动电路连接；所述第二子区和所述第三子区之间设置有一条第三数据线，所述第三数据线与位于所述第三子区中的像素驱动电路连接。
在一些实施例中，所述显示基板还包括多条第一栅线、多条第一电压线和多条第二电压线。所述多条第一栅线均沿所述第一方向延伸，所述多条第一电压线和所述多条第二电压线均沿所述第二方向延伸。所述像素驱动电路包括第一晶体管、驱动晶体管和存储电容。所述存储电容包括第一存储电极和第二存储电极。所述第一晶体管的栅极与所述像素驱动电路对应的一条第一栅线连接；位于所述第一子区的所述第一晶体管的第一极与所述第一数据线连接，位于所述第二子区的所述第一晶体管的第一极与所述第二数据线连接，位于所述第三子区的所述第一晶体管的第一极与所述第三数据线连接；所述第一晶体管的第二极与所述驱动晶体管的栅极连接。所述驱动晶体管的第一极与所述像素驱动电路对应的一条第一电压线连接，所述驱动晶体管的第二极与所述第一存储电极连接；位于所述第一子区的所述存储电容的第一存储电极通过所述第三过孔与所述第三阳极连接；位于所述第二子区的所述存储电容的第一存储电极通过所述第一过孔与所述第一阳极连接，位于所述第三子区的所述存储电容的第一存储电极通过所述第二过孔与所述第二阳极连接。所述第一阴极、所述第二阴极和所述第三阴极与一条第二电压线通过至少一个第四过孔连接。所述第二存储电极与所述驱动晶体管的栅极连接；所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影分别与其对应的存储电容在所述第一衬底上的正投影重叠。
在一些实施例中，所述驱动晶体管还包括有源图案，所述有源图案设置于所述驱动晶体管的栅极靠近所述第一衬底的一侧。所述第一存储电极与所述驱动晶体管的第一极和第二极同层设置；所述第二存储电极与所述驱动晶体管的有源图案同层设置。
在一些实施例中，所述第一晶体管的栅极由对应的所述第一栅线充当。
在一些实施例中，沿所述第一方向，每相邻的两个像素单元为一个像素组，每个像素组的两个像素单元分别为第一像素单元和第二像素单元。所述像素组中的所述第一像素单元和所述第二像素单元之间设置有一条第二电压线；沿所述第一方向，相邻两个像素组之间设置有一条第 一电压线。
在一些实施例中，所述像素驱动电路还包括第二晶体管。所述显示基板还包括多条第二栅线和多条感测信号线；所述多条第二栅线沿所述第一方向延伸，所述多条感测信号线沿所述第二方向延伸。所述像素组中的所述第一像素单元和所述第二像素单元之间设置有一条感测信号线。所述第二晶体管的栅极与对应的一条第二栅线连接；所述第二晶体管的第一极与对应的一条感测信号线连接，所述第二晶体管的第二极与所述第一存储电极连接。
在一些实施例中，所述第二晶体管的栅极由与其连接的第二栅线充当。
在一些实施例中，所述第三发光器件在所述第一衬底上的正投影与所述第二晶体管在所述第一衬底上的正投影具有重叠区域。
在一些实施例中，位于所述像素组的所述第一像素单元中的所述第二发光器件在所述第一衬底上的正投影与所述第二电压线和所述感测信号线在所述第一衬底上的正投影具有重叠区域；位于所述像素组的所述第二像素单元中的所述第二发光器件在所述第一衬底上的正投影与所述第一电压线在所述第一衬底上的正投影具有重叠区域。
在一些实施例中，所述多条第一数据线、所述多条第二数据线、所述多条第三数据线、所述多条第一电压线、所述多条第二电压线和所述多条感测信号线同层设置。
在一些实施例中，所述第一有效发光区与所述第二有效发光区关于所述第三有效发光区的沿所述第二方向的中心轴对称分布。
另一方面，本公开实施例提供一种显示装置，包括上述显示基板，还包括彩膜基板。彩膜基板包括第二衬底和设置于所述第二衬底朝向所述第一衬底一侧的彩膜层。所述彩膜层包括多个第一颜色滤光单元、多个第二颜色滤光单元和多个第三颜色滤光单元；相邻的两个滤光单元之间设置有黑矩阵；每个第一颜色滤光单元和对应的一个第一发光器件在所述第二衬底上的正投影重叠，每个第二颜色滤光单元和对应的一个第二发光器件在所述第二衬底上的正投影重叠，每个第三颜色滤光单元和对应的一个第三发光器件在所述第二衬底上的正投影重叠。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施 例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为本公开实施例提供的一种显示基板的俯视结构图；
图1B为本公开实施例提供的一种显示基板的结构图；
图2A为本公开实施例提供的一种显示装置的俯视结构图；
图2B为本公开实施例提供的一种显示装置的结构图；
图3为相关技术提供的一种显示装置的俯视结构图；
图4为相关技术提供的一种显示装置沿图3中B-B’方向的剖视结构图；
图5A为本公开实施例提供的一种显示基板的俯视结构图；
图5B为本公开实施例提供的一种显示基板的像素区的俯视结构图；
图5C为本公开实施例提供的另一种显示基板的像素区的俯视结构图；
图6为本公开实施例提供的又一种显示基板的像素区的俯视结构图；
图7为本公开实施例提供的又一种显示基板的像素区的俯视结构图；
图8为本公开实施例提供的一种显示基板的俯视结构图；
图9为本公开实施例提供的另一种显示基板的俯视结构图；
图10为本公开实施例提供的一种显示基板的像素驱动电路的结构图；
图11为本公开实施例提供的一种像素区的第一子区的俯视结构图；
图12为图11沿C-C’方向的剖视结构图；
图13为图11沿D-D’方向的剖视结构图；
图14为本公开实施例提供的又一种显示基板的俯视结构图；和
图15本公开实施例提供的另一种显示基板的像素驱动电路的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
本公开的一些实施例提供一种显示装置，该显示装置例如为显示面板、手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等。如图1A和图1B所示，该显示装置包括显示基板1000。
如图1A所示，显示基板1000具有显示区DA和周边区S，周边区S例如围绕显示区DA一周设置。周边区S用于布线，此外，也可以设置至少一个驱动电路(如栅极驱动电路等)。
如图1A所示，显示基板1000包括第一衬底10，以及设置于第一衬底10上且位于显示区DA内的多个像素单元P，该多个像素单元P呈多行和多列排布。该多个像素单元P中的一个像素单元P包括多个发光器件。示例地，每个像素单元P包括多个发光器件。
如图1B所示，该像素单元P具有第一有效发光区1214、第二有效发光区1224和第三有效发光区1234。该多个发光器件包括第一发光器件121、第二发光器件122和第三发光器件123，第一发光器件121、第二发光器件122和第三发光器件123分别包括第一有效发光区1214、第二有效发光区1224和 第三有效发光区1234。
第一发光器件121、第二发光器件122和第三发光器件123用于发出三基色的光。
示例地，第一发光器件121、第二发光器件122和第三发光器件123发出的三基色的光分别为红色光、绿色光和蓝色光。或者，在一些实施例中，第一发光器件121、第二发光器件122和第三发光器件123发出的三基色的光还可以分别为青色光、品红色光和黄色光。
在一些实施例中，如图1B所示，第一发光器件121包括第一阳极1211、第一发光功能层1212和第一阴极1213；第二发光器件122包括第二阳极1221、第二发光功能层1222和第二阴极1223；第三发光器件123包括第三阳极1231、第三发光功能层1232和第三阴极1233。
如图1B所示，显示基板1000还包括像素界定层109，像素界定层109呈网格状，网格的每个开口即为一个有效发光区。也就是说，位于像素单元P所在区域的三个有效发光区分别为第一有效发光区1214、第二有效发光区1224和第三有效发光区1234
如图1A所示，第一有效发光区1214和第二有效发光区1224沿第一方向X间隔排布，第三有效发光区1234与第一有效发光区1214和第二有效发光区1224沿第二方向Y间隔，且第一有效发光区1214和第二有效发光区1224的最小间距分别小于第三有效发光区1234与第一有效发光区1214和第二有效发光区1224的最小间距。上述第一方向X与多个像素单元P的行方向平行，上述第二方向Y与多个像素单元P的列方向平行。
示例地，如图1B所示，所有像素单元P中的第一阴极1213、第二阴极1223和第三阴极1233形成一体化结构的阴极层。又示例的，所有像素单元P中的第一阳极1211、第二阳极1221和第三阳极1231同层设置，且第一阳极1211、第二阳极1221和第三阳极1231位于阳极层中。
在一些示例中，第一发光功能层1212、第二发光功能层1222和第三发光功能层1232均包括一发光层。本领域技术人员应该明白，在第一发光功能层1212、第二发光功能层1222和第三发光功能层1232的发光颜色不同的情况下，第一发光功能层1212、第二发光功能层1222和第三发光功能层1232中的发光层的材料不相同。
在另一些示例中，第一发光功能层1212、第二发光功能层1222和第三发光功能层1232除包括发光层外，还包括电子传输层(electron transporting layer，简称ETL)、电子注入层(electron injection layer，简称EIL)、空穴传输层 (hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)。以第一发光功能层1212为例，电子传输层和电子注入层设置于发光层(称为第一发光层)和第一阴极1213之间，且电子注入层相对电子传输层更靠近第一阴极1213。空穴传输层和空穴注入层设置于第一发光层和第一阳极1211之间，且空穴注入层相对空穴传输层更靠近第一阳极1211。对于第二发光功能层1222和第三发光功能层1232也是类似，在此不再赘述。
在此基础上，所有发光器件中的发光层可位于同一层。所有发光器件中的电子传输层可位于同一层，所有发光器件中的电子注入层可位于同一层，所有发光器件中的空穴传输层可位于同一层，所有发光器件中的空穴注入层可位于同一层。
该发光层例如为有机发光层，基于此，该发光器件为有机发光二极管(organic light emitting diode，OLED)。
发光器件例如为顶发光型发光器件，在此情况下，发光器件发出的光线从远离第一衬底10一侧射出。该阳极层呈不透明，例如为由一层ITO(Indium Tin Oxides，氧化铟锡)、一层银(Ag)单质、再一层ITO构成的层叠结构(即ITO/Ag/ITO)，以反射发光层发出的光线中朝向阳极层射出的部分，从而提高发光器件的出光率；该阴极层呈透明或半透明状，例如为较薄的一层银层，以透射发光层发出的光线。
在一些实施例中，如图1B所示，该显示基板100还包括位于所述显示区DA且设置于发光器件远离第一衬底10一侧的薄膜封装层150。示例的，薄膜封装层150包括层叠设置的第一无机封装层151、有机封装层152和第二无机封装层153，有机封装层152位于第一无机封装层151和第二无机封装层153之间。
在一些实施例中，如图1B所示，该显示基板100还包括位于周边区S且围绕显示区DA一圈设置的挡墙160。由于在制备薄膜封装层150的过程中，有机材料具有一定的流动性，因此为了便于采用该有机材料制备有机封装层，通过设置挡墙160来拦截有机材料向显示基板1000的边缘一侧流动。此外，挡墙160还起到阻隔水氧的作用，防止环境中水氧从显示基板1000的侧面进入到显示区DA中。
相关技术中，如图3所示，显示基板1000中的第一有效发光区1214、第二有效发光区1224和第三有效发光区1234沿第一方向X依次且周期性排布，且第一有效发光区1214和第二有效发光区1224的间距与第二有效发光区1224和第三有效发光区1234的间距相等。如图3所示，在该显示基板1000 应用于显示装置，且该显示装置还包括设置于该显示基板1000出光侧的彩膜基板2000的情况下，如图4所示，由于显示基板1000上的挡墙160的厚度较厚(其厚度可达到11.4μm)，使得第一发光器件121、第二发光器件122和第三发光器件123与彩膜基板2000中的彩膜层210的距离较远，导致第一发光器件121、第二发光器件122和第三发光器件123发出的光线到达彩膜层210所经过的路径较长。基于此，如图4所示，以相邻的三个发光器件为例，第二发光器件122发出的光线(图4中的直虚线)中部分光线可能会射到彩膜层中第一颜色滤光单元211和第三颜色滤光单元213，第一发光器件121发出的光线中部分光线可能会射到第二颜色滤光单元212，第三发光器件123发出的光线中部分光线可能会射到第二颜色滤光单元212。而对于彩膜层210中不同颜色的各个滤光单元对于除其本身颜色光外的其他光的透过率不同，当某一颜色的滤光单元对于其他颜色光的透过率较高时，则会造成混色问题，影响显示装置的显示品质。
在本公开一些实施例提供的显示基板1000中，像素单元P中的第一有效发光区1214和第二有效发光区1224沿第一方向X间隔排布，第三有效发光区1234与第一有效发光区1214和第二有效发光区1224沿第二方向Y间隔。第一有效发光区1214和第二有效发光区1224的最小间距分别小于第三有效发光区1234与第一有效发光区1214和第二有效发光区1224的最小间距。这样一来，在该显示基板1000应用于显示装置，且某一颜色的滤光单元对于除其本身颜色光外的其他颜色光的透过率较高时，将发光颜色与该滤光单元的颜色相同的发光器件作为第三发光器件123，可以减少其他颜色光射到该颜色滤光单元。由此，通过改变像素单元P中第一发光器件121、第二发光器件122和第三发光器件123的排布方式，可改善混色问题，从而提高显示基板的显示品质。
在一些实施例中，第一有效发光区1214和第二有效发光区1224的最小间距约为10～20μm，例如第一有效发光区1214和第二有效发光区1224的最小间距为10μm，11μm，12μm，13μm，15μm，17μm，20μm。第三有效发光区1234与第一有效发光区1214和第二有效发光区1224沿第二方向Y的最小间距约为20～25μm，例如第三有效发光区1234与第一有效发光区1214和第二有效发光区1224的最小间距为20μm，21μm，22μm，23μm，24μm，25μm。
在一些示例中，第一有效发光区1214和第二有效发光区1224的最小间距为10μm，第三有效发光区1234与第一有效发光区1214和第二有效发光区1224的最小间距约为20μm。
在一些实施例中，第三发光器件123被配置为发出绿色光，第一发光器件121和第二发光器件122分别被配置为发出红色和蓝色的光。
由于彩膜层210的绿色滤光单元的透过除绿光外的其他光的透过率相对于红色滤光单元的透过除红光外的其他光的透过率和蓝色滤光单元的透过除蓝光外的其他光的透过率较高，因此当红色光和蓝色光射到绿色滤光单元时，会有部分红色光和蓝色光透过绿色滤光单元。本公开一些实施例提供的显示基板1000中，像素单元P中的第三发光器件123被配置为发出绿色光，且沿第二方向Y，第三有效发光区1234与第一有效发光区1214和第二有效发光区1224的间距较大，因此减少第一发光器件121和第二发光器件122发出的红色和蓝色的光射到绿色滤光单元，从而改善混色问题。
在一些实施例中，如图1B所示，像素单元P还包括多个像素驱动电路100。该像素单元P中第一阳极1211、第二阳极1221和第三阳极1231分别与对应的一个像素驱动电路100连接，像素驱动电路100配置为驱动对应的发光器件发光。每个像素驱动电路100例如包括多个晶体管和存储电容。
需要说明的是，图1B中的像素驱动电路100仅示意了一个晶体管，但本公开实施例中，像素驱动电路可包括多个晶体管。
在一些实施例中，如图5A所示，显示区DA包括多个像素区P’，每个像素单元P所在的区域为一个像素区P’。
如图5B所示，像素区P’包括沿第一方向X依次排布的第一子区131、第二子区132和第三子区133，第一子区131、第二子区132和第三子区133中的每个子区中均设置有像素驱动电路100。
如图5B所示，第一阳极1211位于第一子区131和第二子区132中并与设置于第二子区132中的像素驱动电路100连接。第二阳极1221至少位于第三子区133中且与设置于第三子区133中的像素驱动电路100连接。第三阳极1231位于第一子区131、第二子区132和第三子区133中，且与设置于第一子区131中的像素驱动电路100连接。
在一些实施例中，如图5C所示，第二阳极1221还延伸至第二子区133中。
在一些实施例中，如图5C所示，第一有效发光区1214与第二有效发光区1224关于第三有效发光区1234的沿第二方向Y的中心轴对称分布。这样可使显示基板1000的像素单元P更加对称，有利于显示基板1000的发光均匀性。
在一些实施例中，如图5B和图5C所示，第一阳极1211与设置于第二子 区132中的像素驱动电路100通过第一过孔V1连接，第二阳极1221与设置于第三子区133中的像素驱动电路100通过第二过孔V2连接，第三阳极1231与设置于第一子区131中的像素驱动电路100通过第三过孔V3连接。该第一过孔V1、该第二过孔V2和该第三过孔V3在第一衬底10上的正投影位于第三有效发光区1234与第一有效发光区1214和第二有效发光区1224在第一衬底10上的正投影之间。
在一些实施例中，该第一过孔V1、该第二过孔V2和该第三过孔V3在第一衬底10上的正投影的几何中心处于沿第一方向X的同一直线上。
在一些实施例中，如图6所示，显示基板1000还包括设置于第一衬底10上的多条第一数据线DL1、多条第二数据线DL2和多条第三数据线DL3，且多条第一数据线DL1、多条第二数据线DL2和多条第三数据线DL3均沿第二方向Y延伸。
第一子区131和第二子区132之间设置有一条第一数据线DL1和一条第二数据线DL2，且第一数据线DL1与位于第一子区131中的像素驱动电路100连接，第二数据线DL2与位于第二子区132中的像素驱动电路100连接。第二子区132和第三子区133之间设置有一条第三数据线DL3，第三数据线DL3与位于第三子区133中的像素驱动电路100连接。
第一数据线DL1、第二数据线DL2和第三数据线DL3分别与对应的一个子区中的像素驱动电路100连接，分别用于向各自连接的像素驱动电路100提供数据信号，从而控制与各像素驱动电路100分别连接的发光器件的发光强弱。当然，第一数据线DL1、第二数据线DL2和第三数据线DL3还与例如源极驱动芯片连接，源极驱动芯片用于分别向第一数据线DL1、第二数据线DL2和第三数据线DL3提供数据信号。
本公开一些实施例提供的显示基板1000中，与第一子区131中的像素驱动电路100连接的第一数据线DL1和与第二子区132中的像素驱动电路100连接的第二数据线DL2设置于第一子区131和第二子区132之间，与第三子区133中的像素驱动电路100连接的第三数据线DL3设置于第二子区132和第三子区133之间，这样便于第一数据线DL1、第二数据线DL2和第三数据线DL3分别与其对应的像素驱动电路100连接，方便布线，避免在制作显示基板1000时存在较多的跨线连接而导致工艺复杂。
在一些实施例中，如图7所示，显示基板1000还包括设置于第一衬底10上的多条第一栅线GL1、多条第一电压线PL1和多条第二电压线PL2，多条第一栅线GL1均沿第一方向X延伸，多条第一电压线PL1和多条第二电压线 PL2均沿第二方向Y延伸。第一栅线GL1用于向多个像素驱动电路100提供第一扫描信号，例如每条第一栅线GL1对应一行像素单元P，该第一栅线GL1用于向其对应的一行像素单元P中的像素驱动电路100提供第一扫描信号。第一电压线PL1和第二电压线PL2分别用于向多个像素驱动电路100提供第一电压和第二电压。
在一些实施例中，如图9所示，沿第一方向X，每相邻的两个像素单元P为一个像素组PG，每个像素组PG的两个像素单元P分别为第一像素单元P1和第二像素单元P2。该像素组PG中的第一像素单元P1和第二像素单元P2之间设置有一条第二电压线PL2。沿第一方向X，相邻两个像素组PG之间设置有一条第一电压线PL1。
沿第一方向X，每条第一电压线PL1与相邻的两个像素组PG中的一个像素组PG中的第二像素单元P2的多个像素驱动电路100连接，与另一个像素组PG中的第一像素单元P1的多个像素驱动电路100连接。这样可以减少显示基板1000中第一电压线PL1的数量，从而简化生产工艺。
示例地，如图9所示，显示基板1000还包括设置于第一衬底10上的多个第一辅助图案AL1，多个第一辅助图案AL1沿第一方向X延伸，每个第一辅助图案AL1与一条第一电压线PL1连接。相邻的两个像素组PG中的一个像素组PG中的第二像素单元P2的多个像素驱动电路100和另一个像素组PG中的第一像素单元P1的多个像素驱动电路100，与一个第一辅助图案AL1连接，通过该第一辅助图案AL1与一条第一电压线PL1连接。这样可避免在像素驱动电路100与第一电压线PL1存在较多的跨线连接而导致工艺复杂。
在一些实施例中，如图8所示，像素驱动电路100包括第一晶体管T1、驱动晶体管Td和存储电容Cst。在此情况下，该像素驱动电路为2T1C(2个晶体管和1个电容)结构，以第一发光器件121对应的像素驱动电路100为例，像素驱动电路结构的等效电路如图10所示。此处，驱动晶体管Td用于驱动发光器件发光，通常，其沟道的宽长比大于其余晶体管的沟道的宽长比。
存储电容Cst包括第一存储电极C1和第二存储电极C2，如图8所示，第一存储电极C1和第二存储电极C2相对的部分形成存储电容Cst。
如图8所示，像素单元P中的所有存储电容Cst在第一衬底10上的正投影位于第三有效发光区1234与第一有效发光区1214和第二有效发光区1224在第一衬底10上的正投影之间。
第一晶体管T1的栅极与像素驱动电路100对应的一条第一栅线GL1连接。
在一些实施例中，如图8所示，第一晶体管T1的栅极由对应的第一栅线GL1充当，这样可简化生产工艺。
如图8所示，位于第一子区131的第一晶体管T1的第一极与第一数据线DL1连接，位于第二子区132的第一晶体管T1的第一极与第二数据线DL2连接，位于第三子区133的第一晶体管T1的第一极与第三数据线DL3连接。第一晶体管T1的第二极与驱动晶体管Td的栅极连接。
基于此，如图10所示，第一栅线GL1输入第一扫描信号，第一晶体管T1导通。接下来，第一数据线DL1上的数据信号通过第一晶体管T1输入到驱动晶体管Td的栅极，第一电压线PL1、第一发光器件121和第二电压线PL2连通，第一电压线PL1提供第一电压，第二电压线PL2提供第二电压，使驱动晶体管Td输出驱动电流，使第一发光器件121在驱动电流的作用下发光。在此过程中，第一数据线DL1上的电压信号向导通的第一晶体管T1所连接的存储电容Cst进行充电，当第一扫描信号关断时，利用存储电容Cst存储的电能使驱动晶体管Td保持开启，以维持一帧画面显示所需的时间。
在一些实施例中，如图11和图12所示，第一晶体管T1的有源图案102设置于栅极104靠近第一衬底10一侧。第一晶体管T1的有源图案102和第一晶体管T1的栅极104之间设置有栅绝缘图案103。该像素单元P还包括层间介质层105。第一晶体管T1的第一极1061与第二极1062和栅极104位于层间介质层105的两侧。第一晶体管T1的第一极1061和第二极1062分别通过贯穿层间介质层105的过孔与有源图案102接触。此处，可以理解的，所有像素单元P中的层间介质层105为一体结构。
在一些实施例中，如图12所示，该像素单元P还包括缓冲层101，第一晶体管T1的有源图案102位于缓冲层101和第一衬底10之间，缓冲层101用于防止第一衬底10中的杂质扩散至第一晶体管T1的有源图案102，对晶体管的性能产生影响。此外，该像素单元P还包括钝化层107和平坦层108，钝化层107设置在第一晶体管T1的第一极1061与第二极1062背离第一衬底10的一侧，平坦化层108设置在钝化层107和第一阳极1211之间。此处，所有像素单元P中的钝化层107为一体结构，所有像素单元P中的平坦层108为一体结构。
上述缓冲层101、栅绝缘图案103、层间介质层105和钝化层107的材料例如为氧化硅(SiOx)或氮化硅(SiNx)中的至少一种。平坦层108的材料例如为有机硅。
如图11所示，驱动晶体管Td的第一极与像素驱动电路100对应的第一 电压线PL1连接。示例地，驱动晶体管Td的第一极可以与对应的一条第一电压线PL1直接连接，或者也可以通过第一辅助图案AL1与一条第一电压线PL1连接。驱动晶体管Td的第二极与第一存储电极C1连接。
第二存储电极C2与驱动晶体管Td的栅极连接。
在此基础上，如图8所示，位于第一子区131的存储电容Cst的第一存储电极C1通过第三过孔V3与第三阳极1231连接，位于第二子区132的存储电容Cst的第一存储电极C1通过第一过孔V1与第一阳极1211连接，位于第三子区133的存储电容Cst的第一存储电极C1通过第二过孔V2与第二阳极1221连接。第一阴极1213、第二阴极1223、第三阴极1233与一条第二电压线PL2通过至少一个第四过孔V4连接。示例地，如图8所示，第一阴极1213、第二阴极1223、第三阴极1233形成一体结构的阴极层1230，阴极层1230与一条第二电压线PL2通过至少一个第四过孔V4连接。
在一些实施例中，如图11和图13所示，驱动晶体管Td的有源图案102设置于驱动晶体管Td的栅极104靠近第一衬底10的一侧。驱动晶体管Td的有源图案102和驱动晶体管Td的栅极104之间设置有栅绝缘图案103。驱动晶体管Td的第一极1061和第二极1062分别通过贯穿层间介质层105的过孔与有源图案102接触。
需要说明的是，本公开的实施例中，第一极1061为晶体管的源极和漏极中一者，第二极1062为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极1061和第二极1062在结构上可以是没有区别的。
在一些实施例中，如图13所示，第一存储电极C1与驱动晶体管Td的第一极1061和第二极1062同层设置，且由同种材料制成。这样，第一存储电极C1与驱动晶体管Td的第一极1061和第二极1062可以采用同一工艺制成，从而可简化生产工艺，降低生产成本。
在一些实施例中，第一晶体管T1的第一极1061与第二极1062也可以和驱动晶体管Td的第一极1061和第二极1062同层设置。第一晶体管T1的栅极和驱动晶体管Td的栅极同层设置。第一晶体管T1的有源图案和驱动晶体管Td的有源图案同层设置。
第二存储电极C2与驱动晶体管Td的有源图案102同层设置。示例地，有源图案102采用氧化铟镓锌(indium gallium zinc oxide，IGZO)制成，第二存储电极C2通过对氧化铟镓锌进行导体化得到，例如可以采用离子注入的 方式对氧化铟镓锌进行导体化，离子可以为硼离子或磷离子。本公开的一些实施例中，第二存储电极C2与驱动晶体管Td的有源图案102可以采用同一工艺制成，从而可简化生产工艺，降低生产成本。
如图13所示，像素界定层109设置在平坦层108远离第一衬底10一侧。以第三发光器件123为例，如图13所示，第三发光器件123的第三阳极1231的边缘部分设置于平坦层108和像素界定层109之间，第三阳极1231通过贯穿平坦层108和钝化层107的至少一个第三过孔V3与第一存储电极C1连接。当然，对于第一发光器件121中的第二阳极1221、第二发光器件122中的第二阳极1231的边缘部分也设置于平坦层108和像素界定层109之间。
如图8所示，第一过孔V1、第二过孔V2和第三过孔V3在第一衬底10上的正投影分别与其对应的存储电容Cst在第一衬底10上的正投影重叠。第一过孔V1用于连接第一发光器件121的第一阳极1211与其对应的存储电容Cst中第一存储电极C1，第二过孔V2用于连接第二发光器件122的第二阳极1221与其对应的存储电容Cst中第一存储电极C1，第三过孔V3用于连接第三发光器件123的第三阳极1231与其对应的存储电容Cst中第一存储电极C1。
由于第一过孔V1、第二过孔V2和第三过孔V3均贯穿平坦层108，平坦层108上第一过孔V1、第二过孔V2或第三过孔V3所在的区域相比没有过孔的区域的平坦度较差，会对发光器件的制作和显示造成影响。本公开的一些实施例中，像素单元P中的所有存储电容Cst在第一衬底10上的正投影位于第三有效发光区1234与第一有效发光区1214和第二有效发光区1224在第一衬底10上的正投影之间，用于连接每个第一发光器件121的第一阳极1211与其对应的存储电容Cst中第一存储电极C1的第一过孔V1，用于连接第二发光器件122的第二阳极1221与其对应的存储电容Cst中第一存储电极C1的第二过孔V2，用于连接第三发光器件123的第三阳极1231与其对应的存储电容Cst中第一存储电极C1的第三过孔V3，在第一衬底10上的正投影，分别与其对应的存储电容Cst在第一衬底10上的正投影重叠，即位于像素单元P中的第一过孔V1、第二过孔V2和第三过孔V3位于第三发光器件123与第一发光器件121和第二发光器件122之间的区域，这样可避免第一过孔V1、第二过孔V2和第三过孔V3对发光器件的制作和显示造成影响。
在一些实施例中，如图9和图14所示，像素驱动电路100还包括第二晶体管T2。显示基板1000还包括多条第二栅线GL2和多条感测信号线SL，该多条第二栅线GL2沿第一方向X延伸，该多条感测信号线SL沿第二方向延伸。
如图14所示，第二晶体管T2的栅极与对应的一条第二栅线GL2连接，第二晶体管T2的第一极与对应的一条感测信号线SL连接，第二晶体管T2的第二极与第一存储电极C1连接。在此情况下，该像素驱动电路为3T1C(3个晶体管和1个电容)结构，以第一发光器件121对应的像素驱动电路100为例，驱动电路结构示意图如图15所示。
感测信号线SL用于感测像素驱动电路100中的电信号。如图15所示，在进行信号感测时，第一栅线GL1输入第一扫描信号，第一晶体管T1导通。同时，第二栅线GL2输入第二扫描信号，第二晶体管T2导通。数据线DL1通过第一晶体管T1向第一节点G提供数据信号，感测信号线SL感测经第二晶体管T2传输至第二节点S的电压，当第二节点S的电压稳定时，通过比较数据信号和第二节点S的电压即可得到驱动晶体管Td的阈值电压。从而可对驱动晶体管Td的阈值电压进行外部补偿，进而避免因材料、工艺等原因导致驱动晶体管Td的阈值电压漂移所造成显示不均匀。
如图9所示，像素组PG中的第一像素单元P1和第二像素单元P2之间设置有一条感测信号线SL。该感测信号线SL与对应的像素组PG中的第一像素单元P1中的像素驱动电路100和第二像素单元P2中的像素驱动电路100连接。
在此基础上，如图9所示，在一些实施例中，位于像素组PG的第一像素单元P1中的第二发光器件122在第一衬底10上的正投影与第二电压线PL2和感测信号线SL在第一衬底10上的正投影具有重叠区域。位于像素组PG的第二像素单元P2中的第二发光器件122在第一衬底10上的正投影与第一电压线PL1在第一衬底10上的正投影具有重叠区域。
在一些实施例中，如图9所示，显示基板1000还包括设置于第一衬底10上的多个第二辅助图案AL2，多个第二辅助图案AL2沿第一方向X延伸，每个第二辅助图案AL2与一条感测信号线SL连接。每个像素组PG中的所有像素驱动电路100与一个第二辅助图案AL2连接，通过该第二辅助图案AL2与一条感测信号线SL连接。这样可避免像素驱动电路100与感测信号线SL存在较多的跨线连接而导致工艺复杂。
在一些实施例中，如图9和图14所示，第二晶体管T2的栅极由与其连接的第二栅线GL2充当。这样可以简化生产工艺，节省生产成本。
在一些实施例中，如图9和图14所示，第三发光器件123在第一衬底10上的正投影与第二晶体管T2在第一衬底10上的正投影具有重叠区域。
在一些实施例中，显示基板1000的多条第一数据线DL1、多条第二数据 线DL2、多条第三数据线DL3、多条第一电压线PL1、多条第二电压线PL2和多条感测信号线SL同层设置且采用同一材料制作而成。这样一来，可以采用同一次工艺制作，从而可以简化生产工艺，节省生产成本。
需要说明的是，在多条第一数据线DL1、多条第二数据线DL2、多条第三数据线DL3、多条第一电压线PL1、多条第二电压线PL2和多条感测信号线SL同层设置的情况下，上述第一辅助图案AL1和与其对应的第一电压线PL1设置于不同层，且通过过孔连接；上述第二辅助图案AL2和与其对应的感测信号线SL设置于不同层，且通过过孔连接。这样可避免第一辅助图案AL1与第一数据线DL1、第二数据线DL2和第三数据线DL3发生短路，或者第二辅助图案AL2与第一数据线DL1、第二数据线DL2、第三数据线DL3和第二电压线PL2发生短路。
示例地，多条第一数据线DL1、多条第二数据线DL2、多条第三数据线DL3、多条第一电压线PL1、多条第二电压线PL2和多条感测信号线SL的材料包括铜单质、铝单质、银单质、铜合金、铝合金或银合金中的至少一种。
对于显示装置，在上述描述的显示基板1000基础上，如图2A和图2B所示，该显示装置还包括彩膜基板2000。该彩膜基板2000包括第二衬底20和设置于第二衬底20朝向第一衬底10一侧的彩膜层210。
彩膜层210包括多个第一颜色滤光单元211、多个第二颜色滤光单元212和多个第三颜色滤光单元213。相邻的两个滤光单元之间设置有黑矩阵220。每个第一颜色滤光单元211和对应的一个第一发光器件121在第二衬底20上的正投影重叠，每个第二颜色滤光单元212和对应的一个第二发光器件122在第二衬底20上的正投影重叠，每个第三颜色滤光单元213和对应的一个第三发光器件123在第二衬底20上的正投影重叠。
在一些示例中，该第二衬底20为盖板玻璃。
如图2B所示，至少部分黑矩阵220朝向显示基板1000一侧设置有缓冲胶层230，缓冲胶层230朝向显示基板1000一侧设置有隔离柱(post spacer，PS)240。隔离柱240用于防止显示装置在受到外部压力的作用时发生变形，影响显示效果。缓冲胶层230可以在显示装置受到外部压力的作用时起到缓冲作用。
在一些实施例中，该显示装置还包括设置于显示基板1000和彩膜基板2000之间的填充胶3000。
填充胶3000填充在显示基板1000和彩膜基板2000之间，填充胶3000可以缓解显示装置受到的外部压力作用，防止显示装置受到压力而破坏，并 能进一步隔绝水氧。
上述显示装置包括电视、手机、显示面板等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    第一衬底；以及
    设置于所述第一衬底上的多个像素单元，所述多个像素单元呈多行和多列排布；所述多个像素单元中的一个像素单元，具有第一有效发光区、第二有效发光区和第三有效发光区；所述像素单元包括：
    多个发光器件，所述多个发光器件包括第一发光器件、第二发光器件和第三发光器件，所述第一发光器件、所述第二发光器件和所述第三发光器件分别包括所述第一有效发光区、所述第二有效发光区和所述第三有效发光区，且用于发出三基色的光；
    所述第一有效发光区和所述第二有效发光区沿第一方向间隔排布，所述第三有效发光区与所述第一有效发光区和所述第二有效发光区沿第二方向间隔，且所述第一有效发光区和所述第二有效发光区的最小间距分别小于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区的最小间距；所述第一方向与所述多个像素单元的行方向平行，所述第二方向与所述多个像素单元的列方向平行。
  2. 根据权利要求1所述的显示基板，其中，
    所述第一有效发光区和所述第二有效发光区的最小间距约为10～20μm，所述第三有效发光区与所述第一有效发光区和所述第二有效发光区的最小间距约为20～25μm。
  3. 根据权利要求1或2所述的显示基板，其中，
    所述第三发光器件被配置为发出绿色光；所述第一发光器件和所述第二发光器件分别被配置为发出红色和蓝色的光。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述第一发光器件包括第一阳极、第一发光功能层和第一阴极，所述第二发光器件包括第二阳极、第二发光功能层和第二阴极，所述第三发光器件包括第三阳极、第三发光功能层和第三阴极；
    所述像素单元还包括多个像素驱动电路，所述第一阳极、所述第二阳极和所述第三阳极分别与对应的一个像素驱动电路连接，所述像素驱动电路被配置为驱动对应的发光器件发光；所述像素驱动电路包括存储电容；
    所述像素单元中的所有存储电容在所述第一衬底上的正投影位于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区在所述第一衬底上的正投影之间。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板具有显示区；所述显示区包括多个像素区，每个像素单元所在的区域为一个像素区；
    所述像素区包括沿第一方向依次排布的第一子区、第二子区和第三子区，所述第一子区、所述第二子区和所述第三子区中的每个子区中均设置有所述像素驱动电路；
    所述第一阳极位于所述第一子区和所述第二子区中并与设置于所述第二子区中的像素驱动电路连接；所述第二阳极至少位于所述第三子区中且与设置于所述第三子区中的像素驱动电路连接；所述第三阳极位于所述第一子区、所述第二子区和所述第三子区中，且与设置于所述第一子区中的像素驱动电路连接。
  6. 根据权利要求5所述的显示基板，其中，所述第二阳极还延伸至所述第二子区中。
  7. 根据权利要求5所述的显示基板，其中，所述第一阳极与设置于所述第二子区中的像素驱动电路通过第一过孔连接，所述第二阳极与设置于所述第三子区中的像素驱动电路通过第二过孔连接，所述第三阳极与设置于所述第一子区中的像素驱动电路通过第三过孔连接；所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影位于所述第三有效发光区与所述第一有效发光区和所述第二有效发光区在所述第一衬底上的正投影之间。
  8. 根据权利要求7所述的显示基板，其中，所述像素单元中的所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影的几何中心处于沿所述第一方向的同一直线上。
  9. 根据权利要求7所述的显示基板，还包括：设置于所述第一衬底上的多条第一数据线、多条第二数据线和多条第三数据线，且多条第一数据线、多条第二数据线和多条第三数据线均沿所述第二方向延伸；
    所述第一子区和所述第二子区之间设置有一条第一数据线和一条第二数据线，且所述第一数据线与位于所述第一子区中的像素驱动电路连接，所述第二数据线与位于所述第二子区中的像素驱动电路连接；
    所述第二子区和所述第三子区之间设置有一条第三数据线，所述第三数据线与位于所述第三子区中的像素驱动电路连接。
  10. 根据权利要求9所述的显示基板，还包括多条第一栅线、多条第一电压线和多条第二电压线；所述多条第一栅线均沿所述第一方向延伸，所述多条第一电压线和所述多条第二电压线均沿所述第二方向延伸；
    所述像素驱动电路包括第一晶体管、驱动晶体管和存储电容；所述存储电容包括第一存储电极和第二存储电极；
    所述第一晶体管的栅极与所述像素驱动电路对应的一条第一栅线连接；位于所述第一子区的所述第一晶体管的第一极与所述第一数据线连接，位于所述第二子区的所述第一晶体管的第一极与所述第二数据线连接，位于所述第三子区的所述第一晶体管的第一极与所述第三数据线连接；所述第一晶体管的第二极与所述驱动晶体管的栅极连接；
    所述驱动晶体管的第一极与所述像素驱动电路对应的一条第一电压线连接，所述驱动晶体管的第二极与所述第一存储电极连接；位于所述第一子区的所述存储电容的第一存储电极通过所述第三过孔与所述第三阳极连接，位于所述第二子区的所述存储电容的第一存储电极通过所述第一过孔与所述第一阳极连接，位于所述第三子区的所述存储电容的第一存储电极通过所述第二过孔与所述第二阳极连接；所述第一阴极、所述第二阴极和所述第三阴极与一条第二电压线通过至少一个第四过孔连接；
    所述第二存储电极与所述驱动晶体管的栅极连接；
    所述第一过孔、所述第二过孔和所述第三过孔在所述第一衬底上的正投影分别与其对应的存储电容在所述第一衬底上的正投影重叠。
  11. 根据权利要求10所述的显示基板，其中，
    所述驱动晶体管还包括有源图案，所述有源图案设置于所述驱动晶体管的栅极靠近所述第一衬底的一侧；
    所述第一存储电极与所述驱动晶体管的第一极和第二极同层设置；
    所述第二存储电极与所述驱动晶体管的有源图案同层设置。
  12. 根据权利要求10所述的显示基板，其中，所述第一晶体管的栅极由对应的所述第一栅线充当。
  13. 根据权利要求10所述的显示基板，其中，沿所述第一方向，每相邻的两个像素单元为一个像素组，每个像素组的两个像素单元分别为第一像素单元和第二像素单元；
    所述像素组中的所述第一像素单元和所述第二像素单元之间设置有一条第二电压线；沿所述第一方向，相邻两个像素组之间设置有一条第一电压线。
  14. 根据权利要求13所述的显示基板，所述像素驱动电路还包括第二晶体管；
    所述显示基板还包括多条第二栅线和多条感测信号线；所述多条第二栅线沿所述第一方向延伸，所述多条感测信号线沿所述第二方向延伸；所述像素组中的所述第一像素单元和所述第二像素单元之间设置有一条感测信号线；
    所述第二晶体管的栅极与对应的一条第二栅线连接；所述第二晶体管的第一极与对应的一条感测信号线连接，所述第二晶体管的第二极与所述第一存储电极连接。
  15. 根据权利要求14所述的显示基板，其中，所述第二晶体管的栅极由与其连接的第二栅线充当。
  16. 根据权利要求14或15所述的显示基板，其中，所述第三发光器件在所述第一衬底上的正投影与所述第二晶体管在所述第一衬底上的正投影具有重叠区域。
  17. 根据权利要求14所述的显示基板，其中，位于所述像素组的所述第一像素单元中的所述第二发光器件在所述第一衬底上的正投影与所述第二电压线和所述感测信号线在所述衬底上的正投影具有重叠区域；位于所述像素组的所述第二像素单元中的所述第二发光器件在所述第一衬底上的正投影与所述第一电压线在所述衬底上的正投影具有重叠区域。
  18. 根据权利要求14-17任一项所述的显示基板，其中，
    所述多条第一数据线、所述多条第二数据线、所述多条第三数据线、所述多条第一电压线、所述多条第二电压线和所述多条感测信号线同层设置。
  19. 根据权利要求1-18任一项所述的显示基板，其中，所述第一有效发光区与所述第二有效发光区关于所述第三有效发光区的沿所述第二方向的中心轴对称分布。
  20. 一种显示装置，包括如权利要求1-19任一项所述的显示基板，还包 括：
    彩膜基板，包括第二衬底和设置于所述第二衬底朝向所述第一衬底一侧的彩膜层；
    所述彩膜层包括多个第一颜色滤光单元、多个第二颜色滤光单元和多个第三颜色滤光单元；相邻的两个滤光单元之间设置有黑矩阵；
    每个第一颜色滤光单元和对应的一个第一发光器件在所述第二衬底上的正投影重叠，每个第二颜色滤光单元和对应的一个第二发光器件在所述第二衬底上的正投影重叠，每个第三颜色滤光单元和对应的一个第三发光器件在所述第二衬底上的正投影重叠。
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