WO2022088071A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022088071A1
WO2022088071A1 PCT/CN2020/125398 CN2020125398W WO2022088071A1 WO 2022088071 A1 WO2022088071 A1 WO 2022088071A1 CN 2020125398 W CN2020125398 W CN 2020125398W WO 2022088071 A1 WO2022088071 A1 WO 2022088071A1
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WO
WIPO (PCT)
Prior art keywords
pixel driving
lead
display area
light
display
Prior art date
Application number
PCT/CN2020/125398
Other languages
English (en)
French (fr)
Inventor
邱远游
黄耀
顾品超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002593.9A priority Critical patent/CN115210877A/zh
Priority to US18/033,851 priority patent/US20230402006A1/en
Priority to PCT/CN2020/125398 priority patent/WO2022088071A1/zh
Publication of WO2022088071A1 publication Critical patent/WO2022088071A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • a base substrate including a display area and a frame area outside the display area;
  • the display area includes: a first display area, and a second display area at least on one side of the first display area;
  • a plurality of light-emitting devices are arranged in an array on the base substrate; the plurality of light-emitting devices include: a plurality of first light-emitting devices located in the first display area, and a plurality of light-emitting devices located in the second display area a plurality of second light emitting devices;
  • the plurality of pixel driving circuits include: a plurality of first pixel driving circuits and a plurality of second pixel driving circuits; wherein the plurality of pixel driving circuits A plurality of first pixel driving circuits are electrically connected to the plurality of first light emitting devices, the plurality of second pixel driving circuits and the plurality of second light emitting devices at least partially overlap each other and are correspondingly electrically connected;
  • the two-pixel drive circuit has a drive transistor, a threshold compensation transistor and a gate connection electrode, and the gate connection electrode is electrically connected to the gate of the drive transistor and one of the source or drain of the threshold compensation transistor;
  • a plurality of connecting leads each of at least a part of the connecting leads is electrically connected to at least one of the first pixel driving circuits and one of the first light-emitting devices, and the orthographic projection of the connecting leads on the base substrate is connected to the gate electrode The orthographic projections on the base substrate do not overlap each other.
  • the plurality of connection wires are located on a side of the layer where the plurality of pixel driving circuits are located away from the base substrate.
  • the second display area includes a plurality of pixel driving circuit columns arranged along a first direction; the plurality of pixel driving circuit columns include: a plurality of first pixel driving circuit columns and a plurality of second pixels drive circuit column;
  • the first pixel driving circuit column includes only a plurality of the first pixel driving circuits arranged along the second direction; the first direction and the second direction intersect;
  • the second column of pixel driving circuits includes: the first pixel driving circuits arranged in the second direction, and all the first pixel driving circuits that are at least partially adjacent in the second direction between the first pixel driving circuits. the second pixel driving circuit;
  • the first display area includes a plurality of first light emitting device columns arranged along the first direction, each of the first light emitting device columns includes a plurality of the first light emitting devices arranged along the second direction;
  • Each of the first light-emitting devices in each of the first light-emitting device columns is electrically connected to at least a part of the first pixel driving circuits in a column of the first pixel driving circuit columns, respectively.
  • connection lead is divided into: a first lead part and a second lead part extending along the second direction, and a first lead part and a second lead part extending along the first direction and connected to the first lead part and the the third lead portion electrically connected to the second lead portion;
  • the first lead portion is led out from the first pixel driving circuit column, and is electrically connected with at least part of the first pixel driving circuits in the first pixel driving circuit column;
  • the second lead portion is drawn out from the first light emitting device column and is electrically connected to the first light emitting device in the first light emitting device column;
  • the orthographic projection of the third lead portion on the base substrate does not overlap with the first display area and the second display area; or,
  • At least part of the orthographic projection of the third lead portion on the base substrate does not overlap with the first display area and the second display area, and the orthographic projection of the rest of the third lead portion on the base substrate falls into the first display area and the second display area. display area.
  • the plurality of connection leads include:
  • the first connecting lead is located between the pixel driving circuit and the light-emitting device, the first connecting lead includes multiple layers of connecting sub-leads located in different film layers, and each layer of connecting sub-leads is electrically connected to different first connecting leads respectively. a pixel driving circuit and the first light emitting device.
  • the orthographic projections of the connecting sub-leads located in different film layers on the base substrate overlap;
  • the orthographic projection of at least two layers of the connecting sub-leads in the multiple layers of the connecting sub-leads on the base substrate at least partially overlaps
  • orthographic projections of the multiple layers of the connecting sub-leads on the base substrate do not overlap.
  • the second lead part only includes the first connection lead; and the material of the first connection lead includes a light-transmitting material.
  • the light-transmitting material includes one or a combination of the following: indium tin oxide, graphene.
  • the light-emitting device includes: an anode, a light-emitting functional layer, and a cathode that are stacked in sequence;
  • the connecting lead also includes:
  • the second connecting lead is arranged on the same layer as the anode and is electrically connected to the first connecting lead.
  • At least one of the first lead portion and the third lead portion includes a first connection lead and a second connection lead that are electrically connected.
  • the third lead portion is located in the frame area adjacent to both the first display area and the second display area.
  • the display substrate further includes: a third connection lead electrically connected to the third lead portion in the frame region.
  • At least one of the plurality of pixel drive circuits includes a gate connection electrode; the pixel drive circuit further includes: a first gate between the base substrate and the gate connection electrode a pole layer, and a second gate layer between the first gate layer and the gate connection electrode;
  • the third connection lead is disposed in the same layer as one of the following film layers: the gate connection electrode, the first gate layer, and the second gate layer.
  • the pixel driving circuit further includes: a first transistor and a storage capacitor;
  • the gate of the first transistor is electrically connected to the first reset signal terminal, and the source of the first transistor is electrically connected to the first initial signal terminal;
  • the drain of the first transistor, the first stage of the storage capacitor, and the source of the threshold compensation transistor are electrically connected to the gate of the driving transistor;
  • the gate of the threshold compensation body is electrically connected to the scan signal terminal
  • the second stage of the storage capacitor is electrically connected to the power signal terminal.
  • Embodiments of the present disclosure provide a display device including the display substrate provided by the embodiments of the present disclosure.
  • the display device further includes:
  • the orthographic projection of the light extraction module on the base substrate is located in the first display area and the second display area of the display substrate, and the light extraction module is located away from the display substrate side of the light-emitting surface.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure
  • Fig. 2 is the enlarged structural schematic diagram of the area a in Fig. 1 in the related art
  • FIG. 3 is a schematic diagram of uneven brightness in the related art
  • FIG. 4 is a schematic diagram of uneven brightness in the related art
  • FIG. 5 is an enlarged schematic structural diagram of the area a in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a first connection lead according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another first connection lead according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another first connection lead according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a second display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a second display area of another display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of an active layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a first gate layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a second gate layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of an opening of an interlayer insulating layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 15 is a schematic diagram of a source-drain metal layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • 16 is a schematic diagram of an opening of a first planarization layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of a first conductive layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 18 is a schematic diagram of an opening of a second planarization layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • 19 is a schematic diagram of an opening of a second planarization layer in a second display area of another display substrate according to an embodiment of the present disclosure
  • 20 is a schematic diagram of an anode layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • 21 is a schematic diagram of an anode layer in a second display area of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of an opening of a pixel definition layer in a second display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 23 is a schematic structural diagram of a first display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic diagram of a first conductive layer in a first display area of a display substrate according to an embodiment of the present disclosure
  • 25 is a schematic diagram of an opening of a second planarization layer in a first display area of a display substrate according to an embodiment of the present disclosure
  • 26 is a schematic diagram of an anode layer in a first display area of a display substrate according to an embodiment of the present disclosure
  • FIG. 27 is a schematic diagram of a pixel definition layer in a first display area of a display substrate according to an embodiment of the present disclosure.
  • a display device with an under-screen camera structure includes: a first display area AA1 and a second display area AA2 , and the camera can be arranged at the position of the first display area AA1 .
  • the first display area AA1 is provided with a plurality of light-emitting devices EL
  • the second display area AA2 is provided with a plurality of pixels P and a plurality of pixel driving circuits D, wherein each pixel P includes a light-emitting device EL and a The light-emitting device corresponds to the electrically connected pixel driving circuit D; and the pixel driving circuit D separately arranged in the second display area AA2 is used to control the light-emitting device EL of the first display area AA1 to emit light.
  • a light emitting device EL in the first display area AA1 is electrically connected to a pixel driving circuit D in the second display area AA2 through a transparent connection lead ITO.
  • a pixel driving circuit includes a driving transistor and a threshold compensation transistor, and the gate of the driving transistor and the drain of the threshold compensation transistor are electrically connected through a gate connection electrode.
  • the pixel drive circuit D as an example of a 7T1C structure, as shown in FIG. 3 , the light-emitting process of the 7T1C pixel drive circuit driving the light-emitting device can be divided into the following three stages:
  • the first transistor T1 is turned on, so that the first initialization signal terminal Vin1 resets the N1 node, and the remaining transistors are in an off state, wherein the N1 node and the gate of the driving transistor Td are electrically connected. connect.
  • the threshold compensation transistor T2 and the third transistor T3 are turned on under the control of the scanning signal terminal Gm, the signal of the data signal terminal Dm is written into the N2 node through the third transistor T3, and the threshold compensation transistor T2 is used to realize the driving transistor Td.
  • the sixth transistor T6 is turned on, so that the second initialization signal terminal Vin2 resets the N4 node, and the remaining transistors are in an off state.
  • the N4 node is electrically connected to the anode of the light-emitting device EL, and for the pixel driving circuit D that needs to be electrically connected to the light-emitting device EL, the N4 node and the anode of the light-emitting device EL are connected through a transparent connection lead ITO.
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the driving transistor Td is also turned on at this stage, so as to be the light-emitting device EL provide drive current.
  • the pixel driver circuit further includes the following insulating layer: an interlayer insulating layer 2.
  • the N4 node is electrically connected. After the signal of the light-emitting control signal terminal EM is turned on, when the N4 voltage jumps, the voltage of the N1 node of the pixel drive circuit that the connecting lead spans jumps, and the transparent connection lead is connected to each pixel drive circuit.
  • the capacitances between the N1 nodes are not exactly the same, resulting in uneven brightness.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 and FIG. 5 , wherein FIG. 5 is an enlarged structural diagram of area a in FIG. 1 , and the display substrate includes:
  • the base substrate includes a display area AA and a frame area OO located outside the display area AA;
  • the display area AA includes: a first display area AA1, and a second display area AA2 located at least on one side of the first display area AA1;
  • the plurality of light-emitting devices EL are arranged in an array on the base substrate; the plurality of light-emitting devices EL include: a plurality of first light-emitting devices 6 located in the first display area AA1, and a plurality of first light-emitting devices 6 located in the second display area AA2. two light-emitting devices (not shown);
  • a plurality of pixel driving circuits located in the second display area AA2, between the base substrate and the light-emitting device; the plurality of pixel driving circuits include: a plurality of first pixel driving circuits 7 and a plurality of second pixel driving circuits 8; wherein, A plurality of first pixel driving circuits 7 are electrically connected to a plurality of first light-emitting devices 6, a plurality of second pixel driving circuits 8 and a plurality of second light-emitting devices are at least partially overlapped with each other and are correspondingly electrically connected; at least one second pixel
  • the driving circuit has a driving transistor, a threshold compensation transistor and a gate connection electrode, and the gate connection electrode is electrically connected to the gate of the driving transistor and one of the source or drain of the threshold compensation transistor;
  • a plurality of connecting leads 9, at least part of each of the connecting leads 9 is electrically connected to at least one first pixel driving circuit 7 and one first light emitting device 6, and the orthographic projection of the connecting leads on the base substrate is lined with the gate connecting electrode.
  • the orthographic projections of the base substrates do not overlap each other.
  • the orthographic projection of the connecting lead on the base substrate and the orthographic projection of the gate connecting electrode on the base substrate do not overlap with each other, so that the connecting lead avoids the gate connecting electrode, and the connecting lead and the gate can be avoided.
  • Capacitors are formed between the polar connection electrodes, so that the driving current provided by the second pixel driving circuit can be prevented from jumping, the uneven luminous brightness can be avoided, and the uniformity of luminous brightness can be improved.
  • the display area further includes a third display area AA3 , and the pixel densities of the first display area AA1 and the second display area AA2 are both smaller than the pixel density of the third display area AA3 .
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2.
  • the shape of the first display area AA1 , the shape of the second display area AA2 , and the shape of the area formed by the first display area AA1 and the second display area AA2 are all rectangles.
  • the shape of the first display area AA1, the shape of the second display area AA2, and the shape of the area composed of the first display area AA1 and the second display area AA2 can also be other shapes, such as the first display area.
  • the shape of the area formed by the area AA1 and the second display area AA2 is circular, and the shape of the first display area AA1 is also circular.
  • the first pixel driving circuits electrically connected to different light emitting devices through connecting wires are different.
  • different light emitting devices are electrically connected to the same first pixel driving circuit through different connecting wires, respectively.
  • the plurality of connection wires are located on a side of the layer where the plurality of pixel driving circuits are located away from the base substrate.
  • the second display area AA2 includes a plurality of pixel driving circuit columns arranged along the first direction X; the plurality of pixel driving circuit columns include: a plurality of first pixel driving circuit columns 10 and a plurality of second pixel driving circuit columns 11;
  • the first pixel driving circuit column 10 only includes a plurality of first pixel driving circuits 7 arranged along the second direction Y; the first direction X and the second direction Y intersect;
  • the second pixel driving circuit column 11 includes: first pixel driving circuits 7 arranged in the second direction Y, and second pixel driving circuits 8 located between at least partially adjacent first pixel driving circuits 7 in the second direction Y ;
  • the first display area AA1 includes a plurality of first light emitting device columns 12 arranged along the first direction X, and each first light emitting device column 12 includes a plurality of first light emitting devices 6 arranged along the second direction Y;
  • Each first light emitting device 6 in each first light emitting device column 12 is electrically connected to at least part of the first pixel driving circuits 7 in a first pixel driving circuit column 10, respectively.
  • one column of the first light-emitting device column located in the first display area corresponds to one column of the first pixel driving circuit column located in the second display area, so that the connection between the connecting leads and the second pixel driving circuit can be ensured. While the gate connection electrodes do not overlap each other, the arrangement of the connection leads is easy to realize.
  • the first light emitting devices 6 in a column of the first light emitting device column 12 are electrically connected to a portion of the first pixel driving circuits 7 in a column of first pixel driving circuit columns 10 .
  • first pixel driving circuit columns 10 and the second pixel driving circuit columns 11 are alternately arranged.
  • multiple columns of first pixel drive circuits may also be included between adjacent columns of second pixel driving circuits, or multiple columns of second pixels may be included between adjacent columns of first pixel drive circuits
  • the driving circuit columns, or a plurality of first pixel driving circuit columns are adjacent to each other, or a plurality of second pixel driving circuit columns are adjacent to each other, and so on.
  • the first pixel driving circuits 7 and the second pixel driving circuits 8 are alternately arranged.
  • a plurality of first pixel driving circuits may also be included between adjacent second pixel driving circuits, or a plurality of first pixel driving circuits may be included between adjacent first pixel driving circuits. a plurality of second pixel driving circuits.
  • the first pixel driving circuit in the first pixel driving circuit column that is not electrically connected to the first light emitting device, and the first pixel driving circuit in the second pixel driving circuit column are used as the pixel driving circuit in the dummy pixel. circuit.
  • the dummy pixel does not emit light during display, and the setting of the dummy pixel can ensure the display uniformity of the display product.
  • the first direction X and the second direction Y are perpendicular.
  • connection lead 9 is divided into: a first lead part 13 and a second lead part 14 extending along the second direction Y, and a first lead part 13 extending along the first direction X and connected to the first lead the third lead part 15 electrically connecting the part 13 and the second lead part 14;
  • the first lead portion 13 is led out from the first pixel driving circuit column 10 and is electrically connected with at least part of the first pixel driving circuits 7 in the first pixel driving circuit column 10;
  • the second lead portion 14 is led out from the first light emitting device column 12 and is electrically connected to the first light emitting device 6 in the first light emitting device column 12;
  • the orthographic projection of the third lead portion 15 on the base substrate does not overlap with the first display area AA1 and the second display area AA2.
  • the extending direction of the connecting lead is no longer single, and the connecting lead includes a first lead portion and a second lead portion extending along the second direction, and a third lead portion extending along the first direction.
  • the first lead portion electrically connected with the first pixel driving circuit is drawn out from the column of the first pixel driving circuit, and the first lead portion and the gate connecting electrode of the second pixel driving circuit do not overlap each other. Therefore, the first lead portion and the gate connecting electrode of the second pixel driving circuit do not overlap each other, and the formation of capacitance between the first lead portion and the gate connecting electrode can be avoided.
  • the second lead portion is drawn out from the first light-emitting device column, and the second lead portion does not overlap with the first pixel driving circuit and the second pixel driving circuit; the third lead portion is connected with the first lead portion and the second lead portion.
  • the third lead portion does not overlap with the first pixel driving circuit and the second pixel driving circuit. That is, no capacitance is formed between the second lead portion and the third lead portion and the gate connection electrode. Therefore, the arrangement of the connecting leads in the display substrate provided by the embodiments of the present disclosure does not cause jumping of the driving current in the pixel driving circuit, which can avoid uneven luminous brightness and improve the uniformity of luminous brightness.
  • connection lead is divided into: a first lead part and a second lead part extending in the second direction, and a third lead part extending in the first direction and electrically connected to the first lead part and the second lead part lead part;
  • the first lead portion is led out from the first pixel driving circuit column and is electrically connected with at least part of the first pixel driving circuits in the first pixel driving circuit column;
  • the second lead portion is drawn out from the first light emitting device column and is electrically connected to the first light emitting device in the first light emitting device column;
  • At least part of the orthographic projection of the third lead portion on the base substrate does not overlap with the first display area and the second display area, and the orthographic projection of the rest of the third lead portion on the base substrate falls into the first display area and the second display area. display area.
  • each third connection lead is located on the same side of the second display area and does not overlap with the first display area and the second display area.
  • some of the third connection leads may be located in the frame area, and the rest of the third connection leads may be located in the area between the pixel driving circuit rows, so that they are located between the pixel driving circuit rows.
  • the third connection lead still does not overlap with the gate connection electrode and does not form capacitance with the gate connection electrode. Therefore, the arrangement of the connecting leads in the display substrate provided by the embodiments of the present disclosure does not cause jumping of the driving current in the pixel driving circuit, which can avoid uneven luminous brightness and improve the uniformity of luminous brightness.
  • each of the third lead portions 15 is located on the same side of the second display area AA2 .
  • the lengths of different third lead portions 15 are different.
  • the length of the third lead portion 15 near the second display area AA2 is smaller than the length of the third lead portion 15 away from the second display area AA2 . Therefore, as shown in FIG.
  • connection lead 9 when each first light-emitting device 6 in each first light-emitting device column 12 is electrically connected to at least part of the first pixel driving circuits 7 in a column of first pixel driving circuit columns 10, respectively,
  • the first lead part 13 , the second lead part 14 and the third lead part 15 in each connection lead 9 do not have overlapping areas with the other connection leads 9 , and the setting process of the plurality of connection leads 9 is simple and easy to implement.
  • At least one of the first pixel drive circuits has a drive transistor and a threshold compensation transistor
  • At least one of the plurality of first pixel driving circuits further includes:
  • the gate is connected to the electrode, and is electrically connected to the gate of the driving transistor and the drain of the threshold compensation transistor;
  • the orthographic projection of the first lead portion on the base substrate and the orthographic projection of the gate connection electrode on the base substrate do not overlap with each other.
  • the orthographic projection of the first lead portion on the base substrate does not overlap with the orthographic projection of the gate connection electrode of any pixel driving circuit on the base substrate, that is, the first lead portion avoids
  • the gate connection electrode of any pixel driving circuit can avoid the formation of capacitance between the first lead part and the gate connection electrode in any pixel driving circuit, and avoid causing the driving current in each pixel driving circuit to jump, which further improves the performance. Uniformity of luminous brightness.
  • connecting leads include:
  • the first connecting lead is located between the pixel driving circuit and the light emitting device.
  • the first connection lead includes only one conductive layer.
  • the first connecting lead includes multiple layers of connecting sub-leads located at different film layers; that is, the first connecting lead includes multiple layers of conductive layers located at different film layers.
  • Each layer of connection sub-leads in the multi-layer connection sub-leads is respectively electrically connected to the at least one first pixel driving circuit and a first light emitting device;
  • each of the multi-layer connection sub-leads is electrically connected to the at least one first pixel driving circuit and one first light-emitting device, respectively, so that the wiring space of the first connection leads can be saved.
  • the orthographic projections of the connection sub-leads located in different film layers on the base substrate overlap; or, the orthographic projections of the connection sub-leads of at least two layers of the multi-layer connection sub-leads on the base substrate at least partially overlap; Or, the orthographic projections of the multi-layer connection sub-leads on the base substrate do not overlap.
  • the first connection lead includes, for example, a first connection sub-lead 27 , a second connection sub-lead 28 and a third connection sub-lead 29 located in different film layers.
  • the orthographic projections of the first connection sub-lead 27 , the second connection sub-lead 28 and the third connection sub-lead 29 overlap on the base substrate; or, as shown in FIG. 7 , the first connection sub-lead 27 , At least two layers of the second connection sub-lead 28 and the third connection sub-lead 29 at least partially overlap in the orthographic projection of the base substrate; or as shown in FIG.
  • the first connection sub-lead 27 , the second connection sub-lead 28 and The orthographic projections of the third connecting sub-leads 29 on the base substrate do not overlap. It should be noted that, in FIGS. 6 to 8 , the first connecting sub-lead 27 is located on the first planarization layer 3 , between the first connecting sub-lead 27 and the second connecting sub-lead 28 and the second connecting sub-lead 28 The second planarization layer 4 is included between the third connection sub-lead 29 .
  • the material of the first connection lead includes a light transmissive material.
  • the light-transmitting material includes one or a combination of the following: indium tin oxide, graphene.
  • the second lead portion includes only the first connection lead.
  • the second lead portion only includes the first connection lead, that is, the second lead portion is a light-transmitting lead, so as to avoid affecting the light transmittance of the first display area.
  • connection leads include only the first connection leads.
  • the light-emitting device includes: an anode, a light-emitting functional layer, and a cathode that are stacked in sequence.
  • the light-emitting functional layer includes an organic light-emitting layer, and the light-emitting functional layer may further include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • connection lead includes the first connection lead
  • connection lead further includes:
  • the second connecting lead is arranged on the same layer as the anode and is electrically connected to the first connecting lead.
  • the first lead portion includes only the second connection lead.
  • the wiring space of the first lead part is small, which may limit the wiring space of the first lead part.
  • the number of first lead parts, when the first lead part is replaced by a first connection lead with a second connection lead, can make up for the wiring space and leads lost by the first connection lead in order to avoid the gate connection electrode of any pixel drive circuit quantity.
  • the first lead part and the third lead part may include only one of the first connection lead and the second connection lead.
  • connection lead in an area outside the first display area, at least one of the first lead portion and the third lead portion includes electrically connected first and second connection leads. That is to say, in the area outside the first display area, the connection lead may adopt a double-layer wiring method, which can reduce the resistance of the connection lead.
  • the connecting lead when the connecting lead includes a first connecting lead and a second connecting lead, in order to ensure the light transmittance of the first display area, the second lead part only includes the first connecting lead.
  • the third lead portion may include only the first connection lead, or the third lead portion may include only the second connection lead.
  • the third lead portion 15 is located in the frame area OO adjacent to both the first display area AA1 and the second display area AA2 .
  • the display substrate further includes: a third connection lead electrically connected to the third lead portion in the frame area.
  • a third connecting lead electrically connected to the third lead portion is provided, so that the resistance of the connecting lead can be reduced.
  • the pixel driving circuit further includes: a first gate layer between the base substrate and the gate connection electrode, and a second gate layer between the first gate layer and the gate connection electrode ;
  • the third connecting lead is arranged in the same layer as one of the following film layers: the gate connecting electrode, the first gate layer, and the second gate layer.
  • the pixel driving circuit may have the structure of 7T1C as shown in FIG. 3 .
  • the pixel driving circuit includes: a threshold compensation transistor T2 and a driving transistor Td, and further includes: a first transistor T1 , a third transistor T3 , a fourth transistor T3 a transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst;
  • the gate of the first transistor T1 is electrically connected to the first reset signal terminal Re1, and the source of the first transistor T1 is electrically connected to the first initial signal terminal Vin1;
  • the drain of the first transistor T1, the first stage of the storage capacitor Cst, and the source of the threshold compensation transistor T2 are electrically connected to the gate of the driving transistor Td;
  • the gate of the threshold compensation transistor T2 and the gate of the third transistor T3 are electrically connected to the scan signal terminal Gm;
  • the drain electrode of the threshold compensation transistor T2 and the drain electrode of the driving transistor Td are electrically connected to the source electrode of the fifth transistor T5;
  • the source of the driving transistor Td and the drain of the third transistor T3 are electrically connected to the drain of the fourth transistor T4;
  • the source of the third transistor T3 is electrically connected to the data signal terminal Dm;
  • the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are electrically connected to the light-emitting control signal terminal EM;
  • the source of the fourth transistor T4 and the second stage of the storage capacitor Cst are electrically connected to the power signal terminal VDD;
  • the drain of the fifth transistor T5 and the drain of the sixth transistor T6 are electrically connected to the light emitting device EL;
  • the gate of the sixth transistor T6 is electrically connected to the second reset signal terminal Re2, and the source of the sixth transistor T6 is electrically connected to the second initial signal terminal Vin2.
  • the specific film structure of the pixel driving circuit, the connecting leads and the light emitting device in the display substrate provided by the embodiment of the present disclosure will be introduced by taking the pixel driving circuit as the 7T1C structure as shown in FIG. 3 as an example.
  • each transistor may have a top-gate structure.
  • the display substrate specifically includes: an active layer 16 located on the base substrate, and a first gate located on the active layer. Insulating layer, first gate layer 17 over the first gate insulating layer, second gate insulating layer over the first gate insulating layer 17, second gate layer 18 over the second gate insulating layer , the interlayer insulating layer 2 on the second gate layer 18, the source-drain electrode layer 19 on the interlayer insulating layer 2, the first planarization layer 3 on the source-drain electrode layer 19, the A first conductive layer 20 on the planarization layer 3, a second planarization layer 4 on the first conductive layer 20, an anode layer 21 and a pixel definition layer 22 on the second planarization layer 4, located on A light-emitting functional layer on the anode layer 21, and a cathode layer on the light-emitting functional layer.
  • the first lead portion only includes the first connection lead.
  • the first lead portion only includes the second connection lead.
  • the pattern of the active layer 16 is as shown in FIG. 11 .
  • the active layer includes, for example, a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region of each transistor.
  • the active layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the source contact region and the drain contact region may be regions doped with n-type impurities or p-type impurities.
  • the pattern of the first gate layer 17 is as shown in FIG. 12 .
  • the first gate layer includes, for example, the second electrode of the storage capacitor, a scan signal line, a reset signal line, a light emission control signal line, and gates of each transistor.
  • the pattern of the second gate layer 18 is as shown in FIG. 13 .
  • the second gate layer includes, for example, the first electrode of the storage capacitor, an initialization line, and a light shielding layer. Wherein, the first pole of the storage capacitor and the second pole of the storage capacitor at least partially overlap to form the storage capacitor.
  • the pattern of the openings 23 of the interlayer insulating layer 2 is as shown in FIG. 14 .
  • the pattern of the source-drain metal layer 19 is as shown in FIG. 15 .
  • the source-drain metal layer includes, for example, a first power supply signal line, a data signal line, the source and drain electrodes of each transistor, and an electrode connection portion.
  • the electrode connecting part includes: a gate connecting electrode electrically connecting the gate of the driving transistor and the drain of the threshold compensation transistor, and the gate connecting electrode corresponds to the part of the N1 node in the source-drain metal layer.
  • the source-drain metal layer is electrically connected to the active layer or the gate layer, for example, through the opening of the interlayer insulating layer.
  • the pattern of the openings 24 of the first planarization layer 3 is as shown in FIG. 16 .
  • the pattern of the first conductive layer 20 is as shown in FIG. 17 .
  • the first conductive layer 20 includes first connection leads 26 .
  • the first connection lead is electrically connected to the source-drain electrode layer, for example, through the opening of the first planarization layer.
  • the pattern of the opening 25 of the second planarization layer 4 is shown in FIG. 18 and FIG. 19 .
  • 18 corresponds to the pattern of the opening of the second planarization layer of the display substrate provided in FIG. 9 .
  • FIG. 19 corresponds to the pattern of openings of the second planarization layer of the display substrate provided in FIG. 10 .
  • the pattern of the anode layer 21 is shown in FIG. 20 and FIG. 21 .
  • the anode layer 21 includes the anode of the light emitting device.
  • the anode is electrically connected to the source-drain electrode layer through the opening of the second planarizing layer and the opening of the first planarizing layer.
  • the anode layer 21 further includes a second connection lead 27 .
  • the anode layer is electrically connected to the source-drain electrode layer through the opening of the second planarizing layer and the opening of the first planarizing layer.
  • the pattern of the openings 5 of the pixel definition layer 22 is as shown in FIG. 22 .
  • the opening of the pixel definition layer exposes part of the anode.
  • the structure of the light emitting device in the first display area is as shown in FIG. 23 .
  • the pattern of the first conductive layer 20 in the first display area is as shown in FIG. 24 .
  • the first conductive layer 20 of the first display area includes a first connection lead 26 .
  • the pattern of the openings 25 of the second planarization layer 4 in the first display area is as shown in FIG. 25 .
  • the pattern of the anode layer 21 in the first display area is as shown in FIG. 26 .
  • the pattern of the openings 5 of the pixel definition layer 22 in the first display area is as shown in FIG. 27 .
  • An embodiment of the present disclosure further provides a display panel, including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display panel may be an organic electroluminescence display panel (OLED), a quantum dot light-emitting display panel (QLED), or a micro light emitting diode display panel (Micro LED).
  • OLED organic electroluminescence display panel
  • QLED quantum dot light-emitting display panel
  • Micro LED micro light emitting diode display panel
  • Embodiments of the present disclosure further provide a display device, including the display panel provided by the embodiments of the present disclosure.
  • the display device further includes:
  • the light extraction module is located in the first display area and the second display area of the display substrate in the orthographic projection of the light extraction module on the base substrate, and the light extraction module is located on the side of the display substrate away from the light emitting surface.
  • the light capturing module includes, for example, a camera module, an optical fingerprint recognition module, an ambient light sensor, and the like.
  • the display device is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • the connecting lead and the gate connecting electrode of the second pixel driving circuit do not overlap each other, which can avoid the connecting lead and the gate of the second pixel driving circuit.
  • Capacitors are formed between the polar connection electrodes, so that the driving current provided by the second pixel driving circuit can be prevented from jumping, the uneven luminous brightness can be avoided, and the uniformity of luminous brightness can be improved.

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Abstract

一种显示基板及显示装置，包括：位于第一显示区（AA1）的多个第一发光器件（6），位于第二显示区（AA2）的多个第二发光器件，多个第一像素驱动电路（7）和多个第二像素驱动电路（8）；多个第一像素驱动电路（7）与多个第一发光器件（6）对应电连接，多个第二像素驱动电路（8）与多个第二发光器件相互至少部分交叠并对应电连接；至少一个第二像素驱动电路（8）具有栅极连接电极；还包括多条连接引线（9），至少部分连接引线（9）中的每一条与至少一个第一像素驱动电路（7）和一个第一发光器件（6）电连接，且连接引线（9）与栅极连接电极在衬底基板的正投影互不交叠。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
随着智能手机的高速发展，不仅要求手机的外形美观，还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比，使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展，在性能和功能上的提升需求也与日俱增，屏下摄像头在不影响高屏占比的前提下，在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
本公开实施例提供的一种显示基板，所述显示基板包括：
衬底基板，包括显示区以及位于所述显示区之外的边框区；所述显示区包括：第一显示区，以及至少位于所述第一显示区一侧的第二显示区；
多个发光器件，在所述衬底基板之上呈阵列排布；所述多个发光器件包括：位于所述第一显示区的多个第一发光器件，以及位于所述第二显示区的多个第二发光器件；
多个像素驱动电路，位于所述衬底基板与所述发光器件之间；所述多个像素驱动电路包括：多个第一像素驱动电路和多个第二像素驱动电路；其中，所述多个第一像素驱动电路与所述多个第一发光器件对应电连接，所述多个第二像素驱动电路与所述多个第二发光器件相互至少部分交叠并对应电连接；至少一个第二像素驱动电路具有驱动晶体管、阈值补偿晶体管和栅极连接电极，栅极连接电极电连接驱动晶体管的栅极和阈值补偿晶体管的源极或漏极之一；
多条连接引线，至少部分所述连接引线中的每一条与至少一个所述第一 像素驱动电路和一个所述第一发光器件电连接，连接引线在衬底基板的正投影与栅极连接电极在衬底基板的正投影互不交叠。
在一些实施例中，多条连接引线位于多个像素驱动电路所在层背离衬底基板的一侧。
在一些实施例中，所述第二显示区包括沿第一方向排列的多个像素驱动电路列；多个所述像素驱动电路列包括：多个第一像素驱动电路列和多个第二像素驱动电路列；
所述第一像素驱动电路列仅包括多个沿第二方向排列的所述第一像素驱动电路；所述第一方向和所述第二方向交叉；
所述第二像素驱动电路列包括：沿所述第二方向排列的所述第一像素驱动电路，和在所述第二方向位于至少部分相邻的所述第一像素驱动电路之间的所述第二像素驱动电路；
所述第一显示区包括多个沿所述第一方向排列的第一发光器件列，每一所述第一发光器件列包括多个沿所述第二方向排列的所述第一发光器件；
每一所述第一发光器件列中的各所述第一发光器件，分别与一列所述第一像素驱动电路列中的至少部分所述第一像素驱动电路电连接。
在一些实施例中，所述连接引线划分为：沿所述第二方向延伸的第一引线部和第二引线部，以及沿所述第一方向延伸的且与所述第一引线部和所述第二引线部电连接的第三引线部；
所述第一引线部从所述第一像素驱动电路列引出，且与所述第一像素驱动电路列中的至少部分所述第一像素驱动电路电连接；
所述第二引线部从所述第一发光器件列引出，且与所述第一发光器件列中的所述第一发光器件电连接；
所述第三引线部在所述衬底基板的正投影与所述第一显示区和第二显示区互不交叠；或者，
至少部分第三引线部在衬底基板的正投影与第一显示区和第二显示区互不交叠，其余部分第三引线部在衬底基板的正投影落入第一显示区和第二显 示区。
在一些实施例中，所述多条连接引线包括：
第一连接引线，位于所述像素驱动电路和所述发光器件之间，所述第一连接引线包括位于不同膜层的多层连接子引线，每层连接子引线分别电连接不同的所述第一像素驱动电路和所述第一发光器件。
在一些实施例中，位于不同膜层的各所述连接子引线在所述衬底基板的正投影重叠；
或者，多层所述连接子引线中的至少两层所述连接子引线在所述衬底基板的正投影至少部分重叠；
或者多层所述连接子引线在所述衬底基板的正投影均不存在重叠。
在一些实施例中，所述第二引线部仅包括所述第一连接引线；所述第一连接引线的材料包括透光材料。
在一些实施例中，所述透光材料包括下列之一或其组合：氧化铟锡、石墨烯。
在一些实施例中，所述发光器件包括：依次堆叠设置的阳极、发光功能层、阴极；
所述连接引线还包括：
第二连接引线，与所述阳极同层设置，与所述第一连接引线电连接。
在一些实施例中，在第一显示区之外的区域，第一引线部和第三引线部中的至少一个包括电连接的第一连接引线和第二连接引线。
在一些实施例中，所述第三引线部位于与所述第一显示区和所述第二显示区均相邻的所述边框区。
在一些实施例中，所述显示基板还包括：在所述边框区与所述第三引线部电连接的第三连接引线。
在一些实施例中，所述多个像素驱动电路中的至少一个包括栅极连接电极；所述像素驱动电路还包括：位于所述衬底基板和所述栅极连接电极之间的第一栅极层，以及位于所述第一栅极层和所述栅极连接电极之间的第二栅 极层；
所述第三连接引线与下列膜层之一同层设置：所述栅极连接电极、所述第一栅极层、所述第二栅极层。
在一些实施例中，所述像素驱动电路还包括：第一晶体管以及存储电容；
所述第一晶体管的栅极与第一复位信号端电连接，所述第一晶体管的源极与第一初始信号端电连接；
所述第一晶体管的漏极、所述存储电容的第一级、所述阈值补偿晶体管的源极与所述驱动晶体管的栅极电连接；
所述阈值补偿体管的栅极与扫描信号端电连接；
所述存储电容的第二级与电源信号端电连接。
本公开实施例提供了一种显示装置，包括本公开实施例提供的显示基板。
在一些实施例中，所述显示装置还包括：
取光模组，所述取光模组在所述衬底基板的正投影位于所述显示基板的第一显示区和第二显示区内，且所述取光模组位于所述显示基板背离出光面的一侧。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示装置的结构示意图；
图2为相关技术中图1中a区域的放大结构示意图；
图3为相关技术中亮度不均的原理图；
图4为相关技术中亮度不均的原理图；
图5为本公开实施例提供的图1中a区域的一种放大结构示意图；
图6为本公开实施例提供的一种第一连接引线的结构示意图；
图7为本公开实施例提供的另一种第一连接引线的结构示意图；
图8为本公开实施例提供的又一种第一连接引线的结构示意图；
图9为本公开实施例提供的一种显示基板的第二显示区的结构示意图；
图10为本公开实施例提供的另一种显示基板的第二显示区的结构示意图；
图11为本公开实施例提供的一种显示基板的第二显示区中的有源层的示意图；
图12为本公开实施例提供的一种显示基板的第二显示区中的第一栅极层的示意图；
图13为本公开实施例提供的一种显示基板的第二显示区中的第二栅极层的示意图；
图14为本公开实施例提供的一种显示基板的第二显示区中的层间绝缘层的开口的示意图；
图15为本公开实施例提供的一种显示基板的第二显示区中的源漏金属层的示意图；
图16为本公开实施例提供的一种显示基板的第二显示区中的第一平坦化层的开口的示意图；
图17为本公开实施例提供的一种显示基板的第二显示区中的第一导电层的示意图；
图18为本公开实施例提供的一种显示基板的第二显示区中的第二平坦化层的开口的示意图；
图19为本公开实施例提供的另一种显示基板的第二显示区中的第二平坦化层的开口的示意图；
图20为本公开实施例提供的一种显示基板的第二显示区中的阳极层的示意图；
图21为本公开实施例提供的另一种显示基板的第二显示区中的阳极层的示意图；
图22为本公开实施例提供的一种显示基板的第二显示区中的像素定义层 的开口的示意图；
图23为本公开实施例提供的一种显示基板的第一显示区的结构示意图；
图24为本公开实施例提供的一种显示基板的第一显示区中的第一导电层的示意图；
图25为本公开实施例提供的一种显示基板的第一显示区中的第二平坦化层的开口的示意图；
图26为本公开实施例提供的一种显示基板的第一显示区中的阳极层的示意图；
图27为本公开实施例提供的一种显示基板的第一显示区中的像素定义层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
如图1、图2所示，相关技术中，具有屏下摄像头结构的显示装置包括：第一显示区AA1和第二显示区AA2，摄像头可以设置在第一显示区AA1的位置处。具体地，第一显示区AA1中设置有多个发光器件EL，第二显示区AA2中设置有多个像素P和多个像素驱动电路D，其中，每一个像素P包括一个发光器件EL及与该发光器件对应电连接的像素驱动电路D；而在第二显示区AA2内单独设置的像素驱动电路D用来控制第一显示区AA1的发光器件EL发光。具体地，如图2所示第一显示区AA1的一个发光器件EL通过一条透明连接引线ITO与第二显示区AA2内的一个像素驱动电路D电连接。
一般地，像素驱动电路中均具有驱动晶体管和阈值补偿晶体管，驱动晶体管的栅极和阈值补偿晶体管的漏极通过栅极连接电极电连接。以像素驱动电路D为7T1C的结构为例，如图3所示，7T1C结构的像素驱动电路驱动发光器件的发光过程可分为以下三个阶段：
第一阶段，在复位信号端Re1的控制下，第一晶体管T1开启，使得第一初始化信号端Vin1对N1节点进行复位，其余晶体管处于截止状态，其中，N1节点与驱动晶体管Td的栅极电连接。
第二阶段，在扫描信号端Gm的控制下阈值补偿晶体管T2和第三晶体管T3开启，数据信号端Dm的信号经第三晶体管T3写入N2节点，并通过阈值补偿晶体管T2实现对驱动晶体管Td的阈值补偿；另外，在第二初始化信号端Vin2的控制下，第六晶体管T6开启，使得第二初始化信号端Vin2对N4节点进行复位，其余晶体管处于截止状态。其中，对于像素P，N4节点与发光器件EL的阳极电连接，对于需要与发光器件EL电连接的像素驱动电路D，N4节点与发光器件EL的阳极通过透明连接引线ITO。
第三阶段，在发光控制信号端EM的控制下，第四晶体管T4和第五晶体管T5开启，此时由于存储电容Cst的存在，驱动晶体管Td在该阶段也处于开启状态，从而为发光器件EL提供驱动电流。
然而，当透明连接引线跨越单独设置的像素驱动电路D或像素P所含像 素驱动电路D中的栅极连接电极时，如图3所示，像素驱动电路还包括如下绝缘层：层间绝缘层2、第一平坦化层3、第二平坦化层4，透明连接引线ITO与栅极连接电极1之间存在交叠，透明连接引线ITO与栅极连接电极1之间仅包括一层第一平坦化层3，因此，如图4所示，该透明连接引线ITO与N1节点之间会形成一个较大的电容C_L_N1，并且，如图4所示，由于该透明连接引线与像素驱动电路D的N4节点电连接，在发光控制信号端EM的信号打开后，N4电压发生跳变时，连接引线跨越的像素驱动电路的N1节点的电压发生跳变，并且因透明连接引线与各像素驱动电路的N1节点之间的电容并不完全相同，故造成亮度不均。
针对相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1、图5所示，其中图5为图1中a区域的放大结构图，显示基板包括：
衬底基板，包括为显示区AA以及位于显示区AA之外的边框区OO；显示区AA包括：第一显示区AA1，以及至少位于第一显示区AA1一侧的第二显示区AA2；
多个发光器件EL，在衬底基板之上呈阵列排布；多个发光器件EL包括：位于第一显示区AA1的多个第一发光器件6，以及位于第二显示区AA2的多个第二发光器件(未示出)；
多个像素驱动电路，位于第二显示区AA2，位于衬底基板与发光器件之间；多个像素驱动电路包括：多个第一像素驱动电路7和多个第二像素驱动电路8；其中，多个第一像素驱动电路7与多个第一发光器件6对应电连接，多个第二像素驱动电路8与多个第二发光器件相互至少部分交叠并对应电连接；至少一个第二像素驱动电路具有驱动晶体管、阈值补偿晶体管和栅极连接电极，栅极连接电极电连接驱动晶体管的栅极和阈值补偿晶体管的源极或漏极之一；
多条连接引线9，至少部分连接引线9中的每一条与至少一个第一像素驱动电路7和一个第一发光器件6电连接，连接引线在衬底基板的正投影与栅 极连接电极在衬底基板的正投影互不交叠。
本公开实施例提供的显示基板，连接引线在衬底基板的正投影与栅极连接电极在衬底基板的正投影互不交叠，从而连接引线避让栅极连接电极，可以避免连接引线与栅极连接电极之间形成电容，进而可以避免第二像素驱动电路提供的驱动电流发生跳变，可以避免出现发光亮度不均，提高了发光亮度均一性。
在具体实施时，如图1所示，显示区还包括第三显示区AA3，第一显示区AA1和第二显示区AA2的像素密度均小于第三显示区AA3的像素密度。第一显示区AA1的透光率大于第二显示区AA2的透光率。在一些实施例中，如图1所示，第一显示区AA1的形状、第二显示区AA2的形状以及第一显示区AA1和第二显示区AA2组成的区域的形状均为矩形。当然在具体实施时，第一显示区AA1的形状、第二显示区AA2的形状以及第一显示区AA1和第二显示区AA2组成的区域的形状也可以为其他形状，例如可以是第一显示区AA1和第二显示区AA2组成的区域的形状为圆形，第一显示区AA1的形状也为圆形。
在一些实施例中，不同发光器件通过连接引线电连接的第一像素驱动电路不相同。或者，在一些实施例中，不同发光器件分别通过不同连接引线电连接至同一第一像素驱动电路。
在一些实施例中，多条连接引线位于多个像素驱动电路所在层背离衬底基板的一侧。
在一些实施例中，如图5所示，第二显示区AA2包括沿第一方向X排列的多个像素驱动电路列；多个像素驱动电路列包括：多个第一像素驱动电路列10和多个第二像素驱动电路列11；
第一像素驱动电路列10仅包括多个沿第二方向Y排列的第一像素驱动电路7；第一方向X和第二方向Y交叉；
第二像素驱动电路列11包括：沿第二方向Y排列的第一像素驱动电路7，和在第二方向Y位于至少部分相邻的第一像素驱动电路7之间的第二像素驱 动电路8；
第一显示区AA1包括多个沿第一方向X排列的第一发光器件列12，每一第一发光器件列12包括多个沿第二方向Y排列的第一发光器件6；
每一第一发光器件列12中的各第一发光器件6，分别与一列第一像素驱动电路列10中的至少部分第一像素驱动电路7电连接。
本公开实施例提供的显示基板，位于第一显示区的一列第一发光器件列对应一列位于第二显示区的一列第一像素驱动电路列，从而可以在保证连接引线与第二像素驱动电路的栅极连接电极互不交叠的同时，使得连接引线的设置易于实现。
在一些实施例中，如图5所示，当一列第一发光器件列12中的第一发光器件6的数量小于一列第一像素驱动电路列10中的第一像素驱动电路7的数量时，一列第一发光器件列12中的第一发光器件6与一列第一像素驱动电路列10中的部分第一像素驱动电路7电连接。
在一些实施例中，如图5所示，第一像素驱动电路列10与第二像素驱动电路列11交替排列。当然，在具体实施时，也可以是相邻的第二像素驱动电路列之间包括多列第一像素驱动电路列，或者是相邻的第一像素驱动电路列之间包括多列第二像素驱动电路列，或者是多列第一像素驱动电路列相邻，或者还可以是多列第二像素驱动电路列相邻，等等。
在一些实施例中，如图5所示，第二像素驱动电路列11中，第一像素驱动电路7和第二像素驱动电路8交替排列。当然，在具体实施时，第二像素驱动电路列中，也可以是相邻的第二像素驱动电路之间包括多个第一像素驱动电路，或者是相邻的第一像素驱动电路之间包括多个第二像素驱动电路。
在具体实施时，第一像素驱动电路列中的未与第一发光器件电连接的第一像素驱动电路，以及第二像素驱动电路列中的第一像素驱动电路，作为虚设像素中的像素驱动电路。在显示时虚设像素不发光，虚设像素的设置可以保证显示产品的显示均一性。
在一些实施例中，如图5所示，第一方向X和第二方向Y垂直。
在一些实施例中，如图5所示，连接引线9划分为：沿第二方向Y延伸的第一引线部13和第二引线部14，以及沿第一方向X延伸的且与第一引线部13和第二引线部14电连接的第三引线部15；
第一引线部13从第一像素驱动电路列10引出，且与第一像素驱动电路列10中的至少部分第一像素驱动电路7电连接；
第二引线部14从第一发光器件列12引出，且与第一发光器件列12中的第一发光器件6电连接；
第三引线部15在衬底基板的正投影与第一显示区AA1和第二显示区AA2互不交叠。
本公开实施例提供的显示基板，连接引线的延伸方向不再单一，连接引线包括沿第二方向延伸的第一引线部和第二引线部，以及包括沿第一方向延伸的第三引线部。其中，与第一像素驱动电路电连接的第一引线部从第一像素驱动电路列引出，第一引线部与第二像素驱动电路的栅极连接电极互不交叠。从而第一引线部与第二像素驱动电路的栅极连接电极互不交叠，可以避免第一引线部与栅极连接电极之间形成电容。并且，第二引线部从第一发光器件列引出，第二引线部与第一像素驱动电路和第二像素驱动电路均互不交叠；第三引线部与第一引线部以及第二引线部电连接，即便第三引线部沿第一方向延伸，第三引线部与第一像素驱动电路和第二像素驱动电路均互不交叠。即第二引线部和第三引线部也均不会与栅极连接电极之间形成电容。从而本公开实施例提供的显示基板中的连接引线的设置方式不会引起像素驱动电路中的驱动电流发生跳变，可以避免出现发光亮度不均，提高了发光亮度均一性。
在一些实施例中，连接引线划分为：沿第二方向延伸的第一引线部和第二引线部，以及沿第一方向延伸的且与第一引线部和第二引线部电连接的第三引线部；
第一引线部从第一像素驱动电路列引出，且与第一像素驱动电路列中的至少部分第一像素驱动电路电连接；
第二引线部从第一发光器件列引出，且与第一发光器件列中的第一发光器件电连接；
至少部分第三引线部在衬底基板的正投影与第一显示区和第二显示区互不交叠，其余部分第三引线部在衬底基板的正投影落入第一显示区和第二显示区。
需要说明的是，图5以各第三连接引线位于第二显示区的同一侧且与第一显示区和第二显示区均互不交叠为例进行举例说明。当然，在具体实施时，多条第三连接引线中，可以是部分第三连接引线位于边框区，其余部分第三连接引线位于像素驱动电路行之间的区域，这样位于像素驱动电路行之间的第三连接引线仍不会与栅极连接电极存在交叠，不会与栅极连接电极之间形成电容。从而本公开实施例提供的显示基板中的连接引线的设置方式不会引起像素驱动电路中的驱动电流发生跳变，可以避免出现发光亮度不均，提高了发光亮度均一性。
在一些实施例中，如图5所示，在第二方向Y上，各第三引线部15位于所述第二显示区AA2的同一侧。
在一些实施例中，如图5所示，不同第三引线部15的长度不相同。在一些实施例中，如图5所示，靠近第二显示区AA2的第三引线部15的长度，小于远离第二显示区AA2的第三引线部15的长度。从而，如图5所示，当各第一发光器件列12中的每一第一发光器件6，分别与一列第一像素驱动电路列10中的至少部分第一像素驱动电路7电连接时，每一连接引线9中的第一引线部13、第二引线部14以及第三引线部15，与其余连接引线9均不存在交叠区域，多条连接引线9的设置工艺简单，易于实现。
在一些实施例中，第一像素驱动电路中的至少一个具有驱动晶体管和阈值补偿晶体管；
多个第一像素驱动电路中的至少一个还包括：
栅极连接电极，电连接驱动晶体管的栅极和阈值补偿晶体管的漏极；
第一引线部在衬底基板的正投影与栅极连接电极在衬底基板的正投影互 不交叠。
这样，本公开实施例提供的显示基板，第一引线部在衬底基板的正投影与任意像素驱动电路的栅极连接电极在衬底基板的正投影互不交叠，即第一引线部避让任意像素驱动电路的栅极连接电极，从而可以避免第一引线部与任意像素驱动电路中的栅极连接电极之间形成电容，避免引起各像素驱动电路中的驱动电流发生跳变，进一步提高了发光亮度均一性。
在一些实施例中，连接引线包括：
第一连接引线，位于像素驱动电路和发光器件之间。
在一些实施例中，第一连接引线仅包括一层导电层。
或者，在一些实施例中，第一连接引线包括位于不同膜层的多层连接子引线；即第一连接引线包括位于不同膜层的多层导电层。多层连接子引线中的每层连接子引线分别电连接所述至少一个第一像素驱动电路和一个第一发光器件；
本公开实施例提供的显示基板，多层连接子引线中的每层连接子引线分别电连接所述至少一个第一像素驱动电路和一个第一发光器件，从而可以节省第一连接引线的布线空间。
在一些实施例中，位于不同膜层的各连接子引线在衬底基板的正投影重叠；或者，多层连接子引线中的至少两层连接子引线在衬底基板的正投影至少部分重叠；或者，多层连接子引线在衬底基板的正投影均不存在重叠。
具体实施时，如图6、图7、图8所示，第一连接引线例如包括位于不同膜层的第一连接子引线27、第二连接子引线28以及第三连接子引线29。如图6所示，第一连接子引线27、第二连接子引线28以及第三连接子引线29在衬底基板的正投影重叠；或者，如图7所示，第一连接子引线27、第二连接子引线28以及第三连接子引线29中的至少两层在衬底基板的正投影至少部分重叠；或者如图8所示，第一连接子引线27、第二连接子引线28以及第三连接子引线29在衬底基板的正投影均不存在重叠。需要说明的是，图6～图8中，第一连接子引线27位于第一平坦化层3之上，第一连接子引线27 和第二连接子引线28之间、第二连接子引线28和第三连接子引线29之间包括第二平坦化层4。
在一些实施例中，第一连接引线的材料包括透光材料。
在一些实施例中，透光材料包括下列之一或其组合：氧化铟锡、石墨烯。
在一些实施例中，第二引线部仅包括第一连接引线。
本公开实施例提供的显示基板，第二引线部仅包括第一连接引线，即第二引线部为透光引线，从而可以避免影响第一显示区的透光率。
在一些实施例中，连接引线仅包括第一连接引线。
在一些实施例中，发光器件包括：依次堆叠设置的阳极、发光功能层、阴极。
在一些实施例中，发光功能层包括有机发光层，发光功能层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。
当连接引线包括第一连接引线时，在一些实施例中，连接引线还包括：
第二连接引线，与阳极同层设置，与第一连接引线电连接。
在一些实施例中，第一引线部仅包括第二连接引线。
本公开实施例提供的显示基板，由于第一引线部避让任意像素驱动电路的栅极连接电极，当第一引线部为第一连接引线时，第一引线部的可布线空间较小，可能限制第一引线部的数量，当第一引线部由第一连接引线替换为第二连接引线时，可弥补第一连接引线为了避开任意像素驱动电路的栅极连接电极而损失的布线空间及引线数量。
在一些实施例中，第一引线部、第三引线部可以仅包括第一连接引线和第二连接引线中的一种。
或者，在一些实施例中，在第一显示区之外的区域，第一引线部和第三引线部中的至少一个包括电连接的第一连接引线和第二连接引线。即在第一显示区之外的区域，连接引线可以采用双层布线方式，可以减小连接引线的电阻。
在具体实施时，当连接引线包括第一连接引线和第二连接引线时，为了 保证第一显示区的透光率，第二引线部仅包括第一连接引线。第三引线部可以仅包括第一连接引线，或者第三引线部可以仅包括第二连接引线。
在一些实施例中，如图5所示，第三引线部15位于与第一显示区AA1和第二显示区AA2均相邻的边框区OO。
在一些实施例中，显示基板还包括：在边框区与第三引线部电连接的第三连接引线。
本公开实施例提供的显示基板，设置与第三引线部电连接的第三连接引线，从而可以减小连接引线的电阻。
在一些实施例中，像素驱动电路还包括：位于衬底基板和栅极连接电极之间的第一栅极层，以及位于第一栅极层和栅极连接电极之间的第二栅极层；
第三连接引线与下列膜层之一同层设置：栅极连接电极、第一栅极层、第二栅极层。
在一些实施例中，像素驱动电路可以为如图3所示的7T1C的结构，像素驱动电路包括：阈值补偿晶体管T2和驱动晶体管Td，还包括：第一晶体管T1，第三晶体管T3，第四晶体管T4，第五晶体管T5，第六晶体管T6，以及存储电容Cst；
第一晶体管T1的栅极与第一复位信号端Re1电连接，第一晶体管T1的源极与第一初始信号端Vin1电连接；
第一晶体管T1的漏极、存储电容Cst的第一级、阈值补偿晶体管T2的源极与驱动晶体管Td的栅极电连接；
阈值补偿体管T2的栅极以及第三晶体管T3的栅极与扫描信号端Gm电连接；
阈值补偿晶体管T2的漏极、驱动晶体管Td的漏极与第五晶体管T5的源极电连接；
驱动晶体管Td的源极、第三晶体管T3的漏极与第四晶体管T4的漏极电连接；
第三晶体管T3的源极与数据信号端Dm电连接；
第四晶体管T4的栅极以及第五晶体管T5的栅极与发光控制信号端EM电连接；
第四晶体管T4的源极以及存储电容Cst的第二级与电源信号端VDD电连接；
第五晶体管T5的漏极以及第六晶体管T6的漏极与发光器件EL电连接；
第六晶体管T6的栅极与第二复位信号端Re2电连接，第六晶体管T6的源极与第二初始信号端Vin2电连接。
接下来以像素驱动电路为如图3所示的7T1C的结构为例，对本公开实施例提供的显示基板中的像素驱动电路、连接引线以及发光器件的具体膜层结构进行介绍。
在一些实施例中，各晶体管可以是顶栅结构，如图9～图22所示，显示基板具体包括：位于衬底基板之上的有源层16、位于有源层之上的第一栅绝缘层，位于第一栅绝缘层之上的第一栅极层17，位于第一栅极层17之上的第二栅绝缘层，位于第二栅绝缘层之上的第二栅极层18，位于第二栅极层18之上的层间绝缘层2，位于层间绝缘层2之上的源漏电极层19，位于源漏电极层19之上的第一平坦化层3，位于第一平坦化层3之上的第一导电层20，位于第一导电层20之上的第二平坦化层4，位于第二平坦化层4之上的阳极层21和像素定义层22，位于阳极层21之上的发光功能层，以及位于发光功能层之上的阴极层。
需要说明的是，本公开实施例提供的如图9所示的显示基板，第一引线部仅包括第一连接引线。本公开实施例提供的如图10所示的显示基板，第一引线部仅包括第二连接引线。
在一些实施例中，有源层16的图案如图11所示。有源层例如包括各晶体管的源极接触区域、漏极接触区域以及源极接触区域和漏极接触区域之间的沟道区。在一些实施例中，有源层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，源极接触区域和漏极接触区域可为掺杂有n型杂质或p型杂质的区域。
在一些实施例中，第一栅极层17的图案如图12所示。第一栅极层例如包括存储电容的第二极、扫描信号线、复位信号线、发光控制信号线、以及各晶体管的栅极。
在一些实施例中，第二栅极层18的图案如图13所示。第二栅极层例如包括存储电容的第一极、初始化线、遮光层。其中，存储电容的第一极与存储电容的第二极至少部分交叠以形成存储电容。
在一些实施例中，层间绝缘层2的开口23的图案如图14所示。
在一些实施例中，源漏金属层19的图案如图15所示。源漏金属层例如包括第一电源信号线、数据信号线、各晶体管的源极和漏极，以及电极连接部。其中，电极连接部包括：电连接驱动晶体管的栅极和阈值补偿晶体管的漏极的栅极连接电极，栅极连接电极对应于N1节点在源漏金属层的部分。源漏金属层例如通过层间绝缘层的开口与有源层或栅极层电连接。
在一些实施例中，第一平坦化层3的开口24的图案如图16所示。
在一些实施例中，第一导电层20的图案如图17所示。第一导电层20包括第一连接引线26。第一连接引线例如通过第一平坦化层的开口与源漏电极层电连接。
在一些实施例中，第二平坦化层4的开口25的图案如图18、图19所示。其中，图18对应于图9提供的显示基板的第二平坦化层的开口的图案。图19对应于图10提供的显示基板的第二平坦化层的开口的图案。
在一些实施例中，阳极层21的图案如图20、图21所示。在一些实施例中，如图20所示，阳极层21包括发光器件的阳极。阳极通过第二平坦化层的开口以及第一平坦化层的开口与源漏电极层电连接。在一些实施例中，如图21所示阳极层21还包括第二连接引线27。阳极层通过第二平坦化层的开口以及第一平坦化层的开口与源漏电极层电连接。
在一些实施例中，像素定义层22的开口5的图案如图22所示。像素定义层的开口露出部分阳极。
在一些实施例中，第一显示区的发光器件的结构如图23所示。
在一些实施例中，第一显示区的第一导电层20的图案如图24所示。第一显示区的第一导电层20包括第一连接引线26。
在一些实施例中，第一显示区的第二平坦化层4的开口25的图案如图25所示。
在一些实施例中，第一显示区的阳极层21的图案如图26所示。
在一些实施例中，第一显示区的像素定义层22的开口5的图案如图27所示。
本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
具体实施时，显示面板可以为有机电致发光显示面板(OLED)、量子点发光显示面板(QLED)、或微发光二极管显示面板(Micro LED)。对于显示面板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示面板的实施可以参见上述显示基板的实施例，重复之处不再赘述。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的显示面板。
在一些实施例中，显示装置还包括：
取光模组，取光模组在衬底基板的正投影位于显示基板的第一显示区和第二显示区内，且取光模组位于显示基板背离出光面的一侧。
在一些实施例中，取光模组例如包括摄像头模组、光学指纹识别模组、环境光传感器等。
本公开实施例提供的显示装置为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示基板的实施例，重复之处不再赘述。
综上所述，本公开实施例提供的显示基板、显示面板及显示装置，连接 引线与第二像素驱动电路的栅极连接电极互不交叠，可以避免连接引线与第二像素驱动电路的栅极连接电极之间形成电容，进而可以避免第二像素驱动电路提供的驱动电流发生跳变，可以避免出现发光亮度不均，提高了发光亮度均一性。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板，包括显示区以及位于所述显示区之外的边框区；所述显示区包括：第一显示区，以及至少位于所述第一显示区一侧的第二显示区；
    多个发光器件，在所述衬底基板之上呈阵列排布；所述多个发光器件包括：位于所述第一显示区的多个第一发光器件，以及位于所述第二显示区的多个第二发光器件；
    多个像素驱动电路，位于所述衬底基板与所述发光器件之间；所述多个像素驱动电路包括：多个第一像素驱动电路和多个第二像素驱动电路；其中，所述多个第一像素驱动电路与所述多个第一发光器件对应电连接，所述多个第二像素驱动电路与所述多个第二发光器件相互至少部分交叠并对应电连接；所述至少一个第二像素驱动电路具有驱动晶体管、阈值补偿晶体管和栅极连接电极，所述栅极连接电极电连接所述驱动晶体管的栅极和所述阈值补偿晶体管的源极或漏极之一；
    多条连接引线，至少部分所述连接引线中的每一条与至少一个所述第一像素驱动电路和一个所述第一发光器件电连接，所述连接引线在所述衬底基板的正投影与所述栅极连接电极在所述衬底基板的正投影互不交叠。
  2. 根据权利要求1所述的显示基板，其中，所述多条连接引线位于所述多个像素驱动电路所在层背离所述衬底基板的一侧。
  3. 根据权利要求1所述的显示基板，其中，所述第二显示区包括沿第一方向排列的多个像素驱动电路列；多个所述像素驱动电路列包括：多个第一像素驱动电路列和多个第二像素驱动电路列；
    所述第一像素驱动电路列仅包括多个沿第二方向排列的所述第一像素驱动电路；所述第一方向和所述第二方向交叉；
    所述第二像素驱动电路列包括：沿所述第二方向排列的所述第一像素驱动电路，和在所述第二方向位于至少部分相邻的所述第一像素驱动电路之间 的所述第二像素驱动电路；
    所述第一显示区包括多个沿所述第一方向排列的第一发光器件列，每一所述第一发光器件列包括多个沿所述第二方向排列的所述第一发光器件；
    每一所述第一发光器件列中的各所述第一发光器件，分别与一列所述第一像素驱动电路列中的至少部分所述第一像素驱动电路电连接。
  4. 根据权利要求3所述的显示基板，其中，所述连接引线划分为：沿所述第二方向延伸的第一引线部和第二引线部，以及沿所述第一方向延伸的且与所述第一引线部和所述第二引线部电连接的第三引线部；
    所述第一引线部从所述第一像素驱动电路列引出，且与所述第一像素驱动电路列中的至少部分所述第一像素驱动电路电连接；
    所述第二引线部从所述第一发光器件列引出，且与所述第一发光器件列中的所述第一发光器件电连接；
    所述第三引线部在所述衬底基板的正投影与所述第一显示区和第二显示区互不交叠；或者，
    至少部分所述第三引线部在所述衬底基板的正投影与所述第一显示区和第二显示区互不交叠，其余部分所述第三引线部在所述衬底基板的正投影落入所述第一显示区和第二显示区。
  5. 根据权利要求4所述的显示基板，其中，所述多条连接引线包括：
    第一连接引线，位于所述像素驱动电路和所述发光器件之间，所述第一连接引线包括位于不同膜层的多层连接子引线，每层连接子引线分别电连接不同的所述第一像素驱动电路和所述第一发光器件。
  6. 根据权利要求5所述的显示基板，其中，位于不同膜层的各所述连接子引线在所述衬底基板的正投影重叠；
    或者，多层所述连接子引线中的至少两层所述连接子引线在所述衬底基板的正投影至少部分重叠；
    或者，多层所述连接子引线在所述衬底基板的正投影均不存在重叠。
  7. 根据权利要求5或6所述的显示基板，其中，所述第二引线部仅包括 所述第一连接引线；所述第一连接引线的材料包括透光材料。
  8. 根据权利要求7所述的显示基板，其中，所述透光材料为下列之一或其组合：氧化铟锡、石墨烯。
  9. 根据权利要求7所述的显示基板，其中，所述发光器件包括：依次堆叠设置的阳极、发光功能层、阴极；
    所述连接引线还包括：
    第二连接引线，与所述阳极同层设置，与所述第一连接引线电连接。
  10. 根据权利要求9所述的显示基板，其中，在所述第一显示区之外的区域，所述第一引线部和所述第三引线部中的至少一个包括电连接的所述第一连接引线和所述第二连接引线。
  11. 根据权利要求4～6、8～10任一项所述的显示基板，其中，所述第三引线部位于与所述第一显示区和所述第二显示区均相邻的所述边框区。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括：在所述边框区与所述第三引线部电连接的第三连接引线。
  13. 根据权利要求12所述的显示基板，其中，所述多个像素驱动电路中的至少一个包括栅极连接电极；所述像素驱动电路还包括：位于所述衬底基板和所述栅极连接电极之间的第一栅极层，以及位于所述第一栅极层和所述栅极连接电极之间的第二栅极层；
    所述第三连接引线与下列膜层之一同层设置：所述栅极连接电极、所述第一栅极层、所述第二栅极层。
  14. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括：第一晶体管以及存储电容；
    所述第一晶体管的栅极与第一复位信号端电连接，所述第一晶体管的源极与第一初始信号端电连接；
    所述第一晶体管的漏极、所述存储电容的第一级、所述阈值补偿晶体管的源极与所述驱动晶体管的栅极电连接；
    所述阈值补偿体管的栅极与扫描信号端电连接；
    所述存储电容的第二级与电源信号端电连接。
  15. 一种显示装置，其中，所述显示装置包括根据权利要求1～14任一项所述的显示基板。
  16. 根据权利要求15所述的显示装置，其中，所述显示装置还包括：
    取光模组，所述取光模组在所述衬底基板的正投影位于所述显示基板的第一显示区和第二显示区内，且所述取光模组位于所述显示基板背离出光面的一侧。
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