WO2022017033A1 - 时钟信号产生电路、时钟信号产生方法及电子设备 - Google Patents

时钟信号产生电路、时钟信号产生方法及电子设备 Download PDF

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Publication number
WO2022017033A1
WO2022017033A1 PCT/CN2021/099018 CN2021099018W WO2022017033A1 WO 2022017033 A1 WO2022017033 A1 WO 2022017033A1 CN 2021099018 W CN2021099018 W CN 2021099018W WO 2022017033 A1 WO2022017033 A1 WO 2022017033A1
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WIPO (PCT)
Prior art keywords
spread spectrum
clock signal
circuit
control word
initial
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PCT/CN2021/099018
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English (en)
French (fr)
Inventor
齐爱想
魏祥野
白一鸣
冯洁
王帅
赵可宁
Original Assignee
京东方科技集团股份有限公司
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Priority claimed from CN202010718719.4A external-priority patent/CN113972902B/zh
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/772,482 priority Critical patent/US11831321B2/en
Publication of WO2022017033A1 publication Critical patent/WO2022017033A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present disclosure relates to the field of communication technologies, and in particular, to a clock signal generation circuit, a clock signal generation method, and an electronic device.
  • Spread spectrum also known as spread spectrum
  • Spread spectrum is a technology that effectively suppresses electromagnetic interference generated by electronic equipment during operation by dispersing the spectral energy of a clock signal.
  • the spread spectrum function is generally realized by setting a phase-locked loop circuit and combining with a jitter method.
  • this method it is necessary to control the electronic equipment to stop working first, wait for the spread spectrum to be completed, and then control the electronic equipment to continue to work based on the clock signal obtained by the spread spectrum, and this method cannot adjust the spread spectrum depth, and the spread spectrum is flexible low sex.
  • the present disclosure provides a clock signal generating circuit, a clock signal generating method and an electronic device.
  • the technical solution is as follows:
  • a clock signal generation circuit includes: a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit;
  • the control word generation circuit is respectively connected with the initial clock generation circuit and the spread spectrum clock generation circuit, and the control word generation circuit is configured to generate the first frequency control word, the second frequency control word and the first frequency control word based on the spread spectrum parameter. Three frequency control words, outputting the first frequency control word and the second frequency control word to the initial clock generation circuit, and outputting the third frequency control word to the spread spectrum clock generation circuit;
  • the initial clock generation circuit is also connected to the spread spectrum clock generation circuit, and the initial clock generation circuit is configured to generate an initial clock signal of a target duty cycle according to the first frequency control word and the second frequency control word , and output the initial clock signal to the spread spectrum clock generation circuit;
  • the spread spectrum clock generating circuit is configured to perform spread spectrum processing on the initial clock signal according to the target duty cycle of the initial clock signal and the third frequency control word to obtain a spread spectrum clock signal.
  • the spread spectrum clock generation circuit includes: a voltage conversion subcircuit, a first reference clock generation subcircuit and a spread spectrum clock generation subcircuit;
  • the voltage conversion subcircuit is respectively connected to the initial clock generation circuit and the first reference clock generation subcircuit, and the voltage conversion subcircuit is used for converting the initial voltage to a target duty cycle of the initial clock signal. a target voltage, and provide the target voltage for the first reference clock generation sub-circuit;
  • the first reference clock generation subcircuit is further connected to the spread spectrum clock generation subcircuit, and the first reference clock generation subcircuit is configured to generate a plurality of first reference clock signals under the driving of the target voltage, and outputting the plurality of first reference clock signals to the spread spectrum clock generating sub-circuit, wherein the phase difference between any two adjacent first reference clock signals is the same;
  • the spread spectrum clock generation sub-circuit is further connected to the control word generation circuit, and the spread spectrum clock generation sub-circuit is configured to perform a pairing of the initial frequency control word according to the third frequency control word and the plurality of first reference clock signals.
  • the clock signal is subjected to spread spectrum processing to obtain a spread spectrum clock signal.
  • the first reference clock generating sub-circuit includes: a first ring oscillator.
  • the spread spectrum clock generation sub-circuit includes: a first input unit, a first selection unit and a first output unit;
  • the first input unit is respectively connected to the control word generating circuit and the first selection unit, and the first input unit is configured to output a first selection to the first selection unit according to the third frequency control word control signal;
  • the first selection unit is further connected to the first reference clock generation sub-circuit and the first output unit, respectively, and the first selection unit is configured to select from the plurality of first selection control signals in response to the first selection control signal. Selecting a first candidate clock signal from a reference clock signal, and outputting the first candidate clock signal to the first output unit;
  • the first output unit is configured to perform spread spectrum processing on the initial clock signal according to the first candidate clock signal to obtain a spread spectrum clock signal.
  • the clock signal generating circuit further includes: a power supply;
  • the power supply is connected to the voltage conversion sub-circuit, and the power supply is used to provide the initial voltage for the voltage conversion sub-circuit.
  • the initial clock generation circuit includes: a second reference clock generation subcircuit and an initial clock generation subcircuit;
  • the second reference clock generation sub-circuit is connected to the initial clock generation sub-circuit, and the second reference clock generation sub-circuit is used for generating a plurality of second reference clock signals under the driving of a reference voltage, and converting the outputting a plurality of second reference clock signals to the initial clock generating sub-circuit, wherein the phase difference between any two adjacent second reference clock signals is the same;
  • the initial clock generation subcircuit is further connected to the control word generation circuit and the spread spectrum clock generation circuit, respectively, and the initial clock generation subcircuit is used to control the word according to the first frequency and the second frequency.
  • the initial clock signal is generated by the word and the plurality of second reference clock signals, and the initial clock signal is output to the spread spectrum clock generation circuit.
  • the second reference clock generating sub-circuit includes: a second ring oscillator.
  • the initial clock generation sub-circuit includes: a second input unit, a second selection unit and a second output unit;
  • the second input unit is respectively connected with the control word generating circuit and the second selection unit, and the second input unit is configured to send the signal to the desired frequency according to the first frequency control word and the second frequency control word.
  • the second selection unit outputs a second selection control signal;
  • the second selection unit is further connected to the second reference clock generation sub-circuit and the second output unit, respectively, and the second selection unit is configured to select from the plurality of second output units in response to the second selection control signal. Selecting a second candidate clock signal from the two reference clock signals, and outputting the second candidate clock signal to the second output unit;
  • the second output unit is also connected to the spread spectrum clock generating circuit, and the second output unit is configured to generate the initial clock signal according to the second candidate clock signal, and output the initial clock signal to The spread spectrum clock generating circuit.
  • both the first frequency control word and the second frequency control word are positive integers.
  • the third frequency control word includes an integer part and a fractional part.
  • the spread spectrum parameter includes at least one of the following parameters: a spread spectrum type parameter, a spread spectrum depth parameter, and a center frequency parameter.
  • a method for generating a clock signal comprising:
  • the control word generation circuit generates a first frequency control word, a second frequency control word and a third frequency control word based on the spread spectrum parameter, and outputs the first frequency control word and the second frequency control word to the initial clock generation circuit, and outputting the third frequency control word to a spread spectrum clock generating circuit;
  • the initial clock generation circuit generates an initial clock signal of a target duty cycle according to the first frequency control word and the second frequency control word, and outputs the initial clock signal to the spread spectrum clock generation circuit;
  • the spread spectrum clock generating circuit performs spread spectrum processing on the initial clock signal according to the target duty cycle of the initial clock signal and the third frequency control word to obtain a spread spectrum clock signal.
  • the spread spectrum clock generation circuit includes: a voltage conversion subcircuit, a first reference clock generation subcircuit and a spread spectrum clock generation subcircuit;
  • the spread spectrum clock generation circuit performs spread spectrum processing on the initial clock signal according to the target duty cycle of the initial clock signal and the third frequency control word to obtain a spread spectrum clock signal, including:
  • the voltage conversion subcircuit converts the initial voltage into a target voltage according to the target duty cycle of the initial clock signal, and provides the first reference clock generation subcircuit with the target voltage;
  • the first reference clock generation sub-circuit is driven by the target voltage to generate a plurality of first reference clock signals, and output the plurality of first reference clock signals to the spread spectrum clock generation sub-circuit, wherein , the phase difference between any two adjacent first reference clock signals is the same;
  • the spread spectrum clock generating sub-circuit performs spread spectrum processing on the initial clock signal according to the third frequency control word and the plurality of first reference clock signals to obtain a spread spectrum clock signal.
  • an electronic device comprising: a controlled circuit, and the clock signal generating circuit according to the above aspect;
  • the clock signal generating circuit is connected to the controlled circuit, and the controlled circuit is configured to work in response to the spread spectrum clock signal output by the clock signal generating circuit.
  • FIG. 1 is a schematic structural diagram of a clock signal generating circuit provided by an embodiment of the present disclosure
  • FIG. 2 is an architectural diagram of a control word generation circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another clock signal generating circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a voltage conversion sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a first reference clock generation sub-circuit provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a first reference clock signal provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a spread spectrum clock generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another spread spectrum clock generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another spread spectrum clock generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a signal synthesis provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another clock signal generating circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of an initial clock generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for generating a clock signal provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • Noise generated by power supplies included in electronic equipment and noise generated by clock signal generating circuits are major sources of electromagnetic interference.
  • the noise generated by the power supply can generally be called the noise floor, and the noise generated by the clock signal generating circuit can generally be called the characteristic frequency noise.
  • the eigenfrequency noise has a serious impact on the operation of electronic equipment.
  • the eigenfrequency noise may occupy a key channel or have a coupling effect with other circuits, causing the operating frequency of the electronic equipment to drift, and even lead to abnormal operation or downtime of the electronic equipment. machine.
  • external electromagnetic radiation can generally be reduced by adjusting the wiring mode on the circuit board.
  • an iron case can be used to shield the electromagnetic interference and cut off the propagation path of the electromagnetic interference.
  • spread spectrum processing can be performed on the interference source (ie, the clock signal generated by the clock signal generating circuit) in the manner of dithering.
  • the method of adjusting the wiring or setting the iron casing is relatively expensive.
  • the embodiment of the present disclosure provides a clock signal generating circuit, which can realize the spread spectrum processing of the clock signal without affecting the normal operation of the electronic device, and can realize the spread spectrum depth, center frequency and/or spread spectrum type. real-time adjustment.
  • the clock signal generation circuit can not only effectively suppress electromagnetic interference, but also has higher flexibility of spread spectrum compared with related technologies, and because it does not need to control the electronic equipment to stop working during spread spectrum processing, it also reduces the power of the electronic equipment to a certain extent. power consumption and improve the robustness of electronic devices.
  • FIG. 1 is a schematic structural diagram of a clock signal generating circuit provided by an embodiment of the present disclosure.
  • the clock signal generating circuit may include: a control word generating circuit 10 , an initial clock generating circuit 20 and a spread spectrum clock generating circuit 30 .
  • the control word generation circuit 10 can be connected to the initial clock generation circuit 20 and the spread spectrum clock generation circuit 30, respectively.
  • the control word generation circuit 10 can be configured to generate a first frequency control word, a second frequency control word and a third frequency control word based on the spread spectrum parameter, and output the first frequency control word and the second frequency control word to the initial clock generation circuit 20, and output the third frequency control word to the spread spectrum clock generation circuit 30.
  • the spread spectrum parameter refers to a related parameter that affects the output result of the spread spectrum clock generation circuit 30, that is, the spread spectrum effect.
  • the spread spectrum parameter can be input to the control word generation circuit 10 by a user (eg, a developer), or, the control word generation circuit 10 can be preconfigured with a variety of different spread spectrum parameters for the user to select or for.
  • the control word generation circuit 10 is called directly.
  • the spread spectrum parameter may be the spread spectrum depth.
  • the initial clock generation circuit 20 may also be connected to the spread spectrum clock generation circuit 30 .
  • the initial clock generation circuit 20 may be configured to generate an initial clock signal of a target duty cycle according to the first frequency control word and the second frequency control word, and output the initial clock signal to the spread spectrum clock generation circuit 30 .
  • the target duty cycle is represented by D
  • the first frequency control word is represented by F1
  • the second frequency control word is represented by F2 (all the following embodiments are represented by the same characters).
  • the high potential duration of the initial clock signal is related to the second frequency control word F2
  • the low potential duration of the initial clock signal is related to the difference between the first frequency control word F1 and the second frequency control word F2: F1-F2
  • the spread spectrum clock generating circuit 30 can also be configured to perform spread spectrum processing on the initial clock signal according to the target duty cycle of the initial clock signal and the third frequency control word to obtain a spread spectrum clock signal.
  • control word generation circuit 10 since both the initial clock generation circuit 20 and the spread spectrum clock generation circuit 30 work based on the frequency control word provided by the control word generation circuit 10, the control word generation circuit 10 may also be called a control block. .
  • the embodiments of the present disclosure provide a clock signal generating circuit. Since the clock signal generation circuit is composed of digital circuits such as the control word generation circuit, the initial clock generation circuit and the spread spectrum clock generation circuit, the frequency control word is first generated based on the spread spectrum parameters, and then the target duty cycle is generated based on the frequency control word.
  • the initial clock signal, and the spread spectrum clock signal obtained by performing spread spectrum processing based on the target duty cycle of the initial clock signal, that is, the entire spectrum spread process is performed by a digital circuit, so there is no need to control the electronic equipment including the clock signal generation circuit to stop working, That is, it does not affect the normal operation of electronic equipment.
  • the clock signal generating circuit provided by the present disclosure can realize real-time adjustment of various spread spectrum parameters (eg, spread spectrum depth) that affect the spread spectrum result, and the spread spectrum flexibility is high.
  • the spread spectrum parameter may include at least one of the following parameters: a spread spectrum type (modulation type) parameter, a spread spectrum depth (modulation depth) parameter, and a center frequency (center frequency) parameter.
  • the spread spectrum type refers to the spread spectrum method used in the spread spectrum processing, such as linear modulation, and the spread spectrum type determines the expression form of the spread spectrum clock signal.
  • the spread spectrum depth refers to the magnitude by which the frequency of the spread spectrum clock signal deviates from the frequency of the initial clock signal at a fixed speed, and the spread spectrum depth determines the peak value of the spread spectrum clock signal.
  • the center frequency refers to the arithmetic mean of the frequency of the spread spectrum clock signal, and the center frequency determines the size of the minimum frequency and the maximum frequency of the spread spectrum clock signal.
  • FIG. 2 is an architectural diagram of a control word generating circuit provided by an embodiment of the present disclosure.
  • the control word generation circuit 10 may include an input interface of a spread spectrum type, an input interface of a spread spectrum depth, and an input interface of a center frequency, and the three input interfaces can be used by the user to input corresponding input interfaces according to the required spread spectrum results. parameter.
  • the control word generating circuit 10 After receiving the spread spectrum parameter, the control word generating circuit 10 generally generates a total frequency control word F based on the spread spectrum parameter, and then splits the total frequency control word F into the first frequency control word.
  • the second frequency control word F2 and the third frequency control word F3 are provided to the initial clock generation circuit 20 and the spread spectrum clock generation circuit 30, respectively.
  • the splitting method depends on the required spread spectrum result, which refers to the type, frequency and period of the spread spectrum clock signal to be finally generated. And the spread spectrum result can generally be input by the user or pre-configured in the control word generating circuit 10 .
  • FIG. 3 is a schematic structural diagram of another clock signal generating circuit provided by an embodiment of the present disclosure.
  • the spread spectrum clock generation circuit 30 may include: a voltage conversion subcircuit 301 , a first reference clock generation subcircuit 302 and a spread spectrum clock generation subcircuit 303 .
  • the voltage conversion subcircuit 301 may be connected to the initial clock generation circuit 20 and the first reference clock generation subcircuit 302, respectively.
  • the voltage conversion sub-circuit 301 can convert the initial voltage into a target voltage according to the target duty cycle of the initial clock signal, and provide the first reference clock generation sub-circuit 302 with the target voltage. Since the function of the voltage conversion sub-circuit 301 is voltage conversion, the voltage conversion sub-circuit 301 may also be referred to as a voltage switching circuit.
  • the target voltage may be positively correlated with both the target duty cycle and the initial voltage. That is, the larger the target duty cycle, the higher the target voltage; the smaller the target duty cycle, the lower the target voltage. Similarly, the larger the initial voltage, the larger the target voltage; the smaller the initial voltage, the smaller the target voltage. Moreover, the target voltage and the voltage conversion efficiency of the voltage conversion sub-circuit 301 may also be positively correlated, that is, the higher the voltage conversion efficiency, the higher the target voltage, and the lower the voltage conversion efficiency, the lower the target voltage.
  • the initial voltage may be provided by a power supply module, such as a power supply.
  • the clock signal generating circuit may further include a power supply 40 , which may be connected to the voltage conversion sub-circuit 301 and provide the voltage conversion sub-circuit 301 with an initial voltage.
  • the initial clock generation circuit 20 can be made to generate initial clock signals with different target duty cycles based on the different frequency control words.
  • the voltage conversion sub-circuit 301 can convert the initial voltage provided by the power supply 40 into different target voltages based on different target duty cycles, so that the target voltage output to the first reference clock generation sub-circuit 302 can be adjusted to be: Subsequent spread spectrum laid the foundation.
  • FIG. 4 is a schematic structural diagram of a voltage conversion sub-circuit 301 provided by an embodiment of the present disclosure.
  • the voltage conversion sub-circuit 301 may include: a transistor M1 , a diode D1 , an inductor L1 , a capacitor C1 and a resistor R1 .
  • the gate of the transistor M1 can be connected to the initial clock generation circuit 20 (not shown in FIG. 4 ), the first pole of the transistor M1 can be connected to the first pole of the power supply 40 , and the second pole of the transistor M1 can be connected to the inductor L1 one end of the connection.
  • the other end of the inductor L1 may be respectively connected to one end of the diode D1, one end of the capacitor C1 and one end of the resistor R1, and may be connected to the first end (not shown in FIG. 4 ) of the first reference clock generating sub-circuit 302 .
  • the other end of the diode D1, the other end of the capacitor C1 and the other end of the resistor R1 can be respectively connected to the second pole of the power supply 40 and the second end of the first reference clock generating sub-circuit 302 (not shown in FIG. 4 ). ).
  • the initial clock generation circuit 20 can output the generated initial clock signal of the target duty cycle to the gate of the transistor M1.
  • the transistor M1 when the potential of the initial clock signal is an effective potential, the transistor M1 is turned on, and the initial voltage Vi can be output to one end of the inductor L1 through the transistor M1, and then converted through the inductor L1, the diode D1, the capacitor C1 and the resistor R1. is the target voltage Vo.
  • the triode M1 is turned off, and the initial voltage Vi cannot be output to one end of the inductor L1 through the triode M1.
  • turning on the transistor M1 can also be called charging, and turning off the transistor M1 can also be called discharging.
  • the first reference clock generation sub-circuit 302 may also be connected to the spread spectrum clock generation sub-circuit 303 .
  • the first reference clock generation sub-circuit 302 can generate a plurality of first reference clock signals under the driving of the target voltage, and output the plurality of first reference clock signals to the spread spectrum clock generation sub-circuit 303, wherein any two
  • the phase difference between adjacent first reference clock signals may be the same, and the period and frequency of each first reference clock signal are the same. Since the target voltage is adjustable, correspondingly, the frequency of the first reference clock signal generated by the first reference clock generation sub-circuit 302 can be adjusted.
  • the first reference clock generating sub-circuit 302 may include: a first ring oscillator (ring oscillator, RO), that is, RO1.
  • the first ring oscillator RO1 may be composed of a plurality of NAND gates, and if there are N inputs, the first ring oscillator RO1 may generate 2N outputs, where N is generally equal to 2 n , and n is greater than or equal to 2.
  • FIG. 5 shows a schematic structural diagram of the first ring oscillator RO1. Referring to FIG.
  • the first ring oscillator RO1 has a total of 16 output terminals P1 to P16, and the first ring oscillator RO1 (ie, the first reference clock generating sub-circuit 302) can pass through the 16 output terminals P1 to P16 are connected to the spread spectrum clock generation subcircuit 303 .
  • FIG. 6 shows a schematic diagram of a plurality of first reference clock signals by taking the first reference clock generating sub-circuit 302 generating k first reference clock signals as an example. And, referring to FIG. 6 , it can be seen that the phase difference between every two adjacent first reference clock signals is ⁇ .
  • the number k of the first reference clock signals that can be generated by the first reference clock generation sub-circuit 302 may be pre-configured in the first reference clock generation sub-circuit 302 .
  • it can be provided in the circuit by the user when the circuit is produced.
  • k may be 2 to the power of i, and i may be an integer greater than or equal to 1.
  • k can be 16, 32, 128 or others.
  • the spread spectrum clock generation sub-circuit 303 may also be connected to the control word generation circuit 10, and the spread spectrum clock generation sub-circuit 303 may be used for pairing the initial clock signal according to the third frequency control word and a plurality of first reference clock signals Spread spectrum processing is performed to obtain a spread spectrum clock signal.
  • the period of the spread spectrum clock signal may be negatively correlated with the third frequency control word, the frequency of the first reference clock signal and the number of generated first reference clock signals. That is, the larger the third frequency control word is, the smaller the period of the spread spectrum clock signal is, and the smaller the third frequency control word is, the larger the period of the spread spectrum clock signal is. Similarly, the larger the frequency of the first reference clock signal, the smaller the period of the spread spectrum clock signal, the smaller the frequency of the first reference clock signal, the larger the period of the spread spectrum clock signal. The larger the number of the first reference clock signals, the smaller the period of the spread spectrum clock signal, and the smaller the number of the first reference clock signals, the larger the period of the spread spectrum clock signal.
  • the output range of the first reference clock generation sub-circuit 302 can be further expanded, and the adjustability of the spread spectrum clock signal is enhanced.
  • the third frequency control word F3 may generally include an integer part and a decimal part.
  • FIG. 7 is a schematic structural diagram of a spread spectrum clock generation sub-circuit 303 provided by an embodiment of the present disclosure.
  • the spread spectrum clock generation sub-circuit 303 may include: a first input unit 3031 , a first selection unit 3032 and a first output unit 3033 .
  • the first input unit 3031 may be connected to the control word generation circuit 10 (not shown in the figure) and the first selection unit 3032, respectively.
  • the first input unit 3031 may be configured to output a first selection control signal to the first selection unit 3032 according to the third frequency control word F3.
  • the first selection unit 3032 may also be connected to the first reference clock generation sub-circuit 302 (not shown in the figure) and the first output unit 3033, respectively.
  • the first selection unit 3032 may be configured to select a first candidate clock signal from the plurality of first reference clock signals in response to the first selection control signal, and output the first candidate clock signal to the first output unit 3033 .
  • the first output unit 3033 may be configured to perform spread spectrum processing on the initial clock signal according to the first candidate clock signal to obtain a spread spectrum clock signal.
  • the first input unit 3031 may include multiple registers and multiple accumulators
  • the first selection unit 3032 may include three selectors
  • the first output unit 3033 may include flip flip-flops.
  • the registers may include: a first register R1, a second register R2, a third register R3 and a fourth register R4, and the adder may include: two adders J11 and J12.
  • the selectors may include: a first selector X1, a second selector X2 and a third selector X3.
  • the flip flip-flop may include: a D flip-flop, a first inverter F1 and a second inverter F2.
  • the two adders J11 and J12 can be connected to the control word generating circuit 10 respectively, and one adder J11, the first register R1, the second register R2 and the first selector X1 are connected in sequence; the other adder J12, The third register R3, the fourth register R4 and the second selector X2 are connected in sequence.
  • the two adders J11 and J12 shown in FIG. 9 are both connected to the connection line connecting the third register R3 and the fourth register R4.
  • the first selector X1 and the second selector X2 can be connected to the first reference clock generating sub-circuit 302 and the third selector X3 respectively, and the third selector X3 can also be connected to the first input terminal of the D flip-flop.
  • the second input terminal of the D flip-flop may be connected to the output terminal of the first inverter F1, and the input terminal of the first inverter F1 and the input terminal of the second inverter F2 may be connected to the output terminal of the D flip-flop.
  • the output terminal of the D flip-flop can be used as the output of the first clock signal terminal CLK1
  • the output terminal of the second inverter F2 can be used as the output of the second clock signal terminal CLK2
  • the first clock signal terminal CLK1 The clock signal provided by the second clock signal terminal CLK2 only has the opposite phase and the same frequency.
  • the first selector X1 and the second selector X2 can both be the k->1 selector shown in FIG.
  • One first reference clock signal is selected from among the K first reference clock signals).
  • the third selector X3 is used to select one of the two, in conjunction with FIG. 9 , the third selector X3 can be a 2->1 selector (that is, select one first reference clock signal from the two first reference clock signals) alternative clock signal).
  • an adder J11 can add a portion of the third frequency control word F3 (F3/2 as shown in FIG. 9) and the most significant bit (eg, 5 bits) stored in the third register R3, and then When the rising edge of the second clock signal provided by the clock signal terminal CLK2, the addition result is stored in the first register R1; The information is added, and then the addition result is stored in the first register R1 at the rising edge of the second clock signal. At the next rising edge of the first clock signal, the most significant bit stored in the first register R1 will be stored in the second register R2 and used as the selection signal of the first selector X1.
  • the first selector X1 may select one first reference clock signal from the k first reference clock signals as the output signal of the first selector X1 and output it to the third selector X3 in response to the selection signal.
  • another adder J12 can add the third frequency control word F3 and the most significant bits stored in the third register R3, and then save the addition result to the third register R3 at the rising edge of the second clock signal CLK2. middle.
  • another adder J12 may add up all the information stored in the third frequency control word F3 and the third register R3, and then save the addition result in the third register R3 at the rising edge of the second clock signal CLK2.
  • the most significant bit stored in the third register R3 will be stored in the fourth register R4 and used as the selection signal of the second selector X2.
  • the second selector X2 may select a first reference clock signal from the k first reference clock signals in response to the selection signal as an output signal of the second selector X2 and output it to the third selector X3.
  • the third selector X3 can select one of the output signal from the first selector X1 and the output signal from the first selector X2 as the output of the third selector X3 at the rising edge of the first clock signal
  • the signal is output to the D flip-flop as the input clock signal of the D flip-flop.
  • the clock signal output by one of the output end of the D flip-flop and the output end of the second inverter F2 can be used as the final output signal, so far, the generation of the spread spectrum clock signal is realized.
  • the selection signal output by the fourth register R4 can be used as the falling edge selection signal
  • the selection signal output by the second register R2 can be used as the rising edge selection signal
  • the signal fed back to the adder J12 by the third register R3 can be used to control the generation of cycle of the clock to switch.
  • the selection signal output by the fourth register R4 may be called a falling edge control word
  • the selection signal output by the second register R2 may be called a rising edge control word.
  • the spread spectrum clock generation subcircuit 303 described in the embodiment of the present disclosure may be referred to as a time-average-frequency direct period synthesis (TAF-DPS) circuit based on a time-average frequency.
  • TAF-DPS time-average-frequency direct period synthesis
  • the working principle of the TAF-DPS circuit is schematically illustrated with reference to FIG. 10 :
  • T B (I1+1) ⁇ Formula (4)
  • the clock signal whose period is T A and the clock signal whose period is T B can be synthesized by the "periodic synthesis" technique to obtain a clock signal whose period is the target period, and the target period T TAF can satisfy:
  • T TAF (1-r1) ⁇ T A +r1 ⁇ T B formula (5);
  • T B r1 occurrence probability can be controlled, i.e., the frequency control word F is the fractional part of r1 may control the switching frequency between the period T A and T B.
  • the frequency f TAF of the clock signal output by the TAF-DPS circuit satisfies:
  • I11 is the integer part of the third frequency control word F3
  • r11 is the fractional part of the third frequency control word F3.
  • the spread spectrum clock generation sub-circuit 303 provided by the embodiment of the present disclosure can directly synthesize pulses (ie, clock signals) instead of traditional frequency synthesis. This method also enables the electronic device to keep working normally when the clock frequency is switched.
  • FIG. 11 is a schematic structural diagram of still another clock generation circuit provided by an embodiment of the present disclosure.
  • the initial clock generation circuit 20 may include: a second reference clock generation sub-circuit 201 and an initial clock generation sub-circuit 202 .
  • the second reference clock generation sub-circuit 201 may be connected to the initial clock generation sub-circuit 202 .
  • the second reference clock generation sub-circuit 201 may be configured to generate a plurality of second reference clock signals under the driving of the reference voltage, and output the plurality of second reference clock signals to the initial clock generation sub-circuit 202, wherein any two The phase difference between adjacent second reference clock signals is the same, and the frequency and period of each second reference clock signal are the same, for example, the frequency of each second reference clock signal is f2.
  • the second reference clock generation sub-circuit 201 may include: a second ring oscillator RO2, the second ring oscillator RO2 and the first ring oscillator RO1 have the same structure and working principle, It is not repeated here.
  • the difference between the second ring oscillator RO2 (ie, the second reference clock generating sub-circuit 201 ) and the first ring oscillator RO1 (ie, the first reference clock generating sub-circuit 301 ) is that the second reference clock generating sub-circuit 201 It operates under a fixed voltage (ie, a reference voltage), and the frequency of the generated second reference clock signal is stable.
  • the first reference clock generating sub-circuit 301 operates under a variable target voltage, and the frequency of the generated first reference clock signal is adjustable.
  • the initial clock generation subcircuit 202 may also be connected to the control word generation circuit 10 and the spread spectrum clock generation circuit 30 (eg, the voltage conversion subcircuit 301 included in the spread spectrum clock generation circuit 30 ), respectively.
  • the initial clock generation sub-circuit 202 can be used to generate an initial clock signal according to the first frequency control word F1, the second frequency control word F2 and a plurality of second reference clock signals, and output the initial clock signal to the spread spectrum clock generation circuit 30 .
  • FIG. 12 is a schematic structural diagram of an initial clock generation sub-circuit 202 provided by an embodiment of the present disclosure.
  • the initial clock generation sub-circuit 202 may include: a second input unit 2021 , a second selection unit 2022 and a second output unit 2023 .
  • the second input unit 2021 may be connected to the control word generating circuit 10 (not shown in the figure) and the second selection unit 2022, respectively.
  • the second input unit 2021 may be configured to output a second selection control signal to the second selection unit 2022 according to the first frequency control word F1 and the second frequency control word F2.
  • the second selection unit 2022 may also be connected to the second reference clock generation sub-circuit 201 and the second output unit 2023, respectively.
  • the second selection unit 2022 may be configured to select a second candidate clock signal from the plurality of second reference clock signals in response to the second selection control signal, and output the second candidate clock signal to the second output unit 2023 .
  • the second output unit 2023 may also be connected to the spread spectrum clock generation circuit 30 (not shown in the figure).
  • the second output unit 2023 may be configured to generate an initial clock signal according to the second candidate clock signal, and output the initial clock signal to the spread spectrum clock generation circuit 30 .
  • the structure and working principle of each unit included in the initial clock generation sub-circuit 202 are the same as the structure and working principle of each unit included in the spread spectrum clock generation sub-circuit 303, and will not be repeated here. To repeat, the difference is that the frequency control words received by the initial clock generation sub-circuit 202 and the spread spectrum clock generation sub-circuit 303 are different, and correspondingly, the output results are also different. Therefore, the initial clock generation sub-circuit 202 can also be a TAF-DPS circuit.
  • TAF-DPS1 is used to represent the spread spectrum clock generation sub-circuit 303
  • TAF-DPS2 is used to represent the initial clock generation sub-circuit 202
  • TAF-DPS2 is mainly used to generate the initial clock signal of the target duty cycle.
  • the first frequency control word F1 and the second frequency control word F2 provided by the control word generation circuit 10 to the initial clock generation sub-circuit 202 may both be positive integers.
  • TAF-DPS1 and TAF-DPS2 By setting TAF-DPS1 and TAF-DPS2, it can ensure a wider adjustment range for frequency during spread spectrum processing, and because TAF-DPS2 can generate an initial clock signal with a target duty cycle, the voltage conversion sub-circuit 301 can be based on the target.
  • the initial clock signal of the duty cycle directly changes the initial voltage provided by the power supply 40, which ensures the adjustment accuracy, and further ensures the accuracy of the generated spread spectrum clock signal.
  • the second reference clock generation sub-circuit 201 (eg, the second ring oscillator RO2 ) first generates a plurality of (eg, k) second reference clock signals with the frequency f2 under the driving of the reference voltage, and outputs them to the initial clock generation Subcircuit 202 (eg, TAF-DPS2). Then, the initial clock generation sub-circuit 202 generates an initial clock signal of the target duty cycle based on the received first frequency control word F1, the second frequency control word F2, the number k of the second reference clock signal and the frequency f2 and outputs it to Voltage conversion subcircuit 301 .
  • the initial clock generation Subcircuit 202 eg, TAF-DPS2
  • the voltage conversion sub-circuit 301 converts the initial voltage provided by the power supply 40 into a target voltage based on the target duty cycle, and provides the target voltage to the first reference clock generation sub-circuit 302 .
  • the first reference clock generating sub-circuit 302 eg, the first ring oscillator RO1
  • the spread spectrum clock generation sub-circuit 303 may generate a spread spectrum clock signal based on the received third frequency control word F3 and the second reference clock signal.
  • the first frequency control sub F1 can be controlled to be fixed, and the second frequency control word F2 can be uniformly adjusted within a certain range.
  • the uniform change of Vo will further cause the first reference clock generation sub-circuit 302 , that is, the oscillation frequency of the first ring oscillator RO1 to change uniformly, so as to achieve uniform adjustment of the frequency f1 of the second reference clock signal.
  • the spread spectrum clock generation circuit 30 realizes different types of spread spectrum processing on the original clock signal.
  • the whole circuit structure has the advantages of high frequency spread, simple structure, small size and low power consumption, which can not only ensure the normal operation of electronic equipment, but also reliably suppress electromagnetic interference.
  • the embodiments of the present disclosure provide a clock signal generating circuit. Since the clock signal generation circuit is composed of digital circuits such as the control word generation circuit, the initial clock generation circuit and the spread spectrum clock generation circuit, the frequency control word is first generated based on the spread spectrum parameters, and then the target duty cycle is generated based on the frequency control word. The initial clock signal, and the spread spectrum processing based on the target duty cycle of the initial clock signal to obtain a spread spectrum clock signal, that is, the entire spread spectrum process is performed by a digital circuit, so there is no need to control the electronic equipment including the clock signal generation circuit to stop working , that is, it does not affect the normal operation of electronic equipment. Moreover, the clock signal generating circuit provided by the present disclosure can realize real-time adjustment of various spread spectrum parameters (eg, spread spectrum depth) that affect the spread spectrum result, and the spread spectrum flexibility is high.
  • various spread spectrum parameters eg, spread spectrum depth
  • FIG. 13 is a clock signal generating method provided by an embodiment of the present disclosure, and the method may be applied to the clock signal generating circuit shown in any one of FIG. 1 , FIG. 3 and FIG. 11 . As shown in Figure 13, the method may include:
  • Step 1301 the control word generation circuit generates the first frequency control word, the second frequency control word and the third frequency control word based on the spread spectrum parameter, outputs the first frequency control word and the second frequency control word to the initial clock generation circuit, and The third frequency control word is output to the spread spectrum clock generation circuit.
  • Step 1302 The initial clock generation circuit generates an initial clock signal of the target duty cycle according to the first frequency control word and the second frequency control word, and outputs the initial clock signal to the spread spectrum clock generation circuit.
  • Step 1303 The spread spectrum clock generating circuit performs spread spectrum processing on the initial clock signal according to the target duty cycle of the initial clock signal and the third frequency control word, to obtain a spread spectrum clock signal.
  • the embodiments of the present disclosure provide a method for generating a clock signal, because the method can generate a frequency control word based on a spread spectrum parameter, can generate an initial clock signal of a target duty cycle according to the frequency control word, and The target duty cycle of the clock signal is subjected to spread spectrum processing to obtain a spread spectrum clock signal.
  • the entire spectrum spreading process is a digital processing process, and there is no need to control the electronic equipment including the clock signal generating circuit to stop working, that is, the normal operation of the electronic equipment is not affected.
  • real-time adjustment of the spread spectrum depth, spread spectrum type and/or center frequency can be realized, and the spread spectrum flexibility is high.
  • FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • the electronic device may include: a controlled circuit 01 , and a clock signal generating circuit 02 as shown in any one of FIG. 1 , FIG. 3 and FIG. 11 .
  • the clock signal generating circuit 02 can be connected to the controlled circuit 01 , and the controlled circuit 01 can be used to work in response to the spread spectrum clock signal output by the clock signal generating circuit 02 .
  • the first reference clock generation subcircuit 302 and the second reference clock generation subcircuit 201 are both ring oscillators (RO1 and RO2), and the spread spectrum clock generation subcircuit 303 and the initial clock generation subcircuit 202 are both
  • the TAF-DPS circuits (TAF-DPS1 and TAF-DPS2) are taken as an example to show a schematic diagram of the clock signal generating circuit 02 .

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Abstract

提供了一种时钟信号产生电路、时钟信号产生方法及电子设备，属于通信技术领域。由于该时钟信号产生电路中，是由控制字生成电路、初始时钟生成电路和展频时钟生成电路等数字电路，先基于展频参数生成频率控制字，再基于频率控制字生成目标占空比的初始时钟信号，最后再基于该初始时钟信号的目标占空比和频率控制字进行展频处理得到展频时钟信号，即整个展频过程由数字电路执行，因此无需控制包括该时钟信号产生电路的电子设备停止工作，即不影响电子设备正常运转。且该时钟信号产生电路可以实现对各类影响展频结果的展频参数(如，展频深度)的实时调节，展频灵活性较高。

Description

时钟信号产生电路、时钟信号产生方法及电子设备
本公开要求于2020年7月23日提交的申请号为202010718719.4、发明名称为“时钟信号产生电路、时钟信号产生方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及通信技术领域，特别涉及一种时钟信号产生电路、时钟信号产生方法及电子设备。
背景技术
展频(也称扩展频谱)是一种通过分散时钟信号的频谱能量，来有效抑制电子设备工作时产生的电磁干扰的技术。
相关技术中，一般通过设置锁相环电路并结合抖动(jitter)的方法来实现展频功能。但是，采用该方法进行展频时，需要先控制电子设备停止工作，等待展频完成后，再控制电子设备基于展频得到的时钟信号继续工作，且该方法无法调节展频深度，展频灵活性较低。
发明内容
本公开提供了一种时钟信号产生电路、时钟信号产生方法及电子设备。所述技术方案如下：
一方面，提供了一种时钟信号产生电路，所述时钟信号产生电路包括：控制字生成电路、初始时钟生成电路和展频时钟生成电路；
所述控制字生成电路分别与所述初始时钟生成电路和所述展频时钟生成电路连接，所述控制字生成电路用于基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将所述第一频率控制字和所述第二频率控制字输出至所述初始时钟生成电路，并将所述第三频率控制字输出至所述展频时钟生成电路；
所述初始时钟生成电路还与所述展频时钟生成电路连接，所述初始时钟生 成电路用于根据所述第一频率控制字和所述第二频率控制字生成目标占空比的初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路；
所述展频时钟生成电路用于根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号。
可选的，所述展频时钟生成电路包括：电压转换子电路、第一基准时钟生成子电路和展频时钟生成子电路；
所述电压转换子电路分别与所述初始时钟生成电路和所述第一基准时钟生成子电路连接，所述电压转换子电路用于根据所述初始时钟信号的目标占空比将初始电压转换为目标电压，并为所述第一基准时钟生成子电路提供所述目标电压；
所述第一基准时钟生成子电路还与所述展频时钟生成子电路连接，所述第一基准时钟生成子电路用于在所述目标电压的驱动下，生成多个第一基准时钟信号，并将所述多个第一基准时钟信号输出至所述展频时钟生成子电路，其中，任意两个相邻的所述第一基准时钟信号之间的相位差相同；
所述展频时钟生成子电路还与所述控制字生成电路连接，所述展频时钟生成子电路用于根据所述第三频率控制字和所述多个第一基准时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
可选的，所述第一基准时钟生成子电路包括：第一环路振荡器。
可选的，所述展频时钟生成子电路包括：第一输入单元、第一选择单元和第一输出单元；
所述第一输入单元分别与所述控制字生成电路和所述第一选择单元连接，所述第一输入单元用于根据所述第三频率控制字向所述第一选择单元输出第一选择控制信号；
所述第一选择单元还分别与所述第一基准时钟生成子电路和所述第一输出单元连接，所述第一选择单元用于响应于所述第一选择控制信号从所述多个第一基准时钟信号中选择一个第一备选时钟信号，并将所述第一备选时钟信号输出至所述第一输出单元；
所述第一输出单元用于根据所述第一备选时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
可选的，所述时钟信号产生电路还包括：电源；
所述电源与所述电压转换子电路连接，所述电源用于为所述电压转换子电路提供所述初始电压。
可选的，所述初始时钟生成电路包括：第二基准时钟生成子电路和初始时钟生成子电路；
所述第二基准时钟生成子电路与所述初始时钟生成子电路连接，所述第二基准时钟生成子电路用于在基准电压的驱动下，生成多个第二基准时钟信号，并将所述多个第二基准时钟信号输出至所述初始时钟生成子电路，其中，任意两个相邻的所述第二基准时钟信号之间的相位差相同；
所述初始时钟生成子电路还分别与所述控制字生成电路和所述展频时钟生成电路连接，所述初始时钟生成子电路用于根据所述第一频率控制字、所述第二频率控制字和所述多个第二基准时钟信号生成所述初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路。
可选的，所述第二基准时钟生成子电路包括：第二环路振荡器。
可选的，所述初始时钟生成子电路包括：第二输入单元、第二选择单元和第二输出单元；
所述第二输入单元分别与所述控制字生成电路和所述第二选择单元连接，所述第二输入单元用于根据所述第一频率控制字和所述第二频率控制字，向所述第二选择单元输出第二选择控制信号；
所述第二选择单元还分别与所述第二基准时钟生成子电路和所述第二输出单元连接，所述第二选择单元用于响应于所述第二选择控制信号从所述多个第二基准时钟信号中选择一个第二备选时钟信号，并将所述第二备选时钟信号输出至所述第二输出单元；
所述第二输出单元还与所述展频时钟生成电路连接，所述第二输出单元用于根据所述第二备选时钟信号生成所述初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路。
可选的，所述第一频率控制字和所述第二频率控制字均为正整数。
可选的，所所述第三频率控制字包括整数部分和小数部分。
可选的，所述展频参数包括下述参数中的至少一种：展频类型参数、展频深度参数和中心频率参数。
另一方面，提供了一种时钟信号产生方法，所述方法包括：
控制字生成电路基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将所述第一频率控制字和所述第二频率控制字输出至初始时钟生成电路，并将所述第三频率控制字输出至展频时钟生成电路；
所述初始时钟生成电路根据所述第一频率控制字和所述第二频率控制字生成目标占空比的初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路；
所述展频时钟生成电路根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号。
可选的，所述展频时钟生成电路包括：电压转换子电路、第一基准时钟生成子电路和展频时钟生成子电路；
所述展频时钟生成电路根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号，包括：
所述电压转换子电路根据所述初始时钟信号的目标占空比将初始电压转换为目标电压，并为所述第一基准时钟生成子电路提供所述目标电压；
所述第一基准时钟生成子电路在所述目标电压的驱动下，生成多个第一基准时钟信号，并将所述多个第一基准时钟信号输出至所述展频时钟生成子电路，其中，任意两个相邻的所述第一基准时钟信号之间的相位差相同；
所述展频时钟生成子电路根据所述第三频率控制字和所述多个第一基准时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
又一方面，提供了一种电子设备，所述电子设备包括：被控电路，以及如上述方面所述的时钟信号产生电路；
所述时钟信号产生电路与所述被控电路连接，所述被控电路用于响应于所述时钟信号产生电路输出的展频时钟信号工作。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种时钟信号产生电路的结构示意图；
图2是本公开实施例提供的一种控制字生成电路的架构图；
图3是本公开实施例提供的另一种时钟信号产生电路的结构示意图；
图4是本公开实施例提供的一种电压转换子电路的结构示意图；
图5是本公开实施例提供的一种第一基准时钟生成子电路的结构示意图；
图6是本公开实施例提供的一种第一基准时钟信号的示意图；
图7是本公开实施例提供的一种展频时钟生成子电路的结构示意图；
图8是本公开实施例提供的另一种展频时钟生成子电路的结构示意图；
图9是本公开实施例提供的又一种展频时钟生成子电路的结构示意图；
图10是本公开实施例提供的一种信号合成示意图；
图11是本公开实施例提供的又一种时钟信号产生电路的结构示意图；
图12是本公开实施例提供的一种初始时钟生成子电路的结构示意图；
图13是本公开实施例提供的一种时钟信号产生方法的流程图；
图14是本公开实施例提供的一种电子设备的结构示意图。
具体实施方式
为使本公开实施例的发明构思的目的、技术方案和优点更加清楚，下面将结合附图和一些实施例对本公开实施例保护的发明构思做详细描述。
电子设备包括的电源产生的噪声和时钟信号产生电路产生的噪声是引起电磁干扰的主要来源。其中电源产生的噪声一般可以称为底噪，时钟信号产生电路产生的噪声一般可以称为特征频率噪声。特征频率噪声对电子设备工作带来的影响较为严重，该特征频率噪声可能会占据某个关键信道或与其他电路产生耦合作用，使得电子设备的工作频率发生漂移，甚至导致电子设备工作异常或宕机。
目前，为抑制电磁干扰，一般可以通过调节电路板上的布线方式减少对外的电磁辐射。或者，可以采用铁壳对电磁干扰进行屏蔽，切断电磁干扰的传播途径。或者，可以采用抖动的方式对干扰源(即，时钟信号产生电路产生的时钟信号)进行展频处理。其中，调节布线或设置铁壳的方式成本较高。而采用抖动方式进行展频处理之前，需要先控制电子设备停止工作，在展频处理完成之后，再重新启动电子设备工作，该方式影响电子设备的正常运转，且无法实现对展频深度的调节。
本公开实施例提供了一种时钟信号产生电路，可以在不影响电子设备正常运转的前提下，实现对时钟信号的展频处理，且可以实现对展频深度、中心频率和/或展频类型的实时调节。该时钟信号产生电路不仅能够有效抑制电磁干扰，且相对于相关技术，展频灵活性较高，且因无需控制电子设备在展频处理时停止工作，在一定程度上还降低了电子设备的功耗，提高了电子设备的鲁棒性。
图1是本公开实施例提供的一种时钟信号产生电路的结构示意图。如图1所示，该时钟信号产生电路可以包括：控制字生成电路10、初始时钟生成电路20和展频时钟生成电路30。
该控制字生成电路10可以分别与初始时钟生成电路20和展频时钟生成电路30连接。该控制字生成电路10可以用于基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将第一频率控制字和第二频率控制字输出至初始时钟生成电路20，并将第三频率控制字输出至展频时钟生成电路30。
其中，该展频参数是指影响展频时钟生成电路30输出结果，即展频效果的相关参数。且该展频参数可以由用户(如，开发人员)输入至控制字生成电路10，或者，该控制字生成电路10中可以预先配置有多种不同的展频参数，以供用户选择或以供控制字生成电路10直接调用。如，该展频参数可以为展频深度。
该初始时钟生成电路20还可以与展频时钟生成电路30连接。该初始时钟生成电路20可以用于根据第一频率控制字和第二频率控制字生成目标占空比的初始时钟信号，并将初始时钟信号输出至展频时钟生成电路30。
可选的，假设目标占空比用D表示，第一频率控制字用F1表示，第二频率控制字用F2表示(下述实施例均以相同字符表示)。初始时钟信号的高电位持续时长与第二频率控制字F2相关，初始时钟信号的低电位持续时长与第一频率控制字F1和第二频率控制字F2的差值：F1-F2相关，则初始时钟生成电路20生成的初始时钟信号的目标占空比D可以满足：D＝F2/F1公式(1)。
该展频时钟生成电路30还可以用于根据初始时钟信号的目标占空比和第三频率控制字对初始时钟信号进行展频处理，得到展频时钟信号。
需要说明的是，由于初始时钟生成电路20和展频时钟生成电路30均是基于控制字生成电路10提供的频率控制字工作，因此，控制字生成电路10还可以称为控制模块(control block)。
综上所述，本公开实施例提供了一种时钟信号产生电路。由于该时钟信号产生电路中，是由控制字生成电路、初始时钟生成电路和展频时钟生成电路等数字电路，先基于展频参数生成频率控制字，再基于频率控制字生成目标占空比的初始时钟信号，以及基于该初始时钟信号的目标占空比进行展频处理得到展频时钟信号，即整个展频过程由数字电路执行，因此无需控制包括该时钟信号产生电路的电子设备停止工作，即不影响电子设备正常运转。并且，本公开提供的时钟信号产生电路可以实现对各类影响展频结果的展频参数(如，展频深度)的实时调节，展频灵活性较高。
可选的，展频参数可以包括下述参数中的至少一种：展频类型(modulation type)参数、展频深度(modulation depth)参数和中心频率(center frequency)参数。其中，展频类型是指展频处理所采用的展频方式，如线性调制，展频类型决定了展频时钟信号的表现形式。展频深度是指展频时钟信号的频率以固定速度偏移初始时钟信号的频率的大小，展频深度决定了展频时钟信号的峰值大小。中心频率是指展频时钟信号的频率的算术平均值，中心频率决定了展频时钟信号的最低频率和最高频率的大小。
示例的，以展频参数由用户输入为例，图2是本公开实施例提供的一种控制字生成电路的架构图。如图2所示，该控制字生成电路10可以包括展频类型的输入接口、展频深度的输入接口和中心频率的输入接口，该三个输入接口可以供用户根据所需展频结果输入对应参数。继续参考图2，控制字生成电路10在接收到展频参数后，一般会先基于展频参数生成一总频率控制字F，然后再将该总频率控制字F拆分为第一频率控制字F1、第二频率控制字F2和第三频率控制字F3，分别提供给初始时钟生成电路20和展频时钟生成电路30。其拆分方式取决于所需展频结果，展频结果是指最终所需生成的展频时钟信号的类型、频率和周期等。且展频结果一般可由用户输入或预先配置于控制字生成电路10中。
可选的，图3是本公开实施例提供的另一种时钟信号产生电路的结构示意图。如图3所示，该展频时钟生成电路可以30包括：电压转换子电路301、第一基准时钟生成子电路302和展频时钟生成子电路303。
电压转换子电路301可以分别与初始时钟生成电路20和第一基准时钟生成 子电路302连接。电压转换子电路301可以根据初始时钟信号的目标占空比将初始电压转换为目标电压，并为第一基准时钟生成子电路302提供目标电压。因该电压转换子电路301的功能为电压转换，故该电压转换子电路301也可以称为电压切换电路(switching circuit)。
其中，该目标电压可以与目标占空比和初始电压均正相关。即目标占空比越大，目标电压越大；目标占空比越小，目标电压越小。同理，初始电压越大，目标电压越大；初始电压越小，目标电压越小。且，该目标电压与电压转换子电路301的自身电压转换效率也可以正相关，即电压转换效率越大，目标电压也越大，电压转换效率越小，目标电压也越小。
例如，假设初始电压用Vi表示，目标电压用Vo表示，电压转换效率用μ表示，则目标电压Vo可以满足：Vo＝Vi×μ×D，D是指目标占空比。
可选的，该初始电压可以由一电源提供(power supply)模块提供，如电源。相应的，继续参考图3，该时钟信号产生电路还可以包括电源40，该电源40可以与电压转换子电路301连接，并为电压转换子电路301提供初始电压。
由于控制字生成电路10可以基于不同的展频参数生成不同的频率控制字，因此可以使得初始时钟生成电路20基于不同的频率控制字生成不同目标占空比的初始时钟信号。相应的，电压转换子电路301即可以基于不同的目标占空比将电源40提供的初始电压转换为不同的目标电压，从而使得输出至第一基准时钟生成子电路302的目标电压可调，为后续展频奠定了基础。
可选的，图4是本公开实施例提供的一种电压转换子电路301的结构示意图。如图4所示，该电压转换子电路301可以包括：三极管M1、二极管D1、电感L1、电容C1和电阻R1。
其中，三极管M1的栅极可以与初始时钟生成电路20连接(图4中未示出)，三极管M1的第一极可以与电源40的第一极连接，三极管M1的第二极可以与电感L1的一端连接。电感L1的另一端可以分别与二极管D1的一端、电容C1的一端和电阻R1的一端可以连接，并可以与第一基准时钟生成子电路302的第一端(图4中未示出)连接。二极管D1的另一端、电容C1的另一端和电阻R1的另一端均可以分别与电源40的第二极，和第一基准时钟生成子电路302的第二端连接(图4中均未示出)。
结合图4所示的电压转换子电路301对电压转换原理进行介绍：初始时钟 生成电路20可以将生成的目标占空比的初始时钟信号输出至三极管M1的栅极。如此，当初始时钟信号的电位为有效电位时，三级管M1开启，初始电压Vi可以经该三极管M1输出至电感L1的一端，然后再经电感L1、二极管D1、电容C1和电阻R1被转换为目标电压Vo。而当初始时钟信号的电位为无效电位时，三级管M1关断，初始电压Vi无法经三极管M1输出至电感L1的一端。其中，三极管M1开启也可以称为充电，三极管M1关断也可以称为放电。
继续参考图3，第一基准时钟生成子电路302还可以与展频时钟生成子电路303连接。该第一基准时钟生成子电路302可以在目标电压的驱动下，生成多个第一基准时钟信号，并将多个第一基准时钟信号输出至展频时钟生成子电路303，其中，任意两个相邻的第一基准时钟信号之间的相位差可以相同，且每个第一基准时钟信号的周期和频率均相同。因目标电压可调，相应的，第一基准时钟生成子电路302生成的第一基准时钟信号的频率即可调。
可选的，该第一基准时钟生成子电路302可以包括：第一环路振荡器(ring oscillator，RO)，即RO1。该第一环路振荡器RO1可以由多个与非门组成，且若有N个输入，则第一环路振荡器RO1可以产生2N个输出，N一般可以等于2 n，n大于等于2。例如，以N等于8为例，图5示出了第一环路振荡器RO1的结构示意图。参考图5可以看出，该第一环路振荡器RO1共有16个输出端P1至P16，第一环路振荡器RO1(即，第一基准时钟生成子电路302)可以通过该16个输出端P1至P16与展频时钟生成子电路303连接。
示例的，图6以第一基准时钟生成子电路302共生成k个第一基准时钟信号为例，示出了多个第一基准时钟信号的示意图。且，参考图6可以看出，每相邻两个第一基准时钟信号之间的相位差均为Δ。
需要说明的是，第一基准时钟生成子电路302能够生成的第一基准时钟信号的数量k可以预先配置于第一基准时钟生成子电路302中。如，可以由用户在生产该电路时设置于该电路中。且，k可以为2的i次方，i可以为大于等于1的整数。例如，k可以为16、32、128或其他。
继续参考图3，展频时钟生成子电路303还可以与控制字生成电路10连接，展频时钟生成子电路303可以用于根据第三频率控制字和多个第一基准时钟信号对初始时钟信号进行展频处理，得到展频时钟信号。
其中，展频时钟信号的周期与第三频率控制字、第一基准时钟信号的频率 和生成的第一基准时钟信号的数量均可以负相关。即，第三频率控制字越大，展频时钟信号的周期越小，第三频率控制字越小，展频时钟信号的周期越大。同理，第一基准时钟信号的频率越大，展频时钟信号的周期越小，第一基准时钟信号的频率越小，展频时钟信号的周期越大。第一基准时钟信号的数量越大，展频时钟信号的周期越小，第一基准时钟信号的数量越小，展频时钟信号的周期越大。
例如，假设每个第一基准时钟信号的频率表示为f1，共生成了k个第一基准时钟信号，则展频时钟信号的周期T0可以满足：T0＝1/(F3×k×f1)公式(2)，F3为第三频率控制字。
通过设置展频时钟生成子电路303，可以进一步拓展第一基准时钟生成子电路302的输出范围，增强了展频时钟信号的可调性。且，为了增强展频时钟信号的可调性，第三频率控制字F3一般可以包括整数部分和小数部分。
可选的，图7是本公开实施例提供的一种展频时钟生成子电路303的结构示意图。如图7所示，该展频时钟生成子电路303可以包括：第一输入单元3031、第一选择单元3032和第一输出单元3033。
第一输入单元3031可以分别与控制字生成电路10(图中未示出)和第一选择单元3032连接。第一输入单元3031可以用于根据第三频率控制字F3向第一选择单元3032输出第一选择控制信号。
第一选择单元3032还可以分别与第一基准时钟生成子电路302(图中未示出)和第一输出单元3033连接。第一选择单元3032可以用于响应于第一选择控制信号从多个第一基准时钟信号中选择一个第一备选时钟信号，并将第一备选时钟信号输出至第一输出单元3033。
第一输出单元3033可以用于根据第一备选时钟信号对初始时钟信号进行展频处理，得到展频时钟信号。
示例的，参考图8，第一输入单元3031可以包括多个寄存器和多个累加器，第一选择单元3032可以包括三个选择器，第一输出单元3033可以包括翻转触发器。示例的，再结合图9，寄存器可以包括：第一寄存器R1、第二寄存器R2、第三寄存器R3和第四寄存器R4，加法器可以包括：两个加法器J11和J12。选择器可以包括：第一选择器X1、第二选择器X2和第三选择器X3。翻转触发器可以包括：D触发器、第一反相器F1和第二反相器F2。
其中，两个加法器J11和J12可以均分别与控制字生成电路10连接，且一个加法器J11、第一寄存器R1、第二寄存器R2和第一选择器X1依次连接；另一个加法器J12、第三寄存器R3、第四寄存器R4和第二选择器X2依次连接。例如，图9示出的两个加法器J11和J12均连接至第三寄存器R3与第四寄存器R4相连的连接线上。第一选择器X1和第二选择器X2可以分别与第一基准时钟生成子电路302和第三选择器X3连接，第三选择器X3还可以与D触发器的第一输入端连接。D触发器的第二输入端可以与第一反相器F1的输出端连接，第一反相器F1的输入端和第二反相器F2的输入端可以与D触发器的输出端连接。且，参考图9，D触发器的输出端可以作为第一时钟信号端CLK1的输出，第二反相器F2的输出端可以作为第二时钟信号端CLK2的输出，且第一时钟信号端CLK1和第二时钟信号端CLK2提供的时钟信号仅相位相反且频率相同。
例如，假设第一基准时钟生成子电路302共生成k个第一基准时钟信号，则第一选择器X1和第二选择器X2均可以为图9所示的k->1选择器(即从K个第一基准时钟信号中选择1个第一基准时钟信号)。由于第三选择器X3用于从两个中选择一个，因此结合图9，该第三选择器X3可以为2->1选择器(即从2个第一基准时钟信号中选择1个第一备选时钟信号)。
结合图9，以第二寄存器R2和第三选择器X3连接第一时钟信号端CLK1，且第一寄存器R1、第三寄存器R3和第四寄存器R4均连接第二时钟信号端CLK2为例，对展频时钟生成子电路303生成展频时钟信号的原理进行说明：
例如，一个加法器J11可以将第三频率控制字F3的一部分(如图9所示的F3/2)和第三寄存器R3存储的最高有效位(如，5比特)相加，然后在第二时钟信号端CLK2提供的第二时钟信号的上升沿时将相加结果保存到第一寄存器R1中；或者，一个加法器J11可以将第三频率控制字F3的一部分和第三寄存器R3存储的所有信息相加，然后在第二时钟信号的上升沿时将相加结果保存到第一寄存器R1中。在下一个第一时钟信号的上升沿时，第一寄存器R1存储的最高有效位将被存储到第二寄存器R2中，并作为第一选择器X1的选择信号。相应的，第一选择器X1即可以响应于该选择信号，从k个第一基准时钟信号中选择一个第一基准时钟信号作为第一选择器X1的输出信号并输出至第三选择器X3。
同理，另一个加法器J12可以将第三频率控制字F3和第三寄存器R3存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到 第三寄存器R3中。或者，另一个加法器J12可以将第三频率控制字F3和第三寄存器R3存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器R3中。在下一个第二时钟信号的上升沿时，第三寄存器R3存储的最高有效位将被存储到第四寄存器R4中，并作为第二选择器X2的选择信号。相应的，第二选择器X2即可以响应于该选择信号从k个第一基准时钟信号中选择一个第一基准时钟信号作为第二选择器X2的输出信号并输出至第三选择器X3。
进一步的，第三选择器X3可以在第一时钟信号的上升沿时，选择来自第一选择器X1的输出信号和来自第一选择器X2的输出信号中的一个作为第三选择器X3的输出信号并输出至D触发器，以作为D触发器的输入时钟信号。然后，D触发器的输出端和第二反相器F2的输出端之一输出的时钟信号即可以作为最终的输出信号，至此，即实现了展频时钟信号的生成。
可选的，第四寄存器R4输出的选择信号可以作为下降沿选择信号，第二寄存器R2输出的选择信号可以作为上升沿选择信号，第三寄存器R3反馈至加法器J12的信号可以用于控制生成的时钟的周期切换。相应的，可以将第四寄存器R4输出的选择信号称为下降沿控制字，将第二寄存器R2输出的选择信号称为上升沿控制字。本公开实施例记载的展频时钟生成子电路303可以称为基于时间平均频率脉冲直接合成(Time-Average-Frequency Direct Period Synthesis，TAF-DPS)电路。该TAF-DPS电路的工作原理可以基于时间平均频率(time average frequency，TAF)来实现。
结合图10对该TAF-DPS电路的工作原理进行示意性说明：
假设频率控制字为F(如，第三频率控制字F3)，任意两个相邻的第一基准时钟信号的相位差为Δ，F为F＝I1+r1，I1代表整数部分，r1代表小数部分。则通过该TAF方式可以输出两种具有不同周期的时钟信号，假设一个时钟信号的周期用T A表示，另一个时钟信号的周期用T B表示，则T A和T B可以满足：
T A＝I1×Δ   公式(3)；
T B＝(I1+1)×Δ   公式(4)；
将该周期为T A的时钟信号和周期为T B的时钟信号通过“周期合成”技术可以合成得到一个周期为目标周期的时钟信号，且该目标周期T TAF可以满足：
T TAF＝(1-r1)×T A+r1×T B   公式(5)；
将公式(3)和公式(4)代入公式(5)可以得到：
T TAF＝(I1+r1)×Δ＝F×Δ   公式(6)；
根据公式(6)可以看出，r1可以控制T B出现的概率，即频率控制字F的小数部分r1可以控制周期T A和T B之间的切换频率。基于公式(6)可以进一步计算出TAF-DPS电路输出的时钟信号的频率f TAF满足：
f TAF＝1/T TAF＝1/[(I1+r1)×Δ]＝1/F×Δ   公式(7)。
结合上述工作原理的介绍，展频时钟生成子电路303的输出信号的周期T1可以满足：T1＝F3×Δ＝(I11+r11)×Δ＝(1-r11)×T A+r11×T B   公式(8)，I11是第三频率控制字F3的整数部分，r11是第三频率控制字F3的小数部分。
结合上述原理分析可知，本公开实施例提供的展频时钟生成子电路303可以直接对脉冲(即时钟信号)进行合成，而非传统的频率合成。该方式也使得时钟频率切换时电子设备仍可以保持正常工作。
图11是本公开实施例提供的再一种时钟生成电路的结构示意图。如图11所示，该初始时钟生成电路20可以包括：第二基准时钟生成子电路201和初始时钟生成子电路202。
第二基准时钟生成子电路201可以与初始时钟生成子电路202连接。第二基准时钟生成子电路201可以用于在基准电压的驱动下，生成多个第二基准时钟信号，并将多个第二基准时钟信号输出至初始时钟生成子电路202，其中，任意两个相邻的第二基准时钟信号之间的相位差相同，且各个第二基准时钟信号的频率和周期均相同，如各个第二基准时钟信号的频率均为f2。
可以结合图5和图6，第二基准时钟生成子电路201可以包括：第二环路振荡器RO2，该第二环路振荡器RO2和第一环路振荡器RO1的结构和工作原理相同，在此不再赘述。第二环路振荡器RO2(即，第二基准时钟生成子电路201)和第一环路振荡器RO1(即，第一基准时钟生成子电路301)区别在于：第二基准时钟生成子电路201是在固定电压(即，基准电压)下工作，生成的第二基准时钟信号的频率稳定。而，第一基准时钟生成子电路301是在可变的目标电压下工作，生成的第一基准时钟信号的频率可调。
继续参考图11，该初始时钟生成子电路202还可以分别与控制字生成电路10和展频时钟生成电路30(如，展频时钟生成电路30包括的电压转换子电路301)连接。该初始时钟生成子电路202可以用于根据第一频率控制字F1、第二 频率控制字F2和多个第二基准时钟信号生成初始时钟信号，并将初始时钟信号输出至展频时钟生成电路30。
可选的，图12是本公开实施例提供的一种初始时钟生成子电路202的结构示意图。如图12所示，初始时钟生成子电路202可以包括：第二输入单元2021、第二选择单元2022和第二输出单元2023。
第二输入单元2021可以分别与控制字生成电路10(图中未示出)和第二选择单元2022连接。第二输入单元2021可以用于根据第一频率控制字F1和第二频率控制字F2，向第二选择单元2022输出第二选择控制信号。
第二选择单元2022还可以分别与第二基准时钟生成子电路201和第二输出单元2023连接。第二选择单元2022可以用于响应于第二选择控制信号从多个第二基准时钟信号中选择一个第二备选时钟信号，并将第二备选时钟信号输出至第二输出单元2023。
第二输出单元2023还可以与展频时钟生成电路30连接(图中未示出)。第二输出单元2023可以用于根据第二备选时钟信号生成初始时钟信号，并将初始时钟信号输出至展频时钟生成电路30。
可选的，可以结合图8和图9，初始时钟生成子电路202包括的各单元结构和工作原理，均与展频时钟生成子电路303包括的各单元结构和工作原理相同，在此不再赘述，区别在于初始时钟生成子电路202和展频时钟生成子电路303接收到的频率控制字不同，相应的，输出结果也不相同。故，初始时钟生成子电路202也可以成为TAF-DPS电路。假设用TAF-DPS1表示展频时钟生成子电路303，用TAF-DPS2表示初始时钟生成子电路202，则TAF-DPS2主要用于生成目标占空比的初始时钟信号，相应的，为了保证生成的初始时钟信号的稳定性，控制字生成电路10提供给初始时钟生成子电路202的第一频率控制字F1和第二频率控制字F2可以均为正整数。
假设第一频率控制字F1和第二频率控制字F2均为正整数，则结合上述针对TAF-DPS工作原理的介绍可以确定，初始时钟生成子电路202输出的初始时钟信号的周期T2可以满足：
T2＝F1×Δ＝I12×Δ＝T A＝F2×Δ+(F1-F2)×Δ   公式(9)；I12是指第一频率控制字F1的整数部分，第一频率控制字F1无小数部分。
通过设置TAF-DPS1和TAF-DPS2，可以确保展频处理时针对频率的调节范 围更大，且因TAF-DPS2可以产生目标占空比的初始时钟信号，使得电压转换子电路301可以基于该目标占空比的初始时钟信号，直接改变电源40提供的初始电压，确保了调节精度，进而确保了生成的展频时钟信号的精度。
结合上述实施例可知，采用本公开实施例提供的时钟信号产生电路生成展频时钟信号的整个过程可以概括为：
第二基准时钟生成子电路201(如，第二环路振荡器RO2)先在基准电压驱动下生成多个(如，k个)频率为f2的第二基准时钟信号，并输出至初始时钟生成子电路202(如，TAF-DPS2)。然后，初始时钟生成子电路202基于接收到的第一频率控制字F1、第二频率控制字F2、第二基准时钟信号的数量k和频率f2，生成目标占空比的初始时钟信号并输出至电压转换子电路301。然后，电压转换子电路301基于目标占空比将电源40提供的初始电压转换为目标电压，并将目标电压提供至第一基准时钟生成子电路302。然后，第一基准时钟生成子电路302(如，第一环路振荡器RO1)可以在该目标电压的驱动下工作，并生成多个(如，k个)频率为f1的第二基准时钟信号，且将第二基准时钟信号输出至展频时钟生成子电路303(如，TAF-DPS2)。最后，展频时钟生成子电路303可以基于接收到的第三频率控制字F3和第二基准时钟信号生成展频时钟信号。
例如，假设需要对初始时钟信号进行三角调制，则可以控制第一频率控制子F1固定不变，并将第二频率控制字F2在一定范围内进行均匀调节即可。如，控制字生成电路10可以将生成的第二频率控制字F2，按照加1减1的调节方式，在范围25至75之间进行均匀调节。因目标电压Vo满足：Vo＝Vi×μ×D＝Vi×μ×(F2/F1)，故可以看出若F2均匀变化，则相应的即会使得Vo发生均匀变化。Vo的均匀变化会进一步引起第一基准时钟生成子电路302，即第一环路振荡器RO1的振荡频率均匀变化，实现对第二基准时钟信号的频率f1的均匀调节。又由于展频时钟生成子电路303最终生成的展频时钟信号的周期满T0满足：T0＝1/(F3×k×f1)，因此可以看出T0可以随着频率f1的变化而变化，由此即可以实现三角调制。
当然，若要实现其他类型的调制，仅需向控制字生成电路10输出所需展频参数即可，控制字生成电路10基于不同展频参数生成的第二频率控制字F2根据不同规律变化将形成不同的调制类型，即使得展频时钟生成电路30实现对初始时钟信号进行不同类型的展频处理。整个电路结构展频高效，结构简洁，体 积小，功耗低，既能保证电子设备的正常运转，又能可靠抑制电磁干扰。
综上所述，本公开实施例提供了一种时钟信号产生电路。由于该时钟信号产生电路中，是由控制字生成电路、初始时钟生成电路和展频时钟生成电路等数字电路，先基于展频参数生成频率控制字，再基于频率控制字生成目标占空比的初始时钟信号，以及及基于该初始时钟信号的目标占空比进行展频处理得到展频时钟信号，即整个展频过程由数字电路执行，因此无需控制包括该时钟信号产生电路的电子设备停止工作，即不影响电子设备正常运转。并且，本公开提供的时钟信号产生电路可以实现对各类影响展频结果的展频参数(如，展频深度)的实时调节，展频灵活性较高。
图13是本公开实施例提供的一种时钟信号产生方法，该方法可以应用于如图1、图3和图11任一所示的时钟信号产生电路中。如图13所示，该方法可以包括：
步骤1301、控制字生成电路基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将第一频率控制字和第二频率控制字输出至初始时钟生成电路，并将第三频率控制字输出至展频时钟生成电路。
步骤1302、初始时钟生成电路根据第一频率控制字和第二频率控制字生成目标占空比的初始时钟信号，并将初始时钟信号输出至展频时钟生成电路。
步骤1303、展频时钟生成电路根据初始时钟信号的目标占空比和第三频率控制字对初始时钟信号进行展频处理，得到展频时钟信号。
综上所述，本公开实施例提供了一种时钟信号产生方法，由于该方法可以基于展频参数生成频率控制字，可以根据频率控制字生成目标占空比的初始时钟信号，以及基于该初始时钟信号的目标占空比进行展频处理得到展频时钟信号。整个展频过程均为数字处理过程，无需控制包括该时钟信号产生电路的电子设备停止工作，即不影响电子设备正常运转。且，可以实现对展频深度、展频类型和/或中心频率的实时调节，展频灵活性较高。
需要说明的是，对于时钟信号产生电路包括的各电路的可选结构，以及步骤1301至步骤1303相应的可选实现方式可以参考上述针对装置侧的记载，在方法侧实施例不再赘述。
图14是本公开实施例提供的一种电子设备的结构示意图。如图14所示，该电子设备可以包括：被控电路01，以及如图1、图3和图11任一所示的时钟信号产生电路02。
其中，时钟信号产生电路02可以与被控电路01连接，被控电路01可以用于响应于时钟信号产生电路02输出的展频时钟信号工作。
例如，图14以第一基准时钟生成子电路302和第二基准时钟生成子电路201均为环路振荡器(RO1和RO2)，展频时钟生成子电路303和初始时钟生成子电路202均为TAF-DPS电路(TAF-DPS1和TAF-DPS2)为例示出了时钟信号产生电路02的示意图。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的时钟信号产生方法的具体方式，可以参考前述装置侧实施例中介绍的时钟信号产生电路包括的各电路、各子电路、各单元以及各器件的对应工作过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种时钟信号产生电路，其中，所述时钟信号产生电路包括：控制字生成电路、初始时钟生成电路和展频时钟生成电路；
    所述控制字生成电路分别与所述初始时钟生成电路和所述展频时钟生成电路连接，所述控制字生成电路用于基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将所述第一频率控制字和所述第二频率控制字输出至所述初始时钟生成电路，并将所述第三频率控制字输出至所述展频时钟生成电路；
    所述初始时钟生成电路还与所述展频时钟生成电路连接，所述初始时钟生成电路用于根据所述第一频率控制字和所述第二频率控制字生成目标占空比的初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路；
    所述展频时钟生成电路用于根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号。
  2. 根据权利要求1所述的时钟信号产生电路，其中，所述展频时钟生成电路包括：电压转换子电路、第一基准时钟生成子电路和展频时钟生成子电路；
    所述电压转换子电路分别与所述初始时钟生成电路和所述第一基准时钟生成子电路连接，所述电压转换子电路用于根据所述初始时钟信号的目标占空比将初始电压转换为目标电压，并为所述第一基准时钟生成子电路提供所述目标电压；
    所述第一基准时钟生成子电路还与所述展频时钟生成子电路连接，所述第一基准时钟生成子电路用于在所述目标电压的驱动下，生成多个第一基准时钟信号，并将所述多个第一基准时钟信号输出至所述展频时钟生成子电路，其中，任意两个相邻的所述第一基准时钟信号之间的相位差相同；
    所述展频时钟生成子电路还与所述控制字生成电路连接，所述展频时钟生成子电路用于根据所述第三频率控制字和所述多个第一基准时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
  3. 根据权利要求2所述的时钟信号产生电路，其中，所述第一基准时钟生成 子电路包括：第一环路振荡器。
  4. 根据权利要求2所述的时钟信号产生电路，其中，所述展频时钟生成子电路包括：第一输入单元、第一选择单元和第一输出单元；
    所述第一输入单元分别与所述控制字生成电路和所述第一选择单元连接，所述第一输入单元用于根据所述第三频率控制字向所述第一选择单元输出第一选择控制信号；
    所述第一选择单元还分别与所述第一基准时钟生成子电路和所述第一输出单元连接，所述第一选择单元用于响应于所述第一选择控制信号从所述多个第一基准时钟信号中选择一个第一备选时钟信号，并将所述第一备选时钟信号输出至所述第一输出单元；
    所述第一输出单元用于根据所述第一备选时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
  5. 根据权利要求2所述的时钟信号产生电路，其中，所述时钟信号产生电路还包括：电源；
    所述电源与所述电压转换子电路连接，所述电源用于为所述电压转换子电路提供所述初始电压。
  6. 根据权利要求1至5任一所述的时钟信号产生电路，其中，所述初始时钟生成电路包括：第二基准时钟生成子电路和初始时钟生成子电路；
    所述第二基准时钟生成子电路与所述初始时钟生成子电路连接，所述第二基准时钟生成子电路用于在基准电压的驱动下，生成多个第二基准时钟信号，并将所述多个第二基准时钟信号输出至所述初始时钟生成子电路，其中，任意两个相邻的所述第二基准时钟信号之间的相位差相同；
    所述初始时钟生成子电路还分别与所述控制字生成电路和所述展频时钟生成电路连接，所述初始时钟生成子电路用于根据所述第一频率控制字、所述第二频率控制字和所述多个第二基准时钟信号生成所述初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路。
  7. 根据权利要求6所述的时钟信号产生电路，其中，所述第二基准时钟生成子电路包括：第二环路振荡器。
  8. 根据权利要求6所述的时钟信号产生电路，其中，所述初始时钟生成子电路包括：第二输入单元、第二选择单元和第二输出单元；
    所述第二输入单元分别与所述控制字生成电路和所述第二选择单元连接，所述第二输入单元用于根据所述第一频率控制字和所述第二频率控制字，向所述第二选择单元输出第二选择控制信号；
    所述第二选择单元还分别与所述第二基准时钟生成子电路和所述第二输出单元连接，所述第二选择单元用于响应于所述第二选择控制信号从所述多个第二基准时钟信号中选择一个第二备选时钟信号，并将所述第二备选时钟信号输出至所述第二输出单元；
    所述第二输出单元还与所述展频时钟生成电路连接，所述第二输出单元用于根据所述第二备选时钟信号生成所述初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路。
  9. 根据权利要求1至8任一所述的时钟信号产生电路，其中，所述第一频率控制字和所述第二频率控制字均为正整数。
  10. 根据权利要求1至9任一所述的时钟信号产生电路，其中，所述第三频率控制字包括整数部分和小数部分。
  11. 根据权利要求1至10任一所述的时钟信号产生电路，其中，所述展频参数包括下述参数中的至少一种：展频类型参数、展频深度参数和中心频率参数。
  12. 根据权利要求8所述的时钟信号产生电路，其中，所述展频时钟生成子电路包括：第一输入单元、第一选择单元和第一输出单元；
    所述第一输入单元分别与所述控制字生成电路和所述第一选择单元连接，所述第一输入单元用于根据所述第三频率控制字向所述第一选择单元输出第一选择控制信号；所述第一选择单元还分别与所述第一基准时钟生成子电路和所 述第一输出单元连接，所述第一选择单元用于响应于所述第一选择控制信号从所述多个第一基准时钟信号中选择一个第一备选时钟信号，并将所述第一备选时钟信号输出至所述第一输出单元；所述第一输出单元用于根据所述第一备选时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号；
    所述时钟信号产生电路还包括：电源；所述电源与所述电压转换子电路连接，所述电源用于为所述电压转换子电路提供所述初始电压；
    所述第二基准时钟生成子电路包括：第二环路振荡器；
    所述第一频率控制字和所述第二频率控制字均为正整数；所述第三频率控制字包括整数部分和小数部分；
    所述展频参数包括下述参数中的至少一种：展频类型参数、展频深度参数和中心频率参数。
  13. 一种时钟信号产生方法，其中，所述方法包括：
    控制字生成电路基于展频参数生成第一频率控制字、第二频率控制字和第三频率控制字，将所述第一频率控制字和所述第二频率控制字输出至初始时钟生成电路，并将所述第三频率控制字输出至展频时钟生成电路；
    所述初始时钟生成电路根据所述第一频率控制字和所述第二频率控制字生成目标占空比的初始时钟信号，并将所述初始时钟信号输出至所述展频时钟生成电路；
    所述展频时钟生成电路根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号。
  14. 根据权利要求13所述的方法，其中，所述展频时钟生成电路包括：电压转换子电路、第一基准时钟生成子电路和展频时钟生成子电路；
    所述展频时钟生成电路根据所述初始时钟信号的目标占空比和所述第三频率控制字对所述初始时钟信号进行展频处理，得到展频时钟信号，包括：
    所述电压转换子电路根据所述初始时钟信号的目标占空比将初始电压转换为目标电压，并为所述第一基准时钟生成子电路提供所述目标电压；
    所述第一基准时钟生成子电路在所述目标电压的驱动下，生成多个第一基准时钟信号，并将所述多个第一基准时钟信号输出至所述展频时钟生成子电路， 其中，任意两个相邻的所述第一基准时钟信号之间的相位差相同；
    所述展频时钟生成子电路根据所述第三频率控制字和所述多个第一基准时钟信号对所述初始时钟信号进行展频处理，得到展频时钟信号。
  15. 一种电子设备，其中，所述电子设备包括：被控电路，以及如权利要求1至12任一所述的时钟信号产生电路；
    所述时钟信号产生电路与所述被控电路连接，所述被控电路用于响应于所述时钟信号产生电路输出的展频时钟信号工作。
PCT/CN2021/099018 2020-07-23 2021-06-08 时钟信号产生电路、时钟信号产生方法及电子设备 WO2022017033A1 (zh)

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