WO2022011983A1 - 碳化硅结势垒肖特基半导体器件及其制造方法 - Google Patents

碳化硅结势垒肖特基半导体器件及其制造方法 Download PDF

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WO2022011983A1
WO2022011983A1 PCT/CN2020/140015 CN2020140015W WO2022011983A1 WO 2022011983 A1 WO2022011983 A1 WO 2022011983A1 CN 2020140015 W CN2020140015 W CN 2020140015W WO 2022011983 A1 WO2022011983 A1 WO 2022011983A1
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junction barrier
silicon carbide
semiconductor device
active region
metal layer
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PCT/CN2020/140015
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English (en)
French (fr)
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陈道坤
林苡任
史波
曾丹
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珠海格力电器股份有限公司
珠海零边界集成电路有限公司
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Publication of WO2022011983A1 publication Critical patent/WO2022011983A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, and in particular, to a silicon carbide junction barrier Schottky semiconductor device and a manufacturing method thereof.
  • Silicon carbide is one of the third-generation wide-bandgap semiconductors. It has excellent physical properties such as wide band gap, high breakdown electric field, high thermal conductivity, high temperature resistance, high voltage resistance, and radiation resistance, so SiC power devices are very suitable for high temperature. , high voltage, high power and other power electronic application systems, which have broad application prospects in electric vehicles, photovoltaic inverters, rail transit, wind power generation, motor drives and other application fields.
  • silicon carbide power devices have a smaller chip area and higher current density, so the heat generated by their operating losses is more concentrated. Therefore, for silicon carbide power devices, it is particularly important to optimize the heat distribution of the chip, distribute the heat as uniformly as possible, and avoid the degradation of the performance or reliability of the silicon carbide device caused by the local accumulation of heat.
  • the present disclosure provides a silicon carbide junction barrier Schottky semiconductor device and a manufacturing method thereof.
  • the technical solution provides a silicon carbide junction barrier Schottky semiconductor device.
  • a silicon carbide junction barrier Schottky semiconductor device includes a stacked substrate and an epitaxial layer, an upper surface of the epitaxial layer is provided with an active region and a terminal region located around the active region,
  • the active region includes a number of spaced junction barrier regions, wherein the spacing of the junction barrier regions gradually increases along the direction from the center to the edge of the active region.
  • the width of the junction barrier region gradually increases in the direction from the middle to the edge of the active region.
  • the width of the junction barrier region is 2 ⁇ m, and the spacing of the junction barrier region is gradually increased from 1 ⁇ m to 4 ⁇ m along the direction from the middle to the edge of the active region.
  • the active region further includes an anode metal layer disposed on the upper surface of the epitaxial layer, and an ohmic contact metal layer and a cathode metal layer are disposed on the backside of the substrate in sequence.
  • the junction barrier region is elongated or annular.
  • the silicon carbide junction barrier Schottky semiconductor device further includes a dielectric passivation layer and a protective layer sequentially disposed on the upper surface of the epitaxial layer.
  • the substrate is N-type silicon carbide with a resistivity of 0.01-0.03 ⁇ cm and a thickness of 100 ⁇ m-180 ⁇ m.
  • the anode metal layer includes a first metal layer and a second metal layer arranged in a stack, and the first metal layer can form a Schottky contact barrier with N-type SiC.
  • the technical solution also provides a method for manufacturing a silicon carbide junction barrier Schottky semiconductor device, which is configured to prepare the above-mentioned silicon carbide provided by the technical solution of the present disclosure.
  • Junction barrier Schottky semiconductor devices are configured to prepare the above-mentioned silicon carbide provided by the technical solution of the present disclosure.
  • An anode metal layer, a dielectric passivation layer and a protective layer are sequentially formed on the upper surface of the epitaxial layer.
  • the method further includes: after the substrate is thinned, ohmic contact metal is sequentially formed on the backside of the substrate layer and cathode metal layer.
  • the dielectric passivation layer is a combination of one or more of SiO, SiO 2 , SiN and SiON, the formation method is PECVD, LPCVD or ALD, and the thickness of the dielectric passivation layer is 50 -2000nm.
  • the technical solution of the present disclosure proposes a new active region structure.
  • the current density in the center of the active region is slightly lower than that in the edge region of the active region, so that the SiC junction barrier Schottky
  • the heat distribution of the semiconductor device during forward operation is more uniform, so as to achieve the purpose of optimizing the heat distribution of the device, and avoid the degradation of the performance of the silicon carbide device or the reliability problem caused by the local accumulation of heat.
  • FIG. 1 is a schematic illustration of a silicon carbide Schottky diode in the related art
  • FIG. 2 is a reference diagram of a planar structure of a silicon carbide Schottky diode in the related art
  • FIG. 3 is a cross-sectional structure reference diagram of a silicon carbide Schottky diode in the related art
  • FIG. 4 is a schematic plan view of a silicon carbide junction barrier Schottky semiconductor device provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a silicon carbide junction barrier Schottky semiconductor device according to an embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of another silicon carbide junction barrier Schottky semiconductor device provided by an embodiment of the present disclosure.
  • FIGS. 7-15 are schematic structural diagrams corresponding to each step of the manufacturing method of the silicon carbide junction barrier Schottky semiconductor device provided by the embodiments of the present disclosure.
  • Substrate 1. Substrate; 2. Epitaxial layer; 3. Active region; 4. Termination region; 5. Junction barrier region; 6. Anode metal layer; 7. Ohmic contact metal layer; 8. Cathode metal layer; 9. Dielectric Passivation layer; 10, protective layer; 11, mask layer.
  • orientation or positional relationship indicated by the terms “upper”, “lower”, “inner”, “middle”, “outer”, “front”, “rear”, etc. is based on the orientation or position shown in the drawings relation. These terms are primarily used to better describe the present disclosure and embodiments thereof, and are not intended to limit the fact that the indicated device, element, or component must have a particular orientation, or be constructed and operated in a particular orientation.
  • connection may be a fixed connection, a detachable connection, or a unitary construction; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediary, or two devices, elements or Internal connectivity between components.
  • connection may be a fixed connection, a detachable connection, or a unitary construction; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediary, or two devices, elements or Internal connectivity between components.
  • silicon carbide is a wide bandgap semiconductor
  • the silicon carbide diode adopts a PN junction structure
  • the turn-on electric field is large (about 3V), which will make the conduction loss very high.
  • SiC diodes adopt Schottky junction structure, which has low turn-on electric field (less than 1V) and small conduction loss.
  • SBD silicon carbide Schottky diode
  • the SiC Schottky diode generally adopts a junction barrier Schottky (JBS) structure, that is, the P-type ion implantation regions are distributed on the surface of the epitaxial layer, so that the SiC junction barrier is small.
  • Turki diodes have both the forward characteristics of SBD diodes and the reverse characteristics of PN diodes, with low forward conduction voltage and small reverse leakage.
  • the present disclosure proposes a silicon carbide semiconductor device, which further optimizes the structure of the silicon carbide semiconductor device, optimizes its thermal distribution, and improves its working stability on the basis of the related art.
  • the silicon carbide junction barrier Schottky semiconductor device provided by the embodiment of the present disclosure includes a cathode metal layer 8 , an ohmic contact metal layer 7 , a substrate 1 and an epitaxial layer 2 that are stacked in sequence.
  • An active region 3 and a terminal region 4 located around the active region 3 are provided on the upper surface of the epitaxial layer 2 , and the active region 3 includes a plurality of junction barrier regions 5 arranged at intervals and arranged on the upper surface of the epitaxial layer 2 The anode metal layer 6.
  • the silicon carbide junction barrier Schottky semiconductor device further includes a dielectric passivation layer 9 and a protective layer 10 which are sequentially arranged on the upper surface of the epitaxial layer.
  • the substrate 1 and the epitaxial layer 2 have the first conductivity type, and the substrate 1 is selected to be N-type silicon carbide.
  • the termination field limiting ring and the junction barrier region 5 have the second conductivity type, and the junction barrier region 5 is formed by implantation of P-type impurity ions.
  • the junction barrier region 5 may be in the shape of a strip as shown in FIG. 4 , or may be in a ring shape, which is not specifically limited in the present disclosure, and is specifically determined according to the application scenarios and design requirements of the SiC junction barrier Schottky semiconductor device. Sure.
  • the anode metal layer 6 functions as the anode of the silicon carbide junction barrier Schottky semiconductor device
  • the cathode metal layer 8 functions as the cathode of the silicon carbide junction barrier Schottky semiconductor device.
  • the dielectric passivation layer 9 acts as an electrical isolation between devices and wiring, and acts as an insulating layer, and the protective layer 10 is provided to protect the structures it covers from surface contamination and physical damage.
  • the spacing of the junction barrier regions 5 is gradually increased along the direction from the middle to the edge of the active region 3 .
  • the current density in the center of the chip can be slightly lower than the current density in the edge region of the chip, so as to achieve the purpose of optimizing the heat distribution of the chip and avoid the degradation of the performance or reliability of the silicon carbide device caused by the local accumulation of heat.
  • a specific active region structure scheme may be that the width of the junction barrier region is 2 ⁇ m, and from the center to the edge of the active region, the junction barrier region spacing may be 1.0 ⁇ m, 1.2 ⁇ m, 1.4 ⁇ m, 1.6 ⁇ m
  • the regularity of ⁇ m, 2.0 ⁇ m, 2.4 ⁇ m, 2.7 ⁇ m, 3.0 ⁇ m, 3.5 ⁇ m and 4.0 ⁇ m gradually increased. It should be noted that from the center of the active region to the edge, the change trend of the spacing of the junction barrier region is gradually increasing, but the spacing of a certain width can be one or more, such as from the active region. From the center to the edge, there are 10 elongated junction barrier regions.
  • the spacing of the junction barrier regions can be 1.0 ⁇ m, 1.0 ⁇ m, 1.5 ⁇ m, 1.5 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m , 1.8 ⁇ m, 1.8 ⁇ m, 2.0 ⁇ m, 2.0 ⁇ m, of which there are two spacings of 1.0 ⁇ m and 2.0 ⁇ m, respectively, and three spacings of 1.5 ⁇ m and 1.8 ⁇ m.
  • the spacing of the junction barrier regions 5 is gradually increased, and the width of the junction barrier regions 5 is gradually increased.
  • the structural improvement can also make the current density in the center of the chip slightly lower than the current density in the edge region of the chip, so as to achieve the purpose of optimizing the heat distribution of the chip, and avoid the degradation of the performance or reliability of the silicon carbide device caused by the local accumulation of heat.
  • the silicon carbide junction barrier Schottky semiconductor device may further include other necessary components or structures, and the corresponding arrangement positions and connection relationships can be referred to the silicon carbide semiconductor devices in the related art, and each structure is not mentioned.
  • the connection relationship, operation and working principle of the are known to those skilled in the art, and will not be described in detail here.
  • This embodiment also discloses the processing method of the silicon carbide junction barrier Schottky semiconductor device provided by the above-mentioned embodiment, which includes the following steps:
  • Step 1 As shown in FIG. 7 , a substrate 1 is provided, and an epitaxial layer 2 is formed on the substrate 1 .
  • the substrate 1 is selected to be N-type silicon carbide, its resistivity is 0.01-0.03 ⁇ cm, the thickness is 320-380 ⁇ m, the thickness of the epitaxial layer 2 is 5-100 ⁇ m, and the N-type ion doping concentration is 1 ⁇ 10 14 ⁇ 5 ⁇ 10 16 ions/cm 3 , a suitable N - drift layer can be formed.
  • the thickness of 320-380 ⁇ m facilitates the processing and molding of the front structure, and reserves the processing space for the later substrate thinning process.
  • Step 2 As shown in FIG. 8, a mask layer 11 is deposited on the upper surface of the epitaxial layer 2, and then part of the mask layer is removed by dry etching to expose the ion implantation region, and then P-type impurity ions are implanted into the mask layer.
  • the P-type ion implantation region of the active region and the terminal region can be simultaneously formed in this step, wherein the P-type ion implantation region of the active region is the junction barrier region 5 .
  • the mask layer 11 used in this step can be SiO 2 , polysilicon or a combination of the two, and the thickness of the mask layer is 0.2-4 ⁇ m;
  • the P-type ion implantation process can be a single-step ion implantation process or a multi-step ion implantation process process, the ions used are Al ions, B ions or a combination of the two.
  • Step 3 As shown in FIG. 9 , remove the remaining mask layer implanted, prepare a carbon film on the surface of the structure as a protective layer activated at high temperature, and then activate the implanted P-type impurity ions through high temperature, and remove the carbon film after activation.
  • the preparation method of the carbon film is photoresist carbonization or radio frequency sputtering, the thickness of the carbon film is 0.05-2 ⁇ m, and the activation temperature is 1500-1900° C.
  • Step 4 As shown in FIG. 10 , an anode metal layer 6 is prepared, wherein the anode metal layer 6 is a laminated metal, including a first metal layer and a second metal layer arranged in a laminated manner.
  • the first metal layer is connected to the upper surface of the epitaxial layer, which can form a Schottky contact barrier with N-type silicon carbide, and the material of the first metal layer includes but is not limited to Ti, Mo, W, Pd, Ni, Au or Combinations thereof;
  • the second metal layer includes but is not limited to Al, Ti/Al metal stack, Ni/Al metal stack or Ti/Ni/Al metal stack, and the total thickness of the anode metal layer is 2-5 ⁇ m.
  • a space charge region and a self-built electric field are formed at the junction of the anode metal layer and the SiC semiconductor material.
  • the applied voltage is zero, the diffusion motion of carriers and the reverse drift motion reach a dynamic balance.
  • the anode metal layer and the SiC A contact barrier is formed at the semiconductor junction, which is the Schottky barrier.
  • Step 5 As shown in FIG. 11, a dielectric passivation layer 9 is prepared.
  • the dielectric passivation layer 9 includes but is not limited to SiO, SiO 2 , SiN, SiON or their combination, and can be prepared by a deposition method. Thickness is 50-2000nm.
  • Step 6 As shown in FIG. 12, prepare the protective layer 10 on the top layer, wherein the protective layer 10 is a polyimide (PI) passivation layer, and the thickness of the polyimide (PI) passivation layer after curing is 1-5 ⁇ m .
  • the protective layer 10 is a polyimide (PI) passivation layer
  • the thickness of the polyimide (PI) passivation layer after curing is 1-5 ⁇ m .
  • Step 7 As shown in FIG. 13, the substrate is thinned.
  • the silicon carbide substrate 1 is thinned to 100-180 ⁇ m by grinding or other thinning processes.
  • Step 8 As shown in FIG. 14, ohmic metal is deposited on the back of the substrate 1, and after laser annealing, an ohmic contact metal layer 7 is formed, and the ohmic contact metal layer 7 can be Ni, Ti/Ni metal stack, Ti/ At least one of the Al metal stack and the Ti/Ni/Al metal stack, the thickness of which is 10-500 nm.
  • Step 9 As shown in FIG. 15 , the cathode metal layer 8 is deposited on the basis of the ohmic contact metal layer 7 .
  • the used cathode metal layer is Ti/Ni/Ag metal stack or Ti/Al/Ni/Ag metal stack, and the total thickness of the cathode metal layer is 0.5-4.0 ⁇ m.
  • the processing method of the silicon carbide junction barrier Schottky semiconductor device may further include other necessary steps, and the implementation manner and sequence of the corresponding steps may refer to the related art. It can be known that the detailed description is omitted here.

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Abstract

本公开涉及半导体器件技术领域，具体而言，涉及一种碳化硅结势垒肖特基半导体器件及其制造方法。碳化硅结势垒肖特基半导体器件包括层叠设置的衬底和外延层，所述外延层上表面设置有源区和位于所述有源区周围的终端区，所述有源区包括若干间隔设置的结势垒区，其中，沿所述有源区的中部至边缘的方向，所述结势垒区的间距逐渐增加。有源区中心的电流密度比有源区边缘区域的电流密度稍低，使得碳化硅结势垒肖特基半导体器件在正向工作时的热分布更均匀，以此达到优化器件热分布的目的，避免热量局部积累导致碳化硅器件性能的退化或可靠性问题。

Description

碳化硅结势垒肖特基半导体器件及其制造方法
本公开要求于2020年07月13日提交中国专利局、申请号为202010668498.4、发明名称为“碳化硅结势垒肖特基半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体器件技术领域，具体而言，涉及一种碳化硅结势垒肖特基半导体器件及其制造方法。
背景技术
碳化硅(SiC)是第三代宽禁带半导体之一，具有宽带隙、高击穿电场、高热导率、耐高温、耐高压、抗辐射等优异物理特性，所以SiC功率器件非常适合于高温、高电压、高功率等电力电子应用***，在电动汽车、光伏逆变、轨道交通、风能发电、电机驱动等应用领域具有广阔应用前景。
得益于碳化硅优异的材料特性，相比于硅基功率器件，碳化硅功率器件的芯片面积更小，电流密度更大，故其工作损耗产生的热量更加集中。因此，对碳化硅功率器件而言，优化芯片热分布，尽可能使热量均匀分布，避免热局域积累导致碳化硅器件性能的退化或可靠性问题，显得尤为重要。
发明内容
为了解决碳化硅功率器件热量局域积累导致的碳化硅器件性能的退化或可靠性降低的技术问题，本公开提供了一种碳化硅结势垒肖特基半导体器件及其制造方法。
为了实现上述目的，根据本技术方案的一个方面，本技术方案提 供了一种碳化硅结势垒肖特基半导体器件。
根据本公开实施例的碳化硅结势垒肖特基半导体器件，其包括层叠设置的衬底和外延层，所述外延层上表面设置有源区和位于所述有源区周围的终端区，所述有源区包括若干间隔设置的结势垒区，其中，沿所述有源区的中部至边缘的方向，所述结势垒区的间距逐渐增加。
在一些实施方式中，沿所述有源区的中部至边缘的方向，所述结势垒区的宽度逐渐增加。
在一些实施方式中，所述结势垒区的宽度为2μm，沿所述有源区的中部至边缘的方向，所述结势垒区的间距由1μm逐渐增加到4μm。
在一些实施方式中，所述有源区还包括设置在所述外延层上表面的阳极金属层，所述衬底的背面依次设置有欧姆接触金属层和阴极金属层。
在一些实施方式中，所述结势垒区为长条形或环形。
在一些实施方式中，碳化硅结势垒肖特基半导体器件还包括依次设置在所述外延层上表面的介质钝化层和保护层。
在一些实施方式中，所述衬底为N型碳化硅，电阻率为0.01-0.03Ω·㎝，厚度为100μm-180μm。
在一些实施方式中，所述阳极金属层包括叠层设置的第一金属层及第二金属层，所述第一金属层可以和N型SiC形成肖特基接触势垒。
为了实现上述目的，根据本技术方案的第二个方面，本技术方案还提供了一种碳化硅结势垒肖特基半导体器件的制造方法，被设置为制备本公开技术方案提供的上述碳化硅结势垒肖特基半导体器件。
根据本公开实施例的碳化硅结势垒肖特基半导体器件的制造方法，其包括以下步骤：
于一衬底上形成外延层；
向所述外延层注入P型杂质离子并激活，同时形成有源区和终端区的P型离子注入区，有源区的P型离子注入区即为所述势垒区；
在外延层的上表面依次形成阳极金属层、介质钝化层和保护层。
在一些实施方式中，在外延层的上表面依次形成阳极金属层、介质钝化层和保护层之后还包括：所述衬底经减薄处理后依次在所述衬底的背面形成欧姆接触金属层和阴极金属层。
在一些实施方式中，所述介质钝化层为SiO、SiO 2、SiN和SiON中的一种或多种的组合，形成方法为PECVD、LPCVD或ALD，所述介质钝化层的厚度为50-2000nm。
本公开技术方案提出了一种新的有源区结构，相比于相关技术，使得有源区中心的电流密度比有源区边缘区域的电流密度稍低，使得碳化硅结势垒肖特基半导体器件在正向工作时的热分布更均匀，以此达到优化器件热分布的目的，避免热量局部积累导致碳化硅器件性能的退化或可靠性问题。
附图说明
构成本公开的一部分的附图用来提供对本公开的进一步理解，使得本公开的其它特征、目的和优点变得更明显。本公开的示意性实施例附图及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为相关技术中碳化硅肖特基二极管的原理说明图；
图2为相关技术中碳化硅肖特基二极管的平面结构参考图；
图3为相关技术中碳化硅肖特基二极管的剖面结构参考图；
图4为本公开实施例提供的一种碳化硅结势垒肖特基半导体器件 的平面示意图；
图5为本公开实施例提供的一种碳化硅结势垒肖特基半导体器件的剖面示意图；
图6为本公开实施例提供的另一种碳化硅结势垒肖特基半导体器件的平面示意图；
图7-15为本公开实施例提供的碳化硅结势垒肖特基半导体器件的制造方法各步骤对应的结构示意图。
图中：
1、衬底；2、外延层；3、有源区；4、终端区；5、结势垒区；6、阳极金属层；7、欧姆接触金属层；8、阴极金属层；9、介质钝化层；10、保护层；11、掩膜层。
具体实施方式
为了使本技术领域的人员更好地理解本公开方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分的实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、 方法、产品或设备固有的其它步骤或单元。
在本公开中，术语“上”、“下”、“内”、“中”、“外”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系。这些术语主要是为了更好地描述本公开及其实施例，并非用于限定所指示的装置、元件或组成部分必须具有特定方位，或以特定方位进行构造和操作。
并且，上述部分术语除了可以用于表示方位或位置关系以外，还可能用于表示其他含义，例如术语“上”在某些情况下也可能用于表示某种依附关系或连接关系。对于本领域普通技术人员而言，可以根据具体情况理解这些术语在本公开中的具体含义。
此外，术语“设置”、“连接”、“固定”应做广义理解。例如，“连接”可以是固定连接，可拆卸连接，或整体式构造；可以是机械连接，或电连接；可以是直接相连，或者是通过中间媒介间接相连，又或者是两个装置、元件或组成部分之间内部的连通。对于本领域普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
由于碳化硅属于宽禁带半导体，碳化硅二极管如果采用PN结结构，开启电场大(3V左右)，会使得导通损耗非常高。通常碳化硅二极管采用肖特基结结构，开启电场低(小于1V)，导通损耗小。但碳化硅肖特基二极管(SBD)在反向偏置时，由于肖特基势垒会受镜像力的影响而降低，导致反向漏电偏大。为了解决该问题，如图1所示，碳化硅肖特基二极管一般采用结势垒肖特基(JBS)结构，即在外延层表面间隔分布P型离子注入区，使碳化硅结势垒肖特基二极管兼具SBD二极管正向特性和PN二极管反向特性，正向导通电压低，反向 漏电小。
如图1所示，碳化硅JBS二极管正向导通时，由于碳化硅PN结导通电压大，肖特基结会先导通，电流从依次流过阳极肖特基接触、碳化硅外延层、碳化硅衬底和阴极。相关技术方案中，如图2和3所示，碳化硅JBS二极管有源区的肖特基接触的宽度(即P型离子注入区间距)不变，因此，碳化硅JBS二极管正向工作时电流会均匀流过芯片有源区。但由于芯片的边缘散热快，中心散热慢，所以芯片中心的温度会偏高，可能带来性能退化和可靠性问题。为了解决这一技术问题，本公开提出了一种碳化硅半导体器件，在相关技术的基础上进一步优化碳化硅半导体器件的结构，优化其热分布，提高其工作稳定性。
下面将参照附图对本公开的示例性实施方式作详细说明。在图中，为了方便说明，放大了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不是完全准确的反映出器件的实际尺寸，但是它们还是完整的反映了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。参考图是本公开的理想化实施例的示意图，本公开所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。
如图4和5所示，本公开实施例提供的碳化硅结势垒肖特基半导体器件包括依次层叠设置的阴极金属层8、欧姆接触金属层7、衬底1和外延层2，所述外延层2上表面设置有源区3和位于所述有源区3周围的终端区4，所述有源区3包括若干间隔设置的结势垒区5以及设置在所述外延层2上表面的阳极金属层6。碳化硅结势垒肖特基半导体器件还包括依次设置在所述外延层上表面的介质钝化层9和保护层10。
其中，衬底1和外延层2具有第一导电类型，衬底1选择为N型 碳化硅。终端场限环和结势垒区5具有第二导电类型，结势垒区5通过P型杂质离子的注入形成。结势垒区5可以为如图4所示的长条形，也可以为环形，本公开不做具体的限定，具体根据碳化硅结势垒肖特基半导体器件的具有应用场景和设计需求来确定。
阳极金属层6作为碳化硅结势垒肖特基半导体器件的阳极发挥作用，阴极金属层8作为碳化硅结势垒肖特基半导体器件的阴极发挥作用。介质钝化层9起到器件及布线之间的电气隔离作用，作为绝缘层发挥作用，保护层10被设置为保护其覆盖的结构受到表面污染及物理损坏。
在一些实施例中，如图4和5所示，沿所述有源区3的中部至边缘的方向，所述结势垒区5的间距逐渐增加。通过这一结构改进，可以使得芯片中心的电流密度比芯片边缘区域的电流密度稍低，以此达到优化芯片热分布的目的，避免热局域积累导致碳化硅器件性能的退化或可靠性问题。
在一些实施方式中，一种具体的有源区结构方案可以是结势垒区宽度为2μm，从有源区中心到边缘，结势垒区间距可以按1.0μm、1.2μm、1.4μm、1.6μm、2.0μm、2.4μm、2.7μm、3.0μm、3.5μm、4.0μm的规律逐渐增大。需要说明的是，从有源区中心到边缘，结势垒区的间距的变化趋势为逐渐增大，但是某一特定宽度的间距可以为一个，也可以为多个，例如从有源区的中心往边缘，长条形的结势垒区有10条，它们从中心往边缘排布时，结势垒区的间距可以为1.0μm，1.0μm，1.5μm，1.5μm，1.5μm，1.8μm，1.8μm，1.8μm，2.0μm，2.0μm，其中1.0μm和2.0μm的间距分别存在有两个，1.5μm和1.8μm的间距分别存在有三个。
在一些实施例中，如图6所示，沿所述有源区3的中部至边缘的方向，结势垒区5的间距逐渐增加，并且结势垒区5的宽度逐渐增加， 通过这一结构改进，同样可以使得芯片中心的电流密度比芯片边缘区域的电流密度稍低，以此达到优化芯片热分布的目的，避免热局域积累导致碳化硅器件性能的退化或可靠性问题。
通过实验发现，沿所述有源区的中部至边缘的方向，结势垒区的间距保持不变，结势垒区的宽度逐渐增加，其也有一定的优化热分布的效果，但效果远没有图4-图6的方案好，因为结势垒区宽度的增加对正向电流没有贡献，反而会增加更多的芯片面积。
根据上述实施例的碳化硅结势垒肖特基半导体器件还可以包括其他的必要组件或结构，并且对应的布置位置和连接关系均可参考相关技术中的碳化硅半导体器件，各未述及结构的连接关系、操作及工作原理对于本领域的普通技术人员来说是可知的，在此不再详细描述。
本实施例还公开了上述实施例提供的碳化硅结势垒肖特基半导体器件的加工方法，其包括以下步骤：
步骤1：如图7所示，提供一个衬底1，并在衬底1上形成外延层2。
具体的，衬底1选择为N型碳化硅，其电阻率为0.01～0.03Ωcm，厚度为320～380μm，外延层2的厚度为5-100μm，N型离子掺杂浓度为1×10 14～5×10 16ions/cm 3，可以形成合适的N -漂移层。320～380μm的厚度便于正面结构的加工和成型，而且为后期的衬底减薄工艺预留了加工空间。
步骤2：如图8所示，在外延层2的上表面沉积形成掩膜层11，然后通过干法刻蚀去除部分掩膜层，暴露出离子注入区域，然后将P型杂质离子注入到掩膜层11没有覆盖的离子注入区域，该步骤中可以同时形成有源区和终端区的P型离子注入区，其中有源区部分的P型离子注入区即为结势垒区5。
该步骤中所采用的掩膜层11可以为SiO 2、多晶硅或者二者的组合，掩膜层的厚度为0.2-4μm；P型离子注入的工艺可以为单步离子注入工艺或多步离子注入工艺，所采用的离子为Al离子、B离子或者二者的组合。
步骤3：如图9所示，去除注入剩余的掩膜层，在结构的表面制备碳膜作为高温激活的保护层，然后通过高温来激活注入的P型杂质离子，激活后去除碳膜。其中碳膜的制备方法为光刻胶碳化或射频溅镀，碳膜的厚度为0.05-2μm，激活温度为1500-1900℃。
步骤4：如图10所示，制备阳极金属层6，其中阳极金属层6为叠层金属，包括层叠设置的第一金属层和第二金属层。其中第一金属层与外延层的上表面连接，其可以和N型碳化硅形成肖特基接触势垒，第一金属层的材料包括但不限于Ti、Mo、W、Pd、Ni、Au或其组合；第二金属层包括但不限于Al、Ti/Al金属叠层、Ni/Al金属叠层或Ti/Ni/Al金属叠层，阳极金属层的总厚度为2-5μm。阳极金属层与碳化硅半导体材料的交界处形成空间电荷区和自建电场，在外加电压为零时，载流子的扩散运动与反向的漂移运动达到动态平衡，这时阳极金属层与SiC半导体交界处形成一个接触势垒，这就是肖特基势垒。
步骤5：如图11所示，制备介质钝化层9。介质钝化层9包括但不限于SiO、SiO 2、SiN、SiON或它们的组合，具体可以通过沉积方法来制备，可以采用的沉积方法包括但不限于PECVD、LPCVD、ALD，介质钝化层的厚度为50-2000nm。
步骤6：如图12所示，制备顶层的保护层10，其中保护层10为聚酰亚胺(PI)钝化层，聚酰亚胺(PI)钝化层固化后的厚度为1-5μm。
步骤7：如图13所示，衬底减薄。通过研磨或其他减薄工艺将碳化硅衬底1减薄至100-180μm。
步骤8：如图14所示，在衬底1的背面进行欧姆金属的沉积，经过激光退火后形成欧姆接触金属层7，欧姆接触金属层7可以为Ni、Ti/Ni金属叠层、Ti/Al金属叠层、Ti/Ni/Al金属叠层中的至少一种，其厚度为10-500nm。
步骤9：如图15所示，在欧姆接触金属层7的基础上进行阴极金属层8的沉积。采用的阴极金属层为Ti/Ni/Ag金属叠层或Ti/Al/Ni/Ag金属叠层，阴极金属层的总厚度为0.5-4.0μm。
根据上述实施例的碳化硅结势垒肖特基半导体器件的加工方法还可以包括其他的必要步骤，并且对应的步骤实现方式和顺序均可参考相关技术，对于本领域的普通技术人员来说是可知的，在此不再详细描述。
本说明书中部分实施例采用递进或并列的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
以上仅是本公开的具体实施方式，使本领域技术人员能够理解或实现本公开。对这些实施例的多种修改对本领域的技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本公开的精神或范围的情况下，在其它实施例中实现。因此，本将不会被限制于本文所示的这些实施例，而是要符合与本文所申请的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种碳化硅结势垒肖特基半导体器件，包括层叠设置的衬底和外延层，所述外延层上表面设置有源区和位于所述有源区周围的终端区，所述有源区包括若干间隔设置的结势垒区，沿所述有源区的中部至边缘的方向，所述结势垒区的间距逐渐增加。
  2. 根据权利要求1所述的碳化硅结势垒肖特基半导体器件，其中，沿所述有源区的中部至边缘的方向，所述结势垒区的宽度逐渐增加。
  3. 根据权利要求1所述的碳化硅结势垒肖特基半导体器件，其中，所述结势垒区的宽度为2μm，沿所述有源区的中部至边缘的方向，所述结势垒区的间距由1μm逐渐增加到4μm。
  4. 根据权利要求1所述的碳化硅结势垒肖特基半导体器件，其中，所述有源区还包括设置在所述外延层上表面的阳极金属层，所述衬底的背面依次设置有欧姆接触金属层和阴极金属层。
  5. 根据权利要求4所述的碳化硅结势垒肖特基半导体器件，其中，所述阳极金属层包括叠层设置的第一金属层及第二金属层，所述第一金属层可以和N型SiC形成肖特基接触势垒。
  6. 根据权利要求1所述的碳化硅结势垒肖特基半导体器件，其中，所述结势垒区为长条形或环形。
  7. 根据权利要求1所述的碳化硅结势垒肖特基半导体器件，其中，还包括设置在所述外延层上表面的介质钝化层。
  8. 根据权利要求7所述的碳化硅结势垒肖特基半导体器件，其中，还包括设置在所述介质钝化层上表面的保护层。
  9. 一种碳化硅结势垒肖特基半导体器件的制造方法，用于制备权利要求1-8任一项所述的碳化硅结势垒肖特基半导体器件，包括以下步骤：
    于一衬底上形成外延层；
    向所述外延层注入P型杂质离子并激活，同时形成有源区和终端区的P型离子注入区，有源区的P型离子注入区即为所述势垒区；
    在外延层的上表面依次形成阳极金属层、介质钝化层和保护层。
  10. 根据权利要求9所述的制造方法，其中，在外延层的上表面依次形成阳极金属层、介质钝化层和保护层之后还包括：所述衬底经减薄处理后依次在所述衬底的背面形成欧姆接触金属层和阴极金属层。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4340034A1 (en) * 2022-09-15 2024-03-20 Nexperia B.V. Mps diode having a non-uniformly doped region and method for manufacturing the same
EP4340035A1 (en) * 2022-09-15 2024-03-20 Nexperia B.V. Mps diode having non-uniformly spaced wells and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137368A (ja) * 1988-11-18 1990-05-25 Toshiba Corp 半導体整流装置
JP2010003841A (ja) * 2008-06-19 2010-01-07 Toyota Motor Corp 縦型のショットキーダイオード
CN109244146A (zh) * 2018-11-09 2019-01-18 无锡新洁能股份有限公司 优化热分布的碳化硅肖特基二极管及其制造方法
CN109560142A (zh) * 2018-10-29 2019-04-02 厦门市三安集成电路有限公司 新型碳化硅结势垒肖特基二极管及其制作方法
CN110112221A (zh) * 2019-05-29 2019-08-09 西安电子科技大学 一种能够抑制局部电迁移现象的结型势垒肖特基二极管

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2315255A1 (en) * 2009-10-22 2011-04-27 Nxp B.V. Surge protection device
KR101416361B1 (ko) * 2012-09-14 2014-08-06 현대자동차 주식회사 쇼트키 배리어 다이오드 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137368A (ja) * 1988-11-18 1990-05-25 Toshiba Corp 半導体整流装置
JP2010003841A (ja) * 2008-06-19 2010-01-07 Toyota Motor Corp 縦型のショットキーダイオード
CN109560142A (zh) * 2018-10-29 2019-04-02 厦门市三安集成电路有限公司 新型碳化硅结势垒肖特基二极管及其制作方法
CN109244146A (zh) * 2018-11-09 2019-01-18 无锡新洁能股份有限公司 优化热分布的碳化硅肖特基二极管及其制造方法
CN110112221A (zh) * 2019-05-29 2019-08-09 西安电子科技大学 一种能够抑制局部电迁移现象的结型势垒肖特基二极管

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4340034A1 (en) * 2022-09-15 2024-03-20 Nexperia B.V. Mps diode having a non-uniformly doped region and method for manufacturing the same
EP4340035A1 (en) * 2022-09-15 2024-03-20 Nexperia B.V. Mps diode having non-uniformly spaced wells and method for manufacturing the same

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