WO2021258509A1 - 一种减少贾凡尼效应的线路板加工方法 - Google Patents
一种减少贾凡尼效应的线路板加工方法 Download PDFInfo
- Publication number
- WO2021258509A1 WO2021258509A1 PCT/CN2020/106993 CN2020106993W WO2021258509A1 WO 2021258509 A1 WO2021258509 A1 WO 2021258509A1 CN 2020106993 W CN2020106993 W CN 2020106993W WO 2021258509 A1 WO2021258509 A1 WO 2021258509A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit board
- processing method
- development
- ink
- board processing
- Prior art date
Links
- 230000000694 effects Effects 0.000 title claims abstract description 43
- 238000003672 processing method Methods 0.000 title claims abstract description 20
- 230000003247 decreasing effect Effects 0.000 title abstract 3
- 229910000679 solder Inorganic materials 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 238000003825 pressing Methods 0.000 claims description 18
- 238000004381 surface treatment Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 238000007788 roughening Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000000873 masking effect Effects 0.000 abstract 1
- 230000037452 priming Effects 0.000 abstract 1
- 239000002699 waste material Substances 0.000 abstract 1
- 230000003628 erosive effect Effects 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
Definitions
- the invention belongs to the technical field of circuit board processing, and in particular relates to a circuit board processing method that reduces the Gavani effect.
- the Javani effect is also known as the galvanic effect and galvanic corrosion, that is, two connected metals with different activities dissolve and contact the electrolyte to cause a galvanic reaction, and the more active metal atoms lose electrons and are oxidized (corroded). The essence is that the active metal is oxidized. Due to the potential difference between gold and copper, the copper pads connected to the large gold surface in the OSP process will continue to lose electrons and dissolve into divalent copper ions, which will cause the pads to become smaller and affect subsequent component placement and reliability. sex.
- the present invention provides a circuit board processing method that reduces the Javani effect.
- the present invention can effectively prevent the generation of the Javani effect, improve production quality, significantly reduce scrap and increase yield.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 5-15 minutes; the second curing time is 45-85 minutes.
- the first curing time is 10 minutes; the second curing time is 60 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 1-10um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposure area in the exposure process is larger than the edge of the metal layer area by 0.05-0.2 mm.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast pressing is 0.2-0.8 MPa.
- the surface treatment is a micro-etching or roughening treatment. After the micro-etching or roughening treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 10 minutes; the second curing time is 60 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 8um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposed area in the exposure process is 0.1 mm larger than the edge of the metal layer area.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast press is 0.5 MPa.
- the surface treatment is micro-etching, and after the micro-etching treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 10 minutes; the second curing time is 60 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 8um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposed area in the exposure process is 0.1 mm larger than the edge of the metal layer area.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast press is 0.5 MPa.
- the surface treatment is micro-etching, and after the micro-etching treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 5 minutes; the second curing time is 45 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 5um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposure area in the exposure process is larger than the edge of the metal layer area by 0.05 mm.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast pressing is 0.3 MPa.
- the surface treatment is a roughening treatment. After the roughening treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 12 minutes; the second curing time is 80 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 7um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposed area in the exposure process is 0.15 mm larger than the edge of the metal layer area.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast pressing is 0.6 MPa.
- the surface treatment is a micro-etching treatment. After the micro-etching treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- Solder mask ink primer ⁇ exposure ⁇ first development ⁇ solder mask ⁇ second development ⁇ first curing ⁇ fast pressing ⁇ second curing ⁇ surface treatment;
- the first curing time is 15 minutes; the second curing time is 85 minutes.
- solder resist ink primer a copper layer on the substrate and a metal layer electrically connected to the copper layer are coated with solder resist ink.
- the thickness of the ink is 3um.
- solder resist ink is printed on the surface of the circuit board substrate by a printer or a coating machine.
- the exposed area in the exposure process is 0.2 mm larger than the edge of the metal layer area.
- the substrate is developed after the exposure is completed, and the solder resist ink in the unexposed area is cleaned and removed to expose the copper layer.
- solder mask and the second development process a layer of solder mask ink is added to the surface of the substrate after the first development, and the thickness is increased by the second development process.
- the bonding pressure of the fast pressing is 0.8 MPa.
- the surface treatment is a roughening treatment. After the roughening treatment is completed, the solder resist ink layer on the metal layer is removed by a film stripping process to obtain a finished product.
- the first development, solder mask, and second development process are combined to form a thin layer of ink first, and then process to achieve the required ink thickness, reducing side erosion during development; and then through the first curing
- the process combination of fast pressing and second curing will compact the solder resist ink, which can effectively avoid the side corrosion of the development and avoid the occurrence of the Javanni effect.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
- the invention can effectively prevent the generation of the Javanni effect, improve the production quality, obviously reduce the scrap and increase the yield of good products.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
Claims (10)
- 一种减少贾凡尼效应的线路板加工方法,其特征在于,包括以下步骤:阻焊油墨打底→曝光→第一次显影→防焊→第二次显影→第一次固化→快压→第二次固化→表面处理;所述第一次固化的时间为5-15min;所述第二次固化的时间为45-85min。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述第一次固化的时间为10min;所述第二次固化的时间为60min。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述阻焊油墨打底工艺中为在基板上具有铜层以及与所述铜层电性连接的金属层涂布阻焊油墨。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述阻焊油墨打底工艺中,油墨的厚度为1-10um。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述阻焊油墨通过印刷机或者涂覆机印刷在线路板基板的板面。
- 根据权利要求3所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述曝光工艺中的曝光区域比所述金属层区域的边缘大0.05-0.2mm。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述第一次显影工艺,将曝光完成后对所述基板进行显影处理,将未曝光区域的阻焊油墨清洗去除,露出所述铜层。
- 根据权利要求7所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述防焊和第二次显影工艺,在第一次显影后的基板表面在增加一层阻焊油墨,通过二次显影处理,增加厚度。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述快压的贴合压力为0.2-0.8MPa。
- 根据权利要求1所述的减少贾凡尼效应的线路板加工方法,其特征在于,所述表面处理为微蚀或粗化处理,微蚀或者粗化处理完成后通过剥膜工艺去除所述金属层上的阻焊油墨层,得到成品。
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CN202010585557.1A CN111935907A (zh) | 2020-06-24 | 2020-06-24 | 一种减少贾凡尼效应的线路板加工方法 |
CN202010585557.1 | 2020-06-24 |
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Cited By (3)
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CN114578029A (zh) * | 2022-03-02 | 2022-06-03 | 江苏可信电子材料有限公司 | 一种pcb阻焊油墨性能测试方法 |
CN116261269A (zh) * | 2023-03-10 | 2023-06-13 | 江西景旺精密电路有限公司 | 一种贾凡尼效应影响的pcb板制作装置 |
CN117377217A (zh) * | 2023-12-04 | 2024-01-09 | 淮安特创科技有限公司 | 一种pcb板贾凡尼效应影响的设计与测试方法 |
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2020
- 2020-06-24 CN CN202010585557.1A patent/CN111935907A/zh active Pending
- 2020-08-05 WO PCT/CN2020/106993 patent/WO2021258509A1/zh active Application Filing
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US20040079788A1 (en) * | 2002-10-24 | 2004-04-29 | St Assembly Test Services Pte Ltd | Cost effective substrate fabrication for flip-chip packages |
CN101534612A (zh) * | 2009-04-10 | 2009-09-16 | 深圳市博敏电子有限公司 | Pcb板厚铜线路阻焊叠印工艺 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN114578029A (zh) * | 2022-03-02 | 2022-06-03 | 江苏可信电子材料有限公司 | 一种pcb阻焊油墨性能测试方法 |
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CN116261269B (zh) * | 2023-03-10 | 2024-05-24 | 江西景旺精密电路有限公司 | 一种贾凡尼效应影响的pcb板制作装置 |
CN117377217A (zh) * | 2023-12-04 | 2024-01-09 | 淮安特创科技有限公司 | 一种pcb板贾凡尼效应影响的设计与测试方法 |
CN117377217B (zh) * | 2023-12-04 | 2024-03-29 | 淮安特创科技有限公司 | 一种pcb板贾凡尼效应影响的设计与测试方法 |
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