WO2021249127A1 - 像素驱动电路及其驱动方法、显示面板及显示装置 - Google Patents

像素驱动电路及其驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2021249127A1
WO2021249127A1 PCT/CN2021/094187 CN2021094187W WO2021249127A1 WO 2021249127 A1 WO2021249127 A1 WO 2021249127A1 CN 2021094187 W CN2021094187 W CN 2021094187W WO 2021249127 A1 WO2021249127 A1 WO 2021249127A1
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transistor
circuit
sub
coupled
node
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PCT/CN2021/094187
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English (en)
French (fr)
Inventor
皇甫鲁江
王丽
郑灿
刘利宾
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京东方科技集团股份有限公司
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Priority to US17/791,965 priority Critical patent/US11790850B2/en
Priority to DE112021000457.3T priority patent/DE112021000457T5/de
Publication of WO2021249127A1 publication Critical patent/WO2021249127A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G—PHYSICS
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    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED display devices are widely used due to their self-luminous, fast response, wide viewing angle and can be fabricated on flexible substrates.
  • OLED display devices include multiple sub-pixels. Each sub-pixel includes a pixel drive circuit and a light-emitting device, and the light-emitting device is driven to emit light through the pixel drive circuit to realize display.
  • a pixel driving circuit which includes a reset sub-circuit, a compensation sub-circuit, a light emission control sub-circuit, and a driving sub-circuit.
  • the reset sub-circuit is coupled to the light-emission control sub-circuit, the scanning timing signal terminal and the initialization signal terminal.
  • the lighting control sub-circuit is also coupled to the first node and the first lighting timing signal terminal.
  • the compensation sub-circuit is coupled to the first node, the second node and the scan timing signal terminal.
  • the driving sub-circuit is coupled to the first node, the second node, the first voltage signal terminal, and the second light-emitting timing signal terminal.
  • the reset sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the light emission control sub-circuit in response to the scanning timing signal received at the scanning timing signal terminal.
  • the lighting control sub-circuit is configured to transmit the initialization signal to the first node in response to the first lighting timing signal received at the first lighting timing signal terminal.
  • the compensation sub-circuit is configured to transmit an initialization signal from the first node to the second node under the control of the scan timing signal to reset the voltage of the second node.
  • the driving sub-circuit is configured to, in the process of resetting the voltage of the second node, in response to the second light-emitting timing signal received at the second light-emitting timing signal terminal, turn off the first voltage A conductive path from the signal terminal to the initialization signal terminal.
  • the reset sub-circuit includes a first transistor; the control electrode of the first transistor is coupled to the scan timing signal terminal, and the first electrode of the first transistor is coupled to the initialization signal terminal. Then, the second pole of the first transistor is coupled to the light emission control sub-circuit.
  • the light emission control sub-circuit includes a second transistor; the control electrode of the second transistor is coupled to the first light emission timing signal terminal, and the first electrode of the second transistor is coupled to the first node, so The second electrode of the second transistor is coupled to the second electrode of the first transistor.
  • the compensation sub-circuit includes a third transistor; the control electrode of the third transistor is coupled to the scan timing signal terminal, the first electrode of the third transistor is coupled to the first node, and the third transistor is The second electrode of the transistor is coupled to the second node.
  • the driver sub-circuit includes a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the first voltage signal terminal.
  • the first pole of the five transistor is coupled; the control pole of the fifth transistor is coupled to the second light-emitting timing signal terminal, and the second pole of the fifth transistor is coupled to the first node.
  • the driver sub-circuit includes a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the fourth transistor is Is coupled to the first node; the control electrode of the fifth transistor is coupled to the second light-emitting timing signal terminal, and the first electrode of the fifth transistor is coupled to the first voltage signal terminal.
  • the pixel driving circuit further includes an energy storage sub-circuit and a data writing sub-circuit.
  • the energy storage sub-circuit is coupled to the second node and the third node; the energy storage sub-circuit is configured to charge under the action of the voltage of the second node and the third node , And coupling the voltage of the second node according to the voltage of the third node to change the voltage of the second node and maintain the voltage of the second node.
  • the data writing sub-circuit is coupled to the third node, the input control signal terminal, and the data signal terminal; the data writing sub-circuit is configured to respond to the input control signal received at the input control signal terminal Signal to transmit the data signal received at the data signal terminal to the third node.
  • the energy storage sub-circuit includes a first capacitor; a first terminal of the first capacitor is coupled to the third node, and a second terminal of the first capacitor is coupled to the second node Coupling.
  • the data writing sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is coupled to the input control signal terminal, the first electrode of the sixth transistor is coupled to the data signal terminal, and the The second electrode of the sixth transistor is coupled to the third node.
  • the input control signal terminal is the second light-emitting timing signal terminal
  • the data writing sub-circuit is also coupled to the scanning timing signal terminal; the data writing sub-circuit is configured to , In response to the second light-emitting timing signal and the scanning timing signal, transmitting the data signal received at the data signal terminal to the third node.
  • the data writing sub-circuit includes a sixth transistor and a seventh transistor; the control electrode of the sixth transistor is coupled to the second light-emitting timing signal terminal, and the first The electrode is coupled to the second electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the third node; the control electrode of the seventh transistor is coupled to the scan timing signal terminal, The first electrode of the seventh transistor is coupled to the data signal terminal.
  • the pixel driving circuit further includes a reference voltage sub-circuit; the reference voltage sub-circuit is also coupled to the third node, the first light-emitting timing signal terminal, and the reference voltage signal terminal.
  • the reference voltage sub-circuit is further configured to, in response to the first lighting timing signal received at the first lighting timing signal terminal, transmit the reference voltage signal received at the reference voltage signal terminal to the first lighting timing signal terminal.
  • the reference voltage sub-circuit further includes an eighth transistor; the control electrode of the eighth transistor is coupled to the first light-emitting timing signal terminal, and the first electrode of the eighth transistor is connected to the The reference voltage terminal is coupled, and the second electrode of the eighth transistor is coupled to the third node.
  • the compensation sub-circuit is further configured to cause the driving sub-circuit to generate a self-saturation state under the control of the scan timing signal.
  • the driving sub-circuit is further configured to generate a self-saturation state under the action of the compensation sub-circuit in response to the second light-emitting timing signal, so as to generate a self-saturation state according to the first voltage received at the first voltage signal terminal.
  • Signal generate a compensation signal, and transmit the compensation signal to the second node.
  • a driving signal is generated according to the first voltage signal.
  • the reset sub-circuit is also coupled to the light-emitting device; the reset sub-circuit is further configured to respond to the scan timing signal received at the scan timing signal terminal, The initialization signal received at the initialization signal terminal is transmitted to the light-emitting device to reset the light-emitting device.
  • the light-emitting control sub-circuit is also coupled to the light-emitting device.
  • the light-emitting control sub-circuit is further configured to, in response to the first light-emitting timing signal, transmit a driving signal from the driving sub-circuit to the light-emitting device to drive the light-emitting device to emit light.
  • the reset sub-circuit when the reset sub-circuit includes a first transistor, the second electrode of the first transistor is also coupled to the light emitting device. In the case where the light emission control sub-circuit includes a second transistor, the second pole of the second transistor is also coupled to the light emitting device.
  • the reset sub-circuit includes a first transistor
  • the light emission control sub-circuit includes a second transistor
  • the compensation sub-circuit includes a third transistor
  • the driver sub-circuit includes a fourth transistor and a fifth transistor.
  • the pixel driving circuit further includes an energy storage sub-circuit, a data writing sub-circuit, and a reference voltage sub-circuit; the energy storage sub-circuit includes a first capacitor, the data writing sub-circuit includes a sixth transistor, or the data The writing sub-circuit includes a sixth transistor and a seventh transistor, and the reference voltage sub-circuit includes an eighth transistor.
  • the control electrode of the first transistor is coupled to the scan timing signal terminal, the first electrode of the first transistor is coupled to the initialization signal terminal, and the second electrode of the first transistor is coupled to the second The second electrode of the transistor is coupled to the light emitting device.
  • the control electrode of the second transistor is coupled to the first light-emitting timing signal terminal, the first electrode of the second transistor is coupled to the first node, and the second electrode of the second transistor is coupled to the first node.
  • the second electrode of the first transistor is coupled to the light emitting device.
  • the control electrode of the third transistor is coupled to the scan timing signal terminal, the first electrode of the third transistor is coupled to the first node, and the second electrode of the third transistor is coupled to the second node. Node coupling.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the first voltage signal terminal.
  • the first pole of the five transistor is coupled; the control pole of the fifth transistor is coupled to the second light-emitting timing signal terminal, and the second pole of the fifth transistor is coupled to the first node.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the first electrode of the fourth transistor is coupled to the second node.
  • the two poles are coupled to the first node; the control pole of the fifth transistor is coupled to the second light-emitting timing signal terminal, and the first pole of the fifth transistor is coupled to the first voltage signal terminal.
  • the first end of the first capacitor is coupled to the third node, and the second end of the first capacitor is coupled to the second node.
  • the data writing sub-circuit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the input control signal terminal, the first electrode of the sixth transistor is coupled to the data signal terminal, and the The second electrode of the sixth transistor is coupled to the third node.
  • the control electrode of the sixth transistor is coupled to the second light-emitting timing signal terminal, and the first electrode of the sixth transistor is connected to the The second electrode of the eighth transistor is coupled, the second electrode of the sixth transistor is coupled to the third node; the control electrode of the seventh transistor is coupled to the scan timing signal terminal, the The first electrode of the seventh transistor is coupled to the data signal.
  • the control electrode of the eighth transistor is coupled to the first light-emitting timing signal terminal, the first electrode of the eighth transistor is coupled to the reference voltage terminal, and the second electrode of the eighth transistor is coupled to the The third node is coupled.
  • a pixel driving method is provided, which is applied to the above-mentioned pixel driving circuit, where the pixel driving circuit includes an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a light emission control sub-circuit, a driving sub-circuit, and
  • the data writing sub-circuit and the reference voltage sub-circuit, and the energy storage sub-circuit is coupled to the second node and the third node; the data writing sub-circuit and the third node, the input control signal terminal and The data signal terminal is coupled;
  • the reference voltage sub-circuit is also coupled to the third node, the first light-emitting timing signal terminal, and the reference voltage signal terminal;
  • the reset sub-circuit and the light-emitting control sub-circuit are also connected to the light-emitting device
  • the pixel driving method includes: one frame period includes a reset phase, an input and compensation phase, and a light-emitting phase.
  • the reference voltage sub-circuit transmits the reference voltage signal received at the reference voltage signal terminal to the The third node.
  • the reset sub-circuit transmits the initialization signal received at the initialization signal terminal to the light-emitting control sub-circuit and the light-emitting device, so as The light-emitting device is reset.
  • the lighting control sub-circuit transmits the initialization signal to the first node in response to the first lighting timing signal received at the first lighting timing signal terminal.
  • the compensation sub-circuit transmits the initialization signal from the first node to the second node under the control of the scan timing signal to reset the voltage of the second node.
  • the driving sub-circuit disconnects the conductive path from the first voltage signal terminal to the initialization signal terminal in response to the second lighting timing signal received at the second lighting timing signal terminal.
  • the reset sub-circuit transmits the initialization signal received at the initialization signal terminal to the scan timing signal received at the scan timing signal terminal.
  • the light-emitting device is used to continuously reset the light-emitting device.
  • the data writing sub-circuit transmits the data signal received at the data signal terminal to the third node in response to the input control signal received at the input control signal terminal.
  • the compensation sub-circuit causes the driving sub-circuit to generate a self-saturation state under the control of the scanning timing signal.
  • the driving sub-circuit In response to the second light-emitting timing signal, the driving sub-circuit generates a self-saturation state under the action of the compensation sub-circuit to generate a compensation signal according to the first voltage signal received at the first voltage signal terminal , And transmit the compensation signal to the second node.
  • the energy storage sub-circuit is charged under the action of the voltages of the second node and the third node.
  • the reset sub-circuit transmits the reference voltage signal received at the reference voltage signal terminal to the first light-emitting timing signal received at the first light-emitting timing signal terminal.
  • Three nodes Under the action of the voltage of the third node, the energy storage sub-circuit couples the potential of the second node to change the voltage of the second node and maintain the voltage of the second node.
  • the driving sub-circuit responds to the second light-emitting timing signal, and under the coupling action of the energy storage sub-circuit, generates a driving signal according to the first voltage signal, and transmits the driving signal to the light-emitting Control sub-circuit.
  • the light-emitting control sub-circuit transmits the driving signal from the driving sub-circuit to the light-emitting device in response to the first light-emitting timing signal, so as to drive the light-emitting device to emit light.
  • the data writing sub-circuit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the input control signal terminal, and the first electrode of the sixth transistor is connected to the data The signal terminal is coupled, and when the second electrode of the sixth transistor is coupled to the third node, the sixth transistor is turned on under the control of the input control signal during the input and compensation stage , Transmitting the data signal to the third node.
  • the input control signal terminal is the second light-emitting timing signal terminal
  • the data writing sub-circuit is also coupled to the scanning timing signal terminal
  • the data writing sub-circuit includes a sixth transistor and a seventh transistor
  • the control electrode of the sixth transistor is coupled to the second light-emitting timing signal terminal
  • the first electrode of the sixth transistor is coupled to the second electrode of the seventh transistor
  • the first electrode of the sixth transistor is The two poles are coupled to the third node; when the control pole of the seventh transistor is coupled to the scan timing signal terminal, and the first pole of the seventh transistor is coupled to the data signal terminal
  • the seventh transistor is turned on under the control of the scan timing signal to transmit the data signal to the first pole of the sixth transistor
  • the sixth transistor is in the first pole. Turn on under the control of the light-emitting timing signal, and transmit the data signal to the third node.
  • a display panel including: the pixel driving circuit described above.
  • the display panel includes a plurality of sub-pixels, one sub-pixel includes one pixel driving circuit, and the plurality of sub-pixels are arranged in an array with multiple rows and multiple columns.
  • the display panel further includes a plurality of scanning timing signal lines and a plurality of light-emitting timing signal lines extending along the row direction; the scanning timing signal terminal and the n-th scanning timing signal line of each pixel driving circuit included in the n-th row of sub-pixels Coupled; the first light-emitting timing signal terminal of each pixel driving circuit included in the n-th row of sub-pixels is coupled to the n-th light-emitting timing signal line; in addition to the first row of sub-pixels, each of the n-th row of sub-pixels includes The second light-emitting timing signal terminal of the pixel driving circuit is coupled to the n-1th light-emitting timing signal line.
  • a display device including the display panel as described above.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments
  • 2A is a structural diagram of a pixel driving circuit according to some embodiments of the related art
  • FIG. 2B is a timing diagram corresponding to the pixel driving circuit of FIG. 1;
  • FIG. 3 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is another structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 5 is still another structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 6 is another structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a timing diagram corresponding to the pixel driving circuit of FIG. 3, FIG. 5, and FIG. 6;
  • FIG. 8 is another structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 9 is another structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a timing diagram corresponding to the pixel driving circuit of FIG. 4, FIG. 8 and FIG. 9;
  • FIG. 11 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 12 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed here are not necessarily limited to the content of this document.
  • the display device includes a display panel 01.
  • the display panel 01 includes a display area AA (Active Area, AA area for short; also referred to as an effective display area) and a peripheral area BB located on at least one side of the display area AA.
  • AA Active Area, AA area for short; also referred to as an effective display area
  • BB peripheral area
  • the display area AA is provided with a plurality of sub-pixels 10, a plurality of scanning timing signal lines GL and a plurality of light emitting timing signal lines EL extending in the horizontal direction X, and a plurality of data extending in the vertical direction Y.
  • Signal line DL For the convenience of description, the above-mentioned multiple sub-pixels 10 in the present disclosure are described by taking a matrix arrangement as an example. Illustratively, the multiple sub-pixels 10 are arranged in N rows and M columns.
  • the sub-pixels 10 arranged in a row along the horizontal direction X are called a row of sub-pixels
  • the sub-pixels 10 arranged in a row along the vertical direction Y are called a column of sub-pixels.
  • a row of sub-pixels can be associated with one or two scanning timing signals.
  • Line GL is coupled
  • a row of sub-pixels can also be coupled to one or two light-emitting timing signal lines EL
  • a column of sub-pixels can be coupled to one data signal line DL.
  • the sub-pixel 10 is provided with a pixel driving circuit 100 for controlling the sub-pixel 10 to display, and the pixel driving circuit 100 is provided on the base substrate 001 of the display panel 01.
  • the above-mentioned display panel 01 may be an organic light emitting diode (Organic Light Emitting Diode, OLED for short) display panel, a Quantum Dot Light Emitting Diode (QLED for short) display panel, etc., which are not specifically limited in the present disclosure.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • the pixel driving circuit 100 generally includes elements such as switching transistors, driving transistors, and storage capacitors.
  • the opposite ends of the storage capacitor are the reference potential end and the signal holding end, respectively, and the signal holding end of the storage capacitor is coupled to the control electrode (gate) of the driving transistor.
  • the storage capacitor is used to maintain the voltage signal, so that the potential of the signal holding terminal can be kept constant, and a voltage is formed between the gate and the source of the driving transistor to control the formation of the driving transistor.
  • the driving current formed by the driving transistor is unstable, which affects the light-emitting brightness of the light-emitting device, and further affects the display effect of the display device.
  • a 7T1C pixel driving circuit 100' is provided in the related art.
  • the pixel driving circuit 100' includes a switching transistor T1, a storage capacitor C, a driving transistor T2, a compensation transistor T3, and a first The reset transistor T4, the second reset transistor T5, the first control transistor T6, and the second control transistor T7.
  • the connection relationship between the above-mentioned multiple transistors can be referred to the accompanying drawings.
  • the second transistor T2, the third transistor T3, and the seventh transistor The node where the transistors T7 are coupled to each other is the first node N1, the reference voltage terminal of the storage capacitor C is coupled to the third node N3, the signal holding terminal of the storage capacitor C is coupled to the second node N2, and the control electrode of the driving transistor T2 is connected to The second node N2 is coupled.
  • the driving process of the aforementioned pixel driving circuit 100' is that one frame period includes a reset phase P1, an input and compensation phase P2, and a light-emitting phase P3.
  • the reset phase P1 under the control of the first scan timing signal s1 transmitted from the first scan timing signal terminal S1, the first reset transistor T4 is turned on to transmit the reference voltage signal vref received at the reference voltage terminal Vref to The third node N3, the second reset transistor T5 is turned on, the initialization signal vinit received at the initialization signal terminal Vinit is transmitted to the second node N2, the voltage of the second node N2 is reset, and the signal holding terminal of the storage capacitor C is reset. Reset.
  • the switching transistor T1 is turned on to transmit the data signal data received at the data signal terminal Data to the third node N3; the compensation transistor T3 is turned on, so that the control electrode and the second electrode of the driving transistor T2 are turned on, so that the driving transistor T2 is in a self-saturation state, thereby driving the first voltage signal vdd received at the first voltage signal terminal Vdd
  • the threshold voltage V th of the transistor T2 is written into the second node N2, and the storage capacitor C is charged under the action of the third node N3 and the second node N2.
  • the first control transistor T6 is turned on, and the reference voltage signal vref received at the reference voltage terminal Vref is transmitted to the third node N3, namely
  • the voltage of the reference voltage terminal of the storage capacitor C changes from the voltage of the data signal data to the voltage of the reference voltage signal vref.
  • the storage capacitor C causes the voltage at the signal holding terminal to change by the same voltage difference, that is to say, the voltage at the storage capacitor C Under the action of, the voltage of the second node N2 jumps as the voltage of the third node N3 changes.
  • the driving transistor T2 is turned on and forms a driving signal according to the first voltage signal vdd at the first voltage signal terminal Vdd.
  • the second control transistor T7 is turned on under the control of the light-emitting timing signal emn, and transmits the driving signal to the light-emitting diode L, thereby driving the light-emitting diode L to emit light.
  • each pixel driving circuit 100' in a row of sub-pixels receives from the first scan timing sequence
  • the first scan timing signal s1 at the signal terminal S1 is the same signal as the second scan timing signal s2 from the second scan timing signal terminal S2 received by the pixel driving circuit 100' in the previous row of sub-pixels, that is, the nth row sub-pixel
  • the first scan signal terminal S1 of each pixel drive circuit 100' in the pixel and the second scan signal terminal S2 of each pixel drive circuit 100' in the n-1th row of sub-pixels are connected to the same scan timing signal line GL (n-1th row).
  • One scan timing signal line GL is coupled, and one scan timing signal line GL is coupled to the two rows of sub-pixels before and after it to achieve sharing.
  • the first scan timing signal terminal S1 is simultaneously denoted by S(n-1)
  • the second scan timing signal terminal S2 is simultaneously Expressed by Sn.
  • the driving signal generated by the driving transistor T2 is the driving current.
  • I ⁇ (V gs -V th ) 2
  • V gs is the gate-source voltage difference of the drive transistor T2.
  • the formed drive signal is related to the potential of the gate of the drive transistor.
  • the stability of the gate potential of the drive transistor T2 can affect The stability and effective value of the formed driving signal affects the stability and sustainability of the light-emitting diode.
  • the gate of the driving transistor T2 is coupled to the second node N2, so the voltage retention rate of the second node N2 will affect the light-emitting effect of the light-emitting device, and the voltage of the second node N2 is consistent with the voltage of the signal holding terminal of the storage capacitor C, That is, the higher the voltage retention rate of the storage capacitor C, the more stable the light-emitting brightness of the light-emitting diode, and the better the light-emitting effect.
  • the off-state current is also called leakage current.
  • the compensation transistor T3 and the first control transistor T6 coupled to the second node N2 are both turned off. At this time, the compensation The leakage current of the transistor T3 and the first control transistor T6 will cause the leakage of the second node N2, thereby reducing the voltage retention rate of the second node N2.
  • the pixel driving circuit 100' includes two leakage channels, the first leakage path from the second node N2 through the compensation transistor T3 to the first node N1, and the second node N2 through the second leakage path.
  • the second leakage path from the reset transistor T5 to the initialization signal terminal Vinit.
  • the inventor of the present disclosure has verified that the potential difference between the second node N2 and the initialization signal terminal Vinit is greater than the potential difference between the second node N2 and the first node N1, so the leakage amount of the second leakage channel
  • the (absolute value) is much larger than the leakage amount (absolute value) of the first leakage channel.
  • the second node N2 has a greater degree of leakage, so that the voltage retention rate of the storage capacitor C is insufficient, and the driving signal output by the driving transistor T3 is unstable, thereby causing the light-emitting device
  • the luminous brightness changes too much, the stability is poor, and it produces a sense of visual flicker.
  • the components in each pixel driving circuit in the display device are different, so the leakage degree of the second node N2 in each pixel driving circuit is not consistent, causing the light emitting device driven by each pixel driving circuit to emit light.
  • the brightness is not uniform, which leads to abnormalities such as uneven display on the display screen.
  • the pixel driving circuit 100 includes: an energy storage sub-circuit 101, a reset sub-circuit 102, a compensation sub-circuit 103, The light emission control sub-circuit 104, the driving sub-circuit 105, the data writing sub-circuit 106, and the reference voltage sub-circuit 107.
  • the energy storage sub-circuit 101 is coupled to the second node N2 and the third node N3.
  • the reset sub-circuit 102 is coupled to the light-emitting control sub-circuit 104, the scan timing signal terminal Sn and the initialization signal terminal Vinit.
  • the emission control sub-circuit 104 is also coupled to the first node N1 and the first emission timing signal terminal EM1.
  • the compensation sub-circuit 103 is coupled to the first node N1, the second node N2 and the scan timing signal terminal Sn.
  • the driving sub-circuit 105 is coupled to the first node N1, the second node N2, the first voltage signal terminal Vdd, and the second light emitting timing signal terminal EM2.
  • the energy storage sub-circuit 101 is configured to charge under the action of the voltages of the second node N2 and the third node N3, and couple the voltage of the second node N2 according to the voltage of the third node N3 to change the second node N2.
  • the voltage of the node N2 is maintained, and the voltage of the second node N2 is maintained.
  • the reset sub-circuit 102 is configured to transmit the initialization signal vinit received at the initialization signal terminal Vinit to the light emission control sub-circuit 104 in response to the scan timing signal sn received at the scan timing signal terminal Sn.
  • the light emission control sub-circuit 104 is configured to transmit the initialization signal vinit to the first node N1 in response to the first light emission timing signal em1 received at the first light emission timing signal terminal EM1.
  • the compensation sub-circuit 103 is configured to transmit the initialization signal vinit from the first node N1 to the second node N2 under the control of the scan timing signal sn to reset the voltage of the second node N2.
  • the reset sub-circuit 102 is configured to transmit the initialization signal vinit to the second node N2 through the light emission control sub-circuit 104 and the compensation sub-circuit 103 to reset the potential of the second node N2.
  • the transmission process of the initialization signal vinit to the second node N2 is that the initialization signal vinit transmitted at the initialization signal terminal Vinit sequentially passes through the reset sub-circuit 102, the light-emission control sub-circuit 104, the third node N3 and the compensation sub-circuit 103 , And finally transmitted to the second node N2, resetting the voltage of the second node N2.
  • the reset sub-circuit 102 is also coupled to the light-emitting device 108, and the reset sub-circuit 102 is configured to receive at the initialization signal terminal Vinit in response to the scan timing signal sn received at the scan timing signal terminal Sn.
  • the initialization signal vinit is transmitted to the light-emitting device 108 to reset the light-emitting device 108.
  • the driving sub-circuit 105 is configured to, in the process of resetting the voltage of the second node N2, in response to the second light-emitting timing signal em2 received at the second light-emitting timing signal terminal EM2, disconnect the first voltage signal terminal Vdd to Initialize the conductive path of the signal terminal Vinit.
  • the above-mentioned driving sub-circuit 105 is also configured to generate a self-saturation state under the action of the compensation sub-circuit 103 in response to the second light-emitting timing signal em2, so that according to the first voltage signal vdd received at the first voltage signal terminal Vdd, The compensation signal is generated and transmitted to the second node N2.
  • the driving sub-circuit 105 is configured to generate a compensation signal and transmit the compensation signal to the second node N2.
  • the compensation sub-circuit 103 is also configured to, under the control of the scan timing signal sn, The driver sub-circuit 105 generates a self-saturation state.
  • the above-mentioned driving sub-circuit 105 is also configured to respond to the second light-emitting timing signal em2, and under the coupling action of the energy storage sub-circuit 101, generate a driving signal according to the first voltage signal vdd, and transmit the driving signal to the light-emitting control sub-circuit 104.
  • the light-emitting control sub-circuit 104 is also coupled to the light-emitting device 108.
  • the light-emitting control sub-circuit 104 is further configured to transmit a driving signal from the driving sub-circuit 105 to the light-emitting device 108 in response to the first light-emitting timing signal em1 to drive the light-emitting device 108 to emit light.
  • the above-mentioned data writing sub-circuit 106 is coupled to the third node N3 and the data signal terminal Data.
  • the data writing sub-circuit 106 is configured to transmit the data signal data received at the data signal terminal Data during the input and compensation stage to The third node N3.
  • the energy storage sub-circuit 101 is charged according to the voltage of the third node N3, and the data signal data is stored.
  • the data writing sub-circuit 106 is coupled to the third node N3, the input control signal terminal Dn, and the data signal terminal Data.
  • the data writing sub-circuit 106 is configured to, in response to the input control signal dn received at the input control signal terminal Dn, transmit the data signal data received at the data signal terminal Data to the third node N3.
  • the aforementioned input control signal terminal Dn is the second light-emitting timing signal terminal EM2, and the data writing sub-circuit 106 is also coupled to the scanning timing signal terminal Sn. That is, the data writing sub-circuit 106 is coupled to the third node N3, the second light-emitting timing signal terminal EM2, the scanning timing signal terminal Sn, and the data signal terminal Data.
  • the data writing sub-circuit 106 is configured to transmit the data signal data received at the data signal terminal Data to the third node N3 in response to the second light emission timing signal em2 and the scanning timing signal sn.
  • the reference voltage sub-circuit 107 is coupled to the third node N3, the first light-emitting timing signal terminal EM1 and the reference voltage signal terminal Vref.
  • the reference voltage sub-circuit 107 is configured to, in response to the first lighting timing signal em1 received at the first lighting timing signal terminal EM1, transmit the reference voltage signal vref received at the reference voltage signal terminal Vref to the third node N3, the voltage of the third node N3 is maintained at the reference voltage, and the present disclosure uses the voltage of the reference voltage signal vref as the reference voltage.
  • each pixel driving circuit 100 in a row of sub-pixels receives from the second light-emitting timing signal terminal EM2
  • the first light-emission timing signal em2 is the same signal as the first light-emission timing signal em1 from the first light-emission timing signal terminal EM1 received by the pixel driving circuit 100 in the previous row of sub-pixels, that is, each pixel in the n-th row of sub-pixels
  • the second light-emitting timing signal terminal EM2 of the driving circuit 100 and the first light-emitting timing signal terminal EM1 of each pixel driving circuit 100 in the n-1th row of sub-pixels are connected to the same light-emitting timing signal line EL (the n-1th light-emitting timing signal The line EL) is coupled, and a light-emitting timing signal line EL is coupled to the two rows of
  • the first light-emission timing signal terminal EM1 is also represented by EMn
  • the second light-emission timing signal terminal EM2 is also represented by EM(n- 1) Representation.
  • Adopting the above-mentioned method of combining adjacent light-emitting timing signals can reduce the number of light-emitting timing signal lines EL that need to be provided on the display panel 01, and reduce the difficulty and cost of manufacturing the display panel 01.
  • the pixel driving circuit 100 includes an energy storage sub-circuit 101, a reset sub-circuit 102, a compensation sub-circuit 103, a light emission control sub-circuit 104, a driving sub-circuit 105, a data writing sub-circuit 106 and a reference voltage sub-circuit 107, With reference to FIGS. 7 and 10, the driving process of the pixel driving circuit 100 is roughly as follows:
  • the reference voltage sub-circuit 107 transmits the reference voltage signal vref to the third node N3, while the reset sub-circuit 102 transmits the initialization signal vinit to the second node N2 through the light emission control sub-circuit 104 and the compensation sub-circuit 103 to correct The voltage of the second node N2 is reset.
  • the driving sub-circuit 105 disconnects the conductive path from the first voltage signal terminal Vdd to the initialization signal terminal Vinit under the control of the second light-emitting timing signal em2.
  • the data writing sub-circuit 106 transmits the data signal data to the third node N3, and the compensation sub-circuit 103 is turned on, so that the driving sub-circuit 105 generates a self-saturation state, the driving sub-circuit 105 generates a compensation signal, and The compensation signal is transmitted to the second node N2. Therefore, the energy storage sub-circuit 101 is charged under the action of the voltages of the third node N3 and the second node N2, and stores the data signal data and the compensation signal.
  • the reset sub-circuit 102 transmits the reference voltage signal vref to the third node N3, and the energy storage sub-circuit 101 couples the voltage of the second node under the action of the voltage of the third node N3 to make the second node
  • the voltage of the node N2 jumps
  • the driving sub-circuit 105 responds to the second light-emitting timing signal em2, and generates and outputs a driving signal under the discharge action of the energy storage sub-circuit 101.
  • the light emission control sub-circuit 104 transmits the driving signal to the light emitting device 108 to drive the light emitting device 108 to emit light.
  • the compensation sub-circuit 103 is coupled to the first node N1 and the second node N2.
  • the reset sub-circuit 102 resets the voltage of the second node N2 as follows:
  • the initialization signal vinit is transmitted to the second node N2 through the light emission control sub-circuit 104 and the compensation sub-circuit 103.
  • the compensation sub-circuit 103 is turned on under the control of the scan timing signal sn, so that the driving sub-circuit 105 generates a self-saturation state Therefore, the driving sub-circuit 105 generates a compensation signal to realize the compensation of the threshold voltage.
  • the compensation sub-circuit 103 described above is multiplexed as compensation and reset functions, and the compensation sub-circuit 103 is time-division multiplexed to realize the reset and threshold voltage compensation of the energy storage sub-circuit 101, as shown in Figs. 3 and 4
  • the reset sub-circuit 102 is not directly coupled to the second node N2. Therefore, during the light-emitting phase, no leakage path is formed between the second node N2 and the initialization signal terminal Vinit. That is, the pixel driving circuit 100 provided in the present disclosure only There is a single leakage path from the second node N2 to the first node N1 via the compensation sub-circuit 103.
  • the transistor included in the compensation sub-circuit 103 is in the off state, and the second node N2 will only leak through the compensation sub-circuit 103, and it is mentioned in the related art that because the second node N2 is between the second node N2 and the initialization signal terminal Vinit
  • the potential difference between the second node N2 and the first node N1 is greater than the potential difference between the second node N2 and the first node N1, and the leakage amount (absolute value) of the second leakage channel is much greater than the leakage amount (absolute value) of the first leakage channel.
  • the provided pixel driving circuit 100 is equivalent to only including the first leakage channel with less leakage, thereby significantly reducing the leakage of the second node N2 and improving the voltage retention rate of the energy storage sub-circuit 101.
  • the potential of the signal holding terminal of the first memory C1 included in the energy storage sub-circuit 101 can be kept constant for a long time, and the voltage of the second node N2 can be kept for a longer time, so that the voltage at the second node N2
  • the stability of the driving signal formed by the driving sub-circuit 105 is relatively high, the stability and continuity of the light-emitting brightness of the light-emitting device 108 are improved, the visual flicker is reduced, and the light-emitting effect of the multiple light-emitting devices 108 is improved.
  • the problem of uneven display caused by uneven brightness thereby improving the display effect.
  • the driving sub-circuit 105 includes at least a driving transistor.
  • the control electrode of the driving transistor is coupled to the energy storage sub-circuit 101, that is, to the second node N2.
  • the reset sub-circuit 102 will initialize The signal vinit is transmitted to the second node N2, and the voltage of the second node N2 is reset.
  • the working state of the driving transistor is changed from the saturated driving state of the light-emitting stage of the previous frame to the linear conduction state of the reset stage of this frame. In this way, referring to FIGS.
  • both the reset sub-circuit 102 and the light emission control sub-circuit 104 are turned on, and the driving transistor is at a lower voltage than the voltage of the second node N2. Conduction under control, so that a conductive path from the first voltage signal terminal Vdd to the initialization signal terminal Vinit is formed in the pixel driving circuit 100.
  • the conductive path is a direct current path, which generates a relatively large direct current. And ineffective power consumption, thereby adversely affecting the normal operation of the pixel driving circuit 100.
  • the driving sub-circuit 105 in the present disclosure is coupled to the second light-emitting timing signal terminal EM2, in the process of resetting the voltage of the second node N2, the driving sub-circuit 105 responds to the first light-emitting timing signal terminal EM2 received at the second node N2.
  • the second light-emitting timing signal em2 disconnects the conductive path from the first voltage signal terminal Vdd to the initialization signal terminal Vinit.
  • the data writing sub-circuit 106 is coupled to the third node N3, the input control signal terminal Dn, and the data signal terminal Data.
  • the data writing sub-circuit 106 is coupled to the third node N3, the second light-emitting timing signal terminal EM2, the scanning timing signal terminal Sn, and the data signal terminal Data, and the data writing sub-circuit 106 is controlled by a separately set input control signal
  • the signal transmitted by the terminal Dn or the data writing sub-circuit 106 is simultaneously controlled by the signal transmitted by the second light-emitting timing signal terminal EM2 and the scanning timing signal terminal Sn.
  • the writing of the data signal data is realized without occupying
  • the reset sub-circuit 102 resets the energy storage sub-circuit 101
  • the reset and the writing of the data signal data are performed in time intervals, which can ensure sufficient reset of the energy storage sub-circuit 101 and sufficient writing of the data signal data.
  • the energy storage sub-circuit 101, the reset sub-circuit 102, the compensation sub-circuit 103, the light-emission control sub-circuit 104, the drive sub-circuit 105, the data writing sub-circuit 106 and the reference voltage sub-circuit 107 included in the pixel drive circuit 100 are as follows: The specific structure is introduced separately.
  • the energy storage sub-circuit 101 includes a first capacitor C; the first terminal (reference voltage terminal) of the first capacitor C is coupled to the third node N3 Then, the second terminal (signal holding terminal) of the first capacitor C is coupled to the second node N2.
  • the reset sub-circuit 102 includes a first transistor M1; the control electrode of the first transistor M1 is coupled to the scan timing signal terminal Sn, the first electrode of the first transistor M1 is coupled to the initialization signal terminal Vinit, and the second electrode of the first transistor M1 It is coupled to the light emission control sub-circuit 104.
  • the first transistor M1 is configured to transmit the initialization signal vinit received at the initialization signal terminal Vinit to the light emission control sub-circuit 104 in response to the scan timing signal sn received at the scan timing signal terminal Sn.
  • the second electrode of the first transistor M1 is also coupled to the light-emitting device 108, and the first transistor M1 is also configured to respond to the scan timing signal sn received at the scan timing signal terminal Sn to receive the signal at the initialization signal terminal Vinit.
  • the initialization signal vinit is transmitted to the light-emitting device 108 to reset the light-emitting device 108.
  • the reference voltage sub-circuit 107 includes an eighth transistor M8; the control electrode of the eighth transistor M8 is coupled to the first light-emitting timing signal terminal EM1, the first electrode of the eighth transistor M8 is coupled to the reference voltage signal terminal Vref, and the eighth transistor M8 The second pole of is coupled to the third node N3.
  • the eighth transistor M8 is configured to transmit the reference voltage signal vref received at the reference voltage signal terminal Vref to the third node N3 in response to the first light emission timing signal em1 received at the first light emission timing signal terminal EM1.
  • the light emission control sub-circuit 104 includes a second transistor M2; the control electrode of the second transistor M2 is coupled to the first light emission timing signal terminal EM1, the first electrode of the second transistor M2 is coupled to the first node N1, and the control electrode of the second transistor M2 is coupled to the first node N1.
  • the second electrode is coupled to the second electrode of the first transistor M1.
  • the second transistor M2 is configured to, in the reset phase, in response to the first light-emission timing signal em1 received at the first light-emission timing signal terminal EM1, it will come from the reset sub-circuit 102 (the first transistor M1 in the reset sub-circuit 102)
  • the initialization signal vinit is transmitted to the first node N1.
  • the second electrode of the second transistor M2 is further coupled to the light emitting device 108, and the second transistor M2 is further configured to respond to the first light emission received at the first light emission timing signal terminal EM1 during the light emission phase.
  • the timing signal em1 transmits the driving signal from the first node N1 (or the driving sub-circuit 105) to the light emitting device 108.
  • the compensation sub-circuit 103 includes a third transistor M3; the control electrode of the third transistor M3 is coupled to the scan timing signal terminal Sn, the first electrode of the third transistor M3 is coupled to the first node N1, and the second electrode of the third transistor M3 Coupled with the second node N2.
  • the third transistor M3 is configured to, in the reset phase, in response to the scan timing signal sn received at the scan timing signal terminal Sn, transmit the initialization signal vinit from the first node N1 to the second node N2, so as to respond to the second node N2.
  • the voltage of N2 is reset. And, in the input and compensation stage, it is turned on under the control of the scan timing signal sn, so that the driving sub-circuit 105 generates a self-saturation effect to generate a compensation signal.
  • the driving sub-circuit 105 includes a fourth transistor M4 and a fifth transistor M5, wherein the fourth transistor M4 is a driving transistor.
  • the control electrode of the fourth transistor M4 is coupled to the second node N2, the first electrode of the fourth transistor M4 is coupled to the first voltage signal terminal Vdd, and the second electrode of the fourth transistor M4 is coupled to the fifth transistor.
  • the first pole of M5 is coupled.
  • the control electrode of the fifth transistor M5 is coupled to the second light-emitting timing signal terminal EM2, and the second electrode of the fifth transistor M5 is coupled to the first node N1.
  • the fourth transistor M4 is configured to be turned on under the control of the voltage of the second node N2 to transmit the first voltage signal vdd received at the first voltage signal terminal Vdd to the first pole of the fifth transistor M5, and, The driving current is generated and output according to the first voltage signal vdd.
  • the fifth transistor M5 is configured to be turned on under the control of the second light-emitting timing signal em2 to transmit the driving current to the first node N1.
  • the control electrode of the fourth transistor M4 is coupled to the second node N2, the first electrode of the fourth transistor M4 is coupled to the second electrode of the fifth transistor M5, The second electrode of the fourth transistor M4 is coupled to the first node N1.
  • the control electrode of the fifth transistor M5 is coupled to the second light-emitting timing signal terminal EM2, and the first electrode of the fifth transistor M5 is coupled to the first voltage signal terminal Vdd.
  • the fifth transistor M5 is configured to be turned on under the control of the second light-emitting timing signal em2 to transmit the first voltage signal vdd to the first pole of the fourth transistor M4.
  • the fourth transistor M4 is configured to be turned on under the control of the voltage of the second node N2, and generate and output a driving current according to the received first voltage signal vdd.
  • the data writing sub-circuit 106 when the data writing sub-circuit 106 is coupled to the third node N3, the input control signal terminal Dn, and the data signal terminal Data, the data writing sub-circuit 106 includes The sixth transistor M6.
  • the control electrode of the sixth transistor M6 is coupled to the input control signal terminal Dn
  • the first electrode of the sixth transistor M6 is coupled to the data signal terminal Data
  • the second electrode of the sixth transistor M6 is coupled to the third node N3.
  • the sixth transistor M6 is configured to transmit the data signal data received at the data signal terminal Data to the third node N3 in response to the input control signal dn received at the input control signal terminal Dn.
  • the data writing sub-circuit 106 when the data writing sub-circuit 106 is coupled to the third node N3, the second light-emitting timing signal terminal EM2, the scanning timing signal terminal Sn, and the data signal terminal Data
  • the data writing sub-circuit 106 includes a sixth transistor M6 and a seventh transistor M7.
  • the control electrode of the sixth transistor M6 is coupled to the second light-emitting timing signal terminal EM2, the first electrode of the sixth transistor M6 is coupled to the second electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6 is coupled to the third node N3 is coupled; the control electrode of the seventh transistor M7 is coupled to the scan timing signal terminal Sn, and the first electrode of the seventh transistor M7 is coupled to the data signal data.
  • the seventh transistor M7 is configured to transmit the data signal data received at the data signal terminal Data to the first pole of the sixth transistor M6 in response to the scan timing signal sn received at the scan timing signal terminal Sn.
  • the sixth transistor M6 is configured to transmit the data signal data to the third node N3 in response to the second light-emission timing signal em2 received at the second light-emission timing signal terminal EM2.
  • the energy storage sub-circuit 101, the reset sub-circuit 102, the compensation sub-circuit 103, the light emission control sub-circuit 104, the driving sub-circuit 105, the data writing sub-circuit 106, and the reference voltage sub-circuit The specific implementation manner of the circuit 107 is not limited to the manner described above, and it can be any implementation manner used, such as a conventional connection manner well known to those skilled in the art, and only needs to ensure that the corresponding function is implemented.
  • the above examples cannot limit the protection scope of the present disclosure. In practical applications, the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation. Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • the pixel drive circuit 100 includes an energy storage sub-circuit 101, a reset sub-circuit 102, a compensation sub-circuit 103, a light emission control sub-circuit 104, a drive sub-circuit 105 and data writing Sub-circuit 106 and reference voltage sub-circuit 107.
  • the reset sub-circuit 102 includes a first transistor M1, the light emission control sub-circuit 104 includes a second transistor M2, the compensation sub-circuit 103 includes a third transistor M3, and the driving sub-circuit 105 includes a fourth transistor M4 and a fifth transistor M5.
  • the energy storage sub-circuit 101 includes a first capacitor C, the data writing sub-circuit 106 includes a sixth transistor M6, or the data writing sub-circuit 106 includes a sixth transistor M6 and a seventh transistor M7, and the reference voltage sub-circuit 107 includes an eighth transistor. M8.
  • the first terminal of the first capacitor C is coupled to the third node N3, and the second terminal of the first capacitor C is coupled to the second node N2.
  • the first capacitor C is configured to be charged under the action of the voltages of the third node N3 and the second node N2, and to couple the voltage of the second node N2 according to the voltage of the third node N3 to change the second node N2 And maintain the voltage of the second node N2.
  • the control electrode of the first transistor M1 is coupled to the scan timing signal terminal Sn, the first electrode of the first transistor M1 is coupled to the initialization signal terminal Vinit, and the second electrode of the first transistor M1 is coupled to the second electrode of the second transistor M2
  • the second electrode of the first transistor M1 is also coupled to the light-emitting device 108.
  • the first transistor M1 is configured to, in response to the scan timing signal sn received at the scan timing signal terminal Sn, transmit the initialization signal vinit received at the initialization signal terminal Vinit to the second transistor M2, and transmit the initialization signal vinit to
  • the light-emitting device 108 is used to reset the light-emitting device 108.
  • the control electrode of the second transistor M2 is coupled to the first light emitting timing signal terminal EM1, the first electrode of the second transistor M2 is coupled to the first node N1, and the second electrode of the second transistor M2 is coupled to the second electrode of the first transistor M1.
  • the pole and the light emitting device 108 are coupled.
  • the second transistor M2 is configured to transmit the initialization signal vinit from the first transistor M1 to the first node N1 in response to the first light-emission timing signal em1 received at the first light-emission timing signal terminal EM1 in the reset phase.
  • the driving signal from the first node N1 is transmitted to the light-emitting device 108.
  • the light emitting device 108 is a light emitting diode
  • the second electrode of the first transistor M1 is coupled to the anode of the light emitting diode
  • the second electrode of the third transistor M3 is coupled to the anode of the light emitting diode
  • the cathode of the light emitting diode is coupled to the second electrode of the light emitting diode.
  • the voltage signal terminal is coupled.
  • the control electrode of the third transistor M3 is coupled to the scan timing signal terminal Sn, the first electrode of the third transistor M3 is coupled to the first node N1, and the second electrode of the third transistor M3 is coupled to the second node N2.
  • the third transistor M3 is configured to, in the reset phase, in response to the scan timing signal sn received at the scan timing signal terminal Sn, transmit the initialization signal vinit from the first node N1 to the second node N2, so as to respond to the second node N2.
  • the voltage of N2 is reset. And, in the input and compensation stage, it is turned on under the control of the scan timing signal sn, so that the driving sub-circuit 105 generates a self-saturation effect to generate a compensation signal.
  • the control electrode of the fourth transistor M4 is coupled to the second node N2
  • the first electrode of the fourth transistor M4 is coupled to the first voltage signal terminal Vdd
  • the fourth transistor M4 is coupled to the first voltage signal terminal Vdd.
  • the second electrode of M4 is coupled to the first electrode of the fifth transistor M5.
  • the control electrode of the fifth transistor M5 is coupled to the second light-emitting timing signal terminal EM2, and the second electrode of the fifth transistor M5 is coupled to the first node N1.
  • the fourth transistor M4 is configured to be turned on under the control of the voltage of the second node N2 to transmit the first voltage signal vdd received at the first voltage signal terminal Vdd to the first pole of the fifth transistor M5, and, The driving current is generated and output according to the first voltage signal vdd.
  • the fifth transistor M5 is configured to be turned on under the control of the second light-emitting timing signal em2 to transmit the driving current to the first node N1.
  • the control electrode of the fourth transistor M4 is coupled to the second node N2, the first electrode of the fourth transistor M4 is coupled to the second electrode of the fifth transistor M5, The second electrode of the fourth transistor M4 is coupled to the first node N1; the control electrode of the fifth transistor M5 is coupled to the second light-emitting timing signal terminal EM2, and the first electrode of the fifth transistor M5 is coupled to the first voltage signal terminal Vdd .
  • the fifth transistor M5 is configured to be turned on under the control of the second light-emitting timing signal em2 to transmit the first voltage signal vdd to the first pole of the fourth transistor M4.
  • the fourth transistor M4 is configured to be turned on under the control of the voltage of the second node N2, and generate and output a driving current according to the received first voltage signal vdd.
  • the control electrode of the sixth transistor M6 is coupled to the input control signal terminal Dn, and the first electrode of the sixth transistor M6 is coupled to the input control signal terminal Dn.
  • the data signal terminal Data is coupled, and the second electrode of the sixth transistor M6 is coupled to the third node N3.
  • the sixth transistor M6 is configured to transmit the data signal data received at the data signal terminal Data to the third node N3 in response to the input control signal dn received at the input control signal terminal Dn.
  • the control electrode of the sixth transistor M6 is coupled to the second light emitting timing signal terminal EM2, and the sixth The first pole of the transistor M6 is coupled to the second pole of the eighth transistor M8, and the second pole of the sixth transistor M6 is coupled to the third node N3.
  • the control electrode of the seventh transistor M7 is coupled to the scan timing signal terminal Sn, and the first electrode of the seventh transistor M7 is coupled to the data signal data.
  • the seventh transistor M7 is configured to transmit the data signal data received at the data signal terminal Data to the first pole of the sixth transistor M6 in response to the scan timing signal sn received at the scan timing signal terminal Sn.
  • the sixth transistor M6 is configured to transmit the data signal data to the third node N3 in response to the second light-emission timing signal em2 received at the second light-emission timing signal terminal EM2.
  • the control electrode of the eighth transistor M8 is coupled to the first light-emitting timing signal terminal EM1, the first electrode of the eighth transistor M8 is coupled to the reference voltage terminal, and the second electrode of the eighth transistor M8 is coupled to the third node N3.
  • the eighth transistor M8 is configured to transmit the reference voltage signal vref received at the reference voltage signal terminal Vref to the third node N3 in response to the first light emission timing signal em1 received at the first light emission timing signal terminal EM1.
  • the transistors used in the pixel driving circuit 100 provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the control electrode of each transistor used in the pixel driving circuit 100 is the gate of the transistor, one of the source and drain of the transistor at the first pole, and the source and drain of the transistor at the second pole.
  • the other Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain,
  • the second pole is the source.
  • the transistors are all described by taking the P-type transistor as an example.
  • the P-type transistor is also used as an example for description.
  • the embodiments of the present disclosure include but are not limited to this.
  • one or more transistors in the circuit provided by the embodiments of the present disclosure can also be N-type transistors, and only the poles of the selected type of transistors can be connected with reference to the poles of the corresponding transistors in the embodiments of the present disclosure. , And make the corresponding voltage terminal provide the corresponding high voltage or low voltage.
  • the first node N1, the second node N2, and the third node N3 do not represent actual components, but represent the junction of related electrical connections in the circuit diagram, that is, these nodes It is a node equivalent to the junction of related electrical connections in the circuit diagram.
  • the pixel driving circuit 100 includes an energy storage sub-circuit 101, a reset sub-circuit 102, a compensation sub-circuit 103, a light-emission control sub-circuit 104, a driving sub-circuit 105, a data writing sub-circuit 106, and a reference voltage sub-circuit 107, and the reset sub-circuit 102 is coupled to the light emission control sub-circuit 104, the scan timing signal terminal Sn, and the initialization signal terminal Vinit; the energy storage sub-circuit 101 is coupled to the second node N2 and the third node N3; the data writing sub-circuit 106 is coupled to the third node N3, the input control signal terminal Dn and the data signal terminal Data; the reference voltage sub-circuit 107 is coupled to the third node N3, the first light-emitting timing signal terminal EM1 and the
  • the reference voltage sub-circuit 107 transmits the reference voltage signal vref received at the reference voltage signal terminal Vref to the third node N3.
  • the reset sub-circuit 102 transmits the initialization signal vinit received at the initialization signal terminal Vinit to the light-emitting control sub-circuit 104 and the light-emitting device 108 to reset the light-emitting device 108 .
  • the light emission control sub-circuit 104 transmits the initialization signal vinit to the first node N1 in response to the first light emission timing signal em1 received at the first light emission timing signal terminal EM1.
  • the compensation sub-circuit 103 transmits the initialization signal vinit from the first node N1 to the second node N2 under the control of the scan timing signal sn to reset the voltage of the second node N2.
  • the driving sub-circuit 105 disconnects the conductive path from the first voltage signal terminal Vdd to the initialization signal terminal Vinit.
  • the reset sub-circuit 102 includes a first transistor M1
  • the light emission control sub-circuit 104 includes a second transistor M2
  • the compensation sub-circuit 103 includes a third transistor M3.
  • the driving sub-circuit 105 includes a fourth transistor M4 and a fifth transistor M5
  • the energy storage sub-circuit 101 includes a first capacitor C
  • the data writing sub-circuit 106 includes a sixth transistor M6, or the data writing sub-circuit 106 includes a sixth transistor
  • the reference voltage sub-circuit 107 includes an eighth transistor M8, and the light-emitting device 108 includes a light-emitting diode
  • the reset phase P1 includes:
  • the eighth transistor M8 is turned on under the control of the first light-emitting timing signal em1 to transmit the reference voltage signal vref to the third node N3, and the voltage of the third node N3 is the voltage Vref of the reference voltage signal vref.
  • the first transistor M1 is turned on under the control of the scan timing signal sn, and transmits the initialization signal vinit to the second electrode of the second transistor M2 and the anode of the light emitting diode.
  • the second transistor M2 is turned on under the control of the first light-emitting timing signal em1, and transmits the initialization signal vinit from the first transistor M1 to the first node N1.
  • the third transistor M3 is turned on under the control of the scan timing signal sn, and transmits the initialization signal vinit from the first node N1 to the second node N2, and the voltage of the second node N2 is the voltage V init of the initialization signal vinit. In this way, the voltage of the second node N2 is reset, and the second terminal (signal holding terminal) of the energy storage sub-circuit 101 is reset.
  • the fourth transistor M4 Under the control of the voltage of the second node N2, the fourth transistor M4 is in a linear conduction state, and the fifth transistor M5 is turned off under the control of the second light-emitting timing signal em2, so that the first voltage signal terminal Vdd can be disconnected to the initialization signal
  • the conductive path of the terminal Vinit avoids ineffective power consumption.
  • the seventh transistor M7 is turned on under the control of the scan timing signal sn
  • the sixth transistor M6 is turned on under the control of the scan timing signal sn.
  • the second light-emitting timing signal em2 is turned off under the control, therefore, the data signal data cannot be transmitted to the third node N3, so that the writing of the data signal data does not take up the reset time, and the third node N3 can be fully reset.
  • the reset sub-circuit 102 transmits the initialization signal vinit received at the initialization signal terminal Vinit to the light emitting device 108 to continuously reset the light emitting device 108.
  • the data writing sub-circuit 106 transmits the data signal data received at the data signal terminal Data to the third node N3 in response to the input control signal dn received at the input control signal terminal Dn.
  • the data writing sub-circuit 106 responds to the second light emission timing signal terminal EM2.
  • the second light emission timing signal em2 received at the light emission timing signal terminal EM2 and the scan timing signal sn received at the scan timing signal terminal Sn transmit the data signal data received at the data signal terminal Data to the third node N3.
  • the compensation sub-circuit 103 causes the driving sub-circuit 105 to generate a self-saturation state under the control of the scan timing signal sn.
  • the driving sub-circuit 105 In response to the second light-emitting timing signal em2, the driving sub-circuit 105 generates a self-saturation state under the action of the compensation sub-circuit 103 to generate a compensation signal according to the first voltage signal vdd received at the first voltage signal terminal Vdd, and The compensation signal is transmitted to the second node N2.
  • the energy storage sub-circuit 101 is charged under the action of the voltages of the second node N2 and the third node N3.
  • the reset sub-circuit 102 includes a first transistor M1
  • the light emission control sub-circuit 104 includes a second transistor M2
  • the compensation sub-circuit 103 includes a third transistor M3.
  • the driving sub-circuit 105 includes a fourth transistor M4 and a fifth transistor M5
  • the energy storage sub-circuit 101 includes a first capacitor C
  • the data writing sub-circuit 106 includes a sixth transistor M6, or the data writing sub-circuit 106 includes a sixth transistor
  • the reference voltage sub-circuit 107 includes an eighth transistor M8, and the light-emitting device 108 is a light-emitting diode
  • the input and compensation stage P2 includes:
  • the sixth transistor M6 is turned on under the control of the input control signal dn, and transmits the data signal data to the third node N3.
  • the seventh transistor M7 is turned on under the control of the scan timing signal sn to transmit the data signal data to
  • the first pole of the sixth transistor M6 and the sixth transistor M6 are turned on under the control of the second light-emitting timing signal em2 to transmit the data signal data to the third node N3.
  • the voltage of the third node N3 is the voltage V data of the data signal data, so that the voltage V data of the data signal data is stored in the first capacitor C.
  • the fourth transistor M4 is turned on under the control of the voltage of the second node N2, the fifth transistor M5 is turned on under the control of the second light-emitting timing signal em2, and the third transistor M3 is turned on in the scan timing. It is turned on under the control of the signal sn. Therefore, the third transistor M3 and the fifth transistor M5 make the control electrode of the fourth transistor M4 and its second electrode turn on, and the fourth transistor M4 is in a self-saturated state, and the potential of the control electrode of the fourth transistor M4 is the first one. The sum of the voltage of the pole and its threshold voltage V th .
  • the first electrode of the fourth transistor M4 is coupled to the first voltage signal terminal Vdd, and its voltage is the voltage V dd of the first voltage signal vdd, and the voltage of the control electrode of the fourth transistor M4 is V dd +V th .
  • the second node N2 is coupled to the control electrode of the fourth transistor M4, and the voltage of the second node N2 is V dd +V th , so that the sum of the first voltage signal vdd and the threshold voltage V dd +V th is stored in the first capacitor C.
  • the writing of the threshold voltage V th of the driving transistor is realized.
  • the fourth transistor M4 is turned on under the control of the voltage of the second node N2, the fifth transistor M5 is turned on under the control of the second light-emitting timing signal em2, and the third transistor M3 is turned on in the scan timing. It is turned on under the control of the signal sn. Therefore, the third transistor M3 turns on the control electrode of the fourth transistor M4 and the second electrode thereof, and the fourth transistor M4 is in a self-saturated state, and the potential of the control electrode of the fourth transistor M4 is the voltage of the first electrode and its threshold value.
  • the fifth transistor M5 transmits the first voltage signal vdd to the first pole of the fourth transistor M4, so that the voltage of the fourth transistor M4 is the voltage V dd of the first voltage signal vdd, then the fourth transistor M4
  • the voltage of the control electrode is V dd +V th .
  • the second node N2 is coupled to the control electrode of the fourth transistor M4, so that the voltage of the second node N2 is V dd +V th , so that the sum of the first voltage signal vdd and the threshold voltage V dd +V th is stored in the first
  • the capacitor C realizes the writing of the threshold voltage V th of the driving transistor.
  • the first transistor M1 is turned on under the control of the scan timing signal sn, and transmits the initialization signal vinit to the anode of the light emitting diode to reset the anode of the light emitting diode.
  • the second transistor M2 and the eighth transistor M8 are both turned off during the input and compensation stages.
  • the reset sub-circuit 102 transmits the reference voltage signal vref received at the reference voltage signal terminal Vref to the third node N3 in response to the first light emitting timing signal em1 received at the first light emitting timing signal terminal EM1.
  • the energy storage sub-circuit 101 couples the potential of the second node N2 to change the voltage of the second node N2 and maintain the voltage of the second node N2.
  • the driving sub-circuit 105 responds to the second light-emitting timing signal em2, and under the coupling action of the energy storage sub-circuit 101, generates a driving signal according to the first voltage signal, and transmits the driving signal to the light-emitting control sub-circuit 104.
  • the light emission control sub-circuit 104 transmits the driving signal from the driving sub-circuit 105 to the light-emitting device 108 in response to the first light-emitting timing signal em1 to drive the light-emitting device 108 to emit light.
  • the reset sub-circuit 102 includes a first transistor M1
  • the light emission control sub-circuit 104 includes a second transistor M2
  • the compensation sub-circuit 103 includes The third transistor M3, the driving sub-circuit 105 includes a fourth transistor M4 and a fifth transistor M5, the energy storage sub-circuit 101 includes a first capacitor C, and the data writing sub-circuit 106 includes a sixth transistor M6, or the data writing sub-circuit 106
  • the reference voltage sub-circuit 107 includes the eighth transistor M8, and the light-emitting device 108 is a light-emitting diode
  • the light-emitting stage P3 includes:
  • the eighth transistor M8 is turned on under the control of the first light-emitting timing signal em1, and transmits the reference voltage signal vref to the third node N3, and the voltage of the third node N3 becomes the voltage Vref of the reference voltage.
  • the voltage of the third node N3 changes from the voltage V data of the data signal data to the voltage V ref of the reference voltage, that is, the voltage of the first terminal of the first capacitor C changes from V data to V ref . Therefore, the voltage of the second terminal of the first capacitor C will also change by the same amount, from V dd +V th to V dd +V th +V ref -V data , and the voltage of the second node N2 is V dd +V th +V ref -V data .
  • the fourth transistor M4 is turned on under the control of the voltage of the second node N2, the fifth transistor M5 is turned on under the control of the second light-emitting timing signal em2, and the fourth transistor M4 generates a driving signal according to the first voltage signal vdd, and Drive signal output.
  • the second transistor M2 is turned on under the control of the first light-emitting timing signal em1, and transmits the received driving signal to the light-emitting diode, so that the light-emitting diode emits light.
  • the driving signal is the driving current, and according to the calculation formula of the driving current,
  • I ds is the saturation current of the fourth transistor M4, that is, the operating current of the input light-emitting diode; W/L is the channel width-to-length ratio of the fourth transistor M4; ⁇ is the carrier mobility; C ox is the first The channel capacitance per unit area of the four transistor M4; V gs is the gate-source voltage difference of the fourth transistor M4; V th is the threshold voltage of the fourth transistor M4.
  • the magnitude of the drive current generated by the fourth transistor M4 is only related to the reference voltage signal vref and the data signal data, and has nothing to do with the threshold voltage of the fourth transistor M4, so the magnitude of the drive current generated by the fourth transistor M4 is not affected by it.
  • the influence of the threshold voltage avoids the difference in the threshold voltage of the fourth transistor M4 in each pixel driving circuit 100 caused by the manufacturing process, resulting in different driving currents, which in turn affects the display effect, thereby improving the display effect of each light emitting device 108 The uniformity of luminous brightness.
  • the first transistor M1, the third transistor M3, and the sixth transistor M6 are all turned off.
  • the fourth transistor M4 can generate a relatively stable driving current, and it will not be caused by excessive voltage fluctuations of the second node N2.
  • the display panel 01 includes: a plurality of sub-pixels 10, a plurality of scanning timing signal lines GL, a plurality of light emitting timing signal lines EL, and a plurality of Data signal line DL.
  • One sub pixel (sub pixel) 10 is provided with a pixel driving circuit 100 as provided in the present disclosure.
  • a plurality of sub-pixels 10 are arranged in N rows and M columns.
  • the scanning timing signal line GL includes N, respectively GL(1) to GL(N)
  • the light emitting timing signal line EL includes N, respectively EL(1) to EL(N)
  • the data signal line DL includes M, They are D(1) ⁇ D(M).
  • N and M are both positive integers.
  • the scan timing signal terminal Sn of each pixel driving circuit 100 included in the n-th row of sub-pixels 10 is coupled to the n-th scan timing signal line GL(n).
  • the scan timing signal terminal Sn of each pixel driving circuit 100 included in the first row of sub-pixels 10 is coupled to the first scan timing signal line GL(1), and each pixel included in the N-th row of sub-pixels 10
  • the scanning timing signal terminal Sn of the driving circuit 100 is coupled to the Nth scanning timing signal line GL(N). 1 ⁇ n ⁇ N.
  • the first light-emitting timing signal terminal EM1 of each pixel driving circuit 100 included in the n-th row of sub-pixels 10 is coupled to the n-th light-emitting timing signal line EL(n). Except for the first row of sub-pixels, the n-th row of sub-pixels The second light-emitting timing signal terminal EM2 of each pixel driving circuit 100 included in 10 is coupled to the n-1th light-emitting timing signal line EL(n-1).
  • the first light-emitting timing signal terminal EM1 of each pixel driving circuit 100 included in the second row of sub-pixels 10 is coupled to the second light-emitting timing signal line EL(2), and the second light-emitting timing signal terminal EM2 is coupled to the second light-emitting timing signal line EL(2).
  • One light-emitting timing signal line EL(1) is coupled. 1 ⁇ n ⁇ N.
  • the display panel 01 further includes at least one row of dummy cells arranged before the first row of sub-pixels and after the last row of sub-pixels (the Nth row of sub-pixels).
  • the sub-pixels have the same structure, but there is no corresponding function when the display panel displays. Due to process problems and circuit parasitic parameters, among the N rows of sub-pixels actually used for display, the pixel driving circuit 100 in the edge sub-pixels (the first row of sub-pixels and the N-th row of sub-pixels) and the internal sub-pixels are There are differences in the electrical characteristics of the pixel driving circuit 100.
  • the difference between the edge sub-pixels and the inner sub-pixels in the N rows of sub-pixels actually used for display can be avoided. , To ensure normal display.
  • the display panel 01 also includes corresponding
  • the display panel 01 further includes a dummy scan timing signal line GL (dummy) and a dummy light emission timing signal line EL (dummy).
  • the display panel further includes a dummy light-emitting timing signal line EL (dummy) disposed before the first light-emitting timing signal line EL(1), for example, it is called the 0th light-emitting timing signal line EL. (0).
  • the first light-emitting timing signal terminal EM1 of each pixel driving circuit 100 included in the first row of sub-pixels 10 is coupled to the first light-emitting timing signal line E(1)
  • the second light-emitting timing signal terminal EM2 is coupled to the first light-emitting timing signal line E(1).
  • the light-emitting timing signal line EL(0) is coupled.
  • the 0th light-emitting timing signal line EL(0) is configured to transmit the second light-emitting timing signal em2 to the second light-emitting timing signal terminal EM2 of each pixel driving circuit 100 included in the first row of sub-pixels 10.
  • the data signal terminal Data of each pixel driving circuit 100 included in the sub-pixel 10 of the m-th column is coupled to the m-th data signal line.
  • the data signal terminal Data of each pixel driving circuit 100 included in the first column of sub-pixels 10 is coupled to the first data signal line DL(1), and each pixel driving circuit included in the M-th column of sub-pixels 10
  • the data signal terminal Data of 100 is coupled to the M-th data signal line DL(M).
  • the scan timing signal line GL provides the scan timing signal sn for the scan timing signal terminal Sn
  • the emission timing signal line EL provides the first emission timing signal em1 or the second emission timing signal em1 or the second emission timing signal terminal EM1 and the second emission timing signal terminal EM2.
  • the light-emitting timing signal em2 and the data signal line DL provide the data signal data for the data signal terminal Data.
  • the display panel 01 also includes signal lines such as multiple reset signal lines, multiple initialization signal lines, multiple first voltage signal lines, etc.
  • signal lines such as multiple reset signal lines, multiple initialization signal lines, multiple first voltage signal lines, etc. The present disclosure does not limit the wiring manner.
  • the display panel 01 further includes a gate driving circuit 20, a light emitting driving circuit 30, and a source driving circuit 40 disposed in the peripheral area BB.
  • the gate driving circuit 20 and the light-emitting drive circuit 30 may be provided on the side along the extension direction of the scan timing signal line GL
  • the data drive circuit 40 may be provided on the side along the extension direction of the data signal line DL to drive pixels in the display panel
  • the driving circuit 100 performs display.
  • the aforementioned gate driving circuit 20 may be a gate driving IC (integrated circuit, integrated circuit), the light-emitting driving circuit 30 may be a light-emitting driving IC, and the source driving circuit 40 may be a source driving IC.
  • the gate driving circuit 20 may be a gate driving IC (integrated circuit, integrated circuit)
  • the light-emitting driving circuit 30 may be a light-emitting driving IC
  • the source driving circuit 40 may be a source driving IC.
  • the gate driving circuit 20 may be a GOA (Gate Driver on Array) circuit
  • the light emitting driving circuit 30 may be an EOA (Emitter on Array) circuit, that is, the gate driving circuit 20 and the light emitting driving circuit mentioned above. 30 is directly integrated in the array substrate of the display panel 01. In this way, on the one hand, the manufacturing cost of the display panel can be reduced; on the other hand, the frame width of the display device can also be narrowed.
  • the gate driving circuit 20 is a GOA circuit
  • the light-emitting driving circuit 30 may be an EOA circuit.
  • the display panel 01 is provided with a gate driving circuit 20 and a light-emitting driving circuit 30 on a single side of the peripheral area BB, and each scanning timing signal line GL and each light-emitting timing are sequentially driven row by row from a single side.
  • the signal line EL is single-sided drive.
  • the display panel 01 may be provided with gate driving circuits 20 on two sides along the horizontal direction X in the peripheral area BB, and the two gate driving circuits 20 simultaneously
  • the scanning timing signal lines GL are sequentially driven row by row on the side
  • light-emitting drive circuits 30 are respectively provided on two sides along the horizontal direction X, and each light-emitting timing signal is driven row by row from both sides at the same time through the two light-emitting drive circuits 30 Line GL, that is, double-sided drive.
  • the gate driving circuit 20 is configured to provide a scan timing signal sn.
  • the gate driving circuit 20 includes N stages of cascaded shift registers (RS1, RS2...RS(N)), and N stages of cascaded shift registers (RS1, RS2...RS(N)).
  • the bit registers (RS1, RS2...RS(N)) are respectively coupled to the N scanning timing signal lines GL(1)-GL(N) for outputting corresponding scanning timing signals sn to the scanning timing signal lines.
  • the light-emitting drive circuit 30 is configured to provide light-emitting timing signals.
  • the light-emitting drive circuit 30 includes N stages of cascaded shift registers (RS1', RS2'...RS(N)'), and N stages of cascaded shift registers (RS1', RS2'...RS(N)').
  • the bit registers (RS1', RS2'...RS(N)') are respectively coupled to N light-emitting timing signal lines EL(1)-EL(N).
  • the light-emitting drive circuit 30 further includes a dummy shift register RS (Dummy), which is the same as the first stage shift register RS (Dummy).
  • the register RS1' is coupled to the 0th light-emitting timing signal line EL(0). That is, the light-emitting drive circuit 30 includes N+1 cascaded shift registers for outputting corresponding light-emitting timing signals to the light-emitting timing signal line EL.
  • the display panel 01 Since the pixel driving circuit 100 provided by the present disclosure can increase the voltage retention rate of the energy storage sub-circuit, thereby improving the stability of the light-emitting brightness of the light-emitting device, and ensuring the uniformity of the light-emitting brightness of each light-emitting device, the display panel 01 has The display effect is better, with the effect of low flicker and uniform display brightness.
  • Some embodiments of the present disclosure also provide a display device 02. As shown in FIG. 12, the display device includes the above-mentioned display panel 01.
  • the display device further includes a frame, a circuit board, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories, etc., and the display panel 01 is disposed in the frame.
  • a display driver IC Integrated Circuit, integrated circuit
  • the display device provided by the embodiment of the present disclosure may be any device that displays images, whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (PDAs).
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • the display device provided by the present disclosure has the same beneficial effects as the display panel, and will not be repeated here.

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Abstract

一种像素驱动电路（100），包括：复位子电路（102）、补偿子电路（103）、发光控制子电路（104）和驱动子电路（105）。其中，复位子电路（102）与发光控制子电路（104）、扫描时序信号端（Sn）和初始化信号端（Vinit）耦接。发光控制子电路（104）还与第一节点（N1）和第一发光时序信号端（EM1/EMn）耦接。补偿子电路（103）与第一节点（N1）、第二节点（N2）和扫描时序信号端（Sn）耦接。驱动子电路（105）与第一节点（N1）、第二节点（N2）、第一电压信号端（Vdd）和第二发光时序信号端（EM2/EM(n-1)）耦接。复位子电路（102）被配置为，响应于在扫描时序信号端（Sn）处接收的扫描时序信号（sn），将在初始化信号端（Vinit）处接收的初始化信号（vinit）通过发光控制子电路（104）和补偿子电路（103）传输至第二节点（N2）。驱动子电路（105）被配置为，在对第二节点（N2）的电压复位的过程中，响应于第二发光时序信号（em2），断开第一电压信号端（Vdd）至初始化信号端（Vinit）的导电路径。

Description

像素驱动电路及其驱动方法、显示面板及显示装置
本申请要求于2020年6月8日提交的、申请号为202010514385.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板及显示装置。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置因其具有自发光、快速响应、宽视角和可制作在柔性衬底上等特点，受到广泛应用，OLED显示装置包括多个亚像素，各亚像素包括像素驱动电路和发光器件，通过像素驱动电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种像素驱动电路，包括：复位子电路、补偿子电路、发光控制子电路和驱动子电路。其中，所述复位子电路与所述发光控制子电路、扫描时序信号端和初始化信号端耦接。所述发光控制子电路还与第一节点和第一发光时序信号端耦接。所述补偿子电路与所述第一节点、第二节点和所述扫描时序信号端耦接。所述驱动子电路与所述第一节点、所述第二节点、第一电压信号端和第二发光时序信号端耦接。
所述复位子电路被配置为，响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光控制子电路。所述发光控制子电路被配置为，响应于在所述第一发光时序信号端处接收的第一发光时序信号，将所述初始化信号传输至所述第一节点。所述补偿子电路被配置为，在所述扫描时序信号的控制下，将来自所述第一节点的初始化信号传输至所述第二节点，以对所述第二节点的电压复位。
所述驱动子电路被配置为，在对所述第二节点的电压复位的过程中，响应于在所述第二发光时序信号端处接收的第二发光时序信号，断开所述第一电压信号端至所述初始化信号端的导电路径。
在一些实施例中，所述复位子电路包括第一晶体管；所述第一晶体管的控制极与所述扫描时序信号端耦接，所述第一晶体管的第一极与所述初始化信号端耦接，所述第一晶体管的第二极与所述发光控制子电路耦接。所述发光控制子电路包括第二晶体管；所述第二晶体管的控制极与所述第一发光时序信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶 体管的第二极与所述第一晶体管的第二极耦接。所述补偿子电路包括第三晶体管；所述第三晶体管的控制极与所述扫描时序信号端耦接，所述第三晶体管的第一极与所述第一节点耦接，所述第三晶体管的第二极与所述第二节点耦接。
在一些实施例中，所述驱动子电路包括第四晶体管和第五晶体管。所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；所述第五晶体管的控制极与所述第二发光时序信号端耦接，所述第五晶体管的第二极与所述第一节点耦接。
在一些实施例中，所述驱动子电路包括第四晶体管和第五晶体管。所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述所述第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；所述第五晶体管的控制极所述第二发光时序信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接。
在一些实施例中，像素驱动电路还包括：储能子电路和数据写入子电路。其中，所述储能子电路与所述第二节点和第三节点耦接；所述储能子电路被配置为，在所述第二节点和所述第三节点的电压的作用下进行充电，并根据所述第三节点的电压，对所述第二节点的电压进行耦合，以改变所述第二节点的电压，并保持所述第二节点的电压。所述数据写入子电路与所述第三节点、输入控制信号端和数据信号端耦接；所述数据写入子电路被配置为，响应于在所述输入控制信号端处接收的输入控制信号，将在所述数据信号端处接收的数据信号传输至所述第三节点。
在一些实施例中，所述储能子电路包括第一电容器；所述第一电容器的第一端与所述第三节点耦接，所述第一电容器的第二端与所述第二节点耦接。所述数据写入子电路包括第六晶体管；所述第六晶体管的控制极与所述输入控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接。
在一些实施例中，所述输入控制信号端为所述第二发光时序信号端，所述数据写入子电路还与所述扫描时序信号端耦接；所述数据写入子电路被配置为，响应于所述第二发光时序信号和所述扫描时序信号，将在所述数据信号端处接收的数据信号传输至所述第三节点。
在一些实施例中，所述数据写入子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管 的第一极与所述第七晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号端耦接。
在一些实施例中，像素驱动电路还包括基准电压子电路；所述基准电压子电路还与所述第三节点、第一发光时序信号端和参考电压信号端耦接。所述基准电压子电路还被配置为，响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点。
在一些实施例中，所述基准电压子电路还包括第八晶体管；所述第八晶体管的控制极与所述第一发光时序信号端耦接，所述第八晶体管的第一极与所述参考电压端耦接，所述第八晶体管的第二极与所述第三节点耦接。
在一些实施例中，所述补偿子电路还被配置为，在所述扫描时序信号的控制下，使所述驱动子电路产生自饱和状态。所述驱动子电路还被配置为，响应于所述第二发光时序信号，在所述补偿子电路的作用下产生自饱和状态，以根据在所述第一电压信号端处接收的第一电压信号，生成补偿信号，并将所述补偿信号传输至所述第二节点。以及，响应于所述第二发光时序信号，且在所述储能子电路的放电作用下，根据所述第一电压信号生成驱动信号。
在一些实施例中，所述复位子电路还与所述发光器件耦接；所述复位子电路还被配置为，响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光器件，以对所述发光器件复位。所述发光控制子电路还与发光器件耦接。所述发光控制子电路还被配置为，响应于所述第一发光时序信号，将来自所述驱动子电路的驱动信号传输至所述发光器件，以驱动所述发光器件发光。
在一些实施例中，在所述复位子电路包括第一晶体管的情况下，所述第一晶体管的第二极还与所述发光器件耦接。在所述发光控制子电路包括第二晶体管的情况下，所述第二晶体管的第二极还与所述发光器件耦接。
在一些实施例中，所述复位子电路包括第一晶体管，所述发光控制子电路包括第二晶体管，所述补偿子电路包括第三晶体管，所述驱动子电路包括第四晶体管和第五晶体管。所述像素驱动电路还包括储能子电路、数据写入子电路和基准电压子电路；所述储能子电路包括第一电容器，所述数据写入子电路包括第六晶体管，或者所述数据写入子电路包括第六晶体管和第七晶体管，所述基准电压子电路包括第八晶体管。
所述第一晶体管的控制极与所述扫描时序信号端耦接，所述第一晶体管 的第一极与所述初始化信号端耦接，所述第一晶体管的第二极与所述第二晶体管的第二极和发光器件耦接。所述第二晶体管的控制极与所述第一发光时序信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶体管的第二极与所述第一晶体管的第二极和发光器件耦接。所述第三晶体管的控制极与所述扫描时序信号端耦接，所述第三晶体管的第一极与所述第一节点耦接，所述第三晶体管的第二极与所述第二节点耦接。
所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；所述第五晶体管的控制极与所述第二发光时序信号端耦接，所述第五晶体管的第二极与所述第一节点耦接。或者，所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述所述第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；所述第五晶体管的控制极所述第二发光时序信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接。
所述第一电容器的第一端与第三节点耦接，所述第一电容器的第二端与所述第二节点耦接。在所述数据写入子电路包括第六晶体管的情况下，所述第六晶体管的控制极与输入控制信号端耦接，所述第六晶体管的第一极与数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接。在所述数据写入子电路包括第六晶体管和第七晶体管的情况下，所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管的第一极与所述第八晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号耦接。
所述第八晶体管的控制极与所述第一发光时序信号端耦接，所述第八晶体管的第一极与所述参考电压端耦接，所述第八晶体管的第二极与所述第三节点耦接。
另一方面，提供一种像素驱动方法，应用于如上所述的像素驱动电路，在所述像素驱动电路包括储能子电路、复位子电路、补偿子电路、发光控制子电路、驱动子电路和数据写入子电路和基准电压子电路，且所述储能子电路与所述第二节点和第三节点耦接；所述数据写入子电路与所述第三节点、输入控制信号端和数据信号端耦接；所述基准电压子电路还与所述第三节点、第一发光时序信号端和参考电压信号端耦接；所述复位子电路和所述发光控制子电路还与发光器件耦接的情况下，所述像素驱动方法包括：一个帧周期 包括复位阶段、输入与补偿阶段和发光阶段。
在所述复位阶段：所述基准电压子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点。所述复位子电路响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光控制子电路和所述发光器件，以对所述发光器件进行复位。所述发光控制子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将所述初始化信号传输至所述第一节点。所述补偿子电路在所述扫描时序信号的控制下，将来自所述第一节点的初始化信号传输至所述第二节点，以对所述第二节点的电压复位。所述驱动子电路响应于在所述第二发光时序信号端处接收的第二发光时序信号，断开所述第一电压信号端至所述初始化信号端的导电路径。
在一些实施例中，在所述输入与补偿阶段，所述复位子电路响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光器件，以对所述发光器件进行持续复位。所述数据写入子电路响应于在所述输入控制信号端处接收的输入控制信号，将在所述数据信号端处接收的数据信号传输至所述第三节点。所述补偿子电路在所述扫描时序信号的控制下，使所述驱动子电路产生自饱和状态。所述驱动子电路响应于所述第二发光时序信号，在所述补偿子电路的作用下产生自饱和状态，以根据在所述第一电压信号端处接收的第一电压信号，生成补偿信号，并将所述补偿信号传输至所述第二节点。所述储能子电路在所述第二节点和所述第三节点的电压的作用下进行充电。
在所述发光阶段，所述复位子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点。所述储能子电路在所述第三节点的电压的作用下，对所述第二节点的电位进行耦合，使所述第二节点的电压发生变化，并保持所述第二节点的电压。所述驱动子电路响应于所述第二发光时序信号，且在所述储能子电路的耦合作用下，根据所述第一电压信号生成驱动信号，并将所述驱动信号传输至所述发光控制子电路。所述发光控制子电路响应于所述第一发光时序信号，将来自所述驱动子电路的驱动信号传输至所述发光器件，以驱动所述发光器件发光。
在一些实施例中，在所述数据写入子电路包括第六晶体管，所述第六晶体管的控制极与所述输入控制信号端耦接，所述第六晶体管的第一极与所述 数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接的情况下，在所述输入与补偿阶段，所述第六晶体管在所述输入控制信号的控制下导通，将所述数据信号传输至所述第三节点。
在所述输入控制信号端为所述第二发光时序信号端，所述数据写入子电路还与所述扫描时序信号端耦接，所述数据写入子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管的第一极与所述第七晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号端耦接的情况下，在所述输入与补偿阶段，所述第七晶体管在所述扫描时序信号的控制下导通，将所述数据信号传输至所述第六晶体管的第一极，所述第六晶体管在第一发光时序信号的控制下导通，将所述数据信号传输至所述第三节点。
再一方面，提供一种显示面板，包括：如上所述的像素驱动电路。
在一些实施例中，所述显示面板包括多个亚像素，一个亚像素包括一个像素驱动电路，所述多个亚像素呈多行多列的阵列式布置。所述显示面板还包括沿行方向延伸的多条扫描时序信号线和多条发光时序信号线；第n行亚像素所包括的各像素驱动电路的扫描时序信号端与第n条扫描时序信号线耦接；第n行亚像素所包括的各像素驱动电路的第一发光时序信号端与第n条发光时序信号线耦接；除第一行亚像素外，第n行亚像素所包括的各像素驱动电路的第二发光时序信号端与第n-1条发光时序信号线耦接。
又一方面，提供一种显示装置，包括如上所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的结构图；
图2A为根据相关技术的一些实施例的像素驱动电路的结构图；
图2B为图1的像素驱动电路对应的时序图；
图3为根据本公开的一些实施例的像素驱动电路的一种结构图；
图4为根据本公开的一些实施例的像素驱动电路的另一种结构图；
图5为根据本公开的一些实施例的像素驱动电路的再一种结构图；
图6为根据本公开的一些实施例的像素驱动电路的又一种结构图；
图7为图3、图5和图6的像素驱动电路对应的时序图；
图8为根据本公开的一些实施例的像素驱动电路的又一种结构图；
图9为根据本公开的一些实施例的像素驱动电路的又一种结构图；
图10为图4、图8和图9的像素驱动电路对应的时序图；
图11为根据本公开的一些实施例的显示面板的一种结构图；
图12为根据本公开的一些实施例的显示装置的一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施 例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
在显示装置中，显示装置包括显示面板01。如图1所示，该显示面板01包括显示区AA(Active Area，简称AA区；也可称为有效显示区)和位于显示区AA至少一侧的周边区BB。
上述显示区AA内设置有多个亚像素(sub pixel)10，以及沿水平方向X延伸的多条扫描时序信号线GL和多条发光时序信号线EL、沿竖直方向Y延伸的多条数据信号线DL。为了方便说明，本公开中上述多个亚像素10是以矩阵形式排列为例进行的说明，示例性地，多个亚像素10排成N行M列。此时，沿水平方向X排列成一排的亚像素10称为一行亚像素，沿竖直方向Y排列成一排的亚像素10称为一列亚像素，一行亚像素可以与一条或两条扫描时序信号线GL耦接，一行亚像素还可以与一条或两条发光时序信号线EL耦接，一列亚像素可以与一条数据信号线DL耦接。亚像素10内设置有用于控制亚像素10进行显示的像素驱动电路100，像素驱动电路100设置在显示面板01的衬底基板001上。
上述显示面板01可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板等，本公开对此不做具体限定。
本公开以下实施例均是以上述显示面板01为有机发光二极管显示面板为例，对本公开进行说明的。
示例性的，像素驱动电路100通常包括开关晶体管、驱动晶体管和存储电容等元件。其中，存储电容的相对的两端分别为基准电位端和信号保持端，存储电容的信号保持端与驱动晶体管的控制极(栅极)耦接。
在像素驱动电路100的驱动过程中，在发光阶段，存储电容用以保持电压信号，使其信号保持端的电位得以保持恒定，在驱动晶体管的栅极-源极之间形成电压，控制驱动晶体管形成驱动电流，进而驱动发光二极管发光，在该过程中，由于存储电容的信号保持端与驱动晶体管的控制极耦接的节点处存在漏电通路，使得存储电容的信号保持端的电位无法长时间保持恒定，从而导致驱动晶体管所形成的驱动电流不稳定，影响发光器件的发光亮度，进而影响显示装置的显示效果。
具体来说，如图2A所示，相关技术中提供了一种7T1C的像素驱动电路100’，该像素驱动电路100’包括开关晶体管T1、存储电容器C、驱动晶体 管T2、补偿晶体管T3、第一复位晶体管T4、第二复位晶体管T5、第一控制晶体管T6和第二控制晶体管T7，上述多个晶体管之间的连接关系可参照附图，其中，第二晶体管T2、第三晶体管T3和第七晶体管T7相互耦接的节点为第一节点N1，存储电容器C的基准电压端与第三节点N3耦接，存储电容器C的信号保持端与第二节点N2耦接，驱动晶体管T2的控制极与第二节点N2耦接。
请结合图2B，上述像素驱动电路100’的驱动过程为，一个帧周期包括复位阶段P1、输入与补偿阶段P2和发光阶段P3。其中，在复位阶段P1，在第一扫描时序信号端S1传输的第一扫描时序信号s1的控制下，第一复位晶体管T4导通，将在参考电压端Vref处接收的参考电压信号vref传输至第三节点N3，第二复位晶体管T5导通，将在初始化信号端Vinit处接收的初始化信号vinit传输至第二节点N2，对第二节点N2的电压复位，从而对存储电容器C的信号保持端复位。
在输入与补偿阶段P2，在第二扫描时序信号端S2传输的第二扫描时序信号s2的控制下，开关晶体管T1导通，将在数据信号端Data处接收的数据信号data传输至第三节点N3；补偿晶体管T3导通，使得驱动晶体管T2的控制极和第二极接通，从而驱动晶体管T2处于自饱和状态，从而将在第一电压信号端Vdd处接收的第一电压信号vdd和驱动晶体管T2的阈值电压V th写入第二节点N2，存储电容器C在第三节点N3和第二节点N2的作用下充电。
在发光阶段P3，在发光时序信号端EMn处传输的发光时序信号emn的控制下，第一控制晶体管T6导通，将在参考电压端Vref处接收的参考电压信号vref传输第三节点N3，即存储电容器C的基准电压端的电压由数据信号data的电压变为参考电压信号vref的电压，存储电容器C通过耦合作用，使得其信号保持端的电压发生同样电压差的变化，也就是说在存储电容器C的作用下，第二节点N2的电压随着第三节点N3的电压的改变而发生跳变。驱动晶体管T2导通，根据在第一电压信号端Vdd的第一电压信号vdd形成驱动信号。第二控制晶体管T7在发光时序信号emn的控制下导通，将驱动信号传输至发光二极管L，从而驱动发光二极管L发光。
需要说明的是，如图1、图2A和2B所示，在显示面板01中，多个亚像素10呈阵列排布，一行亚像素中各像素驱动电路100’所接收的来自第一扫描时序信号端S1的第一扫描时序信号s1，与上一行亚像素中像素驱动电路100’所接收的来自第二扫描时序信号端S2的第二扫描时序信号s2为同一个信号，即第n行亚像素中各像素驱动电路100’的第一扫描信号端S1和第n-1 行亚像素中各像素驱动电路100’的第二扫描信号端S2与同一条扫描时序信号线GL(第n-1条扫描时序信号线GL)耦接，一条扫描时序信号线GL与其前后两行亚像素耦接，实现共享。示例性地，如图2A和2B所示，对于第n行亚像素的一个像素驱动电路，其第一扫描时序信号端S1同时用S(n-1)表示，第二扫描时序信号端S2同时用Sn表示。
在一个帧周期的整个发光阶段P3，在发光二极管L的发光过程中，驱动晶体管T2所产生的驱动信号为驱动电流，根据驱动电流的计算公式，I＝β(V gs-V th) 2，其中，V gs为驱动晶体管T2的栅源电压差，对于驱动晶体管T2来说，其所形成的驱动信号与驱动晶体管的栅极的电位相关，驱动晶体管T2的栅极的电位的稳定性能够影响所形成的驱动信号的稳定性和有效值，从而影响发光二极管的发光的稳定性和持续性。驱动晶体管T2的栅极与第二节点N2耦接，因此第二节点N2的电压保持率会对发光器件的发光效果产生影响，第二节点N2的电压与存储电容器C的信号保持端的电压一致，即存储电容器C的的电压保持率越高，发光二极管的发光亮度越稳定，发光效果越好。
由于晶体管在关态下会存在关态电流，该关态电流也叫做漏电流，在发光阶段P3，与第二节点N2相耦接的补偿晶体管T3和第一控制晶体管T6均截止，此时补偿晶体管T3和第一控制晶体管T6存在漏电流，会使得第二节点N2漏电，从而使得第二节点N2的电压保持率降低。
如图1所示，该像素驱动电路100’中包括两个漏电通道，分别是从第二节点N2经补偿晶体管T3至第一节点N1的第一漏电通道，以及从第二节点N2经第二复位晶体管T5至初始化信号端Vinit的第二漏电通道。并且，本公开的发明人经验证得知，第二节点N2与初始化信号端Vinit之间的电位差大于第二节点N2与第一节点N1之间的电位差，因此第二漏电通道的漏电量(绝对值)要远大于第一漏电通道的漏电量(绝对值)。这样，在发光阶段P3，经过两个漏电通道的漏电，第二节点N2漏电程度较大，使得存储电容器C的电压保持率不充分，造成驱动晶体管T3输出的驱动信号不稳定，从而导致发光器件的发光亮度变化过大，稳定性较差，产生视觉闪烁感。并且，在由于工艺问题，显示装置中的各像素驱动电路中的元件会有差异，因此各像素驱动电路中第二节点N2的漏电程度均不一致，造成各像素驱动电路所驱动的发光器件的发光亮度不均匀，从而导致显示画面出现显示不均等异常。
基于此，本公开的一些实施例提供了一种像素驱动电路100，如图3和图4所示，该像素驱动电路100包括：储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105、数据写入子电路106和 基准电压子电路107。
储能子电路101与第二节点N2和第三节点N3耦接。复位子电路102与发光控制子电路104、扫描时序信号端Sn和初始化信号端Vinit耦接。发光控制子电路104还与第一节点N1和第一发光时序信号端EM1耦接。补偿子电路103与第一节点N1、第二节点N2和扫描时序信号端Sn耦接。驱动子电路105与第一节点N1、第二节点N2、第一电压信号端Vdd和第二发光时序信号端EM2耦接。
储能子电路101被配置为，在第二节点N2和第三节点N3的电压的作用下进行充电，并根据第三节点N3的电压，对第二节点N2的电压进行耦合，以改变第二节点N2的电压，并保持第二节点N2的电压。
复位子电路102被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至发光控制子电路104。
发光控制子电路104被配置为，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将初始化信号vinit传输至第一节点N1。
补偿子电路103被配置为，在扫描时序信号sn的控制下，将来自第一节点N1的初始化信号vinit传输至第二节点N2，以对第二节点N2的电压复位。
也就是说，复位子电路102被配置为将初始化信号vinit通过发光控制子电路104和补偿子电路103传输至所述第二节点N2，以对第二节点N2的电位复位。在复位阶段，初始化信号vinit传输至第二节点N2的传输过程为，初始化信号端Vinit处传输的初始化信号vinit依次经过复位子电路102、发光控制子电路104、第三节点N3和补偿子电路103，最终传输至第二节点N2，对第二节点N2的电压进行复位。
在一些示例中，上述复位子电路102还与发光器件108耦接，复位子电路102被配置为在响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至发光器件108，以对发光器件108进行复位。
驱动子电路105被配置为，在对第二节点N2的电压复位的过程中，响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2，断开第一电压信号端Vdd至初始化信号端Vinit的导电路径。
上述驱动子电路105还被配置为，响应于第二发光时序信号em2，在补偿子电路103的作用下产生自饱和状态，以根据在第一电压信号端Vdd处接收的第一电压信号vdd，生成补偿信号，并将补偿信号传输至第二节点N2。
在输入与补偿阶段，驱动子电路105被配置为生成补偿信号，并将补偿信号传输至第二节点N2，在该阶段，补偿子电路103还被配置为，在扫描时序信号sn的控制下，使驱动子电路105产生自饱和状态。
上述驱动子电路105还被配置为响应于第二发光时序信号em2，且在储能子电路101的耦合作用下，根据第一电压信号vdd生成驱动信号，并将驱动信号传输至发光控制子电路104。
发光控制子电路104还与发光器件108耦接。发光控制子电路104还被配置为，响应于第一发光时序信号em1，将来自驱动子电路105的驱动信号传输至所述发光器件108，以驱动发光器件108发光。
上述数据写入子电路106与第三节点N3和数据信号端Data耦接，数据写入子电路106被配置为，在输入与补偿阶段，将在数据信号端Data处接收的数据信号data传输至第三节点N3。在该阶段，储能子电路101根据第三节点N3的电压进行充电，将数据信号data进行存储。
以下介绍数据写入子电路106的两种示例性地结构。在一些示例中，如图3所示，数据写入子电路106与第三节点N3、输入控制信号端Dn和数据信号端Data耦接。数据写入子电路106被配置为，响应于在输入控制信号端Dn处接收的输入控制信号dn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
在另一些示例中，如图4所示，上述输入控制信号端Dn为第二发光时序信号端EM2，数据写入子电路106还与扫描时序信号端Sn耦接。也就是说，数据写入子电路106与第三节点N3、第二发光时序信号端EM2、扫描时序信号端Sn和数据信号端Data耦接。数据写入子电路106被配置为，响应于第二发光时序信号em2和扫描时序信号sn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
上述基准电压子电路107与第三节点N3、第一发光时序信号端EM1和参考电压信号端Vref耦接。基准电压子电路107被配置为，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将在参考电压信号端Vref处接收的参考电压信号vref传输至所述第三节点N3，以对第三节点N3的电压保持在基准电压，本公开以参考电压信号vref的电压为基准电压。
需要说明的是，如图3和图4所示，在显示面板01中，多个亚像素10呈阵列排布，一行亚像素中各像素驱动电路100所接收的来自第二发光时序信号端EM2的第一发光时序信号em2，与上一行亚像素中像素驱动电路100所接收的来自第一发光时序信号端EM1的第一发光时序信号em1为同一个信 号，即第n行亚像素中各像素驱动电路100的第二发光时序信号端EM2和第n-1行亚像素中各像素驱动电路100的第一发光时序信号端EM1与同一条发光时序信号线EL(第n-1条发光时序信号线EL)耦接，一条发光时序信号线EL与其前后两行亚像素耦接，实现共享。示例性地，如图2A和2B所示，对于第n行亚像素的一个像素驱动电路，其第一发光时序信号端EM1同时用EMn表示，第二发光时序信号端EM2同时用EM(n-1)表示。
采用上述相邻发光时序信号组合的方式，可以减少显示面板01所需要设置的发光时序信号线EL的数量，降低显示面板01的制备难度和成本。
本公开所提供的像素驱动电路100包括储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105、数据写入子电路106和基准电压子电路107，结合图7和图10，该像素驱动电路100的驱动过程大致为：
在复位阶段，基准电压子电路107将参考电压信号vref传输至第三节点N3，同时复位子电路102将初始化信号vinit通过发光控制子电路104和补偿子电路103传输至第二节点N2，以对第二节点N2的电压复位。并且，在该阶段，驱动子电路105在第二发光时序信号em2的控制下，断开第一电压信号端Vdd至初始化信号端Vinit的导电路径。
在输入与补偿阶段，数据写入子电路106将数据信号data传输至第三节点N3，同时补偿子电路103打开，使得驱动子电路105产生自饱和状态，驱动子电路105生成补偿信号，并将补偿信号传输至第二节点N2。从而，储能子电路101在第三节点N3和第二节点N2的电压的作用下充电，将数据信号data和补偿信号进行存储。
在发光阶段，复位子电路102将参考电压信号vref传输至第三节点N3，储能子电路101在第三节点N3的电压的作用下,对所述第二节点的电压进行耦合，使第二节点N2的电压发生跳变，驱动子电路105响应于第二发光时序信号em2，且在储能子电路101的放电作用下，生成并输出驱动信号。发光控制子电路104将该驱动信号传输至发光器件108，以驱动发光器件108发光。
在上述像素驱动电路100中，补偿子电路103与耦接于第一节点N1和第二节点N2之间，在复位阶段，复位子电路102对第二节点N2的电压进行复位的过程为，将初始化信号vinit通过发光控制子电路104和补偿子电路103传输至第二节点N2，在输入与补偿阶段，补偿子电路103在扫描时序信号sn的控制下打开，使驱动子电路105产生自饱和状态，从而驱动子电路105生成补偿信号，实现阈值电压的补偿。即上述补偿子电路103被复用为补偿和 复位的功能，通过对补偿子电路103分时复用，实现对储能子电路101的复位和阈值电压的补偿，这样，如图3和图4所示，复位子电路102不直接与第二节点N2耦接，因此在发光阶段，第二节点N2与初始化信号端Vinit之间不会形成漏电通道，即本公开所提供的像素驱动电路100仅存在第二节点N2经补偿子电路103至第一节点N1的单一漏电通道。
这样，在发光阶段，补偿子电路103所包括的晶体管处于关态，第二节点N2仅会通过补偿子电路103漏电，且在相关技术中提到，由于第二节点N2与初始化信号端Vinit之间的电位差大于第二节点N2与第一节点N1之间的电位差，第二漏电通道的漏电量(绝对值)要远大于第一漏电通道的漏电量(绝对值)，因此本公开所提供的像素驱动电路100相当于仅包括漏电量较少的第一漏电通道，从而显著减小了第二节点N2的漏电，提高了储能子电路101的电压保持率。在发光阶段，储能子电路101所包括的第一存储器C1的信号保持端的电位能够在较长时间内保持恒定，第二节点N2的电压能够保持更长时间，从而在第二节点N2的电压的控制下，驱动子电路105所形成的驱动信号的稳定性较高，提高了发光器件108的发光亮度的稳定性和持续性，降低了视觉闪烁感，改善了由于多个发光器件108的发光亮度不均导致的显示不均的问题，从而提高了显示效果。
本领域技术人员可知，驱动子电路105至少包括驱动晶体管，驱动晶体管的控制极与储能子电路101耦接，即与第二节点N2耦接，在复位阶段，随着复位子电路102将初始化信号vinit传输至第二节点N2，对第二节点N2的电压进行复位的过程，驱动晶体管的工作状态由前一帧的发光阶段的饱和驱动状态转变为本帧的复位阶段的线性导通状态。这样，请参见图3和图4，在复位子电路102对第二节点N2的电位复位的过程中，复位子电路102和发光控制子电路104均打开，驱动晶体管在第二节点N2的电压的控制下导通，这样在像素驱动电路100中会形成从第一电压信号端Vdd至初始化信号端Vinit之间的导电路径，示例性地，该导电路径为直流通路，会产生较大的直流电流和无效功耗，从而对像素驱动电路100的正常工作产生不良影响。
由于本公开中驱动子电路105与第二发光时序信号端EM2耦接，在对第二节点N2的电压复位的过程中，驱动子电路105响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2，断开第一电压信号端Vdd至所述初始化信号端Vinit的导电路径。这样，在复位阶段，无论驱动晶体管是否导通，在第二发光时序信号em2的控制下，第一电压信号端Vdd至初始化信号端Vinit之间均不会形成直流通路，从而避免了产生较大的直流电流和无效功耗， 节省了功耗，提高了像素驱动电路100的可靠性。
并且，数据写入子电路106与第三节点N3、输入控制信号端Dn和数据信号端Data耦接。或者，数据写入子电路106与第三节点N3、第二发光时序信号端EM2、扫描时序信号端Sn和数据信号端Data耦接，数据写入子电路106受控于单独设置的输入控制信号端Dn传输的信号，或者数据写入子电路106同时受控于第二发光时序信号端EM2和扫描时序信号端Sn传输的信号，在输入与补偿阶段，实现数据信号data的写入，不占用复位子电路102对储能子电路101进行复位的时间，复位和数据信号data的写入是分时段进行的，能够保证对储能子电路101的充分复位以及数据信号data的充分写入。
以下对像素驱动电路100所包括的储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105、数据写入子电路106和基准电压子电路107所包括的具体结构进行分别介绍。
在一些示例中，如图5、图6、图8和图9所示，储能子电路101包括第一电容器C；第一电容器C的第一端(基准电压端)与第三节点N3耦接，第一电容器C的第二端(信号保持端)与第二节点N2耦接。
复位子电路102包括第一晶体管M1；第一晶体管M1的控制极与扫描时序信号端Sn耦接，第一晶体管M1的第一极与初始化信号端Vinit耦接，第一晶体管M1的第二极与发光控制子电路104耦接。第一晶体管M1被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至发光控制子电路104。
第一晶体管M1的第二极还与发光器件108耦接，第一晶体管M1还被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至发光器件108，以对发光器件108复位。
基准电压子电路107包括第八晶体管M8；第八晶体管M8的控制极与第一发光时序信号端EM1耦接，第八晶体管M8的第一极与参考电压信号端Vref耦接，第八晶体管M8的第二极与第三节点N3耦接。第八晶体管M8被配置为，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将在参考电压信号端Vref处接收的参考电压信号vref传输至第三节点N3。
发光控制子电路104包括第二晶体管M2；第二晶体管M2的控制极与第一发光时序信号端EM1耦接，第二晶体管M2的第一极与第一节点N1耦接，第二晶体管M2的第二极与第一晶体管M1的第二极耦接。第二晶体管M2被配置为，在复位阶段，响应于在第一发光时序信号端EM1处接收的第一发光 时序信号em1，将来自复位子电路102(复位子电路102中的第一晶体管M1)的初始化信号vinit传输至第一节点N1。
在一些示例中，第二晶体管M2的第二极还与发光器件108耦接，第二晶体管M2还被配置为，在发光阶段，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将来自第一节点N1(或驱动子电路105)的驱动信号传输至发光器件108。
补偿子电路103包括第三晶体管M3；第三晶体管M3的控制极与扫描时序信号端Sn耦接，第三晶体管M3的第一极与第一节点N1耦接，第三晶体管M3的第二极与第二节点N2耦接。第三晶体管M3被配置为，在复位阶段，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将来自第一节点N1的初始化信号vinit传输至第二节点N2，以对第二节点N2的电压复位。以及，在输入与补偿阶段，在扫描时序信号sn的控制下打开，使驱动子电路105产生自饱和效应，以生成补偿信号。
在一些实施例中，驱动子电路105包括第四晶体管M4和第五晶体管M5，其中第四晶体管M4为驱动晶体管。
在一些示例中，第四晶体管M4的控制极与第二节点N2耦接，第四晶体管M4的第一极与第一电压信号端Vdd耦接，第四晶体管M4的第二极与第五晶体管M5的第一极耦接。第五晶体管M5的控制极与第二发光时序信号端EM2耦接，第五晶体管M5的第二极与第一节点N1耦接。第四晶体管M4被配置为，在第二节点N2的电压的控制下导通，将在第一电压信号端Vdd处接收的第一电压信号vdd传输至第五晶体管M5的第一极，以及，根据第一电压信号vdd产生并输出驱动电流。第五晶体管M5被配置为，在第二发光时序信号em2的控制下导通，将驱动电流传输至第一节点N1。
在另一些示例中，如图6和图9所示，第四晶体管M4的控制极与第二节点N2耦接，第四晶体管M4的第一极与第五晶体管M5的第二极耦接，第四晶体管M4的第二极与第一节点N1耦接。第五晶体管M5的控制极第二发光时序信号端EM2耦接，第五晶体管M5的第一极与第一电压信号端Vdd耦接。第五晶体管M5被配置为，在第二发光时序信号em2的控制下导通，将第一电压信号vdd传输至第四晶体管M4的第一极。第四晶体管M4被配置为，在第二节点N2的电压的控制下导通，根据所接收的第一电压信号vdd产生并输出驱动电流。
在一些示例中，如图5和图6所示，在数据写入子电路106与第三节点N3、输入控制信号端Dn和数据信号端Data耦接的情况下，数据写入子电路 106包括第六晶体管M6。第六晶体管M6的控制极与输入控制信号端Dn耦接，第六晶体管M6的第一极与数据信号端Data耦接，第六晶体管M6的第二极与第三节点N3耦接。第六晶体管M6被配置为，响应于在输入控制信号端Dn处接收的输入控制信号dn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
在另一些示例中，如图8和图9所示，在数据写入子电路106与第三节点N3、第二发光时序信号端EM2、扫描时序信号端Sn和数据信号端Data耦接的情况下，数据写入子电路106包括第六晶体管M6和第七晶体管M7。第六晶体管M6的控制极与第二发光时序信号端EM2耦接，第六晶体管M6的第一极与第七晶体管M7的第二极耦接，第六晶体管M6的第二极与第三节点N3耦接；第七晶体管M7的控制极与扫描时序信号端Sn耦接，第七晶体管M7的第一极与数据信号data耦接。
第七晶体管M7被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在数据信号端Data处接收的数据信号data传输至第六晶体管M6的第一极。第六晶体管M6被配置为，响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2，将所述数据信号data传输至第三节点N3。
需要说明的是，在本公开的实施例中，储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105、数据写入子电路106和基准电压子电路107的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在此基础上，下面对本公开的一些实施例所提供的像素驱动电路100的具体电路结构进行整体性的、示例性的介绍。
如图5、图6、图8和图9所示，像素驱动电路100包括储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105和数据写入子电路106和基准电压子电路107。
其中，复位子电路102包括第一晶体管M1，发光控制子电路104包括第二晶体管M2，补偿子电路103包括第三晶体管M3，驱动子电路105包括第四晶体管M4和第五晶体管M5。储能子电路101包括第一电容器C，数据写入子电路106包括第六晶体管M6，或者数据写入子电路106包括第六晶体管M6和第七晶体管M7，基准电压子电路107包括第八晶体管M8。
第一电容器C的第一端与第三节点N3耦接，第一电容器C的第二端与第二节点N2耦接。第一电容器C被配置为在第三节点N3和第二节点N2的电压的作用下进行充电，并根据第三节点N3的电压，对第二节点N2的电压进行耦合，以改变第二节点N2的电压，并保持第二节点N2的电压。
第一晶体管M1的控制极与扫描时序信号端Sn耦接，第一晶体管M1的第一极与初始化信号端Vinit耦接，第一晶体管M1的第二极与第二晶体管M2的第二极耦接，且第一晶体管M1的第二极还与发光器件108耦接。第一晶体管M1被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至第二晶体管M2，且将初始化信号vinit传输至发光器件108，以对发光器件108复位。
第二晶体管M2的控制极与第一发光时序信号端EM1耦接，第二晶体管M2的第一极与第一节点N1耦接，第二晶体管M2的第二极与第一晶体管M1的第二极和发光器件108耦接。第二晶体管M2被配置为，在复位阶段，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将来自第一晶体管M1的初始化信号vinit传输至第一节点N1。以及，在发光阶段，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将来自第一节点N1的驱动信号传输至发光器件108。
示例性地，发光器件108为发光二极管，第一晶体管M1的第二极与发光二极管的阳极耦接，第三晶体管M3的第二极与发光二极管的阳极耦接，发光二极管的阴极与第二电压信号端耦接。
第三晶体管M3的控制极与扫描时序信号端Sn耦接，第三晶体管M3的第一极与第一节点N1耦接，第三晶体管M3的第二极与第二节点N2耦接。第三晶体管M3被配置为，在复位阶段，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将来自第一节点N1的初始化信号vinit传输至第二节点N2，以对第二节点N2的电压复位。以及，在输入与补偿阶段，在扫描时序信号sn的控制下打开，使驱动子电路105产生自饱和效应，以生成补偿信号。
在一些示例中，如图5和图8所示，第四晶体管M4的控制极与第二节点N2耦接，第四晶体管M4的第一极与第一电压信号端Vdd耦接，第四晶体管M4的第二极与第五晶体管M5的第一极耦接。第五晶体管M5的控制极与第二发光时序信号端EM2耦接，第五晶体管M5的第二极与第一节点N1耦接。
第四晶体管M4被配置为，在第二节点N2的电压的控制下导通，将在第一电压信号端Vdd处接收的第一电压信号vdd传输至第五晶体管M5的第一极，以及，根据第一电压信号vdd产生并输出驱动电流。第五晶体管M5被配 置为，在第二发光时序信号em2的控制下导通，将驱动电流传输至第一节点N1。
在另一些示例中，如图6和图9所示，第四晶体管M4的控制极与第二节点N2耦接，第四晶体管M4的第一极与第五晶体管M5的第二极耦接，第四晶体管M4的第二极与第一节点N1耦接；第五晶体管M5的控制极第二发光时序信号端EM2耦接，第五晶体管M5的第一极与第一电压信号端Vdd耦接。
第五晶体管M5被配置为，在第二发光时序信号em2的控制下导通，将第一电压信号vdd传输至第四晶体管M4的第一极。第四晶体管M4被配置为，在第二节点N2的电压的控制下导通，根据所接收的第一电压信号vdd产生并输出驱动电流。
如图5和图6所示，在数据写入子电路106包括第六晶体管M6的情况下，第六晶体管M6的控制极与输入控制信号端Dn耦接，第六晶体管M6的第一极与数据信号端Data耦接，第六晶体管M6的第二极与第三节点N3耦接。第六晶体管M6被配置为，响应于在输入控制信号端Dn处接收的输入控制信号dn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
如图8和图9所示，在数据写入子电路106包括第六晶体管M6和第七晶体管M7的情况下，第六晶体管M6的控制极与第二发光时序信号端EM2耦接，第六晶体管M6的第一极与第八晶体管M8的第二极耦接，第六晶体管M6的第二极与第三节点N3耦接。第七晶体管M7的控制极与扫描时序信号端Sn耦接，第七晶体管M7的第一极与数据信号data耦接。
第七晶体管M7被配置为，响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在数据信号端Data处接收的数据信号data传输至第六晶体管M6的第一极。第六晶体管M6被配置为，响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2，将所述数据信号data传输至第三节点N3。
第八晶体管M8的控制极与第一发光时序信号端EM1耦接，第八晶体管M8的第一极与参考电压端耦接，第八晶体管M8的第二极与第三节点N3耦接。第八晶体管M8被配置为，响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将在参考电压信号端Vref处接收的参考电压信号vref传输至第三节点N3。
本公开的实施例提供的像素驱动电路100中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，上述像素驱动电路100中所采用的各晶体管的控制极 为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
另外，在本公开的实施例提供的像素驱动电路100中，晶体管均以P型晶体管为例进行说明，在以下提供的像素驱动方法中，同样是以P型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的电路中的一个或多个晶体管也可以采用N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。
在本公开的实施例提供的电路中，第一节点N1、第二节点N2、第三节点N3并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的一些实施例还提供了一种像素驱动方法，该像素驱动方法应用于如本公开所提供的像素驱动电路100。以图5为例，在像素驱动电路100包括储能子电路101、复位子电路102、补偿子电路103、发光控制子电路104、驱动子电路105、数据写入子电路106和基准电压子电路107，且复位子电路102与发光控制子电路104、扫描时序信号端Sn、初始化信号端Vinit耦接；储能子电路101与第二节点N2和第三节点N3耦接；数据写入子电路106与第三节点N3、输入控制信号端Dn和数据信号端Data耦接；基准电压子电路107与第三节点N3、第一发光时序信号端EM1和参考电压信号端Vref耦接，复位子电路102和发光控制子电路104还与发光器件108耦接的情况下，如图7和图10所示，像素驱动方法包括：一个帧周期包括复位阶段P1、输入与补偿阶段P2和发光阶段P3。
在复位阶段P1：
基准电压子电路107响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将在参考电压信号端Vref处接收的参考电压信号vref传输至第三节点N3。
复位子电路102响应于在扫描时序信号端Sn处接收的扫描时序信号sn，将在初始化信号端Vinit处接收的初始化信号vinit传输至发光控制子电路104 和发光器件108，以对发光器件108复位。
发光控制子电路104响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将初始化信号vinit传输至第一节点N1。
补偿子电路103在扫描时序信号sn的控制下，将来自第一节点N1的初始化信号vinit传输至第二节点N2，以对第二节点N2的电压复位。
驱动子电路105响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2，断开第一电压信号端Vdd至初始化信号端Vinit的导电路径。
示例性地，如图4、图5、图8和图9所示，在复位子电路102包括第一晶体管M1，发光控制子电路104包括第二晶体管M2，补偿子电路103包括第三晶体管M3，驱动子电路105包括第四晶体管M4和第五晶体管M5，储能子电路101包括第一电容器C，数据写入子电路106包括第六晶体管M6，或者数据写入子电路106包括第六晶体管M6和第七晶体管M7，基准电压子电路107包括第八晶体管M8，发光器件108包括发光二极管的情况下，复位阶段P1包括：
第八晶体管M8在第一发光时序信号em1的控制下导通，将参考电压信号vref传输至第三节点N3，第三节点N3的电压为参考电压信号vref的电压V ref。第一晶体管M1在扫描时序信号sn的控制下导通，将初始化信号vinit传输至第二晶体管M2的第二极和发光二极管的阳极。第二晶体管M2在第一发光时序信号em1的控制下导通，将来自第一晶体管M1的初始化信号vinit传输至第一节点N1。第三晶体管M3在扫描时序信号sn的控制下导通，将来自第一节点N1的初始化信号vinit传输至第二节点N2，第二节点N2的电压为初始化信号vinit的电压V init。从而实现了对第二节点N2的电压的复位，实现对储能子电路101的第二端(信号保持端)的复位。
在第二节点N2的电压的控制下，第四晶体管M4处于线性导通状态，第五晶体管M5在第二发光时序信号em2的控制下截止，从而能够断开第一电压信号端Vdd至初始化信号端Vinit的导电路径，避免了无效功耗。
如图8和图9所示，对于数据写入子电路106包括第六晶体管M6和第七晶体管M7的情况，第七晶体管M7在扫描时序信号sn的控制下导通，而第六晶体管M6在第二发光时序信号em2的控制下截止，因此，数据信号data无法传输至第三节点N3，从而数据信号data的写入不会占用复位时间，能够保证对第三节点N3的充分复位。
在输入与补偿阶段P2，
复位子电路102响应于在扫描时序信号端Sn处接收的扫描时序信号sn， 将在初始化信号端Vinit处接收的初始化信号vinit传输至发光器件108，以对发光器件108进行持续复位。
如图3所示，数据写入子电路106响应于在输入控制信号端Dn处接收的输入控制信号dn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
如图4所示，在输入控制信号端为第二发光时序信号端EM2，数据写入子电路106还与扫描时序信号端Sn耦接的情况下，数据写入子电路106响应于在第二发光时序信号端EM2处接收的第二发光时序信号em2和在扫描时序信号端Sn处接收的扫描时序信号sn，将在数据信号端Data处接收的数据信号data传输至第三节点N3。
补偿子电路103在扫描时序信号sn的控制下，使驱动子电路105产生自饱和状态。
驱动子电路105响应于第二发光时序信号em2，在补偿子电路103的作用下产生自饱和状态，以根据在第一电压信号端Vdd处接收的第一电压信号vdd，生成补偿信号，并将补偿信号传输至第二节点N2。
储能子电路101在第二节点N2和第三节点N3的电压的作用下进行充电。
示例性地，如图4、图5、图8和图9所示，在复位子电路102包括第一晶体管M1，发光控制子电路104包括第二晶体管M2，补偿子电路103包括第三晶体管M3，驱动子电路105包括第四晶体管M4和第五晶体管M5，储能子电路101包括第一电容器C，数据写入子电路106包括第六晶体管M6，或者数据写入子电路106包括第六晶体管M6和第七晶体管M7，基准电压子电路107包括第八晶体管M8，且发光器件108为发光二极管的情况下，输入与补偿阶段P2包括：
如图5和图6所示，对于数据写入子电路106包括第六晶体管M6的情况，第六晶体管M6在输入控制信号dn的控制下导通，将数据信号data传输至第三节点N3。
如图8和图9所示，对于数据写入子电路106包括第六晶体管M6和第七晶体管M7的情况，第七晶体管M7在扫描时序信号sn的控制下导通，将数据信号data传输至第六晶体管M6的第一极，同时第六晶体管M6在第二发光时序信号em2的控制下导通，将数据信号data传输至第三节点N3。此时，第三节点N3的电压为数据信号data的电压V data，，从而将数据信号data的电压V data存入第一电容器C。
如图5和图8所示，第四晶体管M4在第二节点N2的电压的控制下导通， 第五晶体管M5在第二发光时序信号em2的控制下导通，第三晶体管M3在扫描时序信号sn的控制下导通。从而，第三晶体管M3和第五晶体管M5使得第四晶体管M4的控制极和其第二极接通，第四晶体管M4处于自饱和状态，则第四晶体管M4的控制极的电位为其第一极的电压与其阈值电压V th之和。第四晶体管M4的第一极与第一电压信号端Vdd耦接，其电压为第一电压信号vdd的电压V dd，则第四晶体管M4的控制极的电压为V dd+V th。第二节点N2与第四晶体管M4的控制极耦接，第二节点N2的电压为V dd+V th，从而将第一电压信号vdd与阈值电压之和V dd+V th存入第一电容器C，实现了驱动晶体管的阈值电压V th的写入。
如图6和图9所示，第四晶体管M4在第二节点N2的电压的控制下导通，第五晶体管M5在第二发光时序信号em2的控制下导通，第三晶体管M3在扫描时序信号sn的控制下导通。从而，第三晶体管M3使得第四晶体管M4的控制极和其第二极接通，第四晶体管M4处于自饱和状态，则第四晶体管M4的控制极的电位为其第一极的电压与其阈值电压V th之和，第五晶体管M5将第一电压信号vdd传输至第四晶体管M4的第一极，从而第四晶体管M4的电压为第一电压信号vdd的电压V dd，则第四晶体管M4的控制极的电压为V dd+V th。第二节点N2与第四晶体管M4的控制极耦接，从而第二节点N2的电压为V dd+V th，从而将第一电压信号vdd与阈值电压之和V dd+V th存入第一电容器C，实现了驱动晶体管的阈值电压V th的写入。
第一晶体管M1在扫描时序信号sn的控制下导通，将初始化信号vinit传输至发光二极管的阳极，以对发光二极管的阳极复位。
第二晶体管M2和第八晶体管M8在输入与补偿阶段均截止。
在发光阶段P3，
复位子电路102响应于在第一发光时序信号端EM1处接收的第一发光时序信号em1，将在参考电压信号端Vref处接收的参考电压信号vref传输至第三节点N3。
储能子电路101在第三节点N3的电压的作用下，对第二节点N2的电位进行耦合，使第二节点N2的电压发生变化，并保持第二节点N2的电压。
驱动子电路105响应于第二发光时序信号em2，且在储能子电路101的耦合作用下，根据第一电压信号生成驱动信号，并将驱动信号传输至发光控制子电路104。
发光控制子电路104响应于第一发光时序信号em1，将来自驱动子电路105的驱动信号传输至发光器件108，以驱动发光器件108发光。
示例性地，示例性地，如图4、图5、图8和图9所示，在复位子电路102包括第一晶体管M1，发光控制子电路104包括第二晶体管M2，补偿子电路103包括第三晶体管M3，驱动子电路105包括第四晶体管M4和第五晶体管M5，储能子电路101包括第一电容器C，数据写入子电路106包括第六晶体管M6，或者数据写入子电路106包括第六晶体管M6和第七晶体管M7，基准电压子电路107包括第八晶体管M8，且发光器件108为发光二极管的情况下，发光阶段P3包括：
第八晶体管M8在第一发光时序信号em1的控制下导通，将参考电压信号vref传输至第三节点N3，第三节点N3的电压变为参考电压的电压V ref。
根据电容的电荷保持定律，由于第三节点N3的电压由数据信号data的电压V data变为参考电压的电压V ref，即第一电容器C的第一端的电压由V data变为V ref，从而第一电容器C的第二端的电压也会发生相同量的变化，由V dd+V th跳变为V dd+V th+V ref-V data，第二节点N2的电压为V dd+V th+V ref-V data。
第四晶体管M4在第二节点N2的电压的控制下导通，第五晶体管M5在第二发光时序信号em2的控制下导通，第四晶体管M4根据第一电压信号vdd生成驱动信号，并将驱动信号输出。
第二晶体管M2在第一发光时序信号em1的控制下导通，将所接收的驱动信号传输至发光二极管，从而发光二极管发光。
示例性的，该驱动信号为驱动电流，根据驱动电流的计算公式，
Figure PCTCN2021094187-appb-000001
其中，其中I ds为第四晶体管M4的饱和电流，也就是输入发光二极管的工作电流；W/L为第四晶体管M4的沟道宽长比；μ为载流子迁移率；C ox为第四晶体管M4的单位面积沟道电容；V gs为第四晶体管M4的栅源电压差；V th为第四晶体管M4的阈值电压。
可见，第四晶体管M4所产生的驱动电流的大小仅与参考电压信号vref和数据信号data有关，与第四晶体管M4的阈值电压无关，因此第四晶体管M4所产生的驱动电流的大小不受其阈值电压的影响，避免了因制备工艺引起的各像素驱动电路100中第四晶体管M4的阈值电压的不同，而造成驱动电流的大小不同，进而影响显示效果的问题，从而提高了各发光器件108的发光 亮度的均一性。
在发光阶段P3，第一晶体管M1、第三晶体管M3和第六晶体管M6(或者是第六晶体管M6和第七晶体管M7)均截止。
由于本公开所提供的像素驱动电路100中，在发光阶段P3，仅存在第二节点N2经第三晶体管M3至第一节点N1的单一漏电通道，能够显著降低第二节点N2的漏电，提高第二电容器的电压保持率，因此，在发光阶段，在第二节点N2的电压的控制下，第四晶体管M4能够产生比较稳定的驱动电流，不会出现由于第二节点N2的电压变动过大造成驱动电流变化过大的问题，从而能够提高发光器件108的发光亮度的稳定性。
本公开的一些实施例还提供了一种显示面板01，如前所述，该显示面板01包括：多个亚像素10，多条扫描时序信号线GL、多条发光时序信号线EL和多条数据信号线DL。一个亚像素(sub pixel)10中设置有如本公开提供的像素驱动电路100。
示例性地，如图11所示，多个亚像素10排列成N行M列。扫描时序信号线GL包括N条，分别为GL(1)～GL(N)，发光时序信号线EL包括N条，分别为EL(1)～EL(N)，数据信号线DL包括M条，分别为D(1)～D(M)。其中，N和M均为正整数。
其中，第n行亚像素10所包括的各像素驱动电路100的扫描时序信号端Sn与第n条扫描时序信号线GL(n)耦接。示例性的，第一行亚像素10所包括的各像素驱动电路100的扫描时序信号端Sn与第1条扫描时序信号线GL(1)耦接，第N行亚像素10所包括的各像素驱动电路100的扫描时序信号端Sn与第N条扫描时序信号线GL(N)耦接。1≤n≤N。
第n行亚像素10所包括的各像素驱动电路100的第一发光时序信号端EM1与第n条发光时序信号线EL(n)耦接，除第一行亚像素外，第n行亚像素10所包括的各像素驱动电路100的第二发光时序信号端EM2与第n-1条发光时序信号线EL(n-1)耦接。示例性的，第2行亚像素10所包括的各像素驱动电路100的第一发光时序信号端EM1与第2条发光时序信号线EL(2)耦接，第二发光时序信号端EM2与第1条发光时序信号线EL(1)耦接。1≤n≤N。
在一些实施例中，显示面板01还包括设置在第一行亚像素之前和最后一行亚像素(第N行亚像素)之后的至少一行哑单元(dummy cell)，该至少一行哑单元具有与上述亚像素相同的结构，但在显示面板进行显示时，没有相应的功能。由于工艺问题以及电路寄生参数的原因，实际用于显示的N行 亚像素中，边缘亚像素(第一行亚像素和第N行亚像素)中的像素驱动电路100与内部的亚像素中的像素驱动电路100的电学特性存在差异，通过设置至少一行哑单元，使得该至少一行哑单元作为边缘行，能够避免实际用于显示的N行亚像素中边缘亚像素和内部亚像素之间存在差异，保证了正常显示。
由此，对应至少一行哑单元，除N条扫描时序信号线GL(1)～GL(N)和N条发光时序信号线EL(1)～EL(N)之外，显示面板01还包括对应的dummy line，例如显示面板01还包括哑扫描时序信号线GL(dummy)和哑发光时序信号线EL(dummy)。示例性地，如图11所示，显示面板还包括设置于第1条发光时序信号线EL(1)之前的哑发光时序信号线EL(dummy)，例如称为第0条发光时序信号线EL(0)。
这样，第一行亚像素10所包括的各像素驱动电路100的第一发光时序信号端EM1与第1条发光时序信号线E(1)耦接，第二发光时序信号端EM2与第0条发光时序信号线EL(0)耦接。第0条发光时序信号线EL(0)被配置为向，第一行亚像素10所包括的各像素驱动电路100的第二发光时序信号端EM2传输第二发光时序信号em2。
如图11所示，示例性地，第m列亚像素10所包括的各像素驱动电路100的数据信号端Data与第m条数据信号线耦接。示例性地，第1列亚像素10所包括的各像素驱动电路100的数据信号端Data与第1条数据信号线DL(1)耦接，第M列亚像素10所包括的各像素驱动电路100的数据信号端Data与第M条数据信号线DL(M)耦接。
这样，扫描时序信号线GL为扫描时序信号端Sn提供扫描时序信号sn，发光时序信号线EL为第一发光时序信号端EM1和第二发光时序信号端EM2提供第一发光时序信号em1或者第二发光时序信号em2，数据信号线DL为数据信号端Data提供数据信号data。
需要说明的是，以上所述的显示面板01所包括的多条信号线的排布，以及图11示出的显示面板01的布线图仅是一种示例，并不构成对显示面板01的结构的限制。
另外，显示面板01还包括多条复位信号线、多条初始化信号线、多条第一电压信号线等信号线，本公开对布线方式不做限定。
在一些实施例中，如图11所示，显示面板01还包括设置于周边区BB的栅极驱动电路20、发光驱动电路30和源极驱动电路40，在一些实施例中，栅极驱动电路20和发光驱动电路30可以设置在沿扫描时序信号线GL的延伸方向上的侧边，数据驱动电路40可以设置在沿数据信号线DL的延伸方向上 的侧边，以驱动显示面板中的像素驱动电路100进行显示。
在一些实施例中，上述栅极驱动电路20可以为栅极驱动IC(integrated circuit，集成电路)，发光驱动电路30可以为发光驱动IC，源极驱动电路40可以为源极驱动IC。
在另一些实施例中，上述栅极驱动电路20可以为GOA(Gate Driver on Array)电路，发光驱动电路30可以为EOA(Emitter on Array)电路，也即上述栅极驱动电路20和发光驱动电路30直接集成在显示面板01的阵列基板中。这样，一方面，可以降低显示面板的制作成本；另一方面，还可以窄化显示装置的边框宽度。以下均是以栅极驱动电路20为GOA电路，发光驱动电路30可以为EOA电路为例进行说明。
需要说明的是的，在一些示例中，显示面板01在周边区BB的单侧设置栅极驱动电路20和发光驱动电路30，从单侧逐行依次驱动各扫描时序信号线GL和各发光时序信号线EL，即单侧驱动。
在另一些示例中，如图11所示，显示面板01可以在周边区BB中沿水平方向X上的两个侧边分别设置栅极驱动电路20，通过两个栅极驱动电路20同时从两侧逐行依次驱动各扫描时序信号线GL，以及在沿水平方向X上的两个侧边分别设置发光驱动电路30，通过两个发光驱动电路30同时从两侧逐行依次驱动各发光时序信号线GL，即双侧驱动。
栅极驱动电路20被配置为提供扫描时序信号sn，示例性地，栅极驱动电路20包括N级级联的移位寄存器(RS1、RS2……RS(N))，N级级联的移位寄存器(RS1、RS2……RS(N))分别对应耦接N条扫描时序信号线GL(1)～GL(N)，用以向扫描时序信号线输出对应的扫描时序信号sn。
发光驱动电路30被配置为提供发光时序信号，示例性的，发光驱动电路30包括N级级联的移位寄存器(RS1’、RS2’……RS(N)’)，N级级联的移位寄存器(RS1’、RS2’……RS(N)’)分别对应耦接N条发光时序信号线EL(1)～EL(N)。在显示面板还包括第0条发光时序信号线EL(0)的情况下，发光驱动电路30还包括哑移位寄存器RS(Dummy)，该哑移位寄存器RS(Dummy)与第一级移位寄存器RS1’耦接，并与第0条发光时序信号线EL(0)耦接。即发光驱动电路30包括N+1级级联的移位寄存器，用以向发光时序信号线EL输出对应的发光时序信号。
由于本公开所提供的像素驱动电路100能够提高储能子电路的电压保持率，从而提高发光器件的发光亮度的稳定性，且保证各发光器件的发光亮度的均一性，因此，显示面板01的显示效果较好，具有闪烁感较低和显示亮度 均一的效果。
本公开的一些实施例还提供了一种显示装置02，如图12所示，该显示装置包括上述显示面板01。
在一些示例中，显示装置还包括框架、电路板、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等，显示面板01设置于框架内。
本公开实施例所提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
本公开所提供的显示装置具有与显示面板相同的有益效果，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素驱动电路，包括：复位子电路、补偿子电路、发光控制子电路和驱动子电路，其中，
    所述复位子电路与所述发光控制子电路、扫描时序信号端和初始化信号端耦接；
    所述发光控制子电路还与第一节点和第一发光时序信号端耦接；
    所述补偿子电路与所述第一节点、第二节点和所述扫描时序信号端耦接；
    所述驱动子电路与所述第一节点、所述第二节点、第一电压信号端和第二发光时序信号端耦接；
    所述复位子电路被配置为，响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光控制子电路；
    所述发光控制子电路被配置为，响应于在所述第一发光时序信号端处接收的第一发光时序信号，将所述初始化信号传输至所述第一节点；
    所述补偿子电路被配置为，在所述扫描时序信号的控制下，将来自所述第一节点的初始化信号传输至所述第二节点，以对所述第二节点的电压复位；
    所述驱动子电路被配置为，在对所述第二节点的电压复位的过程中，响应于在所述第二发光时序信号端处接收的第二发光时序信号，断开所述第一电压信号端至所述初始化信号端的导电路径。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述复位子电路包括第一晶体管；所述第一晶体管的控制极与所述扫描时序信号端耦接，所述第一晶体管的第一极与所述初始化信号端耦接，所述第一晶体管的第二极与所述发光控制子电路耦接；
    所述发光控制子电路包括第二晶体管；所述第二晶体管的控制极与所述第一发光时序信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶体管的第二极与所述第一晶体管的第二极耦接；
    所述补偿子电路包括第三晶体管；所述第三晶体管的控制极与所述扫描时序信号端耦接，所述第三晶体管的第一极与所述第一节点耦接，所述第三晶体管的第二极与所述第二节点耦接。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述驱动子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；所述第五晶体管的控制极与所述第二发光时序信号端耦接， 所述第五晶体管的第二极与所述第一节点耦接。
  4. 根据权利要求1或2所述的像素驱动电路，其中，所述驱动子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述所述第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；所述第五晶体管的控制极所述第二发光时序信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接。
  5. 根据权利要求1～4中任一项所述的像素驱动电路，还包括：储能子电路和数据写入子电路；其中，
    所述储能子电路与所述第二节点和第三节点耦接；所述储能子电路被配置为，在所述第二节点和所述第三节点的电压的作用下进行充电，并根据所述第三节点的电压，对所述第二节点的电压进行耦合，以改变所述第二节点的电压，并保持所述第二节点的电压；
    所述数据写入子电路与所述第三节点、输入控制信号端和数据信号端耦接；所述数据写入子电路被配置为，响应于在所述输入控制信号端处接收的输入控制信号，将在所述数据信号端处接收的数据信号传输至所述第三节点。
  6. 根据权利要求5所述的像素驱动电路，其中，
    所述储能子电路包括第一电容器；所述第一电容器的第一端与所述第三节点耦接，所述第一电容器的第二端与所述第二节点耦接；
    所述数据写入子电路包括第六晶体管；所述第六晶体管的控制极与所述输入控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接。
  7. 根据权利要求5所述的像素驱动电路，其中，所述输入控制信号端为所述第二发光时序信号端，所述数据写入子电路还与所述扫描时序信号端耦接；所述数据写入子电路被配置为，响应于所述第二发光时序信号和所述扫描时序信号，将在所述数据信号端处接收的数据信号传输至所述第三节点。
  8. 根据权利要求7所述的像素驱动电路，其中，所述数据写入子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管的第一极与所述第七晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号端耦接。
  9. 根据权利要求5～8中任一项所述的像素驱动电路，还包括：基准电压子电路；
    所述基准电压子电路与所述第三节点、第一发光时序信号端和参考电压信号端耦接；
    所述基准电压子电路被配置为，响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点。
  10. 根据权利要求9所述的像素驱动电路，其中，所述基准电压子电路包括第八晶体管；
    所述第八晶体管的控制极与所述第一发光时序信号端耦接，所述第八晶体管的第一极与所述参考电压端耦接，所述第八晶体管的第二极与所述第三节点耦接。
  11. 根据权利要求1～10中任一项所述的像素驱动电路，其中，
    所述补偿子电路还被配置为，在所述扫描时序信号的控制下，使所述驱动子电路产生自饱和状态；
    所述驱动子电路还被配置为，响应于所述第二发光时序信号，在所述补偿子电路的作用下产生自饱和状态，以根据在所述第一电压信号端处接收的第一电压信号，生成补偿信号，并将所述补偿信号传输至所述第二节点；
    以及，响应于所述第二发光时序信号，且在所述储能子电路的耦合作用下，根据所述第一电压信号生成驱动信号。
  12. 根据权利要求11所述的像素驱动电路，其中，所述复位子电路还与所述发光器件耦接；所述复位子电路还被配置为，响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光器件，以对所述发光器件复位；
    所述发光控制子电路还与发光器件耦接；所述发光控制子电路还被配置为，响应于所述第一发光时序信号，将来自所述驱动子电路的驱动信号传输至所述发光器件，以驱动所述发光器件发光。
  13. 根据权利要求12所述的像素驱动电路，其中，在所述复位子电路包括第一晶体管的情况下，所述第一晶体管的第二极还与所述发光器件耦接；
    在所述发光控制子电路包括第二晶体管的情况下，所述第二晶体管的第二极还与所述发光器件耦接。
  14. 根据权利要求1～13中任一项所述的像素驱动电路，其中，所述复位子电路包括第一晶体管，所述发光控制子电路包括第二晶体管，所述补偿子电路包括第三晶体管，所述驱动子电路包括第四晶体管和第五晶体管；
    所述像素驱动电路还包括储能子电路、数据写入子电路和基准电压子电 路；所述储能子电路包括第一电容器，所述数据写入子电路包括第六晶体管，或者所述数据写入子电路包括第六晶体管和第七晶体管；所述基准电压子电路包括第八晶体管；
    所述第一晶体管的控制极与所述扫描时序信号端耦接，所述第一晶体管的第一极与所述初始化信号端耦接，所述第一晶体管的第二极与所述第二晶体管的第二极和发光器件耦接；
    所述第二晶体管的控制极与所述第一发光时序信号端耦接，所述第二晶体管的第一极与所述第一节点耦接，所述第二晶体管的第二极与所述第一晶体管的第二极和所述发光器件耦接；
    所述第三晶体管的控制极与所述扫描时序信号端耦接，所述第三晶体管的第一极与所述第一节点耦接，所述第三晶体管的第二极与所述第二节点耦接；
    所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；所述第五晶体管的控制极与所述第二发光时序信号端耦接，所述第五晶体管的第二极与所述第一节点耦接；或者，
    所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述所述第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；所述第五晶体管的控制极所述第二发光时序信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接；
    所述第一电容器的第一端与第三节点耦接，所述第一电容器的第二端与所述第二节点耦接；
    在所述数据写入子电路包括第六晶体管的情况下，所述第六晶体管的控制极与输入控制信号端耦接，所述第六晶体管的第一极与数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接；
    在所述数据写入子电路包括第六晶体管和第七晶体管的情况下，所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管的第一极与所述第八晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号耦接；
    所述第八晶体管的控制极与所述第一发光时序信号端耦接，所述第八晶体管的第一极与所述参考电压端耦接，所述第八晶体管的第二极与所述第三节点耦接。
  15. 一种像素驱动方法，应用于如权利要求1～14中任一项所述的像素驱动电路，
    在所述像素驱动电路包括储能子电路、复位子电路、补偿子电路、发光控制子电路、驱动子电路、数据写入子电路和基准电压子电路，且所述储能子电路与所述第二节点和第三节点耦接；所述数据写入子电路与所述第三节点、输入控制信号端和数据信号端耦接；所述基准电压子电路与所述第三节点、第一发光时序信号端和参考电压信号端耦接；所述复位子电路和所述发光控制子电路还与发光器件耦接的情况下，所述像素驱动方法包括：一个帧周期包括复位阶段、输入与补偿阶段和发光阶段；
    在所述复位阶段：
    所述基准电压子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点；
    所述复位子电路响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光控制子电路和所述发光器件，以对所述发光器件进行复位；
    所述发光控制子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将所述初始化信号传输至所述第一节点；
    所述补偿子电路在所述扫描时序信号的控制下，将来自所述第一节点的初始化信号传输至所述第二节点，以对所述第二节点的电压复位；
    所述驱动子电路响应于在所述第二发光时序信号端处接收的第二发光时序信号，断开所述第一电压信号端至所述初始化信号端的导电路径。
  16. 根据权利要求15所述的像素驱动方法，其中，
    在所述输入与补偿阶段，
    所述复位子电路响应于在所述扫描时序信号端处接收的扫描时序信号，将在所述初始化信号端处接收的初始化信号传输至所述发光器件，以对所述发光器件进行持续复位；
    所述数据写入子电路响应于在所述输入控制信号端处接收的输入控制信号，将在所述数据信号端处接收的数据信号传输至所述第三节点；
    所述补偿子电路在所述扫描时序信号的控制下，使所述驱动子电路产生自饱和状态；
    所述驱动子电路响应于所述第二发光时序信号，在所述补偿子电路的作用下产生自饱和状态，以根据在所述第一电压信号端处接收的第一电压信号， 生成补偿信号，并将所述补偿信号传输至所述第二节点；
    所述储能子电路在所述第二节点和所述第三节点的电压的作用下进行充电；
    在所述发光阶段，
    所述复位子电路响应于在所述第一发光时序信号端处接收的第一发光时序信号，将在所述参考电压信号端处接收的参考电压信号传输至所述第三节点；
    所述储能子电路在所述第三节点的电压的作用下，对所述第二节点的电位进行耦合，使所述第二节点的电压发生变化，并保持所述第二节点的电压；
    所述驱动子电路响应于所述第二发光时序信号，且在所述储能子电路的耦合作用下，根据所述第一电压信号生成驱动信号，并将所述驱动信号传输至所述发光控制子电路；
    所述发光控制子电路响应于所述第一发光时序信号，将来自所述驱动子电路的驱动信号传输至所述发光器件，以驱动所述发光器件发光。
  17. 根据权利要求16所述的像素驱动方法，其中，在所述数据写入子电路包括第六晶体管，所述第六晶体管的控制极与所述输入控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述第三节点耦接的情况下，在所述输入与补偿阶段，
    所述第六晶体管在所述输入控制信号的控制下导通，将所述数据信号传输至所述第三节点；
    在所述输入控制信号端为所述第二发光时序信号端，所述数据写入子电路还与所述扫描时序信号端耦接，所述数据写入子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二发光时序信号端耦接，所述第六晶体管的第一极与所述第七晶体管的第二极耦接，所述第六晶体管的第二极与所述第三节点耦接；所述第七晶体管的控制极与所述扫描时序信号端耦接，所述第七晶体管的第一极与所述数据信号端耦接的情况下，在所述输入与补偿阶段，
    所述第七晶体管在所述扫描时序信号的控制下导通，将所述数据信号传输至所述第六晶体管的第一极，所述第六晶体管在第一发光时序信号的控制下导通，将所述数据信号传输至所述第三节点。
  18. 一种显示面板，包括：如权利要求1～14中任一项所述的像素驱动电路。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板包括多个亚 像素，一个亚像素包括一个像素驱动电路，所述多个亚像素呈多行多列的阵列式布置；
    所述显示面板还包括沿行方向延伸的多条扫描时序信号线和多条发光时序信号线；
    第n行亚像素所包括的各像素驱动电路的扫描时序信号端与第n条扫描时序信号线耦接；
    第n行亚像素所包括的各像素驱动电路的第一发光时序信号端与第n条发光时序信号线耦接，除第一行亚像素外，第n行亚像素所包括的各像素驱动电路的第二发光时序信号端与第n-1条发光时序信号线耦接。
  20. 一种显示装置，包括如权利要求18或19所述的显示面板。
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