WO2021248667A1 - 一种半导体结构 - Google Patents

一种半导体结构 Download PDF

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Publication number
WO2021248667A1
WO2021248667A1 PCT/CN2020/107603 CN2020107603W WO2021248667A1 WO 2021248667 A1 WO2021248667 A1 WO 2021248667A1 CN 2020107603 W CN2020107603 W CN 2020107603W WO 2021248667 A1 WO2021248667 A1 WO 2021248667A1
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WIPO (PCT)
Prior art keywords
bonding area
unit
bit line
substrate
bonding
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PCT/CN2020/107603
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English (en)
French (fr)
Inventor
曹开玮
孙鹏
周俊
占琼
黄蔚
候春源
Original Assignee
武汉新芯集成电路制造有限公司
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Application filed by 武汉新芯集成电路制造有限公司 filed Critical 武汉新芯集成电路制造有限公司
Publication of WO2021248667A1 publication Critical patent/WO2021248667A1/zh
Priority to US17/985,064 priority Critical patent/US20230073118A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Definitions

  • the present invention relates to the field of microelectronics technology, in particular to a semiconductor structure.
  • Flash memory is a widely used non-volatile computer storage technology. It usually uses a floating gate or charge trap structure to store charges in a field effect transistor to form a storage unit.
  • NOR-type flash memory has a completely random access function and can be used for data storage or execution of program code storage.
  • NOR flash memory its storage area and its peripheral driving circuit are fabricated on the same wafer.
  • the NOR flash memory with this planar structure has a long production cycle, a large area occupied by the device, and a high degree of integration. Lower.
  • the present application provides a semiconductor structure, which effectively solves the problem of the larger size of the planar structure of the NOR flash memory, reduces the device area, and improves the integration.
  • the present invention provides a semiconductor structure, including:
  • a storage array unit having a substrate, a storage array located on the substrate, and a first bonding area located on the periphery of the storage array;
  • the memory array includes a plurality of word lines, a plurality of bit lines, and a plurality of source lines
  • the first bonding area includes a first substrate lead-out bonding area, a first bit line bonding area, and a first word line A bonding area and a first source line bonding area; the first substrate lead-out bonding area is used for the lead-out of the substrate, and the first bit line bonding area is used for the lead-out of the bit line,
  • the first word line bonding area is used for the lead-out of the word line, and the first source line bonding area is used for the lead-out of the source line.
  • the semiconductor structure further includes: a peripheral drive circuit unit, located above the projection of the storage array unit, including a peripheral drive circuit located in the middle of the peripheral drive circuit unit, and a second peripheral drive circuit located on the periphery of the peripheral drive circuit.
  • Bonding area; the second bonding area includes a second substrate lead-out bonding area, a second bit line bonding area, a second word line bonding area, and a second source line bonding area;
  • the peripheral drive The circuit includes a power supply circuit, a word line decoder circuit, a bit line decoder circuit, and a source line decoder circuit;
  • the first substrate lead-out bonding area is bonded to the second substrate lead-out bonding area to realize the connection between the substrate in the memory array and the power supply circuit, and the first bit line The bonding area is connected to the second bit line bonding area to realize the connection between the bit line and the bit line decoder circuit, and the first word line bonding area is connected to the second word line The bonding area is bonded to realize the connection between the word line and the word line decoder circuit, and the first source line bonding area is bonded to the second source line bonding area to realize the The source line is connected to the source line decoder circuit.
  • the peripheral driving circuit further includes a logic control circuit; used to control the power supply circuit, the word line decoder circuit, the bit line decoder circuit, and the source line decoder circuit.
  • the substrate includes a triple P-type doped well and a deep N-type doped well on its periphery
  • the first substrate lead-out bonding area includes a plurality of The first substrate bonding unit leads the triple P-type doped well and the deep N-type doped well.
  • the first bit line bonding area is located on at least one side of the periphery of the storage array.
  • bit lines are all connected to the first bit line bonding units in the first bit line bonding area on one side of the periphery of the memory array, and the first bit line bonding units are staggered. .
  • adjacent bit lines are respectively connected to the first bit line bonding units in the first bit line bonding areas located on both sides of the periphery of the memory array.
  • the first word line bonding area is located on at least one side of the periphery of the storage array.
  • the first source wire bonding area is located on at least one side of the periphery of the storage array.
  • a dummy source line is arranged between the plurality of source lines, and each of the source lines has a plurality of the first source line bonding units.
  • the storage array is a NOR-type flash memory architecture.
  • the peripheral circuit also includes an address control addressing unit, an input and output control logic unit, an algorithm control logic unit, an instruction state control logic unit, a static random access memory SRAM, a redundant replacement control unit, a page buffer, a charge pump, At least one of reference source, power-on reset, pin and electrostatic discharge ESD structure, power management unit, digital-to-analog-to-digital converter, and artificial intelligence algorithm unit.
  • the present invention provides a semiconductor structure including a memory array unit having a substrate, a memory array located on the substrate, and a first bonding area located on the periphery of the memory array.
  • the first bonding area includes a first substrate lead-out bonding area, a first bit line bonding area, a first word line bonding area, and a first source line bonding area, wherein the first substrate lead-out bonding area Used for the lead-out of the substrate, the first bit line bonding area is used to lead out the bit line, the first word line bonding area is used to lead out the word line, and the first source line bonding area is used to lead out the source line .
  • the peripheral drive circuit unit is arranged above the projection of the storage array unit, that is, it is arranged separately from the storage array unit, so that the peripheral drive circuit is no longer provided in the storage array unit forming the storage array.
  • the peripheral drive circuit unit of the peripheral drive circuit is also no longer equipped with a storage array, so the first bonding area and the corresponding second bonding area in the peripheral drive circuit unit can be bonded by using wafer bonding technology to realize storage
  • the substrate, multiple word lines, multiple bit lines, and multiple source lines in the array unit are electrically connected to corresponding drive circuits in the peripheral drive circuit unit, so that the semiconductor structure has a three-dimensional structure in the vertical direction. Its size is reduced.
  • FIG. 1 is a schematic diagram of a front view of a semiconductor structure provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the structure of a memory array unit provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the structure of a peripheral driving circuit unit provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the first substrate leading out the bonding area provided by the embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure of a first bit line bonding area provided by an embodiment of the present invention.
  • FIG. 6 is another schematic diagram of the structure of the first bit line bonding area provided by the embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a first word line bonding area provided by an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the first source wire bonding area provided by an embodiment of the present invention.
  • the present invention is directed to the problem of large space occupied by the existing flash memory under the planar structure due to its large size.
  • the embodiment of the present invention is used to solve this problem and takes the NOR flash memory as an example. Explain.
  • FIG. 1 is a front view structural diagram of a semiconductor structure provided by an embodiment of the present invention. From the figure, each component and each component of the embodiment of the present invention can be seen intuitively. The relative position of the components.
  • the semiconductor structure 100 includes a storage array unit 110 and a peripheral driving circuit unit 120, and the peripheral driving circuit unit 120 is located above the projection of the storage array unit 110.
  • FIG. 2 is a schematic structural diagram of a storage array unit 110 provided by an embodiment of the present invention. From the figure, the components of the embodiment of the present invention can be seen intuitively, and The relative position of each component.
  • the memory array unit 110 has a substrate 111, a memory array 112 on the substrate 111, and a first bonding area 113 on the periphery of the memory array 112. As shown in FIG. 2, in this embodiment, the first bit line bonding area 1132 in the first bonding area 113 and the first word line bonding area 1133 and the memory array 112 do not overlap in the projection direction.
  • first bit line bonding area 1132 in the first bonding area 113 and the first word line bonding area 1133 may partially overlap with the memory array 112 in the projection direction.
  • the memory array 112 includes a plurality of word lines 1121, a plurality of bit lines 1122, and a plurality of source lines (not shown in the figure), and the first bonding area 113 includes a first substrate lead-out bonding area 1131 One bit line bonding area 1132, a first word line bonding area 1133, and a first source line bonding area 1134, wherein the first substrate lead-out bonding area 1131 can be used for the lead-out of the substrate 111, the first bit The wire bonding area 1132 can be used to lead out the bit line 1122, the second word line bonding area 1133 can be used to lead out the word line 1121, and the first source line bonding area 1134 can be used to lead out a source line.
  • the first substrate lead-out bonding area 1131 can be located at any corner around the storage array 112, and distributed at least in one corner, and at most four corners; the first bit line bonding area 1132 can be located in the storage array 112 At least one side of the periphery may be distributed on one side of the periphery or on both sides of the periphery; the first word line bonding area 1133 may be located on at least one side of the periphery of the storage array 112, and may be distributed on one side of the periphery , Can also be distributed on both sides of the periphery; the first source wire bonding regions 1134 can be located on at least one side of the periphery of the memory array 112, and can be distributed on one side of the periphery or on both sides of the periphery.
  • the storage array 112 may be a NOR-type flash memory architecture.
  • FIG. 3 is a schematic structural diagram of a peripheral driving circuit unit 120 provided by an embodiment of the present invention. From the figure, the components of the embodiment of the present invention can be seen intuitively. And the relative position of each component.
  • the peripheral drive circuit unit 120 includes a peripheral drive circuit 121 located in the middle of the peripheral drive circuit unit 120, and a second bonding area 122 located on the periphery of the peripheral drive circuit unit 120 for connecting the peripheral drive circuit 121, And it is connected to the first bonding area 113 by bonding correspondingly, so as to realize the connection between the peripheral driving circuit 121 and the storage array 112.
  • the peripheral driving circuit 121 includes a power supply circuit 1211, a word line decoder circuit 1212, a bit line decoder circuit 1213, and a source line decoder circuit 1214.
  • the power supply circuit 1211 is used to supply power to the substrate 111.
  • the line decoder circuit 1212 is used to output word line control signals
  • the bit line decoder circuit 1213 is used to output bit line control signals
  • the source line decoder circuit 1214 is used to output source control signals.
  • the peripheral driving circuit 121 further includes a control logic circuit 1215, and the control logic circuit 1215 is used to control the word line decoder circuit 1212, the bit line decoder circuit 1213, and the source line decoder circuit 1214.
  • the peripheral driving circuit 121 further includes an address control addressing unit, an input and output control logic unit, an algorithm control logic unit, an instruction state control logic unit, a static random access memory SRAM, a redundant replacement control unit, a page buffer, and a charge At least one of a pump, a reference source, a power-on reset, a pin and an electrostatic discharge ESD structure, a power management unit, a digital-to-analog converter, and an artificial intelligence algorithm unit.
  • the second bonding area 122 includes a second substrate lead-out bonding area 1221, a second bit line bonding area 1222, a second word line bonding area 1223, and a second source line bonding area 1224.
  • the two-substrate lead-out bonding area 1221 is used to lead out the power supply circuit 1211
  • the second bit line bonding area 1222 is used to lead out the bit line decoder circuit 1213
  • the second word line bonding area 1223 is used for word line decoding
  • the second source line bonding area 1224 is used for the lead-out of the source line decoder circuit 1214.
  • the second substrate lead-out bonding area 1221 can be located at any corner around the peripheral driving circuit 121, and distributed at least in one corner, and at most four corners; the second bit line bonding area 1222 can be located in the peripheral driver At least one side of the periphery of the circuit 121 may be distributed on one side of the periphery or on both sides of the periphery; the second word line bonding area 1223 may be located on at least one side of the periphery of the peripheral driving circuit 121, and may be distributed on One side of the periphery may also be distributed on both sides of the periphery; the second source wire bonding area 1224 may be located on at least one side of the periphery of the peripheral driving circuit 121, and may be distributed on one side of the periphery or on both sides of the periphery.
  • the distribution mode of the second bonding area 122 should be consistent with the distribution mode of the first bonding area 113, so that the two can be bonded and connected correspondingly.
  • the bonding areas corresponding to the first bonding area 113 and the second bonding area 122 are aligned and connected.
  • the first substrate lead-out bonding area 1131 is bonded to the second substrate lead-out bonding area 1221 to realize electrical connection between the substrate 111 in the memory array unit 110 and the power supply circuit 1211 in the peripheral drive circuit unit 120;
  • the first bit line bonding area 1132 and the second bit line bonding area 1222 are bonded to realize the electrical connection between the bit line 1122 in the memory array unit 110 and the bit line decoder circuit 1213 in the peripheral driving circuit unit 120;
  • a word line bonding area 1133 is bonded to a second word line bonding area 1223 to realize electrical connection between the word line 1121 in the memory array unit 110 and the word line decoder circuit 1212 in the peripheral driving circuit unit 120;
  • first The source line bonding area 1134 and the second source line bonding area 1224 are bonded to realize electrical connection between the
  • FIG. 4 is a schematic diagram of the structure of the first substrate leading out the bonding area 1131 provided by the embodiment of the present invention. From the figure, it can be seen that the embodiment of the present invention is very intuitive. Each component, and the relative position of each component.
  • the substrate 111 may include a triple P-type doped well 1111 and a deep N-type doped well 1112.
  • the deep N-type doped well 1112 may be located at the periphery of the triple P-type doped well 1111 to isolate different
  • the width of the triple P-doped well 1111 can be represented by d1, the width of the deep N-doped well 1112 can be represented by d2, and the distance between the triple P-doped well 1111 and the deep N-doped well 1112 It can be represented by d3, and d1, d2, and d3 can be determined according to actual conditions.
  • the first substrate lead-out bonding area 1131 may include a plurality of first substrate bonding units drawn from the triple P-type doped well 1111 and the deep N-type doped well 1112 and located at any corner around the memory array 112 11311, for bonding and connecting with the second substrate bonding unit connected to the power supply circuit 1211 in the second substrate lead-out bonding area 1221, so that the substrate 111 is supplied with a bias voltage by the power supply circuit 1211.
  • first substrate bonding unit 11311 there may be one first substrate bonding unit 11311, or there may be multiple first substrate bonding units 11311.
  • FIG. 4 there are three connected with the triple P-type doped well 1111.
  • the first substrate bonding unit 11311 Take the first substrate bonding unit 11311 as an example; corresponding to the deep N-type doped well 1112, there may be one first substrate bonding unit 11311, or there may be multiple first substrate bonding units 11311.
  • five first substrate bonding units 11311 are connected to the N-type doped well 1112.
  • the first substrate bonding unit 11311 may be located on the surface of the second substrate lead-out bonding area 1221 away from the substrate.
  • the first substrate bonding unit 11311 and the substrate 111 may be connected by a vertical metal wire 11312.
  • a dielectric layer may be formed between a substrate bonding unit 11311 and the substrate 111, and a metal line 11312 is formed in a through hole penetrating the dielectric layer.
  • the doped well in the substrate 111 may also be of other doping types.
  • the first bit line bonding area 1132 may be located on at least one side of the periphery of the memory array 112, and each first bit line bonding area 1132 may include a plurality of first bit line bonding units 11321 respectively connected to a plurality of bit lines 1122, It is used for bonding and connecting with the second bit line bonding unit connected to the bit line decoder circuit 1213 in the second bit line bonding area 1222.
  • FIG. 5 is a schematic structural diagram of the first bit line bonding area 1132 provided by an embodiment of the present invention. From the figure, it can be seen intuitively that each of the embodiments of the present invention Components, and the relative position of each component.
  • FIG. 5 shows a scene where the first bit line bonding area 1132 is provided above the bit line 1122, and each bit line 1122 is connected to the first bit line bonding unit 11321 above the memory array 112.
  • first bit line bonding unit 11321 may be provided, or multiple first bit line bonding units 11321 may be provided.
  • each bit line 1122 can be connected with two first bit line bonding units 11321.
  • the distance between the two first bit line bonding units 11321 can be represented by d6, and its value can be determined according to the actual situation. .
  • the first bit line bonding unit 11321 may be located on the surface of the first bit line bonding area 1132 away from the substrate 111, and a vertical metal wire 11322 may be used between the first bit line bonding unit 11321 and the bit line 1122, or a vertical metal wire 11322 may be used between the first bit line bonding unit 11321 and the bit line 1122
  • the metal wire 11322 and the horizontal lead wire 11323 are connected, the vertical direction refers to the direction perpendicular to the substrate, and the horizontal direction refers to the direction parallel to the substrate.
  • a dielectric layer may be formed between the first bit line bonding unit 11321 and the bit line 1122, the metal line 11322 may be formed in a through hole penetrating the dielectric layer, and the lead line 11323 may be formed on the same layer as the bit line 1122.
  • each bit line 1122 is connected to the two first bit line bonding units 11321 on it.
  • the first bit line bonding units 11321 can be arranged alternately, and the lead lines 11323 of each bit line 1122 are not flush. Therefore, the problem of too close distance caused by the alignment of the first bit line bonding unit 11321 is avoided, and the occurrence of short circuits is reduced to a certain extent.
  • FIG. 5 is a top view of the memory array unit 110, even though the first bit line bonding unit 11321 connected to the first bit line 1122 overlaps with the second bit line 1122 in the projection direction, the two are parallel. Not connected, the positional relationship between the other bit lines 1122 and the first bit line bonding unit 11321 is similar.
  • a first bit line bonding area 1132 may be provided both above and below the bit line 1122, and the adjacent bit lines 1122 are respectively connected to the first bit line bonding units 11321 on both sides of the memory array 112. At this time, half of the bit lines 1122 may be connected to the upper first bit line bonding unit 11321, and the other half of the bit lines 1122 may be connected to the lower first bit line bonding unit 11321.
  • FIG. 6 it is another schematic diagram of the structure of the first bit line bonding area provided by the embodiment of the present invention. Specifically, FIG. 6 shows that the first bit line bonding area is provided above and below the bit line 1122.
  • a schematic diagram of the first bit line bonding area located above the bit line where the first bit line bonding unit 11321 is only connected to a part of the bit line 1122, specifically, the first, third, fifth... One bit line 1122 is connected to the first bit line bonding unit 11321 located above the bit line 1122 through a lead wire 11323, and the second, fourth, sixth... bit lines 1122 are not connected to the first bit line bonding unit 11321 located above the bit line 1122.
  • the bit line bonding unit 11321 is connected, but is connected to the first bit line bonding unit 11321 located below the bit line 1122 (not shown in the figure). In this way, the gap between the connected adjacent first bit line bonding units 11321 is large, and short circuit is prevented.
  • the first word line bonding area 1133 may be located on at least one side of the periphery of the memory array 112, and each first word line bonding area 1133 may include a plurality of first word line bonding units 11331 respectively connected to a plurality of word lines 1121 , Used for bonding and connecting with the second word line bonding unit connected to the word line decoder circuit 1212 in the second word line bonding area 1223.
  • FIG. 7 is a schematic structural diagram of the first word line bonding area 1133 provided by an embodiment of the present invention. From the figure, you can intuitively see each of the embodiments of the present invention. Components, and the relative position of each component.
  • FIG. 7 shows a scenario where only the first word line bonding unit 11331 is provided on the right side of the word line 1121, and all the word lines 1121 need to be connected to the first word line bonding unit 11331 on the right.
  • one first word line bonding unit 11331 may be provided, or multiple first word line bonding units 11331 may be provided.
  • each word line 1121 may be connected with two first word line bonding units 11331.
  • the first word line bonding unit 11331 may be located on the surface of the first word line bonding area 1133 away from the substrate 111, and a vertical metal wire 11332 may be used between the first word line bonding unit 11331 and the word line 1121, or a vertical metal line 11332 may be used between the first word line bonding unit 11331 and the word line 1121.
  • the metal wire 11332 is connected to the horizontal lead wire 11333.
  • a dielectric layer may be formed between the first word line bonding unit 11331 and the word line 1121, the metal line 11332 may be formed in a through hole penetrating the dielectric layer, and the lead line 11333 may be formed in the same layer as the word line 1121.
  • each word line 1121 is connected to two first word line bonding units 11331 thereon.
  • the first word line bonding units 11331 may be arranged in a staggered manner, and the lead line 11333 of each word line 1121 may be The uneven arrangement avoids the problem of too close distance caused by the alignment of the first word line bonding unit 11331, and reduces the occurrence of short circuits to a certain extent.
  • the first word line bonding unit 11331 connected to the second word line 1121 from top to bottom may be located on the right side of the first word line 1121, the third word line 1121 and the fourth word line 1121
  • the first word line bonding unit 11331 connected by 1121 is not shown.
  • the edge distance of the two first word line bonding units 11331 in the longitudinal direction can be represented by d9, and its value can be determined according to actual conditions.
  • FIG. 7 is a top view of the memory array unit 110, even though the first word line bonding unit 11331 connected to the first word line overlaps the second word line 1121 in the projection direction, they are not For connection, the positional relationship between the other word lines 1121 and the first word line bonding unit 11331 is similar.
  • the first word line bonding unit 11331 when the first word line bonding unit 11331 is provided on both sides of the word line 1121, half of the word line 1121 can be connected on the right side, and the other half of the word line 1121 can be connected on the left side.
  • the description of the bit line 1122 can be referred to, and the illustration and other descriptions are omitted here.
  • the first source line bonding area 1134 may be located on at least one side of the periphery of the memory array 112, and each first source line bonding area 1134 may include a plurality of first source lines respectively connected to a plurality of source lines 1123
  • the bonding unit 11341 is used for bonding and connecting with the second source line bonding unit connected to the source line decoder circuit 1214 in the second source line bonding area 1224.
  • FIG. 8 is a schematic structural diagram of the first source wire bonding area 1134 provided by an embodiment of the present invention. Each component, and the relative position of each component.
  • each source line 1123 is connected to the first source line bonding unit 11341 above the storage array 112.
  • one first source line bonding unit 11341 may be provided, or a plurality of first source line bonding units 11341, such as two, may be provided.
  • the first source line bonding unit 11341 may be located on the surface of the first source line bonding region 1134 away from the substrate 111, and a longitudinal metal wire may be used between the first source line bonding unit 11341 and the source line 1123. 11342, or the vertical metal wire 11342 and the horizontal lead wire 11343 are connected. Specifically, a dielectric layer may be formed between the first source line bonding unit 11341 and the source line 1123, the metal line 11342 may be formed in the through hole penetrating the dielectric layer, and the lead line 11343 may be formed in the same place as the source line 1123. Floor.
  • each source line 1123 is connected to the two first source line bonding units 11341 thereon.
  • the first source line bonding units 11341 can be arranged in a staggered manner, and the lead wires 11343 of each source line 1123 The arrangement is not flush, so as to avoid the problem of too close distance caused by the alignment of the first source wire bonding unit 11341, and to reduce the occurrence of short circuits to a certain extent.
  • the first source line bonding unit 11341 connected to the second source line 1123 from top to bottom may be located at the first source line bonding unit 11341 connected to the first source line 1123.
  • the first source line bonding unit 11341 to which the third source line 1123 and the fourth source line 1123 are connected is not shown.
  • FIG. 8 is a top view of the memory array unit 110, even though the first source line bonding unit 11341 connected to the first source line 1123 overlaps with the second source line 1123 in the projection direction, The two are not connected, and the positional relationship between the other source lines 1123 and the first source line bonding unit 11341 is similar.
  • the first source wire bonding area 1134 can also be disposed above and below the memory array 112, and half of the source wire 1123 is connected to the first source wire bonding unit 11341 above, and the other half is connected to the upper first source wire bonding unit 11341.
  • the source line 1123 is connected to the lower first source line bonding unit 11341 (not shown in the figure).
  • the first source line bonding area 1134 may be adjacent to the first bit line bonding area 1132, or may be adjacent to the first word line bonding area 1133, and may be disposed in the end direction of the word line 1121 or the bit line 1122 The end direction.
  • each source line 1123 has a plurality of first source line bonding units 11341.
  • the present invention provides a semiconductor structure including a memory array unit having a substrate, a memory array on the substrate, and a first bonding area located on the periphery of the memory array.
  • a bonding area includes a first substrate lead-out bonding area, a first bit line bonding area, a first word line bonding area, and a first source line bonding area, wherein the first substrate leads the bonding area
  • the first bit line bonding area is used to lead out the bit line
  • the first word line bonding area is used to lead out the word line
  • the first source line bonding area is used to lead out the source line.
  • the peripheral drive circuit unit is arranged above the projection of the storage array unit, that is, it is arranged separately from the storage array unit, so that the peripheral drive circuit is no longer provided in the storage array unit forming the storage array.
  • the peripheral drive circuit unit of the peripheral drive circuit is also no longer equipped with a storage array, so the first bonding area and the corresponding second bonding area in the peripheral drive circuit unit can be bonded by using wafer bonding technology to realize storage
  • the present invention can also have other embodiments. All technical solutions formed by equivalent replacements or equivalent replacements fall within the protection scope of the present invention.

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Abstract

本发明提供了一种半导体结构，包括存储阵列单元，该存储阵列单元具有衬底、位于衬底上的存储阵列、以及位于存储阵列周边的第一键合区，该第一键合区包括第一衬底引出键合区、第一位线键合区、第一字线键合区以及第一源极线键合区，本发明提供的半导体结构是将***驱动电路单元设置于存储阵列单元的投影上方，即与存储阵列单元分别设置，在形成存储阵列的存储阵列单元中不再设置***驱动电路，利用晶圆键合技术将第一键合区与***驱动电路单元中相对应的第二键合区相键合，实现存储阵列单元中的衬底、多条字线、多条位线以及多条源极线与***驱动电路单元中相对应的驱动电路电连接，从而使得该半导体结构在垂直方向上呈三维结构，减小了其尺寸。

Description

一种半导体结构
本申请要求于2020年06月11日提交中国专利局、申请号为202010529695.8、申请名称为“一种半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子技术领域，特别涉及一种半导体结构。
背景技术
闪存是一种广泛使用的非易失性计算机存储技术，通常采用浮栅或者电荷捕获结构在场效应晶体管中存储电荷，构成存储单元。NOR型闪存具有完全随机存取功能，可用于进行数据存储或执行程序代码存储。
现有技术下的NOR型闪存，是将其存储区域以及其***驱动电路制作在同一片晶圆上，但是，这种平面结构的NOR型闪存生产周期长，器件占用的面积较大，集成度较低。
发明内容
本申请提供了一种半导体结构，有效地解决了因平面结构的NOR型闪存尺寸较大的问题，减小了器件面积，提高了集成度。
为了解决上述问题，本发明提供了一种半导体结构，包括：
存储阵列单元，具有衬底、位于所述衬底上的存储阵列、以及位于所述存储阵列周边的第一键合区；
所述存储阵列包含多条字线、多条位线以及多条源极线，所述第一键合区包括第一衬底引出键合区、第一位线键合区、第一字线键合区以及第一源极线键合区；所述第一衬底引出键合区用于所述衬底的引出，所述第一位线键合区用于所述位线的引出，所述第一字线键合区用于所述字线的引出，所述第一源极线键合区用于所述源极线的引出。
进一步地，所述半导体结构还包括：***驱动电路单元，位于所述存储阵列单元的投影上方，包括位于所述***驱动电路单元中部的***驱动电路，以及位于所述***驱动电路周边的第二键合区；所述第二键合区包括第二衬底引 出键合区、第二位线键合区、第二字线键合区以及第二源极线键合区；所述***驱动电路包括供电电路、字线译码器电路、位线译码器电路、源极线译码器电路；
其中，所述第一衬底引出键合区与所述第二衬底引出键合区键合，以实现所述存储阵列中的衬底与所述供电电路的连接，所述第一位线键合区与所述第二位线键合区连接，以实现所述位线与所述位线译码器电路的连接，所述第一字线键合区与所述第二字线键合区键合，以实现所述字线与所述字线译码器电路的连接，所述第一源极线键合区与所述第二源极线键合区键合，以实现所述源极线与所述源极线译码器电路连接。
进一步地，所述***驱动电路还包括逻辑控制电路；用于对所述供电电路、字线译码器电路、位线译码器电路和所述源极线译码器电路进行控制。
进一步地，所述衬底包括三重P型掺杂阱及其***的深N型掺杂阱，所述第一衬底引出键合区包括多个位于所述存储阵列周围其中任一角隅处的第一衬底键合单元，所述第一衬底键合单元将所述三重P型掺杂阱以及所述深N型掺杂阱引出。
进一步地，所述第一位线键合区位于所述存储阵列周边至少其中一侧边。
进一步地，所述位线均与位于所述存储阵列周边的一侧侧边的第一位线键合区中的第一位线键合单元连接，所述第一位线键合单元交错设置。
进一步地，相邻的位线分别与位于所述存储阵列周边的两侧侧边的第一位线键合区中的第一位线键合单元连接。
进一步地，所述第一字线键合区位于所述存储阵列周边至少其中一侧边。
进一步地，所述第一源极线键合区位于所述存储阵列周边至少其中一侧边。
进一步地，所述多条源极线之间置一条虚拟源极线，每条所述源极线具有多个所述第一源极线键合单元。
进一步地，所述存储阵列为NOR型闪存架构。
进一步地，所述***电路还包括地址控制寻址单元、输入输出控制逻辑单元、算法控制逻辑单元、指令状态控制逻辑单元、静态随机存储器SRAM、冗余替换控制单元、页缓冲器、电荷泵、参考基准源、上电复位、管脚和静电放电ESD结构、电源管理单元、数模模数转换器、人工智能算法单元中的至少一种。
本发明的有益效果为：本发明提供了一种半导体结构，包括存储阵列单元，该存储阵列单元具有衬底、位于衬底上的存储阵列、以及位于存储阵列周边的第一键合区，该第一键合区包括第一衬底引出键合区、第一位线键合区、第一字线键合区以及第一源极线键合区，其中，第一衬底引出键合区用于衬底的引出，第一位线键合区用于位线的引出，第一字线键合区用于字线的引出，第一源极线键合区用于源极线的引出。本发明提供的半导体结构是将***驱动电路单元设置于存储阵列单元的投影上方，即与存储阵列单元分别设置，这样在形成存储阵列的存储阵列单元中不再设置***驱动电路，当然，在设置***驱动电路的***驱动电路单元中也不再设置存储阵列，因此利用晶圆键合技术将第一键合区与***驱动电路单元中相对应的第二键合区相键合，可以实现存储阵列单元中的衬底、多条字线、多条位线以及多条源极线与***驱动电路单元中相对应的驱动电路电连接，从而使得该半导体结构在垂直方向上呈三维结构，减小了其尺寸。
附图说明
为了更清楚地说明本发明的技术方案，下面将对根据本发明而成的各实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例所提供的半导体结构的正视结构示意图；
图2是本发明实施例所提供的存储阵列单元的结构示意图；
图3是本发明实施例所提供的***驱动电路单元的结构示意图；
图4是本发明实施例所提供的第一衬底引出键合区的结构示意图；
图5是本发明实施例所提供的第一位线键合区的结构示意图；
图6是本发明实施例所提供的第一位线键合区的另一结构示意图；
图7是本发明实施例所提供的第一字线键合区的结构示意图；
图8是本发明实施例所提供的第一源极线键合区的结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
需要说明的是，本发明附图中的厚度和形状不反映真实比例，目的只是示意说明本发明而成的各实施内容。
本发明针对现有的平面结构下的闪存，因其尺寸较大，而导致使用该闪存时有较大空间被占用的问题，本发明实施例用以解决该问题，并以NOR型闪存为例进行阐述说明。
请参阅图1，图1是根据本发明而成的实施例所提供的半导体结构的正视结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图1所示，该半导体结构100包括存储阵列单元110以及***驱动电路单元120，且***驱动电路单元120位于存储阵列单元110的投影上方。
请参阅图2，图2是根据本发明而成的实施例所提供的存储阵列单元110的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
该存储阵列单元110具有：衬底111、位于衬底111上的存储阵列112、以及位于存储阵列112周边的第一键合区113。如图2所示，在本实施例中，第一键合区113中的第一位线键合区1132、第一字线键合区1133与存储阵列112在投影方向上不重合。
在另一实施例中，第一键合区113中的第一位线键合区1132、第一字线键合区1133可以与存储阵列112在投影方向上部分重合。
其中，存储阵列112包含多条字线1121、多条位线1122、以及多条源极线(图中未示出)，第一键合区113包括第一衬底引出键合区1131、第一位线键合区1132、第一字线键合区1133以及第一源极线键合区1134，其中，第一衬底引出键合区1131可以用于衬底111的引出，第一位线键合区1132可以用 于位线1122的引出，第二字线键合区1133可以用于字线1121的引出，第一源极线键合区1134可以用于源极线的引出。
进一步地，第一衬底引出键合区1131可以位于存储阵列112周围其中任一角隅处，且至少分布在一角隅，至多分布在四角隅；第一位线键合区1132可以位于存储阵列112周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧；第一字线键合区1133可以位于存储阵列112周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧；第一源极线键合区1134可以位于存储阵列112周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧。
进一步地，该存储阵列112可以为一NOR型闪存架构。
请参阅图3，图3是根据本发明而成的实施例所提供的***驱动电路单元120的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图3所示，该***驱动电路单元120包括位于***驱动电路单元120中部的***驱动电路121，以及位于***驱动电路单元120周边的第二键合区122，用以连接***驱动电路121，并与第一键合区113对应键合连接，从而实现***驱动电路121和存储阵列112的连接。
其中，***驱动电路121包括供电电路1211、字线译码器电路1212、位线译码器电路1213以及源极线译码器电路1214，其中，供电电路1211用于为衬底111供电，字线译码器电路1212用于输出字线控制信号，位线译码器电路1213用于输出位线控制信号，源极线译码器电路1214用于输出源极控制信号。
进一步地，***驱动电路121还包括控制逻辑电路1215，该控制逻辑电路1215用以控制字线译码器电路1212、位线译码器电路1213和源极线译码器电路1214。
进一步地，所述***驱动电路121还包括地址控制寻址单元、输入输出控制逻辑单元、算法控制逻辑单元、指令状态控制逻辑单元、静态随机存储器SRAM、冗余替换控制单元、页缓冲器、电荷泵、参考基准源、上电复位、管脚和静电放电ESD结构、电源管理单元、数模模数转换器、人工智能算法单元中的至少一种。
进一步地，第二键合区122包括第二衬底引出键合区1221、第二位线键合区1222、第二字线键合区1223以及第二源极线键合区1224，其中第二衬底引出键合区1221用于供电电路1211的引出，第二位线键合区1222用于位线译码器电路1213的引出，第二字线键合区1223用于字线译码器电路1212的引出，第二源极线键合区1224用于源极线译码器电路1214的引出。
进一步地，第二衬底引出键合区1221可以位于***驱动电路121周围其中任一角隅处，且至少分布在一角隅，至多分布在四角隅；第二位线键合区1222可以位于***驱动电路121周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧；第二字线键合区1223可以位于***驱动电路121周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧；第二源极线键合区1224可以位于***驱动电路121周边至少其中一侧边，且可以分布在周边一侧，也可以分布在周边两侧。并且，第二键合区122的分布方式应与第一键合区113的分布方式相一致，以使二者能够对应键合连接。
进一步地，在使用晶圆键合技术对存储阵列单元110以及***驱动电路单元120进行键合时，第一键合区113与第二键合区122相对应的键合区对齐并进行连接。具体的，第一衬底引出键合区1131与第二衬底引出键合区1221键合，以实现存储阵列单元110中的衬底111与***驱动电路单元120中的供电电路1211电连接；第一位线键合区1132与第二位线键合区1222键合，以实现存储阵列单元110中的位线1122与***驱动电路单元120中的位线译码器电路1213电连接；第一字线键合区1133与第二字线键合区1223键合，以实现存储阵列单元110中的字线1121与***驱动电路单元120中的字线译码器电路1212电连接；第一源极线键合区1134与第二源极线键合区1224键合，以实现存储阵列单元110中的源极线与***驱动电路单元120中的源极线译码器电路1214实现电连接。
请参阅图4，图4是根据本发明而成的实施例所提供的第一衬底引出键合区1131的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图4所示，衬底111可以包括三重P型掺杂阱1111以及深N型掺杂阱1112，深N型掺杂阱1112可以位于三重P型掺杂阱1111的***，用于隔离不同的器件，三重P型掺杂阱1111的宽度可以用d1表示，深N型掺杂阱1112 的宽度可以用d2表示，三重P型掺杂阱1111和深N型掺杂阱1112之间的距离可以用d3表示，d1、d2和d3可以根据实际情况确定。
第一衬底引出键合区1131中可以包括多个由三重P型掺杂阱1111以及深N型掺杂阱1112引出且位于存储阵列112周围其中任一角隅处的第一衬底键合单元11311，用以与第二衬底引出键合区1221中连接至供电电路1211的第二衬底键合单元相键合连接，从而使衬底111被供电电路1211供应偏置电压。
对应于三重P型掺杂阱1111可以有一个第一衬底键合单元11311，也可以有多个第一衬底键合单元11311，图4中以三重P型掺杂阱1111连接有3个第一衬底键合单元11311为例；对应于深N型掺杂阱1112可以有一个第一衬底键合单元11311，也可以有多个第一衬底键合单元11311，图4中以深N型掺杂阱1112连接有5个第一衬底键合单元11311为例。
第一衬底键合单元11311可以位于第二衬底引出键合区1221的远离衬底的表面，第一衬底键合单元11311和衬底111之间可以利用纵向的金属线11312连接，第一衬底键合单元11311和衬底111之间可以形成介质层，金属线11312形成于贯穿介质层的通孔中。
衬底111中的掺杂阱也可以是其他掺杂类型。
第一位线键合区1132可以位于存储阵列112周边至少一侧边，每个第一位线键合区1132可以包括多个分别连接多条位线1122的第一位线键合单元11321，用以与第二位线键合区1222中连接至位线译码器电路1213的第二位线键合单元相键合连接。
请参阅图5，图5是根据本发明而成的实施例所提供的第一位线键合区1132的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
图5所示为在位线1122上方设置有第一位线键合区1132的场景，各个位线1122均与存储阵列112上方的第一位线键合单元11321连接。对于每个位线1122，可以设置有一个第一位线键合单元11321，也可以设置有多个第一位线键合单元11321。图5所示，每个位线1122可以连接有2个第一位线键合单元11321，2个第一位线键合单元11321之间的距离可以利用d6表示，其数值可以根据实际情况确定。
第一位线键合单元11321可以位于第一位线键合区1132的远离衬底111的表面，第一位线键合单元11321和位线1122之间可以利用纵向的金属线11322，或者纵向的金属线11322以及横向的引出线11323连接，纵向是指垂直于衬底的方向，横向是指平行于衬底的方向。具体的，第一位线键合单元11321和位线1122之间可以形成介质层，金属线11322可以形成于贯穿介质层的通孔中，引出线11323可以与位线1122形成于同一层。
参考图5所示，每个位线1122与其上的两个第一位线键合单元11321连接，第一位线键合单元11321可以交错设置，各个位线1122的引出线11323为不齐平的设置，从而避免第一位线键合单元11321对齐设置产生的距离过近的问题，在一定程度上减少发生短路的情况。
需要说明的是，图5是存储阵列单元110的俯视图，即使与第一条位线1122连接的第一位线键合单元11321在投影方向上与第二条位线1122有重叠，二者并未连接，其他位线1122和第一位线键合单元11321的位置关系类似。
此外，还可以同时在位线1122上方和下方均设置有第一位线键合区1132，则相邻位线1122分别与所述存储阵列112两侧的第一位线键合单元11321连接。此时，可以有一半的位线1122与上方的第一位线键合单元11321连接，另一半的位线1122与下方的第一位线键合单元11321连接。参考图6所示，是本发明实施例所提供的第一位线键合区的另一结构示意图，具体的，图6为在位线1122上方和下方均设置有第一位线键合区1132的场景下，位于位线上方的第一位线键合区的示意图，其中，第一位线键合单元11321只与部分位线1122连接，具体的，第一、第三、第五…条位线1122通过引出线11323与位于位线1122上方的第一位线键合单元11321连接，而第二、第四、第六…条位线1122并不与位于位线1122上方的第一位线键合单元11321连接，而是与位于位线1122下方的第一位线键合单元11321连接(图未示出)。如此使得连接的相邻第一位线键合单元11321间隙较大，防止发生短路。
第一字线键合区1133可以位于存储阵列112周边至少其中一侧边，每个第一字线键合区1133可以包括多个分别连接多条字线1121的第一字线键合单元11331，用以与第二字线键合区1223中连接至字线译码器电路1212的第二字线键合单元相键合连接。
请参阅图7，图7是根据本发明而成的实施例所提供的第一字线键合区 1133的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
图7所示为仅在字线1121右侧设置有第一字线键合单元11331的场景，则所有的字线1121均需要与右边的第一字线键合单元11331连接。对于每个字线1121，可以设置有一个第一字线键合单元11331，也可以设置有多个第一字线键合单元11331。参考图7所示，每个字线1121可以连接有2个第一字线键合单元11331。
第一字线键合单元11331可以位于第一字线键合区1133的远离衬底111的表面，第一字线键合单元11331和字线1121之间可以利用纵向的金属线11332，或者纵向的金属线11332和横向的引出线11333连接。具体的，第一字线键合单元11331和字线1121之间可以形成介质层，金属线11332可以形成于贯穿介质层的通孔中，引出线11333可以与字线1121形成于同一层。
参考图7所示，每个字线1121与其上的两个第一字线键合单元11331连接，所述第一字线键合单元11331可以交错设置，各个字线1121的引出线11333可以为不齐平的设置，从而避免第一字线键合单元11331对齐设置产生的距离过近的问题，在一定程度上减少发生短路的情况。
参考图7所示，从上向下第二条字线1121连接的第一字线键合单元11331可以位于第一条字线1121的右侧，第三条字线1121和第四条字线1121连接的第一字线键合单元11331未示出，在纵向上对其的两个第一字线键合单元11331的边缘距离可以利用d9表示，其数值可以根据实际情况确定。
需要说明的是，图7是存储阵列单元110的俯视图，即使与第一条字线连接的第一字线键合单元11331在投影方向上与第二条字线1121有重叠，二者并未连接，其他字线1121和第一字线键合单元11331的位置关系类似。
另外，在字线1121两侧均设置有第一字线键合单元11331时，可以有一半的字线1121在右侧连接出去，而另一半的字线1121在左侧连接出去，其连接方式可以参考位线1122的说明，在此不做图示及其他说明。
第一源极线键合区1134可以位于存储阵列112周边至少其中一侧边，每个第一源极线键合区1134可以包括多个分别连接多条源极线1123的第一源极线键合单元11341，用以与第二源极线键合区1224中连接至源极线译码器电路1214的第二源极线键合单元相键合连接。
请参阅图8，图8是根据本发明而成的实施例所提供的第一源极线键合区1134的结构示意图，从图中可以很直观的看到根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
图8所示，为在存储阵列112上方设置有第一源极线键合单元11341的场景，各个源极线1123均与存储阵列112上方的第一源极线键合单元11341连接。对于每个源极线1123，可以设置有一个第一源极线键合单元11341，也可以设置有多个第一源极线键合单元11341，例如两个。
第一源极线键合单元11341可以位于第一源极线键合区1134的远离衬底111的表面，第一源极线键合单元11341和源极线1123之间可以利用纵向的金属线11342，或者纵向的金属线11342以及横向的引出线11343连接。具体的，第一源极线键合单元11341和源极线1123之间可以形成介质层，金属线11342可以形成于贯穿介质层的通孔中，引出线11343可以与源极线1123形成于同一层。
参考图8所示，每个源极线1123与其上的两个第一源极线键合单元11341连接，第一源极线键合单元11341可以交错设置，各个源极线1123的引出线11343为不齐平的设置，从而避免第一源极线键合单元11341对齐设置产生的距离过近的问题，在一定程度上减少发生短路的情况。
参考图8所示，从上向下第二条源极线1123连接的第一源极线键合单元11341可以位于与第一条源极线1123连接的第一源极线键合单元11341的右侧，第三条源极线1123和第四条源极线1123连接的第一源极线键合单元11341未示出。
需要说明的是，图8是存储阵列单元110的俯视图，即使与第一条源极线1123连接的第一源极线键合单元11341在投影方向上与第二条源极线1123有重叠，二者并未连接，其他源极线1123和第一源极线键合单元11341的位置关系类似。
另一实施例中，第一源极线键合区1134也可以设置于存储阵列112上方和下方，有一半的源极线1123与上方的第一源极线键合单元11341连接，另一半的源极线1123与下方的第一源极线键合单元11341连接(图中未示出)。
第一源极线键合区1134可以与第一位线键合区1132相邻，也可以与第一字线键合区1133相邻，可以设置于字线1121的端部方向或位线1122的端部 方向。
进一步地，该多条源极线1123每两条之间置一条虚拟源极线11231的布局，且每条源极线1123具有多个第一源极线键合单元11341。
区别于现有技术，本发明提供了一种半导体结构，包括存储阵列单元，该存储阵列单元具有衬底、位于衬底上的存储阵列、以及位于存储阵列周边的第一键合区，该第一键合区包括第一衬底引出键合区、第一位线键合区、第一字线键合区以及第一源极线键合区，其中，第一衬底引出键合区用于衬底的引出，第一位线键合区用于位线的引出，第一字线键合区用于字线的引出，第一源极线键合区用于源极线的引出。本发明提供的半导体结构是将***驱动电路单元设置于存储阵列单元的投影上方，即与存储阵列单元分别设置，这样在形成存储阵列的存储阵列单元中不再设置***驱动电路，当然，在设置***驱动电路的***驱动电路单元中也不再设置存储阵列，因此利用晶圆键合技术将第一键合区与***驱动电路单元中相对应的第二键合区相键合，可以实现存储阵列单元中的衬底、多条字线、多条位线以及多条源极线与***驱动电路单元中相对应的驱动电路的电连接，从而使得该半导体结构在垂直方向上呈三维结构，减小了其尺寸。
除上述实施例外，本发明还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本发明要求的保护范围。
综上所述，虽然本发明已将优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种半导体结构，其特征在于，包括：
    存储阵列单元，具有衬底、位于所述衬底上的存储阵列、以及位于所述存储阵列周边的第一键合区；
    所述存储阵列包含多条字线、多条位线以及多条源极线，所述第一键合区包括第一衬底引出键合区、第一位线键合区、第一字线键合区以及第一源极线键合区；所述第一衬底引出键合区用于所述衬底的引出，所述第一位线键合区用于所述位线的引出，所述第一字线键合区用于所述字线的引出，所述第一源极线键合区用于所述源极线的引出。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：***驱动电路单元，位于所述存储阵列单元的投影上方，包括位于所述***驱动电路单元中部的***驱动电路，以及位于所述***驱动电路周边的第二键合区；所述第二键合区包括第二衬底引出键合区、第二位线键合区、第二字线键合区以及第二源极线键合区；所述***驱动电路包括供电电路、字线译码器电路、位线译码器电路、源极线译码器电路；
    其中，所述第一衬底引出键合区与所述第二衬底引出键合区键合，以实现所述衬底与所述供电电路的电连接；所述第一位线键合区与所述第二位线键合区键合，以实现所述位线与所述位线译码器电路的电连接；所述第一字线键合区与所述第二字线键合区键合，以实现所述字线与所述字线译码器电路的电连接；所述第一源极线键合区与所述第二源极线键合区键合，以实现所述源极线与所述源极线译码器电路电连接。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述***电路还包括：逻辑控制电路；用于对所述供电电路、字线译码器电路、位线译码器电路和所述源极线译码器电路进行控制。
  4. 根据权利要求2或3所述的半导体结构，其特征在于，所述***电路还包括地址控制寻址单元、输入输出控制逻辑单元、算法控制逻辑单元、指令状态控制逻辑单元、静态随机存储器SRAM、冗余替换控制单元、页缓冲器、电荷泵、参考基准源、上电复位、管脚和静电放电ESD结构、电源管理单元、数模模数转换器、人工智能算法单元中的至少一种。
  5. 根据权利要求1-4任意一项所述的半导体结构，其特征在于，所述衬 底包括三重P型掺杂阱及其***的深N型掺杂阱，所述第一衬底引出键合区包括多个位于所述存储阵列周围其中任一角隅处的第一衬底键合单元，所述第一衬底键合单元将所述三重P型掺杂阱以及所述深N型掺杂阱引出。
  6. 根据权利要求1-5任意一项所述的半导体结构，其特征在于，所述第一位线键合区位于所述存储阵列周边至少其中一侧边。
  7. 根据权利要求6所述的半导体结构，其特征在于，所述位线均与位于所述存储阵列周边的一侧侧边的第一位线键合区中的第一位线键合单元连接，所述第一位线键合单元交错设置。
  8. 根据权利要求6所述的半导体结构，其特征在于，相邻的位线分别与位于所述存储阵列周边的两侧侧边的第一位线键合区中的第一位线键合单元连接。
  9. 根据权利要求1-8任意一项所述的半导体结构，其特征在于，所述第一字线键合区位于所述存储阵列周边至少其中一侧边。
  10. 根据权利要求1-9任意一项所述的半导体结构，其特征在于，所述第一源极线键合区位于所述存储阵列周边至少其中一侧边。
  11. 根据权利要求10所述的半导体结构，其特征在于，所述多条源极线之间置一条虚拟源极线，每条所述源极线具有多个所述第一源极线键合单元。
  12. 根据权利要求1-11任意一项所述的半导体结构，其特征在于，所述存储阵列为NOR型闪存架构。
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