WO2021217718A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2021217718A1
WO2021217718A1 PCT/CN2020/089736 CN2020089736W WO2021217718A1 WO 2021217718 A1 WO2021217718 A1 WO 2021217718A1 CN 2020089736 W CN2020089736 W CN 2020089736W WO 2021217718 A1 WO2021217718 A1 WO 2021217718A1
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Prior art keywords
conductive layer
area
layer
conductive
alloy
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PCT/CN2020/089736
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English (en)
French (fr)
Inventor
张鑫
胡小波
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Tcl华星光电技术有限公司
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Priority to US16/954,575 priority Critical patent/US11271021B2/en
Publication of WO2021217718A1 publication Critical patent/WO2021217718A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • the conventional sub-millimeter light emitting diode backlight module includes: a first metal pattern layer formed on a substrate 100, the first metal pattern layer includes a first conductive member 1011 and a gate electrode 1012; and a gate electrode covering the first metal pattern layer and the substrate 100
  • the second conductive member 1041 is electrically connected to the first conductive member 1011; the passivation layer 105 covering the second metal pattern layer and the gate insulating layer 102 and exposing the conductive electrode 1042; formed on the passivation layer 105
  • the indium tin oxide layer 106 is electrically connected to the
  • the second metal pattern layer includes a copper layer, and the indium tin oxide layer 106 is used to prevent the copper layer of the second conductive member 1041 from being oxidized.
  • the conventional sub-millimeter light-emitting diode backlight module has problems with numerous manufacturing processes.
  • the traditional technology uses the second metal pattern layer to simultaneously form a conductive structure for bonding the flip chip film and a conductive electrode for bonding the sub-millimeter light-emitting diode, and the second metal pattern layer includes copper The MoTiNi alloy layer and the MoTiNi alloy layer on the copper layer.
  • the MoTiNi alloy layer is far away from the substrate, and the copper layer is close to the substrate.
  • the MoTiNi alloy layer is used to prevent oxidation of the copper layer, so as to omit the production of the indium tin oxide layer, thereby simplifying the manufacturing process.
  • the conductive electrode in the second metal pattern layer is difficult to form a solid solution alloy with the MoTiNi alloy layer and the solder paste, and the adhesion of the solder paste on the MoTiNi alloy layer is poor, resulting in the use of solder paste to bind the sub-millimeter light-emitting diode to the conductive electrode When up, the sub-millimeter light-emitting diodes cannot be firmly bound.
  • the purpose of this application is to provide an array substrate, a manufacturing method thereof, and a display device.
  • the manufacturing method has simplified manufacturing process, improved oxidation resistance of binding pins, and improved adhesion between connectors and conductive electrodes to make light-emitting elements firmer The advantage of grounding on the array substrate.
  • the present application provides a manufacturing method of an array substrate, the method includes the following steps:
  • a first conductive layer and a second conductive layer are formed in both the first area and the second area of the substrate to form binding pins located in the first area and used for electrical connection with the driving chip, and the second conductive layer is located in A side of the first conductive layer away from the substrate, and an interval between the first area and the second area;
  • the adhesion between the first conductive layer and the connector is greater than the adhesion between the second conductive layer and the connector, and the second conductive layer is used to prevent oxidation of the first conductive layer.
  • the method before removing the second conductive layer in the second region, the method further includes:
  • the method further includes:
  • the insulating layer in the first area is etched by using a first etching gas to expose the binding pins.
  • the rate at which the first etching gas etches the insulating layer is greater than that of the first etching gas.
  • the velocity of the first conductive layer is etched by using a first etching gas to expose the binding pins.
  • the first etching gas includes NF 3 .
  • the first etching gas further includes an inert gas.
  • the first etching gas is a mixture of NF 3 and He.
  • the material for preparing the first conductive layer is selected from Cu or Cu alloy
  • the material for preparing the second conductive layer is selected from Mo or Mo alloy
  • the material for preparing the connecting member is selected from Tin or tin alloy.
  • the material of the second conductive layer is MoTiNi alloy.
  • the removing the second conductive layer of the second region includes:
  • the second conductive layer in the second region is etched using a second etching gas including BCl 3.
  • the second etching gas further includes Cl 2 .
  • a substrate the substrate has a first area and a second area, and there is an interval between the first area and the second area;
  • the binding pin is used to be electrically connected to the driver chip and located in the first area of the substrate, the binding pin includes a first conductive layer and a second conductive layer, and the second conductive layer is located in the first area of the substrate. The side of the first conductive layer away from the substrate; and
  • a conductive electrode for connecting with a light-emitting element through a connector and located in the second area of the substrate, the conductive electrode including the first conductive layer;
  • the adhesion between the first conductive layer and the connector is greater than the adhesion between the second conductive layer and the connector, and the second conductive layer is used to prevent oxidation of the first conductive layer.
  • the material for preparing the first conductive layer is selected from Cu or Cu alloy
  • the material for preparing the second conductive layer is selected from Mo or Mo alloy
  • the material for preparing the connecting member is selected from tin or tin alloy.
  • the material for preparing the second conductive layer is selected from MoTiNi alloy or MoNbTa alloy.
  • a display device the display device includes an array substrate, and the array substrate includes:
  • a substrate the substrate has a first area and a second area, and there is an interval between the first area and the second area;
  • the binding pin is used to be electrically connected to the driver chip and located in the first area of the substrate, the binding pin includes a first conductive layer and a second conductive layer, and the second conductive layer is located in the first area of the substrate. The side of the first conductive layer away from the substrate; and
  • a conductive electrode for connecting with a light-emitting element through a connector and located in the second area of the substrate, the conductive electrode including the first conductive layer;
  • the adhesion between the first conductive layer and the connector is greater than the adhesion between the second conductive layer and the connector, and the second conductive layer is used to prevent oxidation of the first conductive layer.
  • the material of the first conductive layer is selected from Cu or Cu alloy
  • the material of the second conductive layer is selected from Mo or Mo alloy
  • the material of the connector is selected from tin or tin. alloy.
  • the material for preparing the second conductive layer is selected from MoTiNi alloy or MoNbTa alloy.
  • both the binding pin and the conductive electrode include a third conductive layer, and the first conductive layer is located between the second conductive layer and the third conductive layer.
  • the third conductive layer is a MoTiNi alloy layer.
  • the present application provides an array substrate, a manufacturing method thereof, and a display device.
  • the manufacturing method includes: forming a first conductive layer and a second conductive layer in both a first region and a second region of the substrate, and forming a first conductive layer and a second conductive layer located in the first region and used for The binding pin electrically connected to the driving chip, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the first area and the second area are spaced; the second conductive layer in the second area is removed to form the second conductive layer.
  • the conductive layer is oxidized. Since the binding pin and the conductive electrode are made by patterning two different conductive layers compared with the traditional technology, the binding pin and the conductive electrode of the present application are obtained by patterning the first conductive layer and the second conductive layer that are stacked, The manufacturing method further simplifies the manufacturing process, and the second conductive layer of the binding pin plays a role in preventing the oxidation of the first conductive layer, and the oxidation resistance of the binding pin is improved.
  • the first conductive layer of the conductive electrode and the connector have good The adhesion force between the connecting member and the conductive electrode is improved so that the light-emitting element is firmly fixed on the array substrate.
  • Figure 1 is a schematic diagram of a conventional sub-millimeter light-emitting diode backlight module
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the application
  • 3A-3H are schematic diagrams of the process of manufacturing the array substrate according to the embodiment of the present application.
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the application.
  • the manufacturing method of the array substrate includes the following steps:
  • a first conductive layer and a second conductive layer are formed in both the first area and the second area of the substrate to form binding pins located in the first area and used for electrical connection with the driving chip, and the second conductive layer is located in the first area.
  • the conductive layer is away from the side of the substrate, and the first area and the second area are spaced apart.
  • S102 Remove the second conductive layer in the second area to form a conductive electrode located in the second area and used for electrically connecting with the light-emitting element through the connector, wherein the adhesion between the first conductive layer and the connector is greater than that between the second conductive layer and the second conductive layer.
  • the adhesion of the connecting piece, and the second conductive layer is used to prevent oxidation of the first conductive layer.
  • the method before removing the second conductive layer in the second region, the method further includes:
  • the method further includes:
  • the first etching gas is used to etch the insulating layer in the first area to expose the binding pins.
  • the rate of the first etching gas to etch the insulating layer is greater than the rate of the first etching gas to etch the first conductive layer.
  • the rate at which the first etching gas etches the insulating layer is greater than the rate at which the first etching gas etches the first conductive layer to increase the first etching gas.
  • the etching selection ratio of an etching gas to the first conductive layer and the insulating layer avoids unnecessary etching of the first conductive layer during the etching of the insulating layer.
  • the first etching gas includes NF 3 .
  • the mixture of gas SF 6 and Cl 2 will cause corrosion when the first conductive layer is copper or copper alloy.
  • NF 3 will not interact with copper.
  • the reaction functions to protect the copper and prevent the first conductive layer from being oxidized while etching the insulating layer.
  • the first etching gas may also include an inert gas, which is used as a carrier gas, such as inert gas such as He, Ar, etc., to control the morphology of the grooves or openings formed on the etching insulating layer.
  • the first etching gas is a mixture of NF 3 and He.
  • the preparation material of the first conductive layer is selected from Cu or Cu alloy, which is beneficial to improve the conductivity of the binding pins and the conductive electrode, and Cu and Sn paste can form a solid solution alloy, and there is Good adhesion helps light-emitting elements (such as sub-millimeter light-emitting diode Mini-LED and micro-light-emitting diode Micro-LED) to be firmly bound to the conductive electrode.
  • copper alloys include copper-molybdenum alloys, copper-silver alloys, copper-titanium alloys, and the like.
  • the preparation material of the first conductive layer is copper.
  • the material of the second conductive layer is selected from Mo or Mo alloy, which can prevent the first conductive layer from being oxidized and at the same time block the diffusion of the first conductive layer.
  • the material of the second conductive layer is MoTiNi alloy or MoNbTa alloy
  • the oxidation resistance of the second conductive layer is better than that of Mo, which can prevent the bonding pins from oxidizing.
  • Mo and Mo alloys it is difficult for Mo and Mo alloys to form solid solution alloys with tin, resulting in poor adhesion between Mo and Mo alloys and tin.
  • the material for the connection member is selected from tin or tin alloy, and the solder paste is dotted on the conductive electrode, and the light-emitting element is arranged on the solder paste, so that the light-emitting element is bound to the conductive electrode.
  • removing the second conductive layer in the second region includes: etching the second conductive layer in the second region using a second etching gas including BCl3.
  • a second etching gas including BCl3 When the second conductive layer is a MoTiNi alloy, the inventor found through a lot of experiments that, because MoTiNi alloy has better oxidation resistance and corrosion resistance than traditional Mo, it is difficult to etch MoTiNi alloy, and traditional etching gas such as SF 6. Etching gases such as NF 3 and CF 4 cannot etch MoTiNi alloy, but after a lot of experimental exploration, it is found that BCl 3 can etch MoTiNi alloy.
  • the second etching gas may also include an accelerating gas, such as Cl 2 , to play a role in accelerating etching.
  • a manufacturing method of an array substrate includes the following steps:
  • the substrate is a glass substrate.
  • the substrate 200 defines a first area 200a, a second area 200b, and a third area 200c.
  • the third area 200c is located between the first area 200a and the second area 200b, and the first area 200a and the third area 200c The interval between the third area 200c and the second area 200b, and the interval between the first area 200a and the second area 200b, where the interval refers to an area with an interval.
  • the first area 200a is used to set bonding pins 2044, the bonding pins 2044 and the flip chip film are connected by anisotropic conductive glue, or the bonding pins 2044 and the driving chip are connected by anisotropic conductive glue.
  • the second area 200b is used for disposing the conductive electrode 2047 and the light emitting element 208, and the conductive electrode 2047 and the light emitting element 208 are connected by a connector.
  • the binding pin 2044 and the conductive electrode 2047 are electrically insulated.
  • the third region 200c is used to set thin film transistors, which are used to drive the light emitting element 208 and control the light emitting state of the light emitting element 208.
  • the thin film transistor includes a gate 2011, a gate insulating layer, an active layer, and source and drain electrodes.
  • the entire surface of the first metal layer is formed on the substrate 200, and the entire surface of the photoresist layer is formed on the first metal layer.
  • the photoresist layer is subjected to photomask exposure treatment and developer development treatment, and the non-photoresist layer is etched.
  • the remaining photoresist layer is removed to obtain the first metal pattern layer, as shown in FIG. 3A.
  • the first metal pattern layer includes the gate 2011 located in the third region 200c, and may also include a first conductive member (not shown) located in the first region 200a.
  • the first conductive member passes through the first insulating layer 202 formed subsequently.
  • the via hole on the upper side is electrically connected to the binding pin.
  • the first metal layer includes a molybdenum layer and a copper layer sequentially stacked on the substrate 200.
  • the thickness of the molybdenum layer is 300 angstroms to 500 angstroms, and the thickness of the copper layer is 4000 angstroms to 6000 angstroms.
  • S202 forming a first insulating layer 202 covering the substrate 200 and the first metal pattern layer.
  • first insulating layer 202 covering the gate 2011, the first conductive member, and the substrate 200, as shown in FIG. 3B.
  • the first insulating layer 202 is a gate insulating layer.
  • the material of the first insulating layer 202 is silicon nitride or/and silicon oxide.
  • the thickness of the first insulating layer 202 is 800 angstroms to 6000 angstroms.
  • S203 A semiconductor layer and a second metal layer are sequentially formed on the first insulating layer 202, a patterning process is used to form bonding pins in the first region 200a, and an active layer and source and drain electrodes are formed in the third region 200c.
  • the region 200b forms the second conductive layer and the first conductive layer.
  • the second metal layer includes a first conductive layer 2041, a second conductive layer 2042, and a third conductive layer 2043.
  • the first conductive layer 2041 is located between the second conductive layer 2042 and the third conductive layer 2043, and the third conductive layer 2043 Located close to the substrate 200, the second conductive layer 2042 is located on the side of the first conductive layer 2041 away from the substrate 200.
  • the first conductive layer 2041 is a copper layer with a thickness of 3000-6000 angstroms; the second conductive layer 2042 is a MoTiNi alloy layer with a thickness of 300-500 angstroms; the third conductive layer 2043 is a MoTiNi alloy layer with a thickness of 300 angstroms- 500 angstroms.
  • a photoresist layer is formed on the surface of the second metal layer away from the substrate 200. After the photoresist layer is exposed to the first halftone grayscale mask and developed by the developer, the photoresist is completely formed in the first area 200a and the second area 200b. The remaining layer is formed, and a complete photoresist retention layer is formed in the region where the source and drain electrodes are to be formed in the third region 200c, the photoresist layer between the first region 200a and the third region 200c is completely removed, and the second region 200b and the second region 200b and the second region 200b are completely removed.
  • the photoresist layer between the three regions 200c, the region between the region where the source electrode is to be formed in the third region 200c and the region where the drain electrode is to be formed in the third region 200c forms a photoresist semi-reserved layer.
  • the second metal layer between the first area 200a and the third area 200c, and between the second area 200b and the third area 200c, which is not covered by the photoresist layer, is etched by a wet etching process, and the first metal layer is etched by a dry etching process.
  • the drained second metal layer is removed, the remaining photoresist layer is removed, the bonding pins 2044 are formed in the first area 200a, and the active layer and source and drain electrodes (2045, 2046) are formed in the third area 200c.
  • the second region 200b retains the semiconductor layer and the second metal layer, as shown in FIG. 3C.
  • the first area 200a is used for bonding pins 2044 that are electrically connected to the driving chip.
  • the second insulating layer 205 is formed by chemical deposition.
  • the second insulating layer 205 is a passivation layer.
  • the preparation material of the second insulating layer 205 may be a silicon nitride layer, a silicon oxide layer, or a stack of silicon nitride and silicon oxide layers.
  • the thickness of the second insulating layer 205 is 3000 angstroms to 6000 angstroms.
  • a photoresist layer on the entire surface is formed on the second insulating layer 205, and the photoresist layer is exposed by a second halftone gray-scale mask.
  • the first area 200a is defined as a semi-reserved photoresist area
  • the second area 200b is a light
  • the area between the first area 200a and the second area 200b is the area where the photoresist is completely reserved.
  • the exposed photoresist is processed by the developer, and the photoresist layer in the second area 200b is removed.
  • the first area The photoresist layer of 200a remains, the photoresist layer of the region between the first region 200a and the second region 200b is completely retained, and the thickness of the photoresist layer of the first region 200a is less than that of the region between the first region 200a and the second region 200b Thickness of photoresist layer.
  • the second insulating layer 205 of the area except the second area 200b is covered by the patterned photoresist layer 206, using a mixture of SF6 and Cl2, NF3 and One of the mixture of He and the mixture of NF3 and Cl2 etches the second insulating layer 205 of the second region 200b; then a second etching gas including BCl3 is used to etch the second conductive layer 2042 of the second region 200b, the second etching gas Cl2 is also included to promote the BCl3 etching rate of the second conductive layer 2042, remove the second conductive layer 2042 in the second region 200b, and retain the first conductive layer 2041 and the third conductive layer 2043 in the second region 200b, and the second region 200b
  • the first conductive layer 2041 and the third conductive layer 2043 constitute a conductive electrode 2047.
  • S207 Remove the patterned photoresist layer 206 of the first region 200a on the second insulating layer 205, and etch the second insulating layer 205 of the first region 200a with the first etching gas to expose the bonding pins 2044 and remove the remaining
  • the patterned photoresist layer 206 is shown in FIG. 3G.
  • the rate at which the first etching gas etches the second insulating layer 205 is greater than the rate at which the first etching gas etches the first conductive layer 2041.
  • the first etching gas is a mixture of NF3 and He. When the mixture of NF3 and He etches the second insulating layer 205 of the first region 200a, it does not react with the copper layer and protects the conductive electrode 2047 including the copper layer.
  • S208 Use a solder paste 207 to fix the light-emitting element 208 on the conductive electrode 2047, and use an anisotropic conductive adhesive to bind the flip-chip film 209 to the bonding pin 2044, as shown in FIG. 3H.
  • the light-emitting element 208 is a sub-millimeter light-emitting diode.
  • the chip on film 209 includes a flexible film and a driving chip arranged on the flexible film, and the driving chip is used for outputting driving signals.
  • the present application also provides an array substrate, which includes:
  • a substrate the substrate has a first area, a second area, and a third area, the first area and the second area are spaced apart, and the third area is located between the first area and the second area;
  • the binding pin is used to electrically connect to the driver chip and is located in the first area of the substrate.
  • the binding pin includes a first conductive layer and a second conductive layer.
  • the second conductive layer is located on the side of the first conductive layer away from the substrate ;
  • the conductive electrode is used to connect to the light-emitting element through the connector and is located in the second area of the substrate, the conductive electrode includes the first conductive layer;
  • a thin film transistor located in the third area and used to drive the light-emitting element to emit light
  • the adhesion between the first conductive layer and the connector is greater than the adhesion between the second conductive layer and the connector, and the second conductive layer is used to prevent oxidation of the first conductive layer.
  • the material of the first conductive layer is selected from Cu or Cu alloy
  • the material of the second conductive layer is selected from Mo or Mo alloy
  • the material of the connector is selected from tin or tin alloy.
  • the material for preparing the second conductive layer is selected from MoTiNi alloy or MoNbTa alloy.
  • the third area is further provided with a light-shielding layer
  • the light-shielding layer is provided corresponding to the thin film transistor to shield the thin film transistor
  • the light-shielding layer may be a white ink or a black photoresist layer.
  • the bonding pins and conductive electrodes of the array substrate of the present application are formed by patterning the second metal layer.
  • the array substrate of the present application has the advantages of simplifying the manufacturing process.
  • the binding pin includes a second conductive layer and a first conductive layer.
  • the second conductive layer is used to prevent oxidation of the first conductive layer and avoid oxidation of the binding pin.
  • the conductive electrode includes the first conductive layer and the first conductive layer. It has good adhesion with the connecting piece, so that the light-emitting element is firmly fixed on the conductive electrode.
  • the present application also provides a display device, the display device includes a backlight module, the backlight module includes the above-mentioned array substrate, or the display device includes a display panel, and the display panel includes the above-mentioned array substrate.

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Abstract

一种阵列基板及其制造方法、显示装置，方法包括：于基板（200）的第一区域（200a）和第二区域（200b）均形成第一导电层（2041）和第二导电层（2042），形成位于第一区域（200a）且用于与驱动芯片电连接的绑定引脚（2044），第二导电层（2042）位于第一导电层（2041）远离基板（200）的一侧；去除第二区域（200b）的第二导电层（2042），形成位于第二区域（200b）且用于通过连接件（207）与发光元件（208）电连接的导电电极（2047）。

Description

阵列基板及其制造方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
 背景技术
如图1所示，其为传统亚毫米发光二极管（Mini Light Emitting Diode，Mini-LED）背光模组的示意图。传统亚毫米发光二极管背光模组包括：形成于基板100上的第一金属图案层，第一金属图案层包括第一导电件1011以及栅极1012；覆盖第一金属图案层以及基板100的栅极绝缘层102；形成于栅极绝缘层102上的有源层103；形成于有源层103远离基板100一侧的第二金属图案层，第二金属图案层包括第二导电件1041、源漏电极以及导电电极1042，第二导电件1041与第一导电件1011电连接；覆盖第二金属图案层以及栅极绝缘层102且使导电电极1042显露的钝化层105；形成于钝化层105上且通过钝化层105上过孔与第二导电件1041电连接的氧化铟锡层106；以及亚毫米发光二极管107。其中，第二金属图案层包括铜层，氧化铟锡层106用于避免第二导电件1041的铜层被氧化。然而，传统亚毫米发光二极管背光模组存在制程繁多的问题。
为了简化传统亚毫米发光二极管背光模组的制程，传统技术利用第二金属图案层同时形成绑定覆晶薄膜的导电结构以及绑定亚毫米发光二极管的导电电极，且第二金属图案层包括铜层以及位于铜层上的MoTiNi合金层，MoTiNi合金层远离基板，铜层靠近基板，MoTiNi合金层用于防止铜层氧化，以省去氧化铟锡层的制作，从而简化制程。然而，第二金属图案层中的导电电极由于MoTiNi合金层与锡膏难以形成固溶合金，锡膏在MoTiNi合金层上的附着力差，导致采用锡膏将亚毫米发光二极管绑定于导电电极上时，亚毫米发光二极管无法牢固地绑定。
因此，有必要提出一种技术方案以解决MoTiNi合金层与锡膏附着力差导致亚毫米发光二极管绑定不牢固且用于绑定覆晶薄膜的导电结构最外层为铜层时易氧化的问题。
 技术问题
本申请的目的在于提供一种阵列基板及其制造方法、显示装置，制造方法具有简化制程，提高绑定引脚的抗氧化性，且提高连接件与导电电极之间附着力以使发光元件牢固地固定于阵列基板上的优点。
 技术解决方案
为实现上述目的，本申请提供一种阵列基板的制造方法，所述方法包括如下步骤：
于基板的第一区域和第二区域均形成第一导电层和第二导电层，形成位于所述第一区域且用于与驱动芯片电连接的绑定引脚，所述第二导电层位于所述第一导电层远离所述基板的一侧，所述第一区域和所述第二区域之间间隔；
去除所述第二区域的所述第二导电层，形成位于所述第二区域且用于通过连接件与发光元件电连接的导电电极；
其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
在上述阵列基板的制造方法中，去除所述第二区域的所述第二导电层之前，所述方法还包括：
形成覆盖所述第一区域和所述第二区域的所述第二导电层的绝缘层；
去除所述第二区域的所述第二导电层之后，所述方法还包括：
利用第一蚀刻气体蚀刻所述第一区域的所述绝缘层，以使所述绑定引脚显露，所述第一蚀刻气体蚀刻所述绝缘层的速率大于所述第一蚀刻气体蚀刻所述第一导电层的速率。
在上述阵列基板的制造方法中，所述第一蚀刻气体包括NF 3。
在上述阵列基板的制造方法中，第一蚀刻气体还包括惰性气体。
在上述阵列基板的制造方法中，所述第一蚀刻气体为NF 3以及He的混合物。
在上述阵列基板的制造方法中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
在上述阵列基板的制造方法中，所述第二导电层的制备材料为MoTiNi合金。
在上述阵列基板的制造方法中，所述去除所述第二区域的所述第二导电层包括：
采用包括BCl 3的第二蚀刻气体蚀刻所述第二区域的所述第二导电层。
在上述阵列基板的制造方法中，第二蚀刻气体还包括Cl 2。
一种阵列基板，所述阵列基板包括：
基板，所述基板具有第一区域和第二区域，所述第一区域和所述第二区域之间间隔；
绑定引脚，用于与驱动芯片电性连接且位于所述基板的所述第一区域，所述绑定引脚包括第一导电层以及第二导电层，所述第二导电层位于所述第一导电层远离所述基板的一侧；以及
导电电极，用于通过连接件与发光元件连接且位于所述基板的所述第二区域，所述导电电极包括所述第一导电层；
其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
在上述阵列基板中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
在上述阵列基板中，所述第二导电层的制备材料选自MoTiNi合金或MoNbTa合金。
一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括：
基板，所述基板具有第一区域和第二区域，所述第一区域和所述第二区域之间间隔；
绑定引脚，用于与驱动芯片电性连接且位于所述基板的所述第一区域，所述绑定引脚包括第一导电层以及第二导电层，所述第二导电层位于所述第一导电层远离所述基板的一侧；以及
导电电极，用于通过连接件与发光元件连接且位于所述基板的所述第二区域，所述导电电极包括所述第一导电层；
其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
在上述显示装置中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
在上述显示装置中，所述第二导电层的制备材料选自MoTiNi合金或MoNbTa合金。
在上述显示装置中，所述绑定引脚以及所述导电电极均包括第三导电层，所述第一导电层位于所述第二导电层和所述第三导电层之间。
在上述显示装置中，第三导电层为MoTiNi合金层。
 有益效果
本申请提供一种阵列基板及其制造方法、显示装置，制造方法包括：于基板的第一区域和第二区域均形成第一导电层和第二导电层，形成位于第一区域且用于与驱动芯片电连接的绑定引脚，第二导电层位于第一导电层远离基板的一侧，第一区域和第二区域之间间隔；去除第二区域的第二导电层，形成位于第二区域且用于通过连接件与发光元件电连接的导电电极；其中，第一导电层与连接件的附着力大于第二导电层与连接件的附着力，且第二导电层用于防止第一导电层氧化。由于相对于传统技术绑定引脚以及导电电极通过两个不同导电层图案化制得，本申请绑定引脚以及导电电极基于叠置的第一导电层和第二导电层图案化后得到，制造方法进一步地简化制程，且绑定引脚的第二导电层起到防止第一导电层的氧化的作用，提高绑定引脚抗氧化性，导电电极的第一导电层与连接件具有良好的附着力，提高连接件与导电电极之间附着力以使发光元件牢固地固定于阵列基板上。
 附图说明
图1为传统亚毫米发光二极管背光模组的示意图；
图2为本申请实施例阵列基板的制造方法的流程图；
图3A-3H为制造本申请实施例阵列基板地过程示意图。
附图标注如下：
100，200基板；1011第一导电件；2011，1012栅极；102 栅极绝缘层；103有源层；1041 第二导电件；1042，2047导电电极；105 钝化层； 106 氧化铟锡层；107亚毫米发光二极管；
 200a 第一区域；200b 第二区域；200c 第三区域；202第一绝缘层；203非晶硅层；2041 第一导电层；2042 第二导电层； 2043 第三导电层；2044绑定引脚；2045源电极；2046 漏电极；205 第二绝缘层；206图案化光阻层；207锡膏；208发光元件；209 覆晶薄膜。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请实施例阵列基板的制造方法的流程图。阵列基板的制造方法包括如下步骤：
S101:于基板的第一区域和第二区域均形成第一导电层和第二导电层，形成位于第一区域且用于与驱动芯片电连接的绑定引脚，第二导电层位于第一导电层远离基板的一侧，第一区域和第二区域之间间隔。
S102:去除第二区域的第二导电层，形成位于第二区域且用于通过连接件与发光元件电连接的导电电极，其中，第一导电层与连接件的附着力大于第二导电层与连接件的附着力，且第二导电层用于防止第一导电层氧化。
在一些实施例中，去除第二区域的第二导电层之前，方法还包括：
形成覆盖第一区域和第二区域的第二导电层的绝缘层；
去除第二区域的第二导电层之后，方法还包括：
利用第一蚀刻气体蚀刻第一区域的绝缘层，以使绑定引脚显露，第一蚀刻气体蚀刻绝缘层的速率大于第一蚀刻气体蚀刻第一导电层的速率。
由于蚀刻第一区域的绝缘层时，第一导电层也暴露于第一蚀刻气体中，通过控制第一蚀刻气体蚀刻绝缘层的速率大于第一蚀刻气体蚀刻第一导电层的速率，以提高第一蚀刻气体对第一导电层和绝缘层的蚀刻选择比，避免蚀刻绝缘层的过程中造成对第一导电层的不必要蚀刻。
在一些实施例中，第一蚀刻气体包括NF 3。相对于传统蚀刻绝缘层（氮化硅层和/或氧化硅层）的气体SF 6以及Cl 2的混合物等会对第一导电层为铜或铜合金时造成腐蚀，NF 3不会与铜发生反应，在蚀刻绝缘层的同时起到保护铜且避免第一导电层被氧化的作用。第一蚀刻气体还可以包括惰性气体，惰性气体作为载气，例如He，Ar等惰性气体，以控制刻蚀绝缘层上形成的槽或开口的形貌。具体地，第一蚀刻气体为NF 3以及He的混合物。
在一些实施例中，第一导电层的制备材料选自Cu或Cu合金，有利于提高绑定引脚以及导电电极的导电性，且Cu与Sn膏能形成固溶合金，两者之间具有良好的附着力，有利于发光元件（如亚毫米发光二极管Mini-LED以及微型发光二极管Micro-LED）等牢固地绑定于导电电极上。其中，铜合金包括铜钼合金、铜银合金、铜钛合金等。具体地，第一导电层的制备材料为铜。
在一些实施例中，第二导电层的制备材料选自Mo或Mo合金，可以防止第一导电层氧化的同时，还能阻挡第一导电层扩散。特别是，第二导电层的制备材料是MoTiNi合金或MoNbTa合金时，第二导电层的抗氧化性比Mo等更好，更能避免绑定引脚出现氧化。然而，Mo及Mo合金与锡难以形成固溶合金，导致Mo及Mo合金与锡之间的附着力较差。
在一些实施例中，连接件的制备材料选自锡或锡合金，通过将锡膏点在导电电极上，且将发光元件设置在锡膏上，以使发光元件绑定在导电电极上。
在一些实施例中，去除第二区域的第二导电层包括：采用包括BCl3的第二蚀刻气体蚀刻第二区域的第二导电层。当第二导电层为MoTiNi合金时，发明人经过大量的实验发现，由于MoTiNi合金相对传统的Mo等具有更好的抗氧化性以及耐腐蚀性，MoTiNi合金很难蚀刻，传统的蚀刻气体如SF 6、NF 3以及CF 4等蚀刻气体无法蚀刻MoTiNi合金，而经过大量的实验探索发现BCl 3可以蚀刻MoTiNi合金。第二蚀刻气体还可以包括促进气体，例如Cl 2，以起到促进蚀刻的作用。
以下结合具体实施例对上述阵列基板的制造方法进行详述。
一种阵列基板的制造方法，制造方法包括如下步骤：
S201:于基板上形成第一金属图案层。
基板为玻璃基板，基板200定义有第一区域200a、第二区域200b以及第三区域200c，第三区域200c位于第一区域200a和第二区域200b之间，第一区域200a与第三区域200c之间间隔，第三区域200c与第二区域200b之间间隔，第一区域200a和第二区域200b之间间隔，其中，间隔是指有间隔区域。第一区域200a用于设置绑定引脚2044，绑定引脚2044与覆晶薄膜通过各向异性导电胶连接，或绑定引脚2044与驱动芯片通过各向异性导电胶连接。第二区域200b用于设置导电电极2047以及发光元件208，导电电极2047与发光元件208通过连接件连接。绑定引脚2044与导电电极2047之间电性绝缘。第三区域200c用于设置薄膜晶体管，薄膜晶体管用于驱动发光元件208，控制发光元件208的发光状态，薄膜晶体管包括栅极2011、栅极绝缘层、有源层以及源漏电极。
具体地，于基板200上形成整面的第一金属层，于第一金属层上形成整面的光阻层，光阻层经过光罩曝光处理以及显影液显影处理，蚀刻未被光阻层覆盖的第一金属层，去除剩余的光阻层，得第一金属图案层，如图3A所示。
其中，第一金属图案层包括位于第三区域200c的栅极2011，还可以包括位于第一区域200a的第一导电件（未示出），第一导电件通过后续形成的第一绝缘层202上的过孔与绑定引脚电性连接。第一金属层包括依次叠置于基板200上的钼层以及铜层，钼层的厚度为300埃-500埃，铜层的厚度为4000埃-6000埃。
S202:形成覆盖基板200和第一金属图案层的第一绝缘层202。
具体地，采用化学气相沉积形成覆盖栅极2011、第一导电件以及基板200的第一绝缘层202，如图3B所示。
第一绝缘层202为栅极绝缘层。第一绝缘层202的制备材料为氮化硅或/和氧化硅。第一绝缘层202的厚度为800埃-6000埃。
S203:于第一绝缘层202上依次形成半导体层以及第二金属层，采用构图工艺于第一区域200a形成绑定引脚，于第三区域200c形成有源层以及源漏电极，于第二区域200b形成第二导电层和第一导电层。
具体地，于第一绝缘层202上依次形成整面的非晶硅层203，再于非晶硅层203远离基板200的表面上形成整面的第二金属层。其中，第二金属层包括第一导电层2041、第二导电层2042以及第三导电层2043，第一导电层2041位于第二导电层2042以及第三导电层2043之间，第三导电层2043靠近基板200设置，第二导电层2042位于第一导电层2041远离基板200的一侧。第一导电层2041为铜层，厚度为3000埃-6000埃；第二导电层2042为MoTiNi合金层，厚度为300埃-500埃；第三导电层2043为MoTiNi合金层，厚度为300埃-500埃。
于第二金属层远离基板200的表面上形成光阻层，光阻层经过第一半色调灰阶掩膜板曝光以及显影液显影后，于第一区域200a和第二区域200b形成光阻完全保留层，且于第三区域200c待形成源漏电极的区域形成光阻完全保留层，完全去除第一区域200a和第三区域200c之间的光阻层，且完全去除第二区域200b和第三区域200c之间的光阻层，第三区域200c待形成源极的区域与第三区域200c待形成漏极之间的区域形成光阻半保留层。采用一次湿法蚀刻蚀刻第一区域200a和第三区域200c之间、第二区域200b以及第三区域200c之间未被光阻层覆盖的第二金属层，再采用一次干法蚀刻蚀刻第一区域200a和第三区域200c之间、第二区域200b以及第三区域200c之间的非晶硅层203；去除第三区域200c的光阻半保留层，采用一次湿法蚀刻蚀刻光阻半保留层去除后裸漏的第二金属层，去除剩余的光阻层，于第一区域200a形成绑定引脚2044，于第三区域200c形成有源层以及源漏电极（2045，2046），于第二区域200b保留半导体层和第二金属层，如图3C所示。
由于第一区域200a和第二区域200b的第二金属层完全保留，使得本步骤于基板200的第一区域200a和第二区域200b均形成第一导电层2041和第二导电层2042，得位于第一区域200a且用于与驱动芯片电连接的绑定引脚2044。
S204：形成覆盖第一绝缘层202、绑定引脚2044、源漏电极（2045，2046）以及第二区域200b的第二导电层2042 的第二绝缘层205，如图3D所示。
具体地，采用化学沉积形成第二绝缘层205。第二绝缘层205为钝化层。第二绝缘层205的制备材料可以为氮化硅层、氧化硅层或氮化硅与氧化硅层的叠层。第二绝缘层205的厚度为3000埃-6000埃。
S205: 于第二绝缘层205上形成图案化光阻层206，如图3E所示。
于第二绝缘层205上形成整面的光阻层，采用第二半色调灰阶掩膜板对光阻层进行曝光，定义第一区域200a为光阻半保留区，第二区域200b为光阻完全去除区，第一区域200a和第二区域200b之间的区域为光阻完全保留区，采用显影液对曝光后的光阻进行处理，第二区域200b的光阻层去除，第一区域200a的光阻层保留，第一区域200a和第二区域200b之间的区域的光阻层完全保留，第一区域200a光阻层的厚度小于第一区域200a和第二区域200b之间区域的光阻层厚度。
S206: 采用干法蚀刻蚀刻第二区域200b的第二绝缘层205，再去除第二区域200b的第二导电层2042，得位于第二区域200b且用于通过连接件与发光元件电连接的导电电极2047，如图3F所示。
具体地，由于仅第二区域200b的第二绝缘层205显露，除第二区域200b之外区域的第二绝缘层205均为图案化光阻层206覆盖，采用SF6和Cl2的混合物、NF3和He的混合物、NF3和Cl2的混合物中的一种蚀刻第二区域200b的第二绝缘层205；再采用包括BCl3的第二蚀刻气体蚀刻第二区域200b的第二导电层2042，第二蚀刻气体还包括Cl2，以促进BCl3蚀刻第二导电层2042的速率，去除第二区域200b的第二导电层2042，保留第二区域200b的第一导电层2041以及第三导电层2043，第二区域200b的第一导电层2041以及第三导电层2043组成导电电极2047。
S207：去除第一区域200a位于第二绝缘层205上的图案化光阻层206，利用第一蚀刻气体蚀刻第一区域200a的第二绝缘层205，以使绑定引脚2044显露，去除剩余的图案化光阻层206，如图3G所示。
第一蚀刻气体蚀刻第二绝缘层205的速率大于第一蚀刻气体蚀刻第一导电层2041的速率。第一蚀刻气体为NF3以及He的混合物，NF3以及He的混合物蚀刻第一区域200a的第二绝缘层205的同时，与铜层不发生反应，对包括铜层的导电电极2047起到保护作用。
S208: 采用锡膏207将发光元件208固定于导电电极2047上，采用各向异性导电胶将覆晶薄膜209绑定在绑定引脚2044上，如图3H所示。
发光元件208为亚毫米发光二极管。覆晶薄膜209包括柔性薄膜以及设置于柔性薄膜上的驱动芯片，驱动芯片用于输出驱动信号。
本申请还提供一种阵列基板，阵列基板包括：
基板，基板具有第一区域、第二区域以及第三区域，第一区域和第二区域之间间隔，第三区域位于第一区域和第二区域之间；
绑定引脚，用于与驱动芯片电性连接且位于基板的第一区域，绑定引脚包括第一导电层以及第二导电层，第二导电层位于第一导电层远离基板的一侧；
导电电极，用于通过连接件与发光元件连接且位于基板的第二区域，导电电极包括第一导电层；以及
薄膜晶体管，位于第三区域且用于驱动发光元件发光；
其中，第一导电层与连接件的附着力大于第二导电层与连接件的附着力，且第二导电层用于防止第一导电层氧化。
在一些实施例中，第一导电层的制备材料选自Cu或Cu合金，第二导电层的制备材料选自Mo或Mo合金，连接件的制备材料选自锡或锡合金。具体地，第二导电层的制备材料选自MoTiNi合金或MoNbTa合金。
在一些实施例中，第三区域还设置有遮光层，遮光层对应薄膜晶体管设置，以对薄膜晶体管起到遮光作用，遮光层可以为白色油墨或黑色光阻层等。
本申请阵列基板的绑定引脚以及导电电极均通过图案化第二金属层形成，相对于传统绑定引脚以及导电电极分别通过图案化两道导电层形成，本申请阵列基板具有简化制程的优点，且绑定引脚包括第二导电层以及第一导电层，第二导电层用于防止第一导电层氧化，避免绑定引脚氧化，导电电极包括第一导电层，第一导电层与连接件具有良好的附着力，使发光元件牢固地固定于导电电极上。
本申请还一种显示装置，显示装置包括背光模组，背光模组包括上述阵列基板，或，显示装置包括显示面板，显示面板包括上述阵列基板。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (19)

  1. 一种阵列基板的制造方法，其中，所述方法包括如下步骤：
    于基板的第一区域和第二区域均形成第一导电层和第二导电层，形成位于所述第一区域且用于与驱动芯片电连接的绑定引脚，所述第二导电层位于所述第一导电层远离所述基板的一侧，所述第一区域和所述第二区域之间间隔；
    去除所述第二区域的所述第二导电层，形成位于所述第二区域且用于通过连接件与发光元件电连接的导电电极；
    其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
  2. 根据权利要求1所述的阵列基板的制造方法，其中，去除所述第二区域的所述第二导电层之前，所述方法还包括：
    形成覆盖所述第一区域和所述第二区域的所述第二导电层的绝缘层；
    去除所述第二区域的所述第二导电层之后，所述方法还包括：
    利用第一蚀刻气体蚀刻所述第一区域的所述绝缘层，以使所述绑定引脚显露，所述第一蚀刻气体蚀刻所述绝缘层的速率大于所述第一蚀刻气体蚀刻所述第一导电层的速率。
  3. 根据权利要求2所述的阵列基板的制造方法，其中，所述第一蚀刻气体包括NF 3。
  4. 根据权利要求3所述的阵列基板的制造方法，其中，第一蚀刻气体还包括惰性气体。
  5. 根据权利要求2所述的阵列基板的制造方法，其中，所述第一蚀刻气体为NF 3以及He的混合物。
  6. 根据权利要求1所述的阵列基板的制造方法，其中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
  7. 根据权利要求1所述的阵列基板的制造方法，其中，所述第二导电层的制备材料为MoTiNi合金。
  8. 根据权利要求1所述的阵列基板的制造方法，其中，所述去除所述第二区域的所述第二导电层包括：
    采用包括BCl 3的第二蚀刻气体蚀刻所述第二区域的所述第二导电层。
  9. 根据权利要求8所述的阵列基板的制造方法，其中，第二蚀刻气体还包括Cl 2。
  10. 一种阵列基板，其中，所述阵列基板包括：
    基板，所述基板具有第一区域和第二区域，所述第一区域和所述第二区域之间间隔；
    绑定引脚，用于与驱动芯片电性连接且位于所述基板的所述第一区域，所述绑定引脚包括第一导电层以及第二导电层，所述第二导电层位于所述第一导电层远离所述基板的一侧；以及
    导电电极，用于通过连接件与发光元件连接且位于所述基板的所述第二区域，所述导电电极包括所述第一导电层；
    其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
  11. 根据权利要求10所述的阵列基板，其中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
  12. 根据权利要求10所述的阵列基板，其中，所述第二导电层的制备材料选自MoTiNi合金或MoNbTa合金。
  13. 根据权利要求10所述的阵列基板，其中，所述绑定引脚以及所述导电电极均包括第三导电层，所述第一导电层位于所述第二导电层和所述第三导电层之间。
  14. 根据权利要求13所述的阵列基板，其中，第三导电层为MoTiNi合金层。
  15. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括：
    基板，所述基板具有第一区域和第二区域，所述第一区域和所述第二区域之间间隔；
    绑定引脚，用于与驱动芯片电性连接且位于所述基板的所述第一区域，所述绑定引脚包括第一导电层以及第二导电层，所述第二导电层位于所述第一导电层远离所述基板的一侧；以及
    导电电极，用于通过连接件与发光元件连接且位于所述基板的所述第二区域，所述导电电极包括所述第一导电层；
    其中，所述第一导电层与所述连接件的附着力大于所述第二导电层与所述连接件的附着力，且所述第二导电层用于防止所述第一导电层氧化。
  16. 根据权利要求15所述的显示装置，其中，所述第一导电层的制备材料选自Cu或Cu合金，所述第二导电层的制备材料选自Mo或Mo合金，所述连接件的制备材料选自锡或锡合金。
  17. 根据权利要求15所述的显示装置，其中，所述第二导电层的制备材料选自MoTiNi合金或MoNbTa合金。
  18. 根据权利要求15所述的显示装置，其中，所述绑定引脚以及所述导电电极均包括第三导电层，所述第一导电层位于所述第二导电层和所述第三导电层之间。
  19. 根据权利要求18所述的显示装置，其中，第三导电层为MoTiNi合金层。
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