WO2021205918A1 - 基板処理装置及び基板処理方法 - Google Patents
基板処理装置及び基板処理方法 Download PDFInfo
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- WO2021205918A1 WO2021205918A1 PCT/JP2021/013061 JP2021013061W WO2021205918A1 WO 2021205918 A1 WO2021205918 A1 WO 2021205918A1 JP 2021013061 W JP2021013061 W JP 2021013061W WO 2021205918 A1 WO2021205918 A1 WO 2021205918A1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/70733—Handling masks and workpieces, e.g. exchange of workpiece or mask, transport of workpiece or mask
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
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- H01L21/67742—Mechanical parts of transfer devices
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
Definitions
- This disclosure relates to a substrate processing apparatus and a substrate processing method.
- a transfer mechanism may be configured to sequentially transfer a wafer to a plurality of processing modules that perform different processes.
- Patent Document 1 a substrate that performs a first operation of transporting a substrate from a processing unit for processing the substrate to a substrate storage means and a second operation other than the first operation of transporting the substrate between the processing units, respectively.
- the transport device is shown. It is described that when it becomes necessary to perform the first operation during the second operation, the first operation is prioritized, and in other cases, the second operation is prioritized.
- the present disclosure provides a technique capable of obtaining high throughput in a substrate processing apparatus that transports and processes a substrate between a plurality of processing modules.
- the substrate processing apparatus of the present disclosure includes a plurality of processing modules for processing each substrate, and a plurality of relay modules on which the substrate is mounted for transporting the substrate between the plurality of processing modules.
- the loading and unloading of the substrate to the processing module is performed by a common transport mechanism, and the loading and unloading of the substrate to and from the relay module are performed by different transport mechanisms.
- a high throughput can be obtained in a substrate processing apparatus for transporting and processing a substrate between a plurality of processing modules.
- the coating and developing apparatus 1 which is an embodiment of the substrate processing apparatus of the present disclosure, will be described with reference to the longitudinal front view of the cross-sectional plan view 2 of FIG.
- the coating / developing device 1 is configured such that a carrier block D1, an inspection block D2, a processing block D3, and an interface block D4 are arranged in a horizontal row in this order and connected to each other.
- the arrangement direction of the blocks D1 to D4 is the left-right direction
- the carrier block D1 side is the left side
- the interface block D4 side is the right side.
- An exposure machine EIF that performs immersion exposure is connected to the right side of the interface block D4.
- the front side when the carrier block D1 is viewed on the left side and the interface block D4 on the right side is the front side
- the back side is the rear side.
- the coating / developing device 1 includes a large number of modules and a large number of transport mechanisms (convey arms).
- a carrier C for storing a plurality of wafers W for each lot is conveyed from the outside of the coating / developing apparatus 1.
- a large number of transfer mechanisms in the coating and developing apparatus 1 each convey a section assigned in the transfer path, and the wafer W moves in order through each module constituting the transfer path.
- the wafer W is returned to the carrier C after undergoing a series of processes.
- FIG. 2 some of the transport mechanisms are shown at positions shifted to the left and right from the positions shown in FIG.
- a module is a place where a wafer W is placed, and a processing module (process module) that processes the wafer W and a module on which the wafer W is placed to relay the transfer of the wafer W between the processing modules.
- the relay module includes a transfer module TRS, a buffer module SBU, and a temperature control module ICPL.
- TRS and SBU are configured so that a plurality of wafers W can be placed in the vertical direction.
- these modules include a plurality of pins or stages located at different heights above and below, and a wafer W is placed on the pins or stages.
- the temperature adjustment module ICPL is provided with a stage for adjusting the temperature, and adjusts the temperature of the wafer W on which it is placed.
- the modules will be further described.
- the wafer W is carried in by one transport mechanism and the wafer W is carried out by another transport mechanism. That is, the transport mechanisms used for loading and unloading are different from each other.
- a common transfer mechanism is used for loading and unloading the wafer W.
- the processing module is a module that performs processing such as liquid treatment and heat treatment on the wafer W, and the processing includes inspection of the wafer W. Further, in performing the transfer control described later, the exposure machine EIF is also handled as a processing module.
- the above-mentioned delivery module TRS is provided in various places in the apparatus, and in the following description and each figure, a number may be added after "TRS" to distinguish them from each other. This number is attached according to the order in which the wafer W is transported in the transport path.
- a temperature adjustment module SCPL configured so that the temperature of the wafer W can be adjusted like the ICPL is provided at various places in the apparatus. Similar to TRS, this SCPL is also shown with a number in the order of transportation. The number of TRS and SCPL provided in the same step in the transport path is shown in FIG. 2 to be smaller than the actual number in order to prevent complication of the figure.
- FIG. 3 schematically shows the arrangement of each module and the transport mechanism in the coating and developing apparatus 1.
- some of the modules provided in the actual device are omitted from the display.
- the outline of the transfer path of the wafer W in the apparatus is shown by the arrow of the chain line.
- the carrier block D1 includes a plurality of carrier stages 11 on which the above carriers C are placed, and a CRA that is a transfer mechanism for transferring the wafer W between the carrier C and the coating and developing apparatus 1.
- the inspection block D2 includes an inspection module WIS for inspecting the wafer W before processing by the coating and developing apparatus 1, and an inspection module YSM for inspecting the wafer W after processing by the coating and developing apparatus 1, and each of the processing blocks D3. Hand over the wafer W to the height.
- the stack of delivery modules TRS (TRS1, TRS13), the transport mechanism MRA, and the tower T1 are provided in this order.
- the inspection module WIS is provided above the TRS1 and TRS13, and the inspection module YSM is provided behind the MRA.
- the MRA can access the TRS1, TRS13, each inspection module, and some modules included in the tower T1.
- An MPRA which is a transport mechanism, is provided behind the tower T1, and the MPRA can access each module of the tower T1.
- the tower T1 is configured by stacking a large number of delivery modules TRS and a large number of temperature control modules SCPL.
- the processing block D3 is configured by stacking unit blocks E1 to E6.
- the transfer modules TRS (TRS3 to TRS5, TRS11) and the transfer modules TRS (TRS3 to TRS5, TRS11) and the transfer modules TRS (TRS3 to TRS5, TRS11) and Temperature control modules SCPL (SCPL1 to SCPL4) are provided.
- TRS (TRS2, TRS12) for delivery of the wafer W in the inspection block D2 are provided in the tower T1.
- the processing block D3 is formed by stacking unit blocks E (E1 to E6) for performing liquid treatment and heat treatment on the wafer W in order from the bottom, and between the unit blocks E1 and E2 and between E3 and E4. , E5, and E6, respectively, the same processing is performed.
- the antireflection film is formed and the back surface of the wafer W is cleaned before exposure.
- a resist film is formed on the antireflection film and a protective film that protects the resist film during immersion exposure is formed. Development processing is performed on the unit blocks E5 and E6.
- the wafer W is conveyed between the unit blocks in the order of E1, E2 ⁇ E3, E4 ⁇ E1, E2 ⁇ E5, E6.
- the wafer W is transported through the transport path 21 separated for each unit block E, but the transport path 21 is not separated on the right side of the unit blocks E1 and E2, and the transport path straddling the unit blocks E1 and E2. It is configured as 22.
- the unit block E3 will be described with reference to the plan view of FIG.
- the transport path 21 extends to the left and right, and a resist coating module COT and a chemical solution coating module ITC for forming a protective film are provided along the transport path 21 on the front side of the transport path 21.
- 11 heating modules PAB and an inspection module WES for inspecting the wafer W after forming the protective film are provided on the rear side of the transport path 21.
- Some of the 11 heating modules PAB are stacked in two stages and arranged along the transport path 21. Then, some of them are used for heating the wafer W after forming the resist film, and some of the other ones are used for heating the wafer W after forming the protective film.
- the transport path 21 is provided with a transport mechanism, PRA3.
- the PRA3 accesses each module provided in the unit block E3 and a module provided at the height of the unit block E3 in the tower T1 and the tower T2 described later.
- the unit block E4 has the same configuration as the unit block E3. Focusing on the differences between the unit blocks E5 and the unit blocks E3 and E4, eight development modules DEV are provided on the front side of the transport path 21. Actually, a plurality of types of DEVs that supply different developers are provided, but detailed description thereof will be omitted. On the rear side of the transport path 21, six heating modules PEB for performing postexposure bake and inspection module WISD for inspecting the wafer W after development are provided.
- the unit block E6 has the same configuration as the unit block E5. The transport mechanisms corresponding to PRA3 provided in the unit blocks E4 to E6 are shown as PRA4 to PRA6 in FIG. 2 and the like.
- the transport path of the unit block E1 is configured as a transport path 21 separated from the transport path of the unit block E2 on the left side and a transport path 22 leading to the transport path of the unit block E2 on the right side.
- Three chemical solution application modules BCT for forming an antireflection film are provided in front of the transport path 21.
- Behind the transport path 21 six heating modules PAB for heating the wafer W after forming the antireflection film and a hydrophobic treatment module CWH for hydrophobizing the wafer W are provided.
- the transport path 21 is provided with a PRA1 as a transport mechanism corresponding to the PRA3.
- the left side thereof is configured in the same manner as the left side of the unit block E1, and the transport path 21 is provided with the PRA2 corresponding to the PRA3.
- a total of six back surface cleaning modules BST are provided in front of and behind the transport path 22 straddling the unit blocks E1 and E2, and two of them are arranged side by side along the transport path 22.
- the transport path 22 is provided with PRAI, which is a transport mechanism shared by the unit blocks E1 and E2, and accesses each module provided at the height of the unit blocks E1 and E2 in each BST and the tower T2 described later.
- the tower T2 is provided on the left side of the center of the front and rear of the interface block D4.
- the tower T2 is configured by stacking a plurality of delivery modules TRS (TRS6 to TRS10) and a plurality of temperature control modules ICPL.
- TRS6 to TRS10 delivery modules
- ICPL temperature control modules
- Four cleaning modules PIRs are provided one above the other on the right front of the upper part of the tower T2, and each PIR cleans the wafer W and removes the protective film after exposure by the exposure machine EIF and before PEB.
- a buffer module SBU is provided at the rear right of the upper part of the tower T2.
- the interface block D4 includes IRAMC, IRAMB, and IRAI, which are transfer mechanisms.
- the transport mechanism IRAMC is located on the right side of the tower T2 and in the center of the front and rear of the interface block D4, and accesses the cleaning module PIR, the buffer module SBU, and each TRS from the upper part to the central part of the tower T2.
- the transport mechanism IRAMB is located behind the tower T2 and accesses the modules and SBUs at each height of the tower T2, respectively.
- the transport mechanism IRAI accesses the exposure machine EIF, the ICPL provided on the lower side of the tower T2, and the TRS at the center of the height of the tower T2.
- Each transport mechanism provided in the coating and developing apparatus 1 will be supplementarily described.
- Each transfer mechanism includes a substrate holding portion 31, a base 32, and a moving portion 33 (see FIG. 5).
- the substrate holding portion 31 moves back and forth between the base 32.
- the base 32 is configured to be movable up and down around a vertical axis by a moving portion 33.
- the CRA, PRA1 to PRA6, PRAI, and IRAI are provided with a horizontal movement mechanism 34 for moving the moving unit 33 in the horizontal direction, and are configured to be able to access each module and each carrier C described above.
- the transport mechanisms PRA1 to PRA6, PRAI, and IRAMC each include two substrate holding portions 31, and the two substrate holding portions 31 advance and retreat from the base 32 independently of each other. Therefore, with respect to these transfer mechanisms, one substrate holding portion 31 moves forward and backward to receive the wafer W from the module, and then the other substrate holding portion 31 enters the module and holds the wafer W. Can be sent to the module. That is, the wafer W can be replaced in the module without moving and rotating the base 32 in the lateral direction. The wafer W is transferred from the module in the previous stage to the module to be replaced, then the wafer W described above is replaced in the module to be replaced, and then the wafer W received by the replacement is transferred to the module in the subsequent stage of the module to be replaced. About transporting, it shall be replaced transporting.
- the coating / developing device 1 includes a control unit 10 (see FIG. 1).
- the control unit 10 is composed of a computer, and includes a program, a memory, and a CPU.
- the program incorporates a group of steps so that a series of operations in the coating and developing apparatus 1 can be performed.
- the control unit 10 outputs a control signal to each part of the coating and developing apparatus 1 by the program, and the operation of each part is controlled.
- the wafer W of the present embodiment is conveyed and the wafer W is processed.
- the above program is stored in a storage medium such as a compact disk, a hard disk, or a DVD, and is installed in the control unit 10.
- FIG. 6 The upper part of FIG. 6 is a schematic view of a coating / developing device 1 for showing a transfer path of the wafer W.
- the modules are shown in the order of transportation.
- the transport mechanism used for loading and unloading to and from the module is displayed below each module, the transport mechanism used for loading and unloading is shown on the upper side, and the transport mechanism used for loading and unloading is shown on the lower side.
- the wafer W is taken out from the carrier C by the CRA of the carrier block D1 and conveyed to the delivery module TRS1 of the inspection block D2.
- This wafer W is conveyed to the inspection module WIS by MRA for inspection, then conveyed to TRS2 of tower T1 by MRA, and further conveyed to TRS3 of tower T1 by MPRA.
- the wafer W transported to TRS3 is transported by PRA1 or PRA2 in the order of CWH, SCPL1, BCT, PAB to unit blocks E1 and E2, and is subjected to hydrophobization treatment, temperature adjustment, antireflection film film formation treatment, and heat treatment. After receiving them in order, they are transported to TRS4. Then, the wafer W of TRS4 is conveyed to TRS5 by MPRA.
- Wafer W of TRS5 is the unit block E3 or E4 in the order of SCPL2 of tower T1, resist coating module COT, heating module PAB, SCPL3 of tower T1, chemical coating module ITC, heating module PAB, inspection module WES by PRA3 or PRA4. Is transported.
- the wafer W undergoes temperature adjustment, resist film film formation treatment, heat treatment, temperature adjustment, protective film film formation treatment, heat treatment, and inspection in that order, and is then conveyed to TRS6 of the tower T2 by PRA3 or PRA4.
- NS
- the wafer W transported to the TRS 6 is transported to the SBU by the IRAMC and retained, and then transported to the TRS 7 of the tower T2 by the IRAMB. Then, this wafer W is conveyed to BST by PRAI, washed on the back surface, then conveyed to TRS8, and then conveyed to ICPL by IRAMB. After that, the wafer W is conveyed to the exposure machine EIF by IRAI, and the resist film is exposed along a predetermined pattern.
- the wafer W is carried out from the exposure machine EIF by the IRAI and conveyed to the TRS9 of the tower T2, then further conveyed to the cleaning module PIR by the IRAMC for cleaning, and then conveyed to the TRS10 by the IRAMC.
- the wafer W transported to the TRS 10 is transported by the PRA5 or PRA6 in the unit blocks E5 or E6 in the order of the heating module PEB, SCPL4, the developing module DEV, and the inspection module WISD.
- the wafer W undergoes heat treatment, temperature adjustment, development treatment, and inspection in that order.
- a resist pattern is formed along the exposed pattern.
- the wafer W is transported to TRS11 of the tower T1 by PRA5 or PRA6, transported to TRS12 by MPRA, and then transported to the inspection module YSM by MRA for inspection. After that, the wafer W is conveyed to the TRS 13 by the MRA and returned to the carrier C by the CRA.
- the range in which one transfer mechanism conveys the wafer W is described as a “layer”.
- the modules included in this range and between the modules form a layer corresponding to the PRA3. Therefore, the layer corresponds to each section divided for each transport mechanism in charge of transport for the transport route.
- the layers corresponding to the transport mechanism other than PRA PRA1 to PRA6 are given the same names as the transport mechanism.
- each of the layers is referred to as a CRA layer, an MRA layer, an MPRA layer, a PRAI layer, an IRAI layer, an IRAMB layer, and an IRAMC layer.
- the layers corresponding to PRA1 and PRA2 are BCT layers
- the layers corresponding to PRA3 and PRA4 are COT / ITC layers
- the layers corresponding to PRA5 and PRA6 are DEV layers. Therefore, when the layer is viewed as a unit, the wafer W has a CRA layer-> MRA layer-> MPRA layer-> BCT layer-> MPRA layer-> COT / ITC layer-> IRAMC layer-> IRAMB layer-> PRAI layer-> IRAMB layer-> IRAI layer-> IRAMC layer-> DV. It is conveyed in the order of layer ⁇ MPRA layer ⁇ MRA layer ⁇ CRA layer.
- the transport mechanism of each layer repeatedly cyclically moves the modules in the layer in order, and the above is applied to each module excluding the module at the entrance and the module at the exit of the layer. Wafer W is replaced. As a result, one wafer W is sequentially conveyed from the upstream module to the downstream module in each of these layers.
- the IRAMC layer and the PRAI layer can also be replaced and transported in the same manner as the BCT layer and the like, but the determination of whether or not to perform the replacement transport in these layers is a parameter of the time calculated for each layer. It is performed based on the block cycle time (abbreviated as block CT).
- the replacement transfer enables the transfer (cyclic transfer) in which the transfer mechanism repeatedly moves each module in the layer cyclically. By performing the cyclic transfer, the movement of the transfer mechanism in the layer is suppressed, and the wafer W is efficiently conveyed.
- MUTCT MUT cycle time
- the maximum value of this MUTCT is determined for each layer.
- the number of arm steps is the number of steps of how many times the transfer mechanism (conveyor arm) conveys the wafer W from the inlet to the outlet of the layer. Since the wafer W is conveyed between the five modules in the BCT layer as described above, the number of arm steps is 4, which is the number between these modules.
- the set time required for one arm process is predetermined, for example, 3.7 seconds.
- the maximum value of MUTCT of 11.0 seconds is larger than that of 7.4 seconds of ACT. Therefore, it is not the operation of the transport mechanism but the processing in the BCT that determines the rate of productivity in the BCT layer.
- the maximum value of MUTCT and ACT are compared, and the larger one is designated as the block CT.
- the block CT calculated in this way is the time required for transporting one cycle in the layer, that is, the time required for transporting between each module in charge of the transport mechanism once, and the block CT is transferred to the subsequent layer. This corresponds to the expected time interval for transporting the wafer W.
- the processing time of the processing module is used for the calculation of the block CT, but with respect to the processing time of the exposure machine EIF, the control unit 10 acquires information on the carry-out interval of the wafer W from the exposure machine EIF. Determine by doing.
- FIG. 7 shows the block CT (unit: seconds) calculated by arranging the layers in the order of the wafer W transport path and below each layer.
- the numerical value of this block CT is described to assist the understanding of the transport control described later, and does not necessarily match the actual numerical value.
- the block CT of the BCT layer a value different from the value shown in the above description of the calculation method of the block CT is shown.
- the wafer W passes a plurality of times for the MPRA layer, the IRAMC layer, and the like. Since the block CT is calculated and defined as described above, the block CT is the same if it is the same layer, and the block CT having the same value is described in the same layer in each stage in the figure.
- the transfer by the transfer mechanism IRAMC will be described with reference to the schematic views of FIGS. 8 to 16. In these schematic views, the modules in the interface block D4 are shown side by side in the vertical direction according to the transfer order of the wafer W.
- the transfer module TRS6 ⁇ buffer module SBU (second section), the transfer module TRS9 ⁇ cleaning module PIR ⁇ transfer module TRS10 (first section). It is a shared transport mechanism shared for transport.
- the PIR corresponds to one processing module, and the TRS10, SBU, and TRS9 correspond to the first relay module, the second relay module, and the third relay module, respectively.
- the transfer mechanism IRAMC waits for the transfer of the wafer W of PIR ⁇ TRS10.
- the upper limit (waiting time) of the time for performing this meeting is determined from the above block CT. More specifically, it is determined based on the block CT of each layer in the previous stage in the transport path rather than the layer in which the meeting is performed.
- the layer for waiting is the layer in the step of performing such a meeting. That is, the wafer W passes through the IRAMC layer twice, but the IRAMC layer passing through the second time corresponds to the layer to be waited for.
- the CRA layer, the MRA layer, the MPRA layer, the BCT layer, the MPRA layer, the COT / ITC layer, the IRAMC layer, the IRAMB layer, the PRAI layer, and the IRAI layer are in front of the IRAMC layer to be waited for. There is. Then, regarding the block CT, the CRA layer, the MRA layer, the MPRA layer, the BCT layer, the COT / ITC layer, the IRAMC layer, the IRAMB layer, the PRAI layer, and the IRAI layer are 7.5 seconds, 3.7 seconds, and 6.6 seconds, respectively. 9.9 seconds, 7.2 seconds, 8.9 seconds, 7.4 seconds, 9.0 seconds, 10.0 seconds.
- the maximum value in this is 10.0 seconds of the IRAI layer. Since the block CT is the time during which one cycle of transfer is performed in each layer as described above, the wafer W is normally transferred to the IRAMC layer at intervals of 10.0 seconds. Therefore, the meeting time is determined to be 10 seconds. That is, it is set that the waiting is performed for a maximum of 10.0 seconds from the time when the wafer W can be conveyed from the PIR.
- the transfer mechanism IRAMC performs replacement transfer. That is, the wafer W of TRS9 is received (FIG. 10), the wafer W is replaced by PIR, and the wafer W processed by the PIR is conveyed to TRS10 (FIG. 11).
- the wafer W is not transported to the TRS 9 even after the waiting time of 10.0 seconds has elapsed, is there a wafer W that can be transported by the transport mechanism IRAMC? Is it free?) Is judged.
- the section in which the determination of the number of wafers W is performed (referred to as the number determination section) will be described more specifically.
- the wafer W is conveyed to the relay module SBU by the transfer mechanism IRAMC. Seen downstream from this SBU, the most recent processing module is BST (see FIG. 6). Between the BST and the SBU, there is a TRS7 included in the PRAI layer as a relay module. Therefore, SBU to TRS7 is one of the number determination sections, and is shown as 41 surrounded by a dotted line in FIG. Further, since the wafer W is conveyed to the TRS 10 by the IRAMC, the TRS 10 is included in the number determination section.
- the module immediately next to it is the processing module PEB (see FIG. 6), so there is no module to be determined downstream of the TRS10. Therefore, only one TRS10 forms another number determination section, and is shown as 42 surrounded by a dotted line in FIG.
- the number of wafers W existing between the number determination sections 41 and 42 is compared, and it is determined in which number determination section the wafer W is the smallest. Then, the transfer mechanism IRAMC operates so that the number of wafers W is transferred to the module in the number determination section.
- the transfer mechanism IRAMB has one wafer W being transferred from the SBU to the TRS7, and the TRS7 has zero wafers W. doing. Therefore, a total of four wafers W exist in the number-of-sheet determination section 41.
- the TRS 10 which is the number determination section 42. Therefore, regarding the number of wafers W, SBU to TRS7 (4 wafers)> TRS10 (1 wafer), and the number of wafers determination section 42 (TRS10) is smaller. Therefore, the IRAMC transports PIR ⁇ TRS10 (FIG. 14).
- the reason why the transfer mechanism IRAMC conveys the wafer W as shown in FIGS. 13 and 14 will be described below.
- the fact that the wafer W is accumulated from a certain relay module to the relay module immediately before the nearest processing module when viewed from the downstream side in the transport path means that even if the wafer W is transported to a certain relay module, the processing module is concerned. It means that there is a starting wafer W to be transported to. When the number of the starting wafers W is large, even if the wafer W is conveyed downstream from a certain relay module, it takes time for the wafer W to be processed by the processing module.
- the number of wafers W is the same as a result of comparing the number of wafers W between the number determination sections 41 and 42 described in FIG.
- the number of empty slots (slots in which the wafer W is not conveyed) of the relay module is compared for each section of TRS6 ⁇ SBU and TRS9 ⁇ PIR ⁇ TRS10. That is, the number of empty slots in each of TRS6 and TRS9 is compared, and the transfer mechanism IRAMC receives the wafer W from the module having the smaller number of empty slots and transfers it to the downstream side.
- the transport mechanism IRAMC transports TRS6 ⁇ SBU (FIG. 16). If the number of wafers W waiting to be transferred increases for a certain module and the slots are filled, the transfer on the upstream side of the module will be delayed. The wafer W to be conveyed in this way is selected so as to prevent it.
- the transfer mechanism IRAMC promptly conveys the wafer W to the SBU when the wafer W is conveyed to the TRS 6.
- the transfer mechanism IRAMC transfers the wafer W to the SBU as soon as the wafer W is transferred to the TRS 6 even while waiting for the transfer of the wafer W from the PIR. This is to prevent a situation in which the TRS 6 having a smaller number of wafers W that can be stored than the SBU is blocked and the subsequent wafer W cannot be conveyed to the TRS 6 occurs.
- the waiting time set for the replacement by the PIR described in FIGS. 9 to 12 will be supplemented.
- the waiting time is calculated from the block CT of each layer.
- the block CT of each layer is calculated. , Calculated based on the number of available modules. That is, the waiting time during the transfer of the wafer W of one PJ is not constant, and changes according to the status of the modules of each layer.
- the determination of transport in the MPRA layer will be specifically described with reference to FIGS. 17 and 18.
- the wafer W is conveyed to the relay module in the number determination section where the number of wafers is smaller.
- the wafer W can be conveyed in any of TRS2 ⁇ TRS3, TRS4 ⁇ TRS5, and TRS11 ⁇ TRS12.
- the number of sheets determination section is TRS3, TRS5, and TRS12 (in the upper part of FIG. 17, indicated by the dotted arrow). Pointing to). That is, it is determined that the wafer W is conveyed to the module having a smaller number of wafers W among these TRS3, TRS5, and TRS12. In the example shown in FIG. 17, one wafer W is conveyed to TRS3, and two wafers W are conveyed to TRS5 and TRS12. Therefore, since the number of wafers W of TRS3 is the smallest, TRS2 ⁇ TRS3 is conveyed as shown in the lower part of FIG.
- the number of empty slots of the relay module of the transfer source to these modules by MPRA is compared. NS. Then, the wafer W is transported so as to be carried out from the module having a smaller number of empty slots.
- the relay modules of the transport sources of TRS3, TRS5, and TRS12 are TRS2, TRS4, and TRS11, respectively, as indicated by the dotted arrows in the upper part of FIG. In the example shown in FIG. 18, two wafers W are conveyed to TRS2 and one wafer W is conveyed to TRS5 and TRS12. Therefore, since TRS2 has the smallest number of empty slots, TRS2 ⁇ TRS3 is transported as shown in the lower part of FIG.
- the transfer of the next step of the previous transfer is performed. That is, if the previous transfer is TRS2 ⁇ TRS3, TRS4 ⁇ TRS5, if TRS4 ⁇ TRS5, TRS11 ⁇ TRS12, and if TRS11 ⁇ TRS12, TRS2 ⁇ TRS3 is conveyed.
- the layer that determines the transfer destination of the wafer W is the rate-determining factor for the transfer of the wafer W in the apparatus. It is considered that the wafer W is accumulated in the transfer source.
- the PRAI layer includes a back surface cleaning module BST as a processing module. Whether or not replacement transfer is performed in this BST is determined in the same manner as in the IRAM layer. Therefore, if the wafer W is conveyed to TRS7 (see FIG. 6) in the previous stage of the BST when the processing is completed in the BST, the PRAI receives the wafer W, replaces the wafer W in the BST, and replaces the received wafer W with the received wafer W. Transport to TRS8.
- BST back surface cleaning module
- the waiting time is set in the same manner as the transfer in the IRAMC layer described above.
- This waiting time is set to be the maximum time in the block CT of the layer before the PRAI layer. Therefore, when the block CT is calculated as shown in FIG. 7, the largest layer before the PRAI layer is the BCT layer for 9.9 seconds, so that 9.9 seconds is set as the waiting time. Will be done.
- the transport mechanism PRAI performs replacement transport. If the wafer W is not conveyed to the TRS 7 even after the waiting time has elapsed, the transfer mechanism PRAI transfers the wafer W processed by the BST to the TRS 8. That is, the replacement in BST is not performed.
- the above-mentioned meeting is not performed when switching PJs. Specifically, when the wafer W of one PJ finishes processing in BST and the wafer W transferred to the BST is the wafer W of another PJ, the wafer W of one PJ is not waited for. W is transported to TRS8 as soon as the transport mechanism PRAI can be transported. This is because the pressure in the BST may be changed when the PJ is switched, and when the replacement is attempted, after the transfer mechanism PRAI receives the wafer W of one PJ from the BST, the pressure of the next PJ is changed until the end of this pressure change. This is because there is a possibility that the wafer W cannot be conveyed to the BST. That is, by preventing the meeting from being performed, the transportation is prevented from being stopped by the transportation mechanism PRAI.
- the wafer W to be replaced in the BST has not reached the processing module immediately before the BST (that is, WES, see FIG. 6), it takes a long time for the wafer W to reach the BST. , No meeting is done.
- the wafer W to be replaced by the PIR has not reached the processing module immediately before the PIR (that is, EIF, see FIG. 6)
- the wafer W is transported by a common transport mechanism in sections (between steps) of the transport path that are separated from each other.
- the wafer in any section is based on the transfer status of the wafer W from the relay module in which the transfer is performed by this transfer mechanism to the relay module in front of the nearest processing module when viewed from the downstream side. It is decided whether to carry W. As a result, the transfer of the wafer W to the processing module at the end of each section is prevented from being delayed. Therefore, a high throughput can be obtained for the coating and developing apparatus 1.
- the transfer status of the wafer W in the IRAMC layer is also referred to to determine in which section the wafer W is transferred. Will be done. Therefore, the delay in the transfer of the wafer W to the processing module described above can be more reliably prevented, and the throughput of the apparatus can be increased.
- the replacement transfer cannot be performed by PIR in the IRAMC layer
- the above-mentioned section is selected for transfer. That is, the replacement transportation is prioritized.
- the wafer W is continuously carried out and carried in for one module. Therefore, the more the replacement transfer is performed, the more the movement of the transfer mechanism IRAMC between the modules is suppressed, and the transfer mechanism IRAMC is suppressed.
- the number of operation steps can be reduced. Therefore, by giving priority to the replacement transfer as described above, a higher throughput can be obtained more reliably.
- a waiting time for determining whether or not to perform replacement transfer is set in the PRAI layer and the IRAMC layer, and this waiting time is set in each layer before the layer including the processing module to be replaced and transferred. It is set based on the block CT. Then, after the waiting time has elapsed, the processed wafer W is carried out from the processing module without performing replacement transfer. Therefore, when the transfer to each of the PRAI layer and the IRAMC layer is delayed, it is possible to prevent the transfer mechanism from unnecessarily waiting for the wafer W for replacement. As a result, higher throughput can be obtained more reliably.
- the block CT is calculated based on the MUT for the processing module in each layer and the available number as described above. Therefore, for example, even if the number of modules that can be used changes due to trouble or maintenance, an appropriate waiting time is set, so that it is possible to prevent the frequency of replacement transfer from decreasing in the PRAI layer and the IRAMC layer, and it is more reliably higher. Throughput can be obtained.
- the waiting time is not limited to the maximum value of the block CT in each layer before the layer to be replaced, and for example, an arbitrary correction value may be added.
- the determination is not limited to the number of empty slots.
- the determination may be made based on the ratio of the slots in which the wafer W is carried in to all the slots. That is, the above determination can be made based on the transfer status of the wafer W in the relay module of the transfer source by the transfer mechanism.
- the wafer W to be conveyed by the transfer mechanism is based on the transfer status of the wafer W in the section from the relay module in which the transfer is performed by the transfer mechanism to the relay module in front of the nearest processing module when viewed from the downstream side.
- the transfer status of the wafer W is not limited to the number of wafers W in determining the above.
- the ratio of the slots in which the wafer W is carried to all the slots of the relay module existing in the section may be used.
- the number of slots may differ between relay modules.
- the number of slots differs between SBU and TRS. Therefore, in order to grasp the transfer status of each section and perform transfer so as to prevent the decrease in throughput more reliably, it is preferable that the transfer status is the number of wafers W.
- the module mounted on the device is not limited to the above example. Therefore, the substrate processing apparatus of the present disclosure is not limited to being configured as the coating and developing apparatus 1.
- a device configuration may be provided in which a module for applying a chemical solution for forming an insulating film, a module for supplying an adhesive for bonding wafers W to each other, and the like are provided.
- the transfer decision is not made based on the transfer status of the wafer W described above, and the waiting time is calculated based on the block CT in each of the IRAMC layer and the PRAI layer, and within the waiting time. It shall be carried out for the replacement transportation of. Even in that case, the effect described above can be obtained by appropriately setting the waiting time, and the throughput of the apparatus can be improved.
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Abstract
Description
前記処理モジュールへの前記基板の搬入及び搬出が共通の搬送機構で行われ、前記中継モジュールへの前記基板への搬入、搬出が互いに異なる搬送機構で行われ、前記モジュール群により構成される基板の搬送経路を順番に前記基板が搬送されるように、当該搬送経路において割り当てられた区間を各々搬送する複数の搬送機構と、
前記複数の搬送機構のうちの一つをなし、前記基板の搬送経路のうちの互いに離れた第1の区間及び第2の区間の搬送に共用され、前記複数の中継モジュールのうち前記第1の区間に含まれる第1の中継モジュール、前記第2の区間に含まれる第2の中継モジュールの各々に前記基板を搬送する共用搬送機構と、
前記第1の中継モジュール、第2の中継モジュールの各々から前記搬送経路の下流側に見て、直近の前記処理モジュールの手前の中継モジュールに至るまでの各区間における前記基板の搬送状況に基づき、前記共用搬送機構が第1の中継モジュール及び第2の中継モジュールのうちのいずれへ前記基板を搬送するかの決定を行う決定部と、
を備える。
10 制御部
IRAMB 搬送機構
IRAMC 搬送機構
SBU バッファモジュール
TRS10 受け渡しモジュール
PIR 露光後洗浄モジュール
W ウエハ
Claims (11)
- 基板を各々処理する複数の処理モジュールと、前記複数の処理モジュール間で当該基板を搬送するために前記基板が各々載置される複数の中継モジュールと、を含むモジュール群と、
前記処理モジュールへの前記基板の搬入及び搬出が共通の搬送機構で行われ、前記中継モジュールへの前記基板への搬入、搬出が互いに異なる搬送機構で行われ、前記モジュール群により構成される基板の搬送経路を順番に前記基板が搬送されるように、当該搬送経路において割り当てられた区間を各々搬送する複数の搬送機構と、
前記複数の搬送機構のうちの一つをなし、前記基板の搬送経路のうちの互いに離れた第1の区間及び第2の区間の搬送に共用され、前記複数の中継モジュールのうち前記第1の区間に含まれる第1の中継モジュール、前記第2の区間に含まれる第2の中継モジュールの各々に前記基板を搬送する共用搬送機構と、
前記第1の中継モジュール、第2の中継モジュールの各々から前記搬送経路の下流側に見て、直近の前記処理モジュールの手前の中継モジュールに至るまでの各区間における前記基板の搬送状況に基づき、前記共用搬送機構が第1の中継モジュール及び第2の中継モジュールのうちのいずれへ前記基板を搬送するかの決定を行う決定部と、
を備える基板処理装置。 - 前記決定部は、前記第1の区間における前記第1の中継モジュールの上流側の中継モジュール及び前記第2の区間における前記第2の中継モジュールの上流側の中継モジュールの各々における前記基板の搬送状況に基づき、前記決定を行う請求項1記載の基板処理装置。
- 前記第1の中継モジュールの上流側の中継モジュール及び前記第2の中継モジュールの上流側の中継モジュールの各々における前記基板の搬送状況は、各中継モジュールに搬送可能な基板の枚数である請求項2記載の基板処理装置。
- 前記決定部は、前記共用搬送機構が直前に前記基板を搬送した区間に応じて、前記決定を行う請求項2記載の基板処理装置。
- 前記直近の前記処理モジュールの手前の中継モジュールに至るまでの各区間における前記基板の搬送状況は、当該各区間における基板の枚数である請求項1記載の基板処理装置。
- 前記第1の中継モジュールから前記搬送経路の下流側に見て直近の前記処理モジュールの手前の中継モジュールに至るまでの区間、あるいは前記第2の中継モジュールから前記搬送経路の下流側に見て直近の前記処理モジュールの手前の中継モジュールに至るまでの区間には、前記共用搬送機構による前記基板の搬送が行われない中継モジュールが含まれる請求項1記載の基板処理装置。
- 前記第1の区間は、前記第1の中継モジュールの上流側に設けられる一の処理モジュールと、当該一の処理モジュールの上流側に設けられる第3の中継モジュールと、を含み、
前記共用搬送機構は、前記一の処理モジュールにおいて処理済みの基板と、前記第3の中継モジュールから搬出した基板との入れ替えを行うために基板を各々保持する複数の保持部を備え、
前記決定部は、当該第1の処理モジュールから処理済みの基板を搬出可能であり、且つ前記第3の中継モジュールに基板が搬送されていない状態で前記決定を行う請求項1記載の基板処理装置。 - 前記決定部は、前記一の処理モジュールから処理済みの基板を搬出可能になってから、前記決定による搬送を行うまでの時間設定を行う請求項7記載の基板処理装置。
- 前記決定部は、
前記搬送経路における前記第1の区間よりも前段で、搬送を受け持つ搬送機構毎に分けられる各区間について、後段の区間へと基板を搬送する予想の時間間隔を算出し、
前記時間設定は、前記各区間の予想の時間間隔に基づいて行われる請求項8記載の基板処理装置。 - 前記予想の時間間隔は、一つの区間に含まれる前記処理モジュールの数と、当該処理モジュールにおいて必要な基板の滞在時間と、に基づいて算出される請求項9記載の基板処理装置。
- 複数の処理モジュールで基板を各々処理する工程と、
前記複数の処理モジュール間で当該基板を受け渡すために複数の中継モジュールに前記基板を各々載置する工程と、
前記処理モジュールへの前記基板の搬入及び搬出を共通の搬送機構で行う工程と、
前記中継モジュールへの前記基板への搬入、搬出を互いに異なる搬送機構で行う工程と、
前記複数の処理モジュールと前記複数の中継モジュールとからなるモジュール群により構成される基板の搬送経路について、複数の搬送機構に各々割り当てられた区間にて基板を搬送し、当該搬送経路にて順番に前記基板を搬送する工程と、
前記複数の搬送機構のうちの一つをなす共用搬送機構により、前記基板の搬送経路のうちの互いに離れた、前記複数の中継モジュールを構成する第1の中継モジュールを含む第1の区間、及び前記複数の中継モジュールを構成する第2の中継モジュールを含む第2の区間の搬送に共用される共用搬送機構により、前記第1の中継モジュール及び第2の中継モジュールへの搬送を行う工程と、
前記第1の中継モジュール、第2の中継モジュールの各々から前記搬送経路の下流側に見て、直近の前記処理モジュールの手前の中継モジュールに至るまでの各区間における前記基板の搬送状況に基づき、前記共用搬送機構が第1の中継モジュール及び第2の中継モジュールのうちのいずれへ前記基板を搬送するかを決定する工程と、
を備える基板処理方法。
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US (1) | US20230152716A1 (ja) |
JP (1) | JP7347658B2 (ja) |
KR (1) | KR20220164746A (ja) |
CN (1) | CN115362530A (ja) |
TW (1) | TW202141677A (ja) |
WO (1) | WO2021205918A1 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005243776A (ja) * | 2004-02-25 | 2005-09-08 | Dainippon Screen Mfg Co Ltd | 基板搬送装置 |
JP2010147424A (ja) * | 2008-12-22 | 2010-07-01 | Tokyo Electron Ltd | 塗布、現像装置、塗布、現像方法及び記憶媒体 |
JP2015060919A (ja) * | 2013-09-18 | 2015-03-30 | 東京エレクトロン株式会社 | 塗布、現像装置、塗布、現像方法及び記憶媒体 |
JP2016066643A (ja) * | 2014-09-22 | 2016-04-28 | 株式会社Screenホールディングス | 基板処理装置、制御方法、およびコンピュータプログラム |
-
2021
- 2021-03-25 TW TW110110741A patent/TW202141677A/zh unknown
- 2021-03-26 KR KR1020227037971A patent/KR20220164746A/ko active Search and Examination
- 2021-03-26 JP JP2022514413A patent/JP7347658B2/ja active Active
- 2021-03-26 US US17/917,503 patent/US20230152716A1/en active Pending
- 2021-03-26 WO PCT/JP2021/013061 patent/WO2021205918A1/ja active Application Filing
- 2021-03-26 CN CN202180026301.XA patent/CN115362530A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005243776A (ja) * | 2004-02-25 | 2005-09-08 | Dainippon Screen Mfg Co Ltd | 基板搬送装置 |
JP2010147424A (ja) * | 2008-12-22 | 2010-07-01 | Tokyo Electron Ltd | 塗布、現像装置、塗布、現像方法及び記憶媒体 |
JP2015060919A (ja) * | 2013-09-18 | 2015-03-30 | 東京エレクトロン株式会社 | 塗布、現像装置、塗布、現像方法及び記憶媒体 |
JP2016066643A (ja) * | 2014-09-22 | 2016-04-28 | 株式会社Screenホールディングス | 基板処理装置、制御方法、およびコンピュータプログラム |
Also Published As
Publication number | Publication date |
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TW202141677A (zh) | 2021-11-01 |
CN115362530A (zh) | 2022-11-18 |
JPWO2021205918A1 (ja) | 2021-10-14 |
KR20220164746A (ko) | 2022-12-13 |
US20230152716A1 (en) | 2023-05-18 |
JP7347658B2 (ja) | 2023-09-20 |
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