WO2021149452A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2021149452A1
WO2021149452A1 PCT/JP2020/048436 JP2020048436W WO2021149452A1 WO 2021149452 A1 WO2021149452 A1 WO 2021149452A1 JP 2020048436 W JP2020048436 W JP 2020048436W WO 2021149452 A1 WO2021149452 A1 WO 2021149452A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
insulating
semiconductor
connecting member
semiconductor element
Prior art date
Application number
PCT/JP2020/048436
Other languages
English (en)
French (fr)
Inventor
沢水 神田
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to US17/755,842 priority Critical patent/US20220384297A1/en
Priority to CN202080092851.7A priority patent/CN114981959A/zh
Priority to JP2021573030A priority patent/JPWO2021149452A1/ja
Priority to DE112020005302.4T priority patent/DE112020005302T5/de
Priority to DE212020000610.5U priority patent/DE212020000610U1/de
Publication of WO2021149452A1 publication Critical patent/WO2021149452A1/ja

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • H01L23/49844Geometry or layout for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • H01L2224/49052Different loop heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • This disclosure relates to semiconductor devices.
  • a first semiconductor element provided on the first insulating member As an example of the semiconductor device, a first semiconductor element provided on the first insulating member, a second insulating member arranged above the first semiconductor element, and a second semiconductor provided on the second insulating member.
  • a semiconductor device having a double-sided heat dissipation structure including an element is known (see, for example, Patent Document 1).
  • This semiconductor device has a configuration in which a first cooler is attached to a first insulating member and a second cooler is attached to a second insulating member.
  • the semiconductor device may be used in a state where either one of the first cooler and the second cooler, for example, the second cooler is omitted.
  • the difference between the thermal resistance from the first semiconductor element to the first cooler and the thermal resistance from the second semiconductor element to the first cooler becomes large.
  • the semiconductor device is driven, the temperature of the first semiconductor element and the second semiconductor element, whichever has the higher thermal resistance, becomes higher, so that the performance of the semiconductor device may not be fully exhibited.
  • An object of the present disclosure is to provide a semiconductor device capable of suppressing an increase in the difference between the thermal resistance from the first semiconductor element to the cooler and the thermal resistance from the second semiconductor element to the cooler.
  • a semiconductor device that solves the above problems has a first insulating main surface and a first insulating back surface that face opposite sides in the thickness direction, and has a first insulating member with the first insulating back surface exposed and the first insulating member.
  • the first driving conductive layer provided on the insulating main surface, the first semiconductor element mounted on the first driving conductive layer, the second insulating main surface facing opposite to each other in the thickness direction, and the second. It has an insulating back surface, the second insulating back surface is exposed, and the thickness of the first insulating member is such that the second insulating main surface faces the first insulating main surface in the thickness direction.
  • the second insulating member arranged apart from each other in the longitudinal direction, the second driving conductive layer provided on the second insulating main surface, the second semiconductor element mounted on the second driving conductive layer, and the above.
  • a connecting member that forms a heat transfer path between at least one of the first insulating member and the first driving conductive layer and at least one of the second insulating member and the second driving conductive layer, and the said.
  • a first semiconductor element, the second semiconductor element, and a sealing resin for sealing the connecting member are provided, and the thermal conductivity of the connecting member is higher than the thermal conductivity of the sealing resin.
  • a heat transfer path from the second semiconductor element to the cooler is formed via the connecting member. Therefore, when the cooler is not attached to the second insulating member on which the second semiconductor element is mounted. In addition, it is possible to suppress an increase in the difference between the thermal resistance from the first semiconductor element to the cooler and the thermal resistance from the second semiconductor element to the cooler.
  • the above semiconductor device it is possible to suppress an increase in the difference between the thermal resistance from the first semiconductor element to the cooler and the thermal resistance from the second semiconductor element to the cooler.
  • FIG. 1 The perspective view of the semiconductor device of this embodiment.
  • the plan view of the semiconductor device of FIG. A side view of the semiconductor device of FIG. A side view of the semiconductor device of FIG. 1 as viewed from a direction different from that of FIG.
  • FIG. 2 is a cross-sectional view taken along the line 8-8 of FIG.
  • the circuit diagram of the semiconductor device of this embodiment Sectional drawing of the semiconductor device of the comparative example.
  • the plan view of the 2nd semiconductor unit of the semiconductor device of the modified example The plan view of the 2nd semiconductor unit of the semiconductor device of the modified example.
  • the plan view of the 2nd semiconductor unit of the semiconductor device of the modified example The plan view of the 2nd semiconductor unit of the semiconductor device of the modified example.
  • the plan view of the 2nd semiconductor unit of the semiconductor device of the modified example The plan view of the 2nd semiconductor unit of the semiconductor device of the modified example.
  • the plan view of the 2nd semiconductor unit of the semiconductor device of the modified example. The plan view of the 2nd semiconductor unit of the semiconductor device of the modified example.
  • Cross-sectional view of the semiconductor device of the modified example Cross-sectional view of the semiconductor device of the modified example.
  • Cross-sectional view of the semiconductor device of the modified example Cross-sectional view of the semiconductor device of the modified example.
  • the plan view of the 1st semiconductor unit of the semiconductor device of the modified example Cross-sectional view of the semiconductor device of the modified example.
  • the configuration of the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 1 to 9.
  • the cooler 200 which will be described later, is omitted in FIG.
  • the sealing resin 70 which will be described later, is omitted in FIGS. 6 and 7.
  • the two directions orthogonal to each other are defined as the x direction and the y direction, respectively, and the directions orthogonal to the x direction and the y direction are defined as the z direction.
  • the z direction is an example of the thickness direction
  • the y direction is an example of the first direction
  • the x direction is an example of the second direction.
  • the semiconductor device 1 encloses a plurality of (four in this embodiment) first semiconductor elements 50A and a plurality of (four in this embodiment) second semiconductor elements 50B. It is a configuration sealed by 70. As shown in FIGS. 1 to 5, when the semiconductor device 1 is attached to the cooler 200, the heat of each of the first semiconductor elements 50A (see FIG. 6) and each of the second semiconductor elements 50B (see FIG. 7) is generated. Move to cooler 200.
  • the sealing resin 70 is made of a resin material having electrical insulation, for example, a black epoxy resin.
  • the sealing resin 70 has a rectangular parallelepiped shape and has resin side surfaces 71 to 74, a first resin main surface 75A, and a second resin main surface 75B.
  • the resin side surface 71 and the resin side surface 72 face opposite to each other in the y direction.
  • the resin side surfaces 71 and 72 extend along the x direction, respectively.
  • the resin side surface 73 and the resin side surface 74 face opposite to each other in the x direction.
  • the resin side surfaces 73 and 74 extend along the y direction, respectively.
  • the first resin main surface 75A and the second resin main surface 75B face each other in the z direction.
  • the cooler 200 is attached to the first resin main surface 75A. Therefore, the second resin main surface 75B is the surface opposite to the cooler 200 in the z direction.
  • the semiconductor device 1 includes a plurality of terminals 80 protruding from the sealing resin 70.
  • Each of the plurality of terminals 80 is made of a metal plate, for example, Cu (copper).
  • the plurality of terminals 80 include a first input terminal 81, a second input terminal 82, an output terminal 83, a first control terminal 84A, a first detection terminal 85A, a second control terminal 84B, and a second detection terminal 85B.
  • the first input terminal 81, the second input terminal 82, and the output terminal 83 each project from the resin side surface 71 in the y direction.
  • the first control terminal 84A, the first detection terminal 85A, the second control terminal 84B, and the second detection terminal 85B each project from the resin side surface 72 in the y direction.
  • the first input terminal 81, the second input terminal 82, and the output terminal 83, and the first control terminal 84A, the first detection terminal 85A, the second control terminal 84B, and the second detection terminal 85B are The sealing resins 70 project from opposite sides in the y direction.
  • the first input terminal 81, the second input terminal 82, and the output terminal 83 are arranged at the same position in the z direction and separated from each other in the x direction.
  • Each terminal 81 to 83 is formed in a flat plate shape with the z direction as the thickness direction.
  • the first control terminal 84A, the first detection terminal 85A, the second control terminal 84B, and the second detection terminal 85B are arranged at the same position in the z direction and separated from each other in the x direction.
  • the first control terminal 84A and the first detection terminal 85A are arranged closer to the resin side surface 74 when viewed from the z direction.
  • the second control terminal 84B and the second detection terminal 85B are arranged closer to the resin side surface 73 when viewed from the z direction.
  • Each terminal 84A, 84B, 85A, 85B is formed in a square columnar shape extending in the y direction.
  • the semiconductor device 1 includes a first semiconductor unit 1A and a second semiconductor unit 1B.
  • the semiconductor device 1 has a configuration in which the first semiconductor unit 1A and the second semiconductor unit 1B face each other in the z direction.
  • the sealing resin 70 is filled between the first semiconductor unit 1A and the second semiconductor unit 1B in the z direction, and surrounds the first semiconductor unit 1A and the second semiconductor unit 1B from the x direction and the y direction. It is configured. That is, a part of the first semiconductor unit 1A and a part of the second semiconductor unit 1B are each exposed in the z direction from the sealing resin 70.
  • the first semiconductor unit 1A includes a first insulating member 10A, a first driving conductive layer 20A, a control conductive layer 40A, and a plurality of (four in this embodiment) first semiconductor elements 50A. It has.
  • the first semiconductor unit 1A is arranged at both ends of the sealing resin 70 in the z direction, whichever is closer to the first resin main surface 75A. That is, in the z direction, the first semiconductor unit 1A is arranged closer to the cooler 200 than the second semiconductor unit 1B.
  • the first insulating member 10A is a substrate having electrical insulating properties formed in a flat plate shape with the z direction as the thickness direction.
  • the shape of the first insulating member 10A viewed from the z direction is rectangular.
  • the first insulating member 10A has a first insulating main surface 10As and a first insulating back surface 10Ar facing opposite sides in the z direction.
  • the first insulating main surface 10As faces the side opposite to the cooler 200 in the z direction. That is, the first insulating main surface 10As faces the same side as the second resin main surface 75B of the sealing resin 70.
  • the first insulating back surface 10Ar faces the cooler 200 in the z direction.
  • the first insulating back surface 10Ar faces the same side as the first resin main surface 75A of the sealing resin 70. As shown in FIG. 8, the first insulating back surface 10Ar of the first insulating member 10A of the first semiconductor unit 1A is exposed in the z direction from the first resin main surface 75A of the sealing resin 70. In the present embodiment, the first insulating back surface 10Ar is flush with the first resin main surface 75A. A cooler 200 is attached to the first insulating back surface 10Ar.
  • the position of the first insulating back surface 10Ar in the z direction with respect to the first resin main surface 75A can be arbitrarily changed.
  • the first insulating back surface 10Ar may be provided so as to project in the z direction from the first resin main surface 75A.
  • the cooler 200 is attached to the first insulating back surface 10Ar. That is, a gap is formed between the cooler 200 and the first resin main surface 75A in the z direction.
  • the first insulating member 10A has insulating side surfaces 11A to 14A.
  • the insulating side surface 11A and the insulating side surface 12A face each other in the y direction. When viewed from the z direction, the insulating side surfaces 11A and 12A extend in the x direction, respectively.
  • the insulating side surface 11A faces the same side as the resin side surface 71 of the sealing resin 70, and the insulating side surface 12A faces the same side as the resin side surface 72 of the sealing resin 70.
  • the insulating side surface 13A and the insulating side surface 14A face each other in the x direction. When viewed from the z direction, the insulating side surfaces 13A and 14A extend in the y direction, respectively.
  • the insulating side surface 13A faces the same side as the resin side surface 73 of the sealing resin 70, and the insulating side surface 14A faces the same side as the resin side surface 74 of the sealing resin 70.
  • the first driving conductive layer 20A and the controlling conductive layer 40A are each formed on the first insulating main surface 10As of the first insulating member 10A.
  • Each of the conductive layers 20A and 40A is made of, for example, Cu.
  • the first driving conductive layer 20A and the controlling conductive layer 40B are arranged apart from each other on the first insulating main surface 10As.
  • the first drive conductive layer 20A has a first drive wiring 21 and a second drive wiring 22.
  • the first drive wiring 21 and the second drive wiring 22 are arranged apart from each other on the first insulating main surface 10As.
  • the first drive wiring 21 is arranged near the insulating side surface 11A in the y direction and near the insulating side surface 14A in the x direction of the first insulating main surface 10As.
  • the shape of the first driving conductive layer 20A viewed from the z direction is a rectangular shape in which the x direction is the long side direction and the y direction is the short side direction.
  • the first input terminal 81 is connected to the first drive wiring 21. More specifically, a first conductive bonding material (not shown) such as solder or Ag paste is formed on the first drive wiring 21. A conductive connection layer (not shown) is mounted on the first conductive bonding material. A second conductive bonding material (not shown) such as solder or Ag paste is formed on the connecting layer. The first input terminal 81 is mounted on the second conductive joint material. In this way, the first input terminal 81 is electrically connected to the first driving conductive layer 20A via each conductive bonding material and connecting layer.
  • the connecting layer is made of, for example, a metal material, and in the present embodiment, is made of Cu.
  • An example of the connecting layer is formed in a columnar shape.
  • the connecting layer is, for example, a quadrangular prism.
  • the shape of the connecting layer is not limited to this, and may be a polygonal prism other than a square prism such as a cylinder or a triangular prism.
  • a plurality of first semiconductor elements 50A are mounted on the first drive wiring 21.
  • the plurality of first semiconductor elements 50A are arranged at the same position in the y direction and separated from each other in the x direction.
  • the maximum value of the deviation amount of the plurality of first semiconductor elements 50A in the y direction is within 10% of the dimension of the first semiconductor element 50A in the y direction, the plurality of first semiconductor elements 50A are in the y direction. It can be said that they are in the same position as each other.
  • each first semiconductor element 50A is arranged at the center of the first drive wiring 21 in the y direction.
  • the arrangement position of each first semiconductor element 50A in the first drive wiring 21 can be arbitrarily changed.
  • each first semiconductor element 50A may be arranged closer to the insulating side surface 12A than the center of the first drive wiring 21 in the y direction.
  • Each first semiconductor element 50A is a switching element, for example, Si (silicon), SiC (silicon carbide), GaN (gallium nitride), GaAs (gallium arsenide), or Ga 2 O 3 (gallium oxide).
  • a transistor consisting of such as is used.
  • each first semiconductor element 50A is made of SiC, it is suitable for speeding up switching.
  • each first semiconductor element 50A uses an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) made of SiC.
  • the first semiconductor element 50A is not limited to MOSFETs, and is a transistor such as a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor including an IGBT (Insulated Gate Bipolar Transistor). May be good.
  • Each first semiconductor element 50A may be a P-channel MOSFET instead of the N-channel MOSFET.
  • the first semiconductor element 50A is arranged closer to the first insulating member 10A than the second semiconductor element 50B in the z direction.
  • the first semiconductor element 50A is arranged between the first insulating member 10A and the second insulating member 10B in the z direction closer to the first insulating member 10A than the second insulating member 10B.
  • the first semiconductor element 50A has a first element main surface 50As and a first element back surface 50Ar facing opposite sides in the z direction.
  • the first element main surface 50As faces the same side as the first insulating main surface 10As. In other words, the first element main surface 50As faces the same side as the second resin main surface 75B.
  • the back surface 50Ar of the first element faces the same side as the back surface 10Ar of the first insulation. In other words, the back surface 50Ar of the first element faces the same side as the main surface 75A of the first resin.
  • a drain electrode 51A which is an example of the first back surface side drive electrode, is formed on the first insulating back surface 10Ar.
  • a source electrode 52A and a gate electrode 53A which are examples of the first main surface side drive electrode, are formed on the first element main surface 50As.
  • the back surface 50Ar of the first element of each first semiconductor element 50A is bonded to the first driving conductive layer 20A by a conductive bonding material JA such as solder or Ag paste. As a result, the drain electrode 51A of each first semiconductor element 50A is electrically connected to the first driving conductive layer 20A.
  • the second drive wiring 22 is formed so as to surround the first drive wiring 21 from the vicinity of the insulating side surface 13A and the vicinity of the insulating side surface 12A.
  • the shape of the second drive wiring 22 as viewed from the z direction is L-shaped.
  • the second drive wiring 22 has a main wiring portion 22a extending in the x direction and a connection wiring portion 22b extending in the y direction from the main wiring portion 22a.
  • the main wiring portion 22a and the connection wiring portion 22b are a single member integrally formed.
  • the main wiring portion 22a is arranged closer to the insulating side surface 12A than the first drive wiring 21 in the y direction.
  • the shape of the main wiring portion 22a viewed from the z direction is a rectangular shape in which the x direction is the long side direction and the y direction is the short side direction.
  • the main wiring portion 22a has a portion that overlaps with the first drive wiring 21 when viewed from the y direction.
  • the main wiring portion 22a and the first drive wiring 21 are displaced from each other in the x direction. More specifically, the main wiring portion 22a has a portion protruding closer to the insulating side surface 13A than the first drive wiring 21 in the x direction.
  • the first drive wiring 21 has a portion protruding closer to the insulating side surface 14A than the main wiring portion 22a in the x direction.
  • connection wiring portion 22b extends from both ends of the main wiring portion 22a in the x direction near the insulating side surface 13A toward the insulating side surface 11A.
  • the shape of the connection wiring portion 22b viewed from the z direction is a rectangular shape in which the y direction is the long side direction and the x direction is the short side direction.
  • the connection wiring portion 22b is arranged closer to the insulating side surface 14A than the first drive wiring 21, and is arranged so as to overlap the first drive wiring 21 when viewed from the x direction.
  • the second input terminal 82 is connected to the connection wiring portion 22b.
  • the connection structure between the connection wiring portion 22b and the second input terminal 82 is the same as the connection structure between the first drive conductive layer 20A and the first input terminal 81.
  • the control conductive layer 40A has a control wiring 41A and a detection wiring 42A.
  • the control wiring 41A and the detection wiring 42A are arranged apart from each other on the first insulating main surface 10As.
  • the control wiring 41A and the detection wiring 42A are formed so as to surround the main wiring portion 22a of the second drive wiring 22 from the insulating side surface 11A, the insulating side surface 14A, and the insulating side surface 12A, respectively.
  • the shape of each of the control wiring 41A and the detection wiring 42A when viewed from the z direction is substantially U-shaped.
  • the detection wiring 42A is arranged closer to the main wiring portion 22a of the second drive wiring 22 than the control wiring 41A.
  • the control wiring 41A is formed so as to surround the detection wiring 42A from the insulating side surface 11A, the insulating side surface 14A, and the insulating side surface 12A.
  • the first control terminal 84A is connected to the control wiring 41A.
  • the first detection terminal 85A is connected to the detection wiring 42A.
  • the joint structure between the control wiring 41A and the first control terminal 84A and the joint structure between the detection wiring 42A and the first detection terminal 85A are the first drive conductive layer 20A and the first, respectively. 1
  • the connection structure with the input terminal 81 is the same.
  • the first control terminal 84A is arranged closer to the insulating side surface 14A than the first detection terminal 85A.
  • the arrangement positions of the first control terminal 84A and the first detection terminal 85A as viewed from the z direction can be arbitrarily changed.
  • the first detection terminal 85A may be arranged closer to the insulating side surface 14A than the first control terminal 84A when viewed from the z direction.
  • the first semiconductor unit 1A includes a wire W1 connecting the source electrode 52A of each first semiconductor element 50A and the detection wiring 42A, a gate electrode 53A of each first semiconductor element 50A, and control. It has a wire W2 for connecting to the wiring 41A.
  • the wires W1 and W2 are each made of, for example, Au (gold).
  • the wires W1 and W2 may be made of Cu or Al (aluminum), respectively.
  • the source electrode 52A of each first semiconductor element 50A and the detection wiring 42A are electrically connected via the wire W2.
  • the gate electrode 53A of each first semiconductor element 50A and the control wiring 41A are electrically connected via the wire W1.
  • the second semiconductor unit 1B includes a second insulating member 10B, a second driving conductive layer 20B, a control conductive layer 40B, and a plurality of (four in this embodiment) second semiconductor elements 50B. And a second connecting layer 60B is provided.
  • the second semiconductor unit 1B is arranged at both ends of the sealing resin 70 in the z direction, whichever is closer to the second resin main surface 75B. That is, the second semiconductor unit 1B is arranged at a position far from the cooler 200.
  • the second insulating member 10B is a substrate having electrical insulation and formed in a flat plate shape with the z direction as the thickness direction.
  • the second insulating member 10B is arranged so as to face the first insulating member 10A in the z direction while being separated from the first insulating member 10A in the z direction.
  • the shape of the second insulating member 10B when viewed from the z direction is rectangular.
  • the second insulating member 10B has a second insulating main surface 10Bs and a second insulating back surface 10Br facing opposite sides in the z direction.
  • the second insulating back surface 10Br faces the side opposite to the cooler 200 in the z direction.
  • the second insulating back surface 10Br faces the same side as the second resin main surface 75B of the sealing resin 70.
  • the second insulating back surface 10Br of the second insulating member 10B of the second semiconductor unit 1B is exposed in the z direction from the second resin main surface 75B of the sealing resin 70.
  • the second insulating back surface 10Br is flush with the second resin main surface 75B.
  • the second insulating main surface 10Bs faces the cooler 200 in the z direction. That is, the second insulating main surface 10Bs faces the same side as the first resin main surface 75A of the sealing resin 70. Further, it can be said that the second insulating main surface 10Bs is arranged so as to face the first insulating main surface 10As of the first insulating member 10A in the z direction.
  • the position of the second insulating back surface 10Br with respect to the second resin main surface 75B in the z direction can be arbitrarily changed.
  • the second insulating back surface 10Br may be provided so as to project from the second resin main surface 75B in the z direction.
  • the second insulating member 10B has insulating side surfaces 11B to 14B.
  • the insulating side surface 11B and the insulating side surface 12B face each other in the y direction. When viewed from the z direction, the insulating side surfaces 11B and 12B each extend in the x direction.
  • the insulating side surface 11B faces the same side as the resin side surface 71 of the sealing resin 70, and the insulating side surface 12B faces the same side as the resin side surface 72 of the sealing resin 70. Therefore, the insulating side surface 11B faces the same side as the insulating side surface 11A of the first insulating member 10A, and the insulating side surface 12B faces the same side as the insulating side surface 12A of the first insulating member 10A.
  • the insulating side surface 13B and the insulating side surface 14B face each other in the x direction. When viewed from the z direction, the insulating side surfaces 13B and 14B each extend in the y direction.
  • the insulating side surface 13B faces the same side as the resin side surface 73 of the sealing resin 70, and the insulating side surface 14B faces the same side as the resin side surface 74 of the sealing resin 70. Therefore, the insulating side surface 13B faces the same side as the insulating side surface 13A of the first insulating member 10A, and the insulating side surface 14B faces the same side as the insulating side surface 14A of the first insulating member 10A.
  • the second driving conductive layer 20B and the controlling conductive layer 40B are each formed on the second insulating main surface 10Bs of the second insulating member 10B.
  • Each of the conductive layers 20B and 40B is made of, for example, Cu.
  • the second driving conductive layer 20B and the controlling conductive layer 40B are arranged apart from each other on the second insulating main surface 10Bs.
  • the second driving conductive layer 20B is arranged closer to the insulating side surface 11B in the y direction of the second insulating main surface 10Bs of the second insulating member 10B.
  • the second driving conductive layer 20B is formed over most of the second insulating main surface 10Bs.
  • the shape of the second driving conductive layer 20B viewed from the z direction is rectangular.
  • the output terminal 83 is connected to the second drive conductive layer 20B.
  • the connection structure between the second drive conductive layer 20B and the output terminal 83 is the same as the connection structure between the first drive conductive layer 20A and the first input terminal 81. That is, as shown in FIG. 8, a first conductive bonding material JE1 such as solder or Ag paste is formed on the second driving conductive layer 20B.
  • a conductive connecting layer 30 is mounted on the first conductive bonding material JE1.
  • a second conductive bonding material JE2 such as solder or Ag paste is formed on the connecting layer 30.
  • An output terminal 83 is mounted on the second conductive bonding material JE2.
  • the output terminal 83 is electrically connected to the second driving conductive layer 20B via the conductive bonding materials JE1 and JE2 and the connecting layer 30.
  • the connection layer 30 is made of, for example, a metal material, and in the present embodiment, is made of Cu.
  • An example of the connecting layer 30 is formed in a columnar shape.
  • the connecting layer 30 is, for example, a quadrangular prism.
  • the shape of the connecting layer 30 is not limited to this, and may be a polygonal prism other than a square prism such as a cylinder or a triangular prism.
  • each of the second semiconductor elements 50B is arranged closer to the insulating side surface 12B and closer to the insulating side surface 13B of the second driving conductive layer 20B. Specifically, each of the second semiconductor elements 50B is arranged in a region R of the second drive conductive layer 20B facing the main wiring portion 22a of the second drive wiring 22 of the first semiconductor unit 1A in the z direction. There is.
  • the plurality of second semiconductor elements 50B are arranged at the same position in the y direction and separated from each other in the x direction.
  • the maximum value of the deviation amount in the y direction of the plurality of second semiconductor elements 50B is within 10% of the dimension of the second semiconductor element 50B in the y direction
  • the plurality of second semiconductor elements 50B are in the y direction. It can be said that they are in the same position as each other.
  • the second semiconductor element 50B is arranged apart from the first semiconductor element 50A in the y direction. When viewed from the z direction, the plurality of first semiconductor elements 50A and the plurality of second semiconductor elements 50B are displaced from each other in the x direction.
  • the plurality of first semiconductor elements 50A are arranged so as to be offset from the resin side surface 74 with respect to the plurality of second semiconductor elements 50B. When viewed from the y direction, each of the first semiconductor elements 50A and each of the second semiconductor elements 50B are arranged so as to partially overlap each other.
  • each second semiconductor element 50B for example, a transistor made of Si, SiC, GaN, GaAs, Ga 2 O 3, or the like is used.
  • each second semiconductor element 50B is made of SiC, it is suitable for speeding up switching.
  • each second semiconductor element 50B uses an N-channel MOSFET made of SiC.
  • the second semiconductor element 50B is not limited to the MOSFET, and may be a transistor such as a field effect transistor including a MISFET or a bipolar transistor including an IGBT.
  • Each second semiconductor element 50B may be a P-channel MOSFET instead of the N-channel MOSFET.
  • the second semiconductor element 50B is arranged closer to the second insulating member 10B than the first semiconductor element 50A in the z direction.
  • the second semiconductor element 50B is arranged between the first insulating member 10A and the second insulating member 10B in the z direction closer to the second insulating member 10B than the first insulating member 10A.
  • the second semiconductor element 50B has a second element main surface 50Bs and a second element back surface 50Br facing opposite sides in the z direction.
  • the second element main surface 50Bs faces the same side as the second insulating main surface 10Bs. In other words, the second element main surface 50Bs faces the same side as the first resin main surface 75A.
  • the back surface 50Br of the second element faces the same side as the back surface 10Br of the second insulation. In other words, the back surface 50Br of the second element faces the same side as the main surface 75B of the second resin.
  • the arrangement direction of the second semiconductor element 50B in the z direction is opposite to the arrangement direction of the first semiconductor element 50A.
  • a drain electrode 51B which is an example of a second back surface side drive electrode, is formed on the second insulating back surface 10Br.
  • a source electrode 52B and a gate electrode 53B which are examples of the second main surface side drive electrode, are formed on the second element main surface 50Bs.
  • each second semiconductor element 50B is bonded to the second drive conductive layer 20B by a conductive bonding material JB such as solder or Ag paste.
  • a conductive bonding material JB such as solder or Ag paste.
  • the control conductive layer 40B is arranged between the second driving conductive layer 20B and the insulating side surface 12B in the y direction of the second insulating main surface 10Bs of the second insulating member 10B.
  • the control conductive layer 40B has a control wiring 41B and a detection wiring 42B.
  • the shapes of the control wiring 41B and the detection wiring 42B viewed from the z direction are strips extending in the x direction, respectively.
  • the control wiring 41B and the detection wiring 42B are arranged at the same position in the x direction and separated from each other in the y direction.
  • the control wiring 41B is arranged closer to the second drive conductive layer 20B than the detection wiring 42B.
  • the second control terminal 84B is connected to the control wiring 41B.
  • a second detection terminal 85B is connected to the detection wiring 42B.
  • the joint structure between the control wiring 41B and the second control terminal 84B and the joint structure between the detection wiring 42B and the second detection terminal 85B are the first drive conductive layer 20A and the second, respectively. 1
  • the connection structure with the input terminal 81 is the same.
  • the second detection terminal 85B is arranged closer to the insulating side surface 13A than the second control terminal 84B.
  • the arrangement positions of the second control terminal 84B and the second detection terminal 85B can be arbitrarily changed when viewed from the z direction.
  • the second control terminal 84B may be arranged closer to the insulating side surface 13A than the second detection terminal 85B when viewed from the z direction.
  • the second semiconductor unit 1B includes a wire W3 that connects the source electrode 52B of each second semiconductor element 50B and the detection wiring 42B, a gate electrode 53B of each second semiconductor element 50B, and a control. It has a wire W4 for connecting to the wiring 41B.
  • the wires W3 and W4 are each made of, for example, Au.
  • the wires W3 and W4 may be made of Cu or Al, respectively.
  • the source electrode 52B of each second semiconductor element 50B and the detection wiring 42B are electrically connected.
  • the gate electrode 53B of each second semiconductor element 50B and the control wiring 41B are electrically connected.
  • the source electrodes 52A of the plurality of first semiconductor elements 50A are electrically connected to the second driving conductive layer 20B of the second semiconductor unit 1B, respectively. More specifically, a first conductive bonding material JA1 such as solder or Ag paste is arranged on the source electrode 52A. A conductive first connecting layer 60A is placed on the first conductive bonding material JA1. A second conductive bonding material JA2 such as solder or Ag paste is arranged at a portion of the second drive wiring 22 facing the first connection layer 60A in the z direction. The second conductive bonding material JA2 is in contact with the first connecting layer 60A.
  • a first conductive bonding material JA1 such as solder or Ag paste is arranged on the source electrode 52A.
  • a conductive first connecting layer 60A is placed on the first conductive bonding material JA1.
  • a second conductive bonding material JA2 such as solder or Ag paste is arranged at a portion of the second drive wiring 22 facing the first connection layer 60A in the z direction. The
  • the first connecting layer 60A is joined to the source electrode 52A and the second driving conductive layer 20B by the conductive bonding materials JA1 and JA2.
  • the source electrode 52A and the second driving conductive layer 20B are electrically connected to each other via the conductive bonding materials JA1 and JA2 and the first connecting layer 60A.
  • the first connection layer 60A is made of, for example, a metal material, and in this embodiment, it is made of Cu.
  • An example of the first connection layer 60A is formed in a columnar shape.
  • the first connecting layer 60A is, for example, a quadrangular prism.
  • the shape of the first connecting layer 60A is not limited to this, and may be a polygonal prism other than a square prism such as a cylinder or a triangular prism.
  • the thickness of the first connection layer 60A (the dimension of the first connection layer 60A in the z direction) is the thickness of the first semiconductor element 50A (the z direction of the first semiconductor element 50A). Dimension) thicker than.
  • the source electrodes 52B of the plurality of second semiconductor elements 50B are electrically connected to the second drive wiring 22 of the first drive conductive layer 20A of the first semiconductor unit 1A, respectively. More specifically, a first conductive bonding material JB1 such as solder or Ag paste is arranged on the source electrode 52B. A conductive second connecting layer 60B is placed on the first conductive bonding material JB1. A second conductive bonding material JB2 such as solder or Ag paste is arranged at a portion of the second drive wiring 22 facing the second connection layer 60B in the z direction. The second conductive bonding material JB2 is in contact with the second connecting layer 60B.
  • a first conductive bonding material JB1 such as solder or Ag paste is arranged on the source electrode 52B.
  • a conductive second connecting layer 60B is placed on the first conductive bonding material JB1.
  • a second conductive bonding material JB2 such as solder or Ag paste is arranged at a portion of the second drive wiring 22 facing the second connection layer 60B in
  • the second connection layer 60B is joined to the source electrode 52B and the second drive wiring 22 by the conductive bonding materials JB1 and JB2. In this way, the source electrode 52B and the second drive wiring 22 are electrically connected via the conductive bonding materials JB1 and JB2 and the second connecting layer 60B.
  • the second connection layer 60B is made of, for example, a metal material, and is made of Cu in this embodiment.
  • An example of the second connecting layer 60B is formed in a columnar shape.
  • the second connecting layer 60B is, for example, a quadrangular prism.
  • the shape of the second connecting layer 60B is not limited to this, and may be a polygonal prism other than a square prism such as a cylinder or a triangular prism.
  • the thickness of the second connection layer 60B (the dimension of the second connection layer 60B in the z direction) is the thickness of the second semiconductor element 50B (the z direction of the second semiconductor element 50B). Dimension) thicker than.
  • the thickness of the first connection layer 60A and the thickness of the second connection layer 60B can be changed arbitrarily. In one example, the thickness of the first connection layer 60A may be less than or equal to the thickness of the first semiconductor element 50A. The thickness of the second connection layer 60B may be less than or equal to the thickness of the second semiconductor element 50B.
  • the circuit configuration of the semiconductor device 1 having such a configuration is a half-bridge type in which four first semiconductor elements 50A connected in parallel to each other and four second semiconductor elements 50B connected in parallel to each other are connected in series.
  • Inverter circuit FIG. 9 shows an example of the inverter circuit of the semiconductor device 1.
  • four first semiconductor elements 50A connected in parallel to each other are shown as one first semiconductor element 50A
  • four second semiconductor elements 50B connected in parallel to each other are shown as one second semiconductor element. It is shown as 50B.
  • the drain electrode 51A of the first semiconductor element 50A is electrically connected to the first input terminal 81.
  • the source electrode 52A of the first semiconductor element 50A is electrically connected to the drain electrode 51B of the second semiconductor element 50B.
  • An output terminal 83 is connected to the node N of the source electrode 52A of the first semiconductor element 50A and the drain electrode 51B of the second semiconductor element 50B.
  • the source electrode 52B of the second semiconductor element 50B is electrically connected to the second input terminal 82.
  • the gate electrode 53A of the first semiconductor element 50A is connected to the first control terminal 84A.
  • the gate electrode 53B of the second semiconductor element 50B is connected to the second control terminal 84B.
  • the first detection terminal 85A is connected to the node NA between the source electrode 52A and the node N of the first semiconductor element 50A.
  • a second detection terminal 85B is connected to the node NB between the source electrode 52B of the second semiconductor element 50B and the second input terminal 82.
  • the semiconductor device 1 includes a connecting member 90 that connects the first driving conductive layer 20A and the second driving conductive layer 20B.
  • the connecting member 90 is joined to each of the first driving conductive layer 20A and the second driving conductive layer 20B by, for example, an adhesive (not shown).
  • the thermal conductivity of the connecting member 90 is higher than the thermal conductivity of the sealing resin 70. Further, the thermal conductivity of the connecting member 90 is higher than the thermal conductivity of air.
  • the thermal conductivity of the connecting member 90 is preferably 10 W / mK or more.
  • the connecting member 90 is made of a material having electrical insulation, and is made of a material having excellent heat dissipation such as Si or ceramics such as alumina and aluminum nitride. In this embodiment, the connecting member 90 is made of ceramics.
  • the connecting member 90 is a member for assisting heat dissipation of the semiconductor element (in this embodiment, each second semiconductor element 50B of the second semiconductor unit 1B) of the semiconductor unit to which the cooler 200 is not attached. In the present embodiment, the connecting member 90 forms a heat transfer path between the second drive wiring 22 of the first drive conductive layer 20A and the second drive conductive layer 20B.
  • the connecting member 90 is arranged on the side opposite to the control conductive layer 40B with respect to the second semiconductor element 50B in the y direction.
  • the connecting member 90 is arranged between the first semiconductor element 50A and the second semiconductor element 50B in the y direction. More specifically, the connecting member 90 is arranged closer to the second semiconductor element 50B than the first semiconductor element 50A in the y direction.
  • the connecting member 90 is arranged at a position adjacent to the second semiconductor element 50B in the y direction. As shown in FIG. 7, the connecting member 90 is arranged in the region R.
  • the connecting member 90 extends in the x direction so as to face all the second semiconductor elements 50B in the y direction. That is, the connecting member 90 is arranged so as to be adjacent to all the second semiconductor elements 50B in the y direction.
  • the shape of the connecting member 90 when viewed from the z direction is a rectangular shape in which the x direction is the long side direction and the y direction is the short side direction.
  • the size of the connecting member 90 in the y direction is smaller than the size of the second semiconductor element 50B in the y direction.
  • the connecting member 90 of the present embodiment is composed of a flat plate-shaped block having the y direction as the thickness direction.
  • FIG. 10 shows the cross-sectional structure of the semiconductor device 1X of the comparative example.
  • the semiconductor device 1X of the comparative example has a configuration in which the connecting member 90 is omitted from the semiconductor device 1 of the present embodiment. Therefore, in the semiconductor device 1X of the comparative example, the components common to the semiconductor device 1 are designated by the same reference numerals, and the description thereof will be omitted.
  • each of the first semiconductor element 50A and each second semiconductor element 50B When each of the first semiconductor element 50A and each second semiconductor element 50B is driven in the semiconductor device 1X, each of the first semiconductor element 50A and each second semiconductor element 50B generates heat. Since the cooler 200 is attached to the first insulating member 10A of the first semiconductor unit 1A, the heat of each first semiconductor element 50A is as shown by the arrow YX1 in FIG. It moves to the cooler 200 via the first drive wiring 21 of the drive conductive layer 20A and the first insulating member 10A. Further, since the cooler 200 is not attached to the second insulating member 10B of the second semiconductor unit 1B, the heat of each second semiconductor element 50B is the heat of the first conductive bonding material JB1 as shown by the arrow YX2 in FIG.
  • the second connecting layer 60B, the second conductive bonding material JB2, the second driving wiring 22 of the first driving conductive layer 20A, and the first insulating member 10A move to the cooler 200.
  • the thermal resistance from each of the second semiconductor elements 50B to the cooler 200 is higher than the thermal resistance from each of the first semiconductor elements 50A to the cooler 200.
  • each of the second semiconductor elements 50B is less likely to dissipate heat than each of the first semiconductor elements 50A, and tends to have a higher temperature than each of the first semiconductor elements 50A.
  • the heat of each of the first semiconductor elements 50A is conductively bonded as shown by the arrow Y1 in FIG. It moves to the cooler 200 via the material JA, the first drive wiring 21 of the first drive conductive layer 20A, and the first insulating member 10A.
  • each second semiconductor element 50B is transferred to the cooler 200 via the two heat transfer paths. More specifically, as shown by the arrow Y2 in FIG. 8, the heat of each second semiconductor element 50B is the first conductive bonding material JB1, the second connecting layer 60B, the second conductive bonding material JB2, and the first driving conductive material. It moves to the cooler 200 via the second drive wiring 22 of the layer 20A and the first insulating member 10A. Further, as shown by the arrow Y3 in FIG. 8, the heat of each second semiconductor element 50B is transferred to the conductive bonding material JB, the second drive conductive layer 20B, the connecting member 90, the second drive wiring 22 of the first drive conductive layer 20A, and the like.
  • each second semiconductor element 50B It moves to the cooler 200 via the first insulating member 10A.
  • the cooler is transferred from each second semiconductor element 50B. It is possible to suppress an increase in the difference between the thermal resistance up to 200 and the thermal resistance from each first semiconductor element 50A to the cooler 200.
  • each of the second semiconductor elements 50B has the same heat dissipation performance as each of the first semiconductor elements 50A, and it is possible to suppress that the temperature tends to be higher than that of each of the first semiconductor elements 50A.
  • the semiconductor device 1 seals a connecting member 90 connecting the first driving conductive layer 20A and the second driving conductive layer 20B, and the first semiconductor element 50A, the second semiconductor element 50B, and the connecting member 90.
  • the sealing resin 70 and the sealing resin 70 are provided.
  • the connecting member 90 forms a heat transfer path from each second semiconductor element 50B to the cooler 200.
  • the thermal conductivity of the connecting member 90 is higher than the thermal conductivity of the sealing resin 70. According to this configuration, the heat transfer path between the second semiconductor element 50B and the cooler 200, which is farther from the cooler 200 than the first semiconductor element 50A, can be increased, so that the first semiconductor element 50A in the semiconductor device 1 is cooled.
  • the connecting member 90 is connected to the second driving conductive layer 20B. According to this configuration, the heat of the second semiconductor element 50B is transferred from the second driving conductive layer 20B to the connecting member 90, so that the heat transfer path is shortened. Therefore, the heat of the second semiconductor element 50B is easily transferred to the connecting member 90.
  • the connecting member 90 When viewed from the z direction, the connecting member 90 is arranged closer to the second semiconductor element 50B than to the first semiconductor element 50A. According to this configuration, the heat of the second semiconductor element 50B is more likely to be transferred to the connecting member 90 than the heat of the first semiconductor element 50A, so that the temperature of the second semiconductor element 50B is likely to be higher than that of the first semiconductor element 50A. It can be suppressed.
  • a source electrode 52B is formed on the second element main surface 50Bs of the second semiconductor element 50B, and is connected to the second drive wiring 22 of the first drive conductive layer 20A via the second connection layer 60B. There is. According to this configuration, the heat of the second semiconductor element 50B is transferred to the cooler 200 via the second connection layer 60B, the second drive wiring 22, and the first insulating member 10A. Therefore, it is possible to prevent the temperature of the second semiconductor element 50B from becoming excessively high.
  • a source electrode 52A is formed on the first element main surface 50As of the first semiconductor element 50A, and is connected to the second drive conductive layer 20B via the first connection layer 60A. According to this configuration, the heat of the first semiconductor element 50A is transferred to the first connecting layer 60A, the second driving conductive layer 20B, and the second insulating member 10B, so that the temperature of the first semiconductor element 50A becomes excessively high. Can be suppressed.
  • the connecting member 90 When viewed from the y direction, the connecting member 90 is arranged so as to overlap all of the plurality of second semiconductor elements 50B. According to this configuration, since the heat of the plurality of second semiconductor elements 50B is transferred to the connecting member 90, the temperature variation of the plurality of second semiconductor elements 50B can be suppressed.
  • the connecting member 90 is arranged so that all of the plurality of second semiconductor elements 50B are adjacent to each other in the y direction. According to this configuration, the heat of the plurality of second semiconductor elements 50B can be easily transferred to the connecting member 90, respectively. Therefore, it is possible to prevent the temperatures of the plurality of second semiconductor elements 50B from becoming excessively high.
  • the connecting member 90 is arranged on the side opposite to the control conductive layer 40B. According to this configuration, since it is not necessary to form the wires W3 and W4 so as to avoid the connecting member 90, the wires W3 and W4 can be easily formed and the lengths of the wires W3 and W4 can be shortened. ..
  • the first insulating member 10A and the second insulating member 10B are each made of ceramics. According to this configuration, the heat of each of the first semiconductor elements 50A and each of the second semiconductor elements 50B is easily transferred from the first insulating member 10A to the cooler 200. Further, the heat of each of the first semiconductor elements 50A and each of the second semiconductor elements 50B can be easily dissipated to the outside through the second insulating member 10B.
  • the first input terminal 81, the second input terminal 82, and the output terminal 83 each project from the resin side surface 74 of the sealing resin 70. According to this configuration, when the semiconductor device 1 is mounted on a mounting board and, for example, a snubber capacitor is provided on the mounting board, wiring for connecting the semiconductor device 1 and the snubber capacitor can be easily formed.
  • the size of the connecting member 90 in the y direction is smaller than the size of the second semiconductor element 50B in the y direction. According to this configuration, it is possible to suppress an increase in the size of the second drive wiring 22 of the first drive conductive layer 20A in the y direction, so that it is possible to suppress an increase in the size of the semiconductor device 1 in the y direction.
  • the above-described embodiment is an example of possible embodiments of the semiconductor device according to the present disclosure, and is not intended to limit the embodiments.
  • the semiconductor device according to the present disclosure may take a form different from the form exemplified in the above embodiment.
  • An example thereof is a form in which a part of the configuration of the above embodiment is replaced, changed, or omitted, or a new configuration is added to the above embodiment.
  • the following modification examples can be combined with each other as long as they are not technically inconsistent.
  • the parts common to the above-described embodiment are designated by the same reference numerals as those in the above-described embodiment, and the description thereof will be omitted.
  • the size of the sealing resin 70 in the x direction and the size in the y direction can be arbitrarily changed.
  • the sealing resin 70 may be formed so that the insulating side surfaces 11A to 14A of the first insulating member 10A are exposed.
  • the sealing resin 70 may be formed so that the insulating side surfaces 11B to 14B of the second insulating member 10B are exposed.
  • At least one of the adhesive between the connecting member 90 and the first driving conductive layer 20A and the adhesive between the connecting member 90 and the second driving conductive layer 20B may be omitted. ..
  • the adhesive between the connecting member 90 and the first driving conductive layer 20A is omitted, the connecting member 90 and the first driving conductive layer 20A are in contact with each other.
  • the adhesive between the connecting member 90 and the second driving conductive layer 20B is omitted, the connecting member 90 and the second driving conductive layer 20B are in contact with each other.
  • the dimensions of the connecting member 90 in the y direction can be arbitrarily changed.
  • the dimension of the connecting member 90 in the y direction may be larger than the dimension of the connecting member 90 of the above embodiment in the y direction.
  • each of the second semiconductor elements 50B is arranged at both ends of the second driving conductive layer 20B in the y direction, whichever is closer to the insulating side surface 12B.
  • the space in which the connecting member 90 can be arranged can be expanded in the y direction in the area R (see FIG. 7).
  • the connecting member 90 is contained in the region R.
  • the length of the connecting member 90 in the x direction can be arbitrarily changed.
  • the length of the connecting member 90 in the x direction may be such that it faces a part of the second semiconductor elements 50B among the plurality of second semiconductor elements 50B in the y direction.
  • the shape of the connecting member 90 viewed from the z direction can be arbitrarily changed.
  • the shape of the connecting member 90 as viewed from the z direction may be changed as follows (A) to (C), for example.
  • the connecting member 90 is attached to each of the main facing wall 91 facing all the second semiconductor elements 50B in the y direction and the second semiconductor elements 50B arranged at both ends in the x direction. It has an end facing wall 92 that faces in the x direction.
  • the connecting member 90 is a single component in which the main facing wall 91 and the end facing wall 92 are integrally formed.
  • the main facing wall 91 is arranged at a position adjacent to the second semiconductor element 50B in the y direction, and extends along the x direction.
  • the end facing wall 92 extends along the y direction from both ends of the main facing wall 91 in the x direction.
  • the end facing walls 92 are arranged at positions adjacent to each of the second semiconductor elements 50B arranged at both ends in the x direction in the x direction.
  • the end facing wall 92 is provided so as to overlap all of the second semiconductor elements 50B when viewed from the x direction.
  • each second semiconductor element 50B is driven by increasing the volume of the connecting member 90 as compared with the connecting member 90 in which the end facing wall 92 is omitted.
  • the heat of the semiconductor element 50B is easily transferred to the connecting member 90.
  • the connecting member 90 may be configured so that the main facing wall 91 and at least one of the two end facing walls 92 are separated from each other.
  • the connecting member 90 is arranged between the main facing wall 91 facing all the second semiconductor elements 50B in the y direction and the second semiconductor elements 50B adjacent to each other in the x direction. It has a plurality of (three in the illustrated example) intermediate facing walls 93.
  • the connecting member 90 is a single component in which the main facing wall 91 and the intermediate facing wall 93 are integrally formed.
  • the main facing wall 91 is arranged at a position adjacent to the second semiconductor element 50B in the y direction, and extends along the x direction.
  • Each intermediate facing wall 93 extends from the main facing wall 91 along the y direction.
  • Each intermediate facing wall 93 faces the second semiconductor element 50B in the x direction.
  • Each intermediate facing wall 93 is provided so as to overlap all of the second semiconductor elements 50B when viewed from the x direction.
  • each second semiconductor element 50B is driven by increasing the volume of the connecting member 90 as compared with the connecting member 90 in which the intermediate facing wall 93 is omitted.
  • the heat of the element 50B is easily transferred to the connecting member 90.
  • the connecting member 90 may be configured so that the main facing wall 91 and at least one of the three intermediate facing walls 93 are separated from each other.
  • the connecting member 90 is attached to each of the main facing wall 91 facing all the second semiconductor elements 50B in the y direction and the second semiconductor elements 50B arranged at both ends in the x direction. It has an end facing wall 92 facing in the x direction and an intermediate facing wall 93 arranged between adjacent second semiconductor elements 50B in the x direction.
  • the connecting member 90 is a single component in which the main facing wall 91, the end facing wall 92, and the intermediate facing wall 93 are integrally formed.
  • the main facing wall 91 is arranged at a position adjacent to the second semiconductor element 50B in the y direction, and extends along the x direction.
  • the end facing wall 92 extends along the y direction from both ends of the main facing wall 91 in the x direction.
  • the end facing walls 92 are arranged at positions adjacent to each of the second semiconductor elements 50B arranged at both ends in the x direction in the x direction.
  • the end facing wall 92 is provided so as to overlap all of the second semiconductor elements 50B when viewed from the x direction.
  • Each intermediate facing wall 93 extends from the main facing wall 91 along the y direction.
  • Each intermediate facing wall 93 faces the second semiconductor element 50B in the x direction.
  • Each intermediate facing wall 93 is provided so as to overlap all of the second semiconductor elements 50B when viewed from the x direction.
  • each second semiconductor element 50B is driven by increasing the volume of the connecting member 90 as compared with the connecting member 90 in which at least one of the end facing wall 92 and the intermediate facing wall 93 is omitted. In this case, the heat of each second semiconductor element 50B is easily transferred to the connecting member 90.
  • the connecting member 90 may be configured so that the main facing wall 91 and at least one of the two end facing walls 92 are separated from each other. Further, the connecting member 90 may be configured so that the main facing wall 91 and at least one of the three intermediate facing walls 93 are separated from each other. Further, the connecting member 90 is configured such that the main facing wall 91, at least one of the two end facing walls 92, and at least one of the three intermediate facing walls 93 are separated from each other. May be done.
  • the length of the end facing wall 92 in the y direction can be arbitrarily changed.
  • the end facing wall 92 may be provided so as to overlap a part of the second semiconductor element 50B when viewed from the x direction. Further, the end facing wall 92 may be provided so as to protrude toward the insulating side surface 12B from the second semiconductor element 50B in the y direction when viewed from the z direction.
  • the length of the intermediate facing wall 93 in the y direction can be arbitrarily changed.
  • the intermediate facing wall 93 may be provided so as to overlap a part of the second semiconductor element 50B when viewed from the x direction.
  • the intermediate facing wall 93 may be provided so as to protrude from the second semiconductor element 50B toward the insulating side surface 12B in the y direction when viewed from the z direction.
  • a common connecting member 90 is provided for the plurality of second semiconductor elements 50B, but the present invention is not limited to this.
  • one connecting member 90 may be provided for each second semiconductor element 50B.
  • Each connecting member 90 is arranged so as to face the second semiconductor element 50B corresponding to the connecting member 90 in the y direction. More specifically, each connecting member 90 is arranged so as to be adjacent to the second semiconductor element 50B corresponding to the connecting member 90 in the y direction.
  • the connecting member 90 may be arranged between the second semiconductor elements 50B adjacent to each other in the x direction. Further, the connecting member 90 is arranged on the side opposite to the second semiconductor element 50B adjacent to the second semiconductor element 50B arranged at both ends in the x direction among the plurality of second semiconductor elements 50B in the x direction. May be good. That is, the connecting members 90 are arranged on both sides of the second semiconductor element 50B arranged at both ends in the x direction in the x direction. When viewed from the z direction, the connecting member 90 extends in the y direction. In the illustrated example, the connecting member 90 is provided so as to overlap the entire second semiconductor element 50B when viewed from the x direction.
  • each connecting member 90 may be provided so as to surround the second semiconductor element 50B from both sides in the x direction and from the y direction.
  • Each connecting member 90 may be provided so as to surround the second semiconductor element 50B from one of the x directions and the y direction.
  • the number of connecting members 90 can be arbitrarily changed.
  • one connecting member 90 may be provided for two second semiconductor elements 50B.
  • the connecting member 90 is provided so as to overlap the entire two second semiconductor elements 50B when viewed from the y direction.
  • the number of connecting members 90 can be arbitrarily changed.
  • the connecting members 90 at both ends in the x direction may be omitted.
  • the connecting member 90 is located between the two second semiconductor elements 50B near the insulating side surface 13B in the x direction and between the two second semiconductor elements 50B near the insulating side surface 14B in the x direction. It may be arranged in each.
  • the connecting member 90 is connected to each of the first driving conductive layer 20A and the second driving conductive layer 20B by an adhesive, but the present invention is not limited to this.
  • the connecting member 90 and the first driving conductive layer 20A are joined by a first conductive bonding material JC1 such as solder or Ag paste, and the connecting member 90 and the second driving conductive layer 20B are formed.
  • Solder, Ag paste or the like may be bonded by a second conductive bonding material JC2.
  • the thermal conductivity of each of the conductive bonding materials JC1 and JC2 is higher than the thermal conductivity of the adhesive.
  • the heat of the second semiconductor element 50B is the second driving conductive layer as compared with the configuration in which the connecting member 90, the first driving conductive layer 20A, and the second driving conductive layer 20B are connected by an adhesive. It becomes easy to move from 20B to the connecting member 90, and it becomes easy to move from the connecting member 90 to the first driving conductive layer 20A.
  • the connecting member 90 is composed of a flat plate-shaped block whose thickness direction is the y direction, but the present invention is not limited to this.
  • the connecting member 90 may be composed of a thin plate having a substantially S shape when viewed from the x direction.
  • the connecting member 90 is made of, for example, a spring material having electrical insulation.
  • the connecting member 90 may be made of a conductive spring material, and at least both ends of the connecting member 90 in the z direction may be covered with an insulating coating.
  • the connecting member 90 is in contact with the first driving conductive layer 20A and the second driving conductive layer 20B in a state of being compressed by the first driving conductive layer 20A and the second driving conductive layer 20B. That is, the ends of the connecting member 90 closer to the first driving conductive layer 20A among both ends in the z direction are urged toward the first driving conductive layer 20A. Of both ends of the connecting member 90 in the z direction, the end closer to the second driving conductive layer 20B is urged toward the second driving conductive layer 20B.
  • the connecting member 90 and the first driving conductive layer 20A and the second driving conductive layer 20B are surely in contact with each other, the heat of the second semiconductor element 50B is transferred from the second driving conductive layer 20B to the connecting member 90. It becomes easy to move, and it becomes easy to move from the connecting member 90 to the first driving conductive layer 20A.
  • the connecting member 90 may be composed of a plurality of spring probes.
  • the connecting member 90 is configured to be urged toward the first driving conductive layer 20A.
  • the connecting member 90 and the second driving conductive layer 20B are joined by a conductive bonding material JD such as solder or Ag paste. According to this configuration, since the connecting member 90 and the first driving conductive layer 20A are surely in contact with each other, the heat of the second semiconductor element 50B is easily transferred from the connecting member 90 to the first driving conductive layer 20A.
  • the connecting member 90 is made of a material having electrical insulation, but the present invention is not limited to this.
  • the connecting member 90 may be made of a metal material such as Cu or Al.
  • the adhesive that connects the connecting member 90 and the first driving conductive layer 20A and the adhesive that connects the connecting member 90 and the second driving conductive layer 20B are made of materials having electrical insulation. Become. As a result, the connecting member 90 and the first driving conductive layer 20A are insulated, and the connecting member 90 and the second driving conductive layer 20B are insulated.
  • the connecting member 90 may be connected to a drive wiring different from the second drive wiring 22.
  • the first drive conductive layer 20A may have a third drive wiring 23 as a drive wiring different from the second drive wiring 22.
  • the third drive wiring 23 is electrically insulated from the second drive wiring 22 and is formed so as to be adjacent to the second drive wiring 22 via a gap in the y direction.
  • the third drive wiring 23 extends in the x direction.
  • the third drive wiring 23 is arranged so as to be separated from the main wiring portion 22a of the second drive wiring 22 in the y direction and separated from the connection wiring portion 22b in the x direction.
  • the connecting member 90 may be made of a conductive material, for example, a metal material.
  • the connecting member 90 is connected to the first driving conductive layer 20A and the second driving conductive layer 20B, but the present invention is not limited to this.
  • the connecting member 90 may be connected to the first insulating main surface 10As of the first insulating member 10A instead of the first driving conductive layer 20A, or may be connected to the second insulating member 10B instead of the second driving conductive layer 20B. 2 It may be connected to the insulating main surface 10Bs.
  • the connecting member 90 is connected to the first insulating main surface 10As of the first insulating member 10A and is connected to the second insulating main surface 10Bs of the second insulating member 10B. ..
  • a through hole 24 is formed in a portion of the second driving conductive layer 20B where the connecting member 90 is arranged.
  • the through hole 24 penetrates the second driving conductive layer 20B in the z direction.
  • the connecting member 90 is inserted through the through hole 24 and connected to the second insulating main surface 10Bs of the second insulating member 10B.
  • the connecting member 90 may be connected so as to straddle the first insulating main surface 10As of the first driving conductive layer 20A and the first insulating member 10A, and the second driving conductive layer 20B and the second insulating member 10B may be connected. It may be connected so as to straddle the insulating main surface 10Bs.
  • the connecting member 90 includes at least one of the first insulating main surface 10As of the first driving conductive layer 20A and the first insulating member 10A, and the second of the second driving conductive layer 20B and the second insulating member 10B. It suffices to be connected to at least one of the insulating main surfaces 10Bs.
  • the connecting member 90 is connected to the first insulating main surface 10As of the first insulating member 10A or the second insulating main surface 10Bs of the second insulating member 10B, for example, the connecting member 90 is connected to a conductive material, for example, a metal material. It may be composed of.
  • each of the connecting layers 60A and 60B may be made of a conductive bonding material such as solder or Ag paste.
  • the first connecting layer connecting the first semiconductor element 50A and the second driving conductive layer 20B including the conductive bonding materials JA1 and JA2 formed at both ends of the first connecting layer 60A in the z direction.
  • the second semiconductor element 50B and the first drive conductive layer 20A include the conductive bonding materials JB1 and JB2 formed at both ends of the second connection layer 60B in the z direction. It constitutes a second connection layer to be connected.
  • the first control terminal 84A and the first detection terminal 85A may each project from the resin side surface 74 in the x direction. Further, the second control terminal 84B and the second detection terminal 85B may each project from the resin side surface 73 in the x direction.
  • the respective arrangement positions of the control wiring 41A and the detection wiring 42A can be arbitrarily changed.
  • the detection wiring 42A may be arranged closer to the main wiring portion 22a of the second drive wiring 22 than the control wiring 41A.
  • the shapes of the control wiring 41A and the detection wiring 42A viewed from the z direction can be arbitrarily changed.
  • the portion arranged between the second drive wiring 22 and the insulating side surface 12A in the y direction may be omitted.
  • the respective arrangement positions of the control wiring 41B and the detection wiring 42B can be arbitrarily changed.
  • the detection wiring 42B may be arranged closer to the second drive conductive layer 20B than the control wiring 41B.
  • the configuration of the second driving conductive layer 20B can be arbitrarily changed.
  • the second driving conductive layer 20B is divided into a first conductive portion to which each first semiconductor element 50A is connected and a second conductive portion to which each second semiconductor element 50B is connected. May be good.
  • the first conductive portion and the second conductive portion may be connected by a conductive connecting member.
  • the numbers of the first semiconductor element 50A and the second semiconductor element 50B can be arbitrarily changed.
  • the number of the first semiconductor element 50A and the number of the second semiconductor element 50B may be 1 to 3, or 5 or more, respectively, depending on the characteristics of the semiconductor device 1.
  • the first connection layer 60A and the second connection layer 60B may be omitted.
  • the first semiconductor element 50A is directly connected to the second driving conductive layer 20B.
  • the second semiconductor element 50B is directly connected to the second drive wiring 22 of the first drive conductive layer 20A.
  • the first semiconductor element 50A may be connected to the second driving conductive layer 20B via a conductive bonding material such as solder or Ag paste, or may be second driven in contact with the second driving conductive layer 20B. It may be connected to the conductive layer 20B.
  • the second semiconductor element 50B may be connected to the second drive wiring 22 of the first drive conductive layer 20A via a conductive bonding material such as solder or Ag paste, or may be in contact with the second drive wiring 22. It may be connected to the second drive wiring 22 in the state.
  • the bonding material JA between the first semiconductor element 50A and the first drive wiring 21 of the first drive conductive layer 20A may be omitted.
  • the first semiconductor element 50A is connected to the first drive wiring 21 in contact with the first drive wiring 21.
  • the bonding material JB between the second semiconductor element 50B and the second driving conductive layer 20B may be omitted.
  • the second semiconductor element 50B is connected to the second driving conductive layer 20B in contact with the second driving conductive layer 20B.
  • the first semiconductor element 50A is arranged closer to the first insulating member 10A than the second semiconductor element 50B, and the second semiconductor element 50B is closer to the second insulating member 10B than the first semiconductor element 50A. It was placed in, but it is not limited to this.
  • the first semiconductor element 50A and the second semiconductor element 50B may be arranged at the center between the first insulating member 10A and the second insulating member 10B in the z direction, respectively.
  • the joining materials JA, JB and the respective connections are used as a configuration in which the layers 60A and 60B are omitted, and a configuration in which the thickness of the first drive wiring 21 and the thickness of the second drive conductive layer 20B are increased.
  • the drain electrode 51A, the source electrode 52A, and the gate electrode 53A may be formed on the first element main surface 50As of the first semiconductor element 50A.
  • the drain electrode 51A is connected to the first drive wiring 21 of the first drive conductive layer 20A by a wire or a band-shaped connecting member.
  • the drain electrode 51B, the source electrode 52B and the gate electrode 53B may be formed on the second element main surface 50Bs of the second semiconductor element 50B.
  • the drain electrode 51B is connected to the second driving conductive layer 20B by a wire or a band-shaped connecting member.
  • each of the semiconductor elements 50A and 50B may be a semiconductor element other than a switching element such as a diode.
  • drain electrode (1st back surface side drive electrode) 52A Source electrode (first main surface side drive electrode) 50B ... Second semiconductor element 50Bs ... Second element main surface 50Br ... Second element back surface 51B ... Drain electrode (second back surface side drive electrode) 52B ... Source electrode (second main surface side drive electrode) 70 ... Sealing resin 90 ... Connecting member 92 ... End facing wall (a portion of a plurality of second semiconductor elements that surrounds one of the second semiconductor elements at both ends in the second direction from the second direction) 93 ... Intermediate facing wall (a portion of a plurality of second semiconductor elements located between adjacent second semiconductor elements in the second direction) 200 ... Cooler

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

半導体装置(1)は、第1絶縁部材(10A)と、第1駆動導電層(20A)と、第1半導体素子(50A)と、第2絶縁部材(10B)と、第2駆動導電層(20B)と、第2半導体素子(50B)と、接続部材(90)と、封止樹脂(70)と、を備える。封止部材(70)は、第1半導体素子(50A)、第2半導体素子(50B)および接続部材(90)を封止する。接続部材(90)は、第1絶縁部材(10A)および/または第1駆動導電層(20A)と、第2絶縁部材(10B)および/または第2駆動導電層(20B)との間に伝熱経路を形成する。接続部材(90)の熱伝導率は、封止樹脂(70)の熱伝導率よりも高い。

Description

半導体装置
 本開示は、半導体装置に関する。
 半導体装置の一例として、第1絶縁部材上に設けられた第1半導体素子と、第1半導体素子よりも上方に配置された第2絶縁部材と、第2絶縁部材上に設けられた第2半導体素子と、を備えた両面放熱構造の半導体装置が知られている(たとえば特許文献1参照)。この半導体装置は、第1絶縁部材に第1冷却器が取り付けられており、第2絶縁部材に第2冷却器が取り付けられた構成である。
特開2010-97967号公報
 ところで、搭載場所の状態によっては、上記半導体装置は、第1冷却器と第2冷却器のいずれか一方、たとえば第2冷却器が省略された状態で使用される場合がある。この場合、第1半導体素子から第1冷却器までの熱抵抗と、第2半導体素子から第1冷却器までの熱抵抗との差が大きくなる。その結果、半導体装置の駆動時において第1半導体素子および第2半導体素子のうち熱抵抗が高い方の温度が高くなるため、半導体装置の性能を十分に発揮できないおそれがある。
 本開示の目的は、第1半導体素子から冷却器までの熱抵抗と第2半導体素子から冷却器までの熱抵抗との差の増加を抑制できる半導体装置を提供することにある。
 上記課題を解決する半導体装置は、厚さ方向において互いに反対側を向く第1絶縁主面および第1絶縁裏面を有しており、前記第1絶縁裏面が露出した第1絶縁部材と、前記第1絶縁主面上に設けられた第1駆動導電層と、前記第1駆動導電層に搭載された第1半導体素子と、前記厚さ方向において互いに反対側を向く第2絶縁主面および第2絶縁裏面を有しており、前記第2絶縁裏面が露出し、前記第2絶縁主面が前記第1絶縁主面と前記厚さ方向において対向するように前記第1絶縁部材に対して前記厚さ方向に離間して配置された第2絶縁部材と、前記第2絶縁主面上に設けられた第2駆動導電層と、前記第2駆動導電層に搭載された第2半導体素子と、前記第1絶縁部材および前記第1駆動導電層のうちの少なくとも一方と、前記第2絶縁部材および前記第2駆動導電層のうちの少なくとも一方との間に伝熱経路を形成する接続部材と、前記第1半導体素子、前記第2半導体素子および前記接続部材を封止する封止樹脂と、を備え、前記接続部材の熱伝導率は、前記封止樹脂の熱伝導率よりも高い。
 この構成によれば、接続部材を介して第2半導体素子から冷却器までの伝熱経路が形成されるため、第2半導体素子が搭載される第2絶縁部材に冷却器が取り付けられていない場合に第1半導体素子から冷却器までの熱抵抗と第2半導体素子から冷却器までの熱抵抗との差の増加を抑制できる。
 上記半導体装置によれば、第1半導体素子から冷却器までの熱抵抗と第2半導体素子から冷却器までの熱抵抗との差の増加を抑制できる。
本実施形態の半導体装置の斜視図。 図1の半導体装置の平面図。 図1の半導体装置の側面図。 図3とは異なる方向から視た図1の半導体装置の側面図。 図3および図4とは異なる方向から視た図1の半導体装置の側面図。 本実施形態の半導体装置の第1半導体ユニットの平面図。 本実施形態の半導体装置の第2半導体ユニットの平面図。 図2の8-8線の断面図。 本実施形態の半導体装置の回路図。 比較例の半導体装置の断面図。 変更例の半導体装置の断面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の第2半導体ユニットの平面図。 変更例の半導体装置の断面図。 変更例の半導体装置の断面図。 変更例の半導体装置の断面図。 変更例の半導体装置の断面図。 変更例の半導体装置の第1半導体ユニットの平面図。 変更例の半導体装置の断面図。 変更例の半導体装置の第2半導体ユニットの平面図。
 以下、半導体装置の実施形態について図面を参照して説明する。以下に示す実施形態は、技術的思想を具体化するための構成や方法を例示するものであり、各構成部品の材質、形状、構造、配置、寸法等を下記のものに限定するものではない。以下の実施形態は、種々の変更を加えることができる。また、添付図面は、理解を容易にするために構成要素を拡大して示している場合がある。構成要素の寸法比率は実際のものと、または別の図面中のものと異なる場合がある。また断面図では、理解を容易にするために一部の構成要素のハッチングを省略している場合がある。
 図1~図9を参照して、本実施形態の半導体装置1の構成について説明する。なお、便宜上、図6において、後述する冷却器200を省略して示している。また便宜上、図6および図7において、後述する封止樹脂70を省略して示している。
 また、以降の説明において、半導体装置1の平面視において、互いに直交する2方向をそれぞれx方向およびy方向とし、x方向およびy方向と直交する方向をz方向とする。ここで、z方向は厚さ方向の一例であり、y方向は第1方向の一例であり、x方向は第2方向の一例である。
 図1~図8に示すように、半導体装置1は、複数(本実施形態では4個)の第1半導体素子50Aおよび複数(本実施形態では4個)の第2半導体素子50Bを封止樹脂70によって封止した構成である。図1~図5に示すように、半導体装置1が冷却器200に取り付けられることによって各第1半導体素子50A(図6参照)および各第2半導体素子50B(図7参照)のそれぞれの熱が冷却器200に移動する。
 封止樹脂70は、電気絶縁性を有する樹脂材料からなり、たとえば黒色のエポキシ樹脂からなる。封止樹脂70は、直方体状であり、樹脂側面71~74と、第1樹脂主面75Aおよび第2樹脂主面75Bと、を有している。
 樹脂側面71および樹脂側面72は、y方向において互いに反対側を向いている。z方向から視て、樹脂側面71,72はそれぞれ、x方向に沿って延びている。樹脂側面73および樹脂側面74は、x方向において互いに反対側を向いている。z方向から視て、樹脂側面73,74はそれぞれ、y方向に沿って延びている。第1樹脂主面75Aおよび第2樹脂主面75Bは、z方向において互いに反対側を向いている。本実施形態では、第1樹脂主面75Aには、冷却器200が取り付けられている。このため、第2樹脂主面75Bは、z方向において冷却器200とは反対側の面となる。
 図1~図5に示すように、半導体装置1は、封止樹脂70から突出する複数の端子80を備えている。複数の端子80は、それぞれ金属板からなり、たとえばCu(銅)からなる。複数の端子80は、第1入力端子81、第2入力端子82、出力端子83、第1制御用端子84A、第1検出用端子85A、第2制御用端子84Bおよび第2検出用端子85Bを有している。第1入力端子81、第2入力端子82および出力端子83はそれぞれ、樹脂側面71からy方向に向けて突出している。第1制御用端子84A、第1検出用端子85A、第2制御用端子84Bおよび第2検出用端子85Bはそれぞれ、樹脂側面72からy方向に向けて突出している。換言すると、第1入力端子81、第2入力端子82および出力端子83と、第1制御用端子84A、第1検出用端子85A、第2制御用端子84Bおよび第2検出用端子85Bとは、y方向において封止樹脂70の互いに反対側から突出している。
 第1入力端子81、第2入力端子82および出力端子83は、z方向において互いに同じ位置でx方向において互いに離間して配列されている。各端子81~83は、z方向を厚さ方向とする平板状に形成されている。
 第1制御用端子84A、第1検出用端子85A、第2制御用端子84Bおよび第2検出用端子85Bは、z方向において互いに同じ位置でx方向において互いに離間して配列されている。第1制御用端子84Aおよび第1検出用端子85Aは、z方向から視て、樹脂側面74寄りに配置されている。第2制御用端子84Bおよび第2検出用端子85Bは、z方向から視て、樹脂側面73寄りに配置されている。各端子84A,84B,85A,85Bは、y方向に延びる四角柱状に形成されている。
 図8に示すように、半導体装置1は、第1半導体ユニット1Aおよび第2半導体ユニット1Bを備えている。半導体装置1は、第1半導体ユニット1Aと第2半導体ユニット1Bとがz方向において対向する構成である。封止樹脂70は、z方向において第1半導体ユニット1Aと第2半導体ユニット1Bとの間に充填されており、第1半導体ユニット1Aおよび第2半導体ユニット1Bをx方向およびy方向から取り囲むように構成されている。つまり、第1半導体ユニット1Aの一部および第2半導体ユニット1Bの一部はそれぞれ、封止樹脂70からz方向において露出している。
 図6および図8に示すように、第1半導体ユニット1Aは、第1絶縁部材10A、第1駆動導電層20A、制御導電層40A、複数(本実施形態では4個)の第1半導体素子50Aを備えている。第1半導体ユニット1Aは、封止樹脂70のz方向の両端部のうち第1樹脂主面75Aに近い方の端部に配置されている。つまり、z方向において、第1半導体ユニット1Aは、第2半導体ユニット1Bよりも冷却器200の近くに配置されている。
 第1絶縁部材10Aは、z方向を厚さ方向とする平板状に形成された電気絶縁性を有する基板である。z方向から視た第1絶縁部材10Aの形状は、矩形状である。第1絶縁部材10Aは、z方向において互いに反対側を向く第1絶縁主面10Asおよび第1絶縁裏面10Arを有している。第1絶縁主面10Asは、z方向において冷却器200とは反対側を向いている。すなわち第1絶縁主面10Asは、封止樹脂70の第2樹脂主面75Bと同じ側を向いている。第1絶縁裏面10Arは、z方向において冷却器200に向いている。すなわち第1絶縁裏面10Arは、封止樹脂70の第1樹脂主面75Aと同じ側を向いている。図8に示すように、第1半導体ユニット1Aの第1絶縁部材10Aの第1絶縁裏面10Arは、封止樹脂70の第1樹脂主面75Aからz方向において露出している。本実施形態では、第1絶縁裏面10Arは、第1樹脂主面75Aと面一である。第1絶縁裏面10Arには、冷却器200が取り付けられている。
 なお、第1樹脂主面75Aに対する第1絶縁裏面10Arのz方向の位置は任意に変更可能である。一例では、第1絶縁裏面10Arは、第1樹脂主面75Aよりもz方向に突出するように設けられてもよい。この場合、冷却器200は、第1絶縁裏面10Arに取り付けられる。すなわち、冷却器200と第1樹脂主面75Aとのz方向の間には空隙が形成される。
 図6に示すように、第1絶縁部材10Aは、絶縁側面11A~14Aを有している。絶縁側面11Aおよび絶縁側面12Aは、y方向において互いに反対側を向いている。z方向から視て、絶縁側面11A,12Aはそれぞれ、x方向に延びている。絶縁側面11Aは封止樹脂70の樹脂側面71と同じ側を向いており、絶縁側面12Aは封止樹脂70の樹脂側面72と同じ側を向いている。絶縁側面13Aおよび絶縁側面14Aは、x方向において互いに反対側を向いている。z方向から視て、絶縁側面13A,14Aはそれぞれ、y方向に延びている。絶縁側面13Aは封止樹脂70の樹脂側面73と同じ側を向いており、絶縁側面14Aは封止樹脂70の樹脂側面74と同じ側を向いている。
 第1駆動導電層20Aおよび制御導電層40Aはそれぞれ、第1絶縁部材10Aの第1絶縁主面10As上に形成されている。各導電層20A,40Aは、たとえばCuからなる。第1駆動導電層20Aおよび制御導電層40Bは、第1絶縁主面10Asにおいて互いに離間して配置されている。
 第1駆動導電層20Aは、第1駆動配線21および第2駆動配線22を有している。第1駆動配線21および第2駆動配線22は、第1絶縁主面10Asにおいて互いに離間して配置されている。
 第1駆動配線21は、第1絶縁主面10Asのうちy方向において絶縁側面11Aの近く、かつx方向において絶縁側面14Aの近くに配置されている。z方向から視た第1駆動導電層20Aの形状は、x方向が長辺方向となり、y方向が短辺方向となる矩形状である。
 第1駆動配線21には、第1入力端子81が接続されている。より詳細には、第1駆動配線21上には、はんだやAgペースト等の第1導電性接合材(図示略)が形成されている。第1導電性接合材上には、導電性の接続層(図示略)が搭載されている。接続層上には、はんだやAgペースト等の第2導電性接合材(図示略)が形成されている。第2導電性接合材上には、第1入力端子81が搭載されている。このように、第1入力端子81は、各導電性接合材および接続層を介して第1駆動導電層20Aと電気的に接続されている。ここで、接続層は、たとえば金属材料からなり、本実施形態では、Cuからなる。接続層の一例は、柱状に形成されている。接続層は、たとえば四角柱である。なお、接続層の形状はこれに限られず、円柱、三角柱等の四角柱以外の多角柱であってもよい。
 また、第1駆動配線21には、複数の第1半導体素子50Aが搭載されている。複数の第1半導体素子50Aは、y方向において互いに同じ位置でx方向において互いに離間して配列されている。ここで、複数の第1半導体素子50Aのy方向のずれ量の最大値が第1半導体素子50Aのy方向の寸法の10%以内であれば、複数の第1半導体素子50Aは、y方向において互いに同じ位置にあるといえる。
 本実施形態では、各第1半導体素子50Aは、第1駆動配線21のy方向の中央に配置されている。なお、第1駆動配線21における各第1半導体素子50Aの配置位置は任意に変更可能である。一例では、各第1半導体素子50Aは、第1駆動配線21のy方向の中央よりも絶縁側面12A寄りに配置されていてもよい。
 各第1半導体素子50Aは、スイッチング素子であり、たとえば、Si(ケイ素)、SiC(炭化ケイ素)、または、GaN(窒化ガリウム)やGaAs(ヒ化ガリウム)、あるいはGa(酸化ガリウム)などからなるトランジスタが用いられる。各第1半導体素子50AがSiCからなる場合、スイッチングの高速化に適している。本実施形態では、各第1半導体素子50Aは、SiCからなるNチャネル型のMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)が用いられている。なお、各第1半導体素子50Aは、MOSFETに限定されず、MISFET(Metal-Insulator-Semiconductor FET)を含む電界効果トランジスタ、または、IGBT(Insulated Gate Bipolar Transistor)を含むバイポーラトランジスタなどのトランジスタであってもよい。各第1半導体素子50Aは、Nチャネル型のMOSFETに代えて、Pチャネル型のMOSFETとしてもよい。
 図8に示すように、第1半導体素子50Aは、z方向において第2半導体素子50Bよりも第1絶縁部材10A寄りに配置されている。換言すると、第1半導体素子50Aは、第1絶縁部材10Aと第2絶縁部材10Bとのz方向の間のうち第2絶縁部材10Bよりも第1絶縁部材10Aの近くに配置されている。第1半導体素子50Aは、z方向において互いに反対側を向く第1素子主面50Asおよび第1素子裏面50Arを有している。第1素子主面50Asは、第1絶縁主面10Asと同じ側を向いている。換言すると、第1素子主面50Asは、第2樹脂主面75Bと同じ側を向いている。第1素子裏面50Arは、第1絶縁裏面10Arと同じ側を向いている。換言すると、第1素子裏面50Arは、第1樹脂主面75Aと同じ側を向いている。第1絶縁裏面10Arには、第1裏面側駆動電極の一例であるドレイン電極51Aが形成されている。第1素子主面50Asには、第1主面側駆動電極の一例であるソース電極52Aと、ゲート電極53Aとが形成されている。各第1半導体素子50Aの第1素子裏面50Arは、はんだやAgペースト等の導電性接合材JAによって第1駆動導電層20Aに接合されている。これにより、各第1半導体素子50Aのドレイン電極51Aは、第1駆動導電層20Aと電気的に接続されている。
 第2駆動配線22は、第1駆動配線21を絶縁側面13Aの近くおよび絶縁側面12Aの近くから取り囲むように形成されている。z方向から視た第2駆動配線22の形状は、L字状である。第2駆動配線22は、x方向に延びる主配線部22aと、主配線部22aからy方向に延びる接続配線部22bと、を有している。本実施形態では、主配線部22aおよび接続配線部22bは、一体的に形成された単一部材である。
 主配線部22aは、y方向において第1駆動配線21よりも絶縁側面12Aの近くに配置されている。z方向から視た主配線部22aの形状は、x方向が長辺方向となり、y方向が短辺方向となる矩形状である。主配線部22aは、y方向から視て、第1駆動配線21と重なる部分を有している。一方、主配線部22aおよび第1駆動配線21は、x方向において互いにずれている。より詳細には、主配線部22aは、x方向において第1駆動配線21よりも絶縁側面13A寄りにはみ出す部分を有している。第1駆動配線21は、x方向において主配線部22aよりも絶縁側面14A寄りにはみ出す部分を有している。
 接続配線部22bは、主配線部22aのx方向の両端部のうち絶縁側面13Aの近くの端部から絶縁側面11Aに向けて延びている。z方向から視た接続配線部22bの形状は、y方向が長辺方向となり、x方向が短辺方向となる矩形状である。接続配線部22bは、第1駆動配線21よりも絶縁側面14Aの近くに配置されており、x方向から視て第1駆動配線21と重なるように配置されている。
 接続配線部22bには、第2入力端子82が接続されている。図示されていないが、接続配線部22bと第2入力端子82との接続構造は、第1駆動導電層20Aと第1入力端子81との接続構造と同じである。
 制御導電層40Aは、制御用配線41Aおよび検出用配線42Aを有している。制御用配線41Aおよび検出用配線42Aは、第1絶縁主面10Asにおいて互いに離間して配置されている。制御用配線41Aおよび検出用配線42Aはそれぞれ、第2駆動配線22の主配線部22aを絶縁側面11A、絶縁側面14Aおよび絶縁側面12Aから取り囲むように形成されている。z方向から視た制御用配線41Aおよび検出用配線42Aのそれぞれの形状は、略U字状である。検出用配線42Aは、制御用配線41Aよりも第2駆動配線22の主配線部22aの近くに配置されている。換言すると、制御用配線41Aは、検出用配線42Aを絶縁側面11A、絶縁側面14Aおよび絶縁側面12Aから取り囲むように形成されている。
 制御用配線41Aには、第1制御用端子84Aが接続されている。検出用配線42Aには、第1検出用端子85Aが接続されている。図示されていないが、制御用配線41Aと第1制御用端子84Aとの接合構造、および、検出用配線42Aと第1検出用端子85Aとの接合構造はそれぞれ、第1駆動導電層20Aと第1入力端子81との接続構造と同じである。z方向から視て、第1制御用端子84Aは、第1検出用端子85Aよりも絶縁側面14Aの近くに配置されている。なお、z方向から視た第1制御用端子84Aおよび第1検出用端子85Aの配置位置は任意に変更可能である。一例では、z方向から視て、第1検出用端子85Aは、第1制御用端子84Aよりも絶縁側面14Aの近くに配置されていてもよい。
 図6に示すように、第1半導体ユニット1Aは、各第1半導体素子50Aのソース電極52Aと検出用配線42Aとを接続するワイヤW1と、各第1半導体素子50Aのゲート電極53Aと制御用配線41Aとを接続するワイヤW2と、を有している。ワイヤW1,W2はそれぞれ、たとえばAu(金)からなる。なお、ワイヤW1,W2はそれぞれ、CuまたはAl(アルミニウム)からなる構成であってもよい。これにより、各第1半導体素子50Aのソース電極52Aと検出用配線42AとがワイヤW2を介して電気的に接続されている。各第1半導体素子50Aのゲート電極53Aと制御用配線41AとがワイヤW1を介して電気的に接続されている。
 図7および図8に示すように、第2半導体ユニット1Bは、第2絶縁部材10B、第2駆動導電層20B、制御導電層40B、複数(本実施形態では4個)の第2半導体素子50Bおよび第2接続層60Bを備えている。第2半導体ユニット1Bは、封止樹脂70のz方向の両端部のうち第2樹脂主面75Bに近い方の端部に配置されている。つまり、第2半導体ユニット1Bは、冷却器200から遠い位置に配置されている。
 第2絶縁部材10Bは、z方向を厚さ方向とする平板状に形成された電気絶縁性を有する基板である。第2絶縁部材10Bは、z方向において第1絶縁部材10Aと離間した状態でz方向において第1絶縁部材10Aと対向するように配置されている。z方向から視た第2絶縁部材10Bの形状は、矩形状である。第2絶縁部材10Bは、z方向において互いに反対側を向く第2絶縁主面10Bsおよび第2絶縁裏面10Brを有している。第2絶縁裏面10Brは、z方向において冷却器200とは反対側を向いている。すなわち第2絶縁裏面10Brは、封止樹脂70の第2樹脂主面75Bと同じ側を向いている。図8に示すように、第2半導体ユニット1Bの第2絶縁部材10Bの第2絶縁裏面10Brは、封止樹脂70の第2樹脂主面75Bからz方向において露出している。本実施形態では、第2絶縁裏面10Brは、第2樹脂主面75Bと面一である。第2絶縁主面10Bsは、z方向において冷却器200に向いている。すなわち第2絶縁主面10Bsは、封止樹脂70の第1樹脂主面75Aと同じ側を向いている。また、第2絶縁主面10Bsは、第1絶縁部材10Aの第1絶縁主面10Asとz方向に対向するように配置されているともいえる。
 なお、第2樹脂主面75Bに対する第2絶縁裏面10Brのz方向の位置は任意に変更可能である。一例では、第2絶縁裏面10Brは、第2樹脂主面75Bからz方向に突出するように設けられてもよい。
 また、第2絶縁部材10Bは、絶縁側面11B~14Bを有している。絶縁側面11Bおよび絶縁側面12Bは、y方向において互いに反対側を向いている。z方向から視て、絶縁側面11B,12Bはそれぞれ、x方向に延びている。絶縁側面11Bは封止樹脂70の樹脂側面71と同じ側を向いており、絶縁側面12Bは封止樹脂70の樹脂側面72と同じ側を向いている。このため、絶縁側面11Bは第1絶縁部材10Aの絶縁側面11Aと同じ側を向いており、絶縁側面12Bは第1絶縁部材10Aの絶縁側面12Aと同じ側を向いている。絶縁側面13Bおよび絶縁側面14Bは、x方向において互いに反対側を向いている。z方向から視て、絶縁側面13B,14Bはそれぞれ、y方向に延びている。絶縁側面13Bは封止樹脂70の樹脂側面73と同じ側を向いており、絶縁側面14Bは封止樹脂70の樹脂側面74と同じ側を向いている。このため、絶縁側面13Bは第1絶縁部材10Aの絶縁側面13Aと同じ側を向いており、絶縁側面14Bは第1絶縁部材10Aの絶縁側面14Aと同じ側を向いている。
 第2駆動導電層20Bおよび制御導電層40Bはそれぞれ、第2絶縁部材10Bの第2絶縁主面10Bs上に形成されている。各導電層20B,40Bは、たとえばCuからなる。第2駆動導電層20Bおよび制御導電層40Bは、第2絶縁主面10Bsにおいて互いに離間して配置されている。
 第2駆動導電層20Bは、第2絶縁部材10Bの第2絶縁主面10Bsのうちy方向における絶縁側面11B寄りに配置されている。第2駆動導電層20Bは、第2絶縁主面10Bsのうち大部分にわたり形成されている。z方向から視た第2駆動導電層20Bの形状は、矩形状である。
 第2駆動導電層20Bには、出力端子83が接続されている。第2駆動導電層20Bと出力端子83との接続構造は、第1駆動導電層20Aと第1入力端子81との接続構造と同じである。すなわち、図8に示すように、第2駆動導電層20B上には、はんだやAgペースト等の第1導電性接合材JE1が形成されている。第1導電性接合材JE1上には、導電性の接続層30が搭載されている。接続層30上には、はんだやAgペースト等の第2導電性接合材JE2が形成されている。第2導電性接合材JE2上には、出力端子83が搭載されている。このように、出力端子83は、各導電性接合材JE1,JE2および接続層30を介して第2駆動導電層20Bと電気的に接続されている。ここで、接続層30は、たとえば金属材料からなり、本実施形態では、Cuからなる。接続層30の一例は、柱状に形成されている。接続層30は、たとえば四角柱である。なお、接続層30の形状はこれに限られず、円柱、三角柱等の四角柱以外の多角柱であってもよい。
 図7に示すように、第2駆動導電層20Bには、複数の第2半導体素子50Bが搭載されている。本実施形態では、各第2半導体素子50Bは、第2駆動導電層20Bのうち絶縁側面12B寄りかつ絶縁側面13B寄りに配置されている。具体的には、各第2半導体素子50Bは、第2駆動導電層20Bのうちz方向において第1半導体ユニット1Aの第2駆動配線22の主配線部22aと対向する領域R内に配置されている。
 複数の第2半導体素子50Bは、y方向において互いに同じ位置でx方向において互いに離間して配列されている。ここで、複数の第2半導体素子50Bのy方向のずれ量の最大値が第2半導体素子50Bのy方向の寸法の10%以内であれば、複数の第2半導体素子50Bは、y方向において互いに同じ位置にあるといえる。図6~図8に示すように、第2半導体素子50Bは、y方向において第1半導体素子50Aと離間して配置されている。z方向から視て、複数の第1半導体素子50Aと複数の第2半導体素子50Bとはx方向において互いにずれている。複数の第1半導体素子50Aは、複数の第2半導体素子50Bに対して樹脂側面74寄りにずれて配置されている。y方向からみて、各第1半導体素子50Aと各第2半導体素子50Bとは、一部が重なるように配置されている。
 各第2半導体素子50Bは、たとえば、Si、SiC、または、GaNやGaAs、あるいはGaなどからなるトランジスタが用いられる。各第2半導体素子50BがSiCからなる場合、スイッチングの高速化に適している。本実施形態では、各第2半導体素子50Bは、SiCからなるNチャネル型のMOSFETが用いられている。なお、各第2半導体素子50Bは、MOSFETに限定されず、MISFETを含む電界効果トランジスタ、または、IGBTを含むバイポーラトランジスタなどのトランジスタであってもよい。各第2半導体素子50Bは、Nチャネル型のMOSFETに代えて、Pチャネル型のMOSFETとしてもよい。
 図8に示すように、第2半導体素子50Bは、z方向において第1半導体素子50Aよりも第2絶縁部材10B寄りに配置されている。換言すると、第2半導体素子50Bは、第1絶縁部材10Aと第2絶縁部材10Bとのz方向の間のうち第1絶縁部材10Aよりも第2絶縁部材10Bの近くに配置されている。第2半導体素子50Bは、z方向において互いに反対側を向く第2素子主面50Bsおよび第2素子裏面50Brを有している。第2素子主面50Bsは、第2絶縁主面10Bsと同じ側を向いている。換言すると、第2素子主面50Bsは、第1樹脂主面75Aと同じ側を向いている。第2素子裏面50Brは、第2絶縁裏面10Brと同じ側を向いている。換言すると、第2素子裏面50Brは、第2樹脂主面75Bと同じ側を向いている。図8に示すとおり、z方向において第2半導体素子50Bの配置方向は、第1半導体素子50Aの配置方向と逆向きとなる。第2絶縁裏面10Brには、第2裏面側駆動電極の一例であるドレイン電極51Bが形成されている。第2素子主面50Bsには、第2主面側駆動電極の一例であるソース電極52Bと、ゲート電極53Bとが形成されている。各第2半導体素子50Bの第2素子裏面50Brは、はんだやAgペースト等の導電性接合材JBによって第2駆動導電層20Bに接合されている。これにより、各第2半導体素子50Bのドレイン電極51Bは、第2駆動導電層20Bと電気的に接続されている。
 図7に示すように、制御導電層40Bは、第2絶縁部材10Bの第2絶縁主面10Bsのうちy方向における第2駆動導電層20Bと絶縁側面12Bとの間に配置されている。制御導電層40Bは、制御用配線41Bおよび検出用配線42Bを有している。z方向から視た制御用配線41Bおよび検出用配線42Bの形状はそれぞれ、x方向に延びる細帯状である。制御用配線41Bおよび検出用配線42Bは、x方向において互いに同じ位置でy方向において互いに離間して配列されている。制御用配線41Bは、検出用配線42Bよりも第2駆動導電層20Bの近くに配置されている。
 制御用配線41Bには、第2制御用端子84Bが接続されている。検出用配線42Bには、第2検出用端子85Bが接続されている。図示されていないが、制御用配線41Bと第2制御用端子84Bとの接合構造、および、検出用配線42Bと第2検出用端子85Bとの接合構造はそれぞれ、第1駆動導電層20Aと第1入力端子81との接続構造と同じである。z方向から視て、第2検出用端子85Bは、第2制御用端子84Bよりも絶縁側面13Aの近くに配置されている。なお、z方向から視て、第2制御用端子84Bおよび第2検出用端子85Bの配置位置は任意に変更可能である。一例では、z方向から視て、第2制御用端子84Bは、第2検出用端子85Bよりも絶縁側面13Aの近くに配置されていてもよい。
 図7に示すように、第2半導体ユニット1Bは、各第2半導体素子50Bのソース電極52Bと検出用配線42Bとを接続するワイヤW3と、各第2半導体素子50Bのゲート電極53Bと制御用配線41Bとを接続するワイヤW4と、を有している。ワイヤW3,W4はそれぞれ、たとえばAuからなる。なお、ワイヤW3,W4はそれぞれ、CuまたはAlからなる構成であってもよい。これにより、各第2半導体素子50Bのソース電極52Bと検出用配線42Bとが電気的に接続されている。各第2半導体素子50Bのゲート電極53Bと制御用配線41Bとが電気的に接続されている。
 図8に示すように、複数の第1半導体素子50Aのソース電極52Aはそれぞれ、第2半導体ユニット1Bの第2駆動導電層20Bと電気的に接続されている。より詳細には、ソース電極52A上には、はんだやAgペースト等の第1導電性接合材JA1が配置されている。第1導電性接合材JA1上には、導電性の第1接続層60Aが載置されている。第2駆動配線22において第1接続層60Aとz方向に対向する部分には、はんだやAgペースト等の第2導電性接合材JA2が配置されている。第2導電性接合材JA2は、第1接続層60Aと接触している。すなわち、第1接続層60Aは、各導電性接合材JA1,JA2によってソース電極52Aと第2駆動導電層20Bとに接合されている。このように、ソース電極52Aと第2駆動導電層20Bとは、各導電性接合材JA1,JA2および第1接続層60Aを介して電気的に接続されている。
 第1接続層60Aは、たとえば金属材料からなり、本実施形態ではCuからなる。第1接続層60Aの一例は、柱状に形成されている。第1接続層60Aは、たとえば四角柱である。なお、第1接続層60Aの形状はこれに限られず、円柱、三角柱等の四角柱以外の多角柱であってもよい。図8に示すとおり、本実施形態では、第1接続層60Aの厚さ(第1接続層60Aのz方向の寸法)は、第1半導体素子50Aの厚さ(第1半導体素子50Aのz方向の寸法)よりも厚い。
 図8に示すように、複数の第2半導体素子50Bのソース電極52Bはそれぞれ、第1半導体ユニット1Aの第1駆動導電層20Aの第2駆動配線22と電気的に接続されている。より詳細には、ソース電極52B上には、はんだやAgペースト等の第1導電性接合材JB1が配置されている。第1導電性接合材JB1上には、導電性の第2接続層60Bが載置されている。第2駆動配線22において第2接続層60Bとz方向に対向する部分には、はんだやAgペースト等の第2導電性接合材JB2が配置されている。第2導電性接合材JB2は、第2接続層60Bと接触している。すなわち、第2接続層60Bは、各導電性接合材JB1,JB2によってソース電極52Bと第2駆動配線22とに接合されている。このように、ソース電極52Bと第2駆動配線22とは、各導電性接合材JB1,JB2および第2接続層60Bを介して電気的に接続されている。
 第2接続層60Bは、たとえば金属材料からなり、本実施形態ではCuからなる。第2接続層60Bの一例は、柱状に形成されている。第2接続層60Bは、たとえば四角柱である。なお、第2接続層60Bの形状はこれに限られず、円柱、三角柱等の四角柱以外の多角柱であってもよい。図8に示すとおり、本実施形態では、第2接続層60Bの厚さ(第2接続層60Bのz方向の寸法)は、第2半導体素子50Bの厚さ(第2半導体素子50Bのz方向の寸法)よりも厚い。
 なお、第1接続層60Aおよび第2接続層60Bの厚さはそれぞれ任意に変更可能である。一例では、第1接続層60Aの厚さは、第1半導体素子50Aの厚さ以下であってもよい。第2接続層60Bの厚さは、第2半導体素子50Bの厚さ以下であってもよい。
 このような構成の半導体装置1の回路構成は、互いに並列接続された4個の第1半導体素子50Aと、互いに並列接続された4個の第2半導体素子50Bとが直列接続されたハーフブリッジ型のインバータ回路である。図9は、半導体装置1のインバータ回路の一例を示している。図9では、便宜上、互いに並列接続された4個の第1半導体素子50Aを1つの第1半導体素子50Aとして示し、互いに並列接続された4個の第2半導体素子50Bを1つの第2半導体素子50Bとして示している。
 図9に示すように、第1半導体素子50Aのドレイン電極51Aは、第1入力端子81に電気的に接続されている。第1半導体素子50Aのソース電極52Aは、第2半導体素子50Bのドレイン電極51Bと電気的に接続されている。第1半導体素子50Aのソース電極52Aと第2半導体素子50Bのドレイン電極51BとのノードNには、出力端子83が接続されている。第2半導体素子50Bのソース電極52Bは、第2入力端子82に電気的に接続されている。
 第1半導体素子50Aのゲート電極53Aは、第1制御用端子84Aに接続されている。第2半導体素子50Bのゲート電極53Bは、第2制御用端子84Bに接続されている。第1半導体素子50Aのソース電極52AとノードNとの間のノードNAには、第1検出用端子85Aが接続されている。第2半導体素子50Bのソース電極52Bと第2入力端子82との間のノードNBには、第2検出用端子85Bが接続されている。
 次に、図7および図8を参照して、半導体装置1の放熱構造について説明する。
 図8に示すように、半導体装置1は、第1駆動導電層20Aと第2駆動導電層20Bとを接続する接続部材90を備えている。本実施形態では、接続部材90は、たとえば接着剤(図示略)によって第1駆動導電層20Aと第2駆動導電層20Bとのそれぞれに接合されている。
 接続部材90の熱伝導率は、封止樹脂70の熱伝導率よりも高い。また接続部材90の熱伝導率は、空気の熱伝導率よりも高い。接続部材90の熱伝導率は、10W/mK以上であることが好ましい。接続部材90は、電気絶縁性を有する材料からなり、たとえばSi、またはアルミナ、窒化アルミニウム等のセラミックスのような放熱性に優れた材料からなる。本実施形態では、接続部材90は、セラミックスからなる。接続部材90は、冷却器200が取り付けられていない半導体ユニットの半導体素子(本実施形態では、第2半導体ユニット1Bの各第2半導体素子50B)の放熱を補助するための部材である。本実施形態では、接続部材90は、第1駆動導電層20Aの第2駆動配線22と、第2駆動導電層20Bとの間に伝熱経路を形成している。
 接続部材90は、y方向において第2半導体素子50Bに対して制御導電層40Bとは反対側に配置されている。本実施形態では、接続部材90は、y方向において第1半導体素子50Aと第2半導体素子50Bとの間に配置されている。より詳細には、接続部材90は、y方向において第1半導体素子50Aよりも第2半導体素子50Bの近くに配置されている。接続部材90は、y方向において第2半導体素子50Bと隣り合う位置に配置されている。図7に示すように、接続部材90は、領域R内に配置されている。
 図7に示すように、接続部材90は、全ての第2半導体素子50Bとy方向に対向するようにx方向に延びている。つまり、接続部材90は、y方向において全ての第2半導体素子50Bと隣り合うように配置されている。z方向から視た接続部材90の形状は、x方向が長辺方向となり、y方向が短辺方向となる矩形状である。接続部材90のy方向の大きさは、第2半導体素子50Bのy方向の大きさよりも小さい。図7および図8に示すように、本実施形態の接続部材90は、y方向を厚さ方向とする平板状のブロックからなる。
 図8および図10を参照して、本実施形態の作用について説明する。
 図10は、比較例の半導体装置1Xの断面構造を示している。比較例の半導体装置1Xは、本実施形態の半導体装置1から接続部材90を省略した構成である。このため、比較例の半導体装置1Xにおいて、半導体装置1と共通する構成要素については同一符号を付し、その説明を省略する。
 半導体装置1Xにおいて各第1半導体素子50Aおよび各第2半導体素子50Bが駆動する場合、各第1半導体素子50Aおよび各第2半導体素子50Bは発熱する。第1半導体ユニット1Aの第1絶縁部材10Aには冷却器200が取り付けられているため、各第1半導体素子50Aの熱は、図10の矢印YX1に示すとおり、導電性接合材JA、第1駆動導電層20Aの第1駆動配線21および第1絶縁部材10Aを介して冷却器200に移動する。また、第2半導体ユニット1Bの第2絶縁部材10Bに冷却器200が取り付けられていないため、各第2半導体素子50Bの熱は、図10の矢印YX2に示すとおり、第1導電性接合材JB1、第2接続層60B、第2導電性接合材JB2、第1駆動導電層20Aの第2駆動配線22および第1絶縁部材10Aを介して冷却器200に移動する。このように、各第2半導体素子50Bから冷却器200までの熱抵抗は、各第1半導体素子50Aから冷却器200までの熱抵抗よりも高くなる。その結果、各第2半導体素子50Bは、各第1半導体素子50Aよりも放熱しにくくなり、各第1半導体素子50Aよりも温度が高くなりやすい。
 一方、本実施形態の半導体装置1において各第1半導体素子50Aおよび各第2半導体素子50Bが駆動する場合、各第1半導体素子50Aの熱は、図8の矢印Y1に示すとおり、導電性接合材JA、第1駆動導電層20Aの第1駆動配線21および第1絶縁部材10Aを介して冷却器200に移動する。
 また、各第2半導体素子50Bの熱は、2つの伝熱経路を介して冷却器200に移動する。より詳細には、各第2半導体素子50Bの熱は、図8の矢印Y2に示すとおり、第1導電性接合材JB1、第2接続層60B、第2導電性接合材JB2、第1駆動導電層20Aの第2駆動配線22および第1絶縁部材10Aを介して冷却器200に移動する。また各第2半導体素子50Bの熱は、図8の矢印Y3に示すとおり、導電性接合材JB、第2駆動導電層20B、接続部材90、第1駆動導電層20Aの第2駆動配線22および第1絶縁部材10Aを介して冷却器200に移動する。このように、各第2半導体素子50Bの熱が矢印Y2の伝熱経路および矢印Y3の伝熱経路の2つの経路を介して冷却器200に移動するため、各第2半導体素子50Bから冷却器200までの熱抵抗と、各第1半導体素子50Aから冷却器200までの熱抵抗との差の増加を抑制できる。これにより、各第2半導体素子50Bは、各第1半導体素子50Aと同様の放熱性能を有し、各第1半導体素子50Aよりも温度が高くなりやすくなることを抑制できる。
 本実施形態の半導体装置1によれば、以下の効果が得られる。
 (1)半導体装置1は、第1駆動導電層20Aと第2駆動導電層20Bとを接続している接続部材90と、第1半導体素子50A、第2半導体素子50Bおよび接続部材90を封止する封止樹脂70と、を備えている。接続部材90は、各第2半導体素子50Bから冷却器200への伝熱経路を形成している。接続部材90の熱伝導率は、封止樹脂70の熱伝導率よりも高い。この構成によれば、第1半導体素子50Aよりも冷却器200から遠い第2半導体素子50Bと冷却器200との伝熱経路を増やすことができるため、半導体装置1における第1半導体素子50Aから冷却器200までの熱抵抗と第2半導体素子50Bから冷却器200までの熱抵抗との差の増加を抑制できる。したがって、第1半導体素子50Aおよび第2半導体素子50Bが駆動しているときに、第2半導体素子50Bの温度が第1半導体素子50Aの温度よりも高くなりすぎることを抑制できるため、半導体装置1の性能を十分に発揮できる。
 (2)たとえば、接続部材90が第2絶縁部材10Bの第2絶縁主面10Bsに接続される構成では、第2半導体素子50Bの熱は、第2駆動導電層20Bおよび第2絶縁部材10Bに伝わり、再び第2駆動導電層20Bに伝わって接続部材90に移動する。このため、第2半導体素子50Bから接続部材90までの伝熱経路が長くなる。
 その点、本実施形態では、接続部材90は、第2駆動導電層20Bと接続している。この構成によれば、第2半導体素子50Bの熱が第2駆動導電層20Bから接続部材90に伝わるため、伝熱経路が短くなる。したがって、第2半導体素子50Bの熱が接続部材90に伝わりやすくなる。
 (3)z方向から視て、接続部材90は、第1半導体素子50Aよりも第2半導体素子50Bの近くに配置されている。この構成によれば、第1半導体素子50Aの熱よりも第2半導体素子50Bの熱が接続部材90に伝わりやすくなるため、第2半導体素子50Bが第1半導体素子50Aよりも温度が高くなりやすくなることを抑制できる。
 (4)第2半導体素子50Bの第2素子主面50Bsにはソース電極52Bが形成されており、第2接続層60Bを介して第1駆動導電層20Aの第2駆動配線22と接続されている。この構成によれば、第2半導体素子50Bの熱が第2接続層60B、第2駆動配線22および第1絶縁部材10Aを介して冷却器200に移動する。したがって、第2半導体素子50Bの温度が過度に高くなることを抑制できる。
 第1半導体素子50Aの第1素子主面50Asにはソース電極52Aが形成されており、第1接続層60Aを介して第2駆動導電層20Bと接続されている。この構成によれば、第1半導体素子50Aの熱が第1接続層60A、第2駆動導電層20Bおよび第2絶縁部材10Bに伝わるため、第1半導体素子50Aの温度が過度に高くなることを抑制できる。
 (5)y方向から視て、接続部材90は、複数の第2半導体素子50Bの全てと重なるように配置されている。この構成によれば、複数の第2半導体素子50Bの熱がそれぞれ接続部材90に移動するため、複数の第2半導体素子50Bの温度のばらつきを抑制できる。
 (6)接続部材90は、y方向において複数の第2半導体素子50Bの全て隣り合うように配置されている。この構成によれば、複数の第2半導体素子50Bの熱がそれぞれ接続部材90に移動しやすくなる。したがって、複数の第2半導体素子50Bの温度がそれぞれ過度に高くなることを抑制できる。
 (7)接続部材90が第2半導体素子50Bと、第2絶縁部材10Bの第2絶縁主面10Bs上に形成された制御導電層40Bとの間に配置された場合、第2半導体素子50Bと制御用配線41Bとを接続するワイヤW3と、第2半導体素子50Bと検出用配線42Bとを接続するワイヤW4とを接続部材90を避けて形成する必要がある。このため、ワイヤW3,W4の長さが長くなったり、ワイヤW3,W4の形成が困難となったりする場合がある。
 その点、本実施形態では、接続部材90は、制御導電層40Bとは反対側に配置されている。この構成によれば、接続部材90を避けるようにワイヤW3,W4を形成する必要がないため、ワイヤW3,W4を容易に形成できるとともにワイヤW3,W4のそれぞれの長さを短くすることができる。
 (8)第1絶縁部材10Aおよび第2絶縁部材10Bはそれぞれ、セラミックスからなる。この構成によれば、各第1半導体素子50Aおよび各第2半導体素子50Bの熱が第1絶縁部材10Aから冷却器200に伝わりやすくなる。また各第1半導体素子50Aおよび各第2半導体素子50Bの熱が第2絶縁部材10Bを介して外部に放熱しやすくなる。
 (9)第1入力端子81、第2入力端子82、および出力端子83はそれぞれ封止樹脂70の樹脂側面74から突出している。この構成によれば、半導体装置1を実装基板に実装し、実装基板にたとえばスナバ用コンデンサを設ける場合、半導体装置1とスナバ用コンデンサとを接続する配線を容易に形成できる。
 (10)接続部材90のy方向の大きさは、第2半導体素子50Bのy方向の大きさよりも小さい。この構成によれば、第1駆動導電層20Aの第2駆動配線22のy方向の大きさの増加を抑制できるため、半導体装置1のy方向の大型化を抑制できる。
 (変更例)
 上記実施形態は本開示に関する半導体装置が取り得る形態の例示であり、その形態を制限することを意図していない。本開示に関する半導体装置は、上記実施形態に例示された形態とは異なる形態を取り得る。その一例は、上記実施形態の構成の一部を置換、変更、もしくは、省略した形態、または上記実施形態に新たな構成を付加した形態である。また、以下の各変更例は、技術的に矛盾しない限り、互いに組み合わせることができる。以下の各変更例において、上記実施形態と共通する部分については、上記実施形態と同一の符号を付してその説明を省略する。
 ・上記実施形態において、封止樹脂70のx方向の大きさおよびy方向の大きさはそれぞれ任意に変更可能である。一例では、封止樹脂70は、第1絶縁部材10Aの絶縁側面11A~14Aが露出するように形成されてもよい。封止樹脂70は、第2絶縁部材10Bの絶縁側面11B~14Bが露出するように形成されてもよい。
 ・上記実施形態において、接続部材90と第1駆動導電層20Aとの間の接着剤と、接続部材90と第2駆動導電層20Bとの間の接着剤との少なくとも一方を省略してもよい。たとえば接続部材90と第1駆動導電層20Aとの間の接着剤を省略した場合、接続部材90と第1駆動導電層20Aとは互いに接触している。またたとえば接続部材90と第2駆動導電層20Bとの間の接着剤を省略した場合、接続部材90と第2駆動導電層20Bとは互いに接触している。
 ・上記実施形態において、接続部材90のy方向の寸法は任意に変更可能である。一例では、図11に示すように、接続部材90のy方向の寸法を上記実施形態の接続部材90のy方向の寸法よりも大きくしてもよい。この場合、各第2半導体素子50Bは、第2駆動導電層20Bのy方向の両端部のうち絶縁側面12Bに近い方の端部に配置されている。これにより、領域R(図7参照)のうちy方向において接続部材90が配置可能なスペースを拡大させることができる。これにより、接続部材90のy方向の寸法を大きくしても、接続部材90は、領域R内に収まっている。
 この構成によれば、接続部材90の体積が大きくなるため、各第2半導体素子50Bの熱が接続部材90を介して冷却器200に移動しやすくなる。したがって、各第2半導体素子50Bの温度が各第1半導体素子50Aの温度よりも高くなりやすくなることを一層抑制できる。
 ・上記実施形態において、接続部材90のx方向の長さは任意に変更可能である。接続部材90のx方向の長さは、y方向において複数の第2半導体素子50Bのうち一部の第2半導体素子50Bと対向するような長さであってもよい。
 ・上記実施形態において、z方向から視た接続部材90の形状は任意に変更可能である。z方向から視た接続部材90の形状は、たとえば次の(A)~(C)のように変更してもよい。
 (A)図12に示すように、接続部材90は、y方向において全ての第2半導体素子50Bと対向する主対向壁91と、x方向の両端に配置された第2半導体素子50Bのそれぞれに対してx方向において対向する端部対向壁92と、を有している。図示された例においては、接続部材90は、主対向壁91と端部対向壁92とが一体に形成された単一部品である。主対向壁91は、y方向において第2半導体素子50Bと隣り合う位置に配置されており、x方向に沿って延びている。端部対向壁92は、主対向壁91のx方向の両端部からy方向に沿って延びている。端部対向壁92は、x方向の両端に配置された第2半導体素子50Bのそれぞれとx方向に隣り合う位置に配置されている。図示された例においては、端部対向壁92は、x方向から視て、第2半導体素子50Bの全てと重なるように設けられている。
 この構成によれば、端部対向壁92が省略された接続部材90と比較して、接続部材90の体積が増加することによって、各第2半導体素子50Bが駆動している場合において各第2半導体素子50Bの熱が接続部材90に移動しやすくなる。なお、図12に示す変更例において、接続部材90は、主対向壁91と、2個の端部対向壁92のうちの少なくとも1つとが分離した状態となるように構成されてもよい。
 (B)図13に示すように、接続部材90は、y方向において全ての第2半導体素子50Bと対向する主対向壁91と、x方向において隣り合う第2半導体素子50Bの間に配置された複数(図示された例では3個)の中間対向壁93と、を有している。図示された例においては、接続部材90は、主対向壁91と中間対向壁93とが一体に形成された単一部品である。主対向壁91は、y方向において第2半導体素子50Bと隣り合う位置に配置されており、x方向に沿って延びている。各中間対向壁93は、主対向壁91からy方向に沿って延びている。各中間対向壁93は、x方向において第2半導体素子50Bと対向している。各中間対向壁93は、x方向から視て、第2半導体素子50Bの全てと重なるように設けられている。
 この構成によれば、中間対向壁93が省略された接続部材90と比較して、接続部材90の体積が増加することによって、各第2半導体素子50Bが駆動している場合において各第2半導体素子50Bの熱が接続部材90に移動しやすくなる。なお、図13に示す変更例において、接続部材90は、主対向壁91と、3個の中間対向壁93のうちの少なくとも1つとが分離した状態となるように構成されてもよい。
 (C)図14に示すように、接続部材90は、y方向において全ての第2半導体素子50Bと対向する主対向壁91と、x方向の両端に配置された第2半導体素子50Bのそれぞれに対してx方向において対向する端部対向壁92と、x方向において隣り合う第2半導体素子50Bの間に配置された中間対向壁93と、を有している。図示された例においては、接続部材90は、主対向壁91と端部対向壁92と中間対向壁93とが一体に形成された単一部品である。主対向壁91は、y方向において第2半導体素子50Bと隣り合う位置に配置されており、x方向に沿って延びている。端部対向壁92は、主対向壁91のx方向の両端部からy方向に沿って延びている。端部対向壁92は、x方向の両端に配置された第2半導体素子50Bのそれぞれとx方向に隣り合う位置に配置されている。図示された例においては、端部対向壁92は、x方向から視て、第2半導体素子50Bの全てと重なるように設けられている。各中間対向壁93は、主対向壁91からy方向に沿って延びている。各中間対向壁93は、x方向において第2半導体素子50Bと対向している。各中間対向壁93は、x方向から視て、第2半導体素子50Bの全てと重なるように設けられている。
 この構成によれば、端部対向壁92および中間対向壁93の少なくとも一方が省略された接続部材90と比較して、接続部材90の体積が増加することによって、各第2半導体素子50Bが駆動している場合において各第2半導体素子50Bの熱が接続部材90に移動しやすくなる。
 なお、図14に示す変更例において、接続部材90は、主対向壁91と、2個の端部対向壁92のうちの少なくとも1つとが分離した状態となるように構成されてもよい。また接続部材90は、主対向壁91と、3個の中間対向壁93のうちの少なくとも1つとが分離した状態となるように構成されてもよい。また接続部材90は、主対向壁91と、2個の端部対向壁92のうちの少なくとも1つと、3個の中間対向壁93のうちの少なくとも1つとが互いに分離した状態となるように構成されてもよい。
 なお、上記(A)および(C)について、端部対向壁92のy方向の長さは任意に変更可能である。一例では、端部対向壁92は、x方向から視て、第2半導体素子50Bの一部と重なるように設けられていてもよい。また、端部対向壁92は、z方向から視て、y方向において第2半導体素子50Bよりも絶縁側面12Bに向けてはみ出すように設けられてもよい。
 また、上記(B)および(C)について、中間対向壁93のy方向の長さは任意に変更可能である。一例では、中間対向壁93は、x方向から視て、第2半導体素子50Bの一部と重なるように設けられていてもよい。また、中間対向壁93は、z方向から視て、y方向において第2半導体素子50Bよりも絶縁側面12Bに向けてはみ出すように設けられてもよい。
 ・上記実施形態では、複数の第2半導体素子50Bに対して共通の接続部材90が設けられたが、これに限られない。たとえば、図15に示すように、各第2半導体素子50Bに対して1つの接続部材90が設けられてもよい。各接続部材90は、その接続部材90と対応する第2半導体素子50Bに対してy方向において対向するように配置されている。より詳細には、各接続部材90は、その接続部材90と対応する第2半導体素子50Bとy方向において隣り合うように配置されている。
 ・図15の変更例において、第2半導体素子50Bに対する接続部材90の配置位置は任意に変更可能である。一例では、図16に示すように、接続部材90は、x方向において隣り合う第2半導体素子50Bの間に配置されてもよい。また接続部材90は、複数の第2半導体素子50Bのうちx方向の両端部に配置された第2半導体素子50Bに対してx方向に隣り合う第2半導体素子50Bとは反対側に配置されてもよい。つまり、接続部材90は、x方向の両端部に配置された第2半導体素子50Bのx方向の両側に配置されている。z方向から視て、接続部材90は、y方向に延びている。図示された例においては、接続部材90は、x方向から視て、第2半導体素子50Bの全体と重なるように設けられている。
 ・図15の変更例において、各接続部材90のz方向から視た形状は任意に変更可能である。一例では、図17に示すように、各接続部材90は、第2半導体素子50Bをx方向の両側およびy方向から囲うように設けられてもよい。なお、各接続部材90は、第2半導体素子50Bをx方向の一方およびy方向から囲うように設けられてもよい。
 ・図15の変更例および図17の変更例において、接続部材90の個数は任意に変更可能である。一例では、2個の第2半導体素子50Bに対して1個の接続部材90が設けられてもよい。この場合、接続部材90は、y方向から視て、2個の第2半導体素子50Bの全体と重なるように設けられることが好ましい。
 ・図16の変更例において、接続部材90の個数は任意に変更可能である。一例では、図16の複数の接続部材90のうちx方向の両端部の接続部材90を省略してもよい。また別例では、接続部材90は、絶縁側面13B寄りの2個の第2半導体素子50Bのx方向の間と、絶縁側面14B寄りの2個の第2半導体素子50Bのx方向の間とのそれぞれに配置されてもよい。
 ・上記実施形態では、接続部材90は、接着剤によって第1駆動導電層20Aおよび第2駆動導電層20Bのそれぞれに接続されていたが、これに限られない。たとえば図18に示すように、接続部材90と第1駆動導電層20Aとは、はんだやAgペースト等の第1導電性接合材JC1によって接合され、接続部材90と第2駆動導電層20Bとは、はんだやAgペースト等の第2導電性接合材JC2によって接合されてもよい。ここで、各導電性接合材JC1,JC2の熱伝導率は、接着剤の熱伝導率よりも高い。
 この構成によれば、接続部材90と第1駆動導電層20Aおよび第2駆動導電層20Bとが接着剤によって接続された構成と比較して、第2半導体素子50Bの熱が第2駆動導電層20Bから接続部材90に移動しやすくなり、接続部材90から第1駆動導電層20Aに移動しやすくなる。
 ・上記実施形態では、接続部材90は、y方向が厚さ方向となる平板状のブロックからなる構成であったが、これに限られない。たとえば図19に示すように、接続部材90は、x方向から視て略S字状となる薄板から構成されてもよい。接続部材90は、たとえば電気絶縁性を有するスプリング材からなる。また接続部材90は、導電性のスプリング材からなり、接続部材90のうち少なくともz方向の両端部が絶縁被膜によって覆われた構成であってもよい。図示された例においては、接続部材90は、第1駆動導電層20Aおよび第2駆動導電層20Bによって圧縮された状態で第1駆動導電層20Aおよび第2駆動導電層20Bに接触している。つまり、接続部材90のz方向の両端部のうち第1駆動導電層20Aに近い方の端部は、第1駆動導電層20Aに向けて付勢されている。接続部材90のz方向の両端部のうち第2駆動導電層20Bに近い方の端部は、第2駆動導電層20Bに向けて付勢されている。
 この構成によれば、接続部材90と第1駆動導電層20Aおよび第2駆動導電層20Bとが確実に接触するため、第2半導体素子50Bの熱が第2駆動導電層20Bから接続部材90に移動しやすくなり、接続部材90から第1駆動導電層20Aに移動しやすくなる。
 また図20に示すように、接続部材90は、複数本のスプリングプローブから構成されてもよい。図示された例においては、接続部材90は、第1駆動導電層20Aに向けて付勢される構成である。接続部材90と第2駆動導電層20Bとは、はんだやAgペースト等の導電性接合材JDによって接合されている。この構成によれば、接続部材90と第1駆動導電層20Aとが確実に接触するため、第2半導体素子50Bの熱が接続部材90から第1駆動導電層20Aに移動しやすくなる。
 ・上記実施形態では、接続部材90が電気絶縁性を有する材料からなる構成であったが、これに限られない。たとえば接続部材90は、Cu、Al等の金属材料からなる構成であってもよい。この場合、たとえば接続部材90と第1駆動導電層20Aとを接続する接着剤と、接続部材90と第2駆動導電層20Bとを接続する接着剤とのそれぞれは、電気絶縁性を有する材料からなる。これにより、接続部材90と第1駆動導電層20Aとが絶縁され、接続部材90と第2駆動導電層20Bとが絶縁される。
 ・上記実施形態において、接続部材90は、第2駆動配線22とは異なる駆動配線に接続されてもよい。一例では、図21に示すように、第1駆動導電層20Aは、第2駆動配線22とは異なる駆動配線として、第3駆動配線23を有していてもよい。第3駆動配線23は、第2駆動配線22と電気的に絶縁されており、y方向において第2駆動配線22と隙間を介して隣り合うように形成されている。図22に示すように、第3駆動配線23は、x方向に延びている。第3駆動配線23は、第2駆動配線22の主配線部22aとy方向に離間し、接続配線部22bとx方向に離間するように配置されている。この場合、接続部材90は、導電性を有する材料、たとえば金属材料から構成されてもよい。
 ・上記実施形態では、接続部材90は、第1駆動導電層20Aおよび第2駆動導電層20Bに接続されていたが、これに限られない。接続部材90は、第1駆動導電層20Aに代えて第1絶縁部材10Aの第1絶縁主面10Asに接続されてもよいし、第2駆動導電層20Bに代えて第2絶縁部材10Bの第2絶縁主面10Bsに接続されてもよい。一例では、図23に示すように、接続部材90は、第1絶縁部材10Aの第1絶縁主面10Asに接続されており、第2絶縁部材10Bの第2絶縁主面10Bsに接続されている。
 図24に示すように、第2駆動導電層20Bのうち接続部材90が配置される部分には、貫通孔24が形成されている。貫通孔24は、z方向において第2駆動導電層20Bを貫通している。接続部材90は、貫通孔24に挿通されて第2絶縁部材10Bの第2絶縁主面10Bsに接続されている。
 また、接続部材90は、第1駆動導電層20Aおよび第1絶縁部材10Aの第1絶縁主面10Asに跨って接続されてもよく、第2駆動導電層20Bおよび第2絶縁部材10Bの第2絶縁主面10Bsに跨って接続されてもよい。
 このように、接続部材90は、第1駆動導電層20Aおよび第1絶縁部材10Aの第1絶縁主面10Asのうちの少なくとも一方と、第2駆動導電層20Bおよび第2絶縁部材10Bの第2絶縁主面10Bsのうちの少なくとも一方一方とに接続されていればよい。接続部材90が第1絶縁部材10Aの第1絶縁主面10Asまたは第2絶縁部材10Bの第2絶縁主面10Bsに接続される場合、たとえば接続部材90を、導電性を有する材料、たとえば金属材料から構成されてもよい。
 ・上記実施形態において、第1接続層60Aおよび第2接続層60Bの構成は任意に変更可能である。一例では、各接続層60A,60Bは、はんだやAgペースト等の導電性接合材から構成されてもよい。この場合、第1接続層60Aのz方向の両端部に形成される各導電性接合材JA1,JA2を含めて、第1半導体素子50Aと第2駆動導電層20Bとを接続する第1接続層を構成する。また、第2接続層60Bのz方向の両端部に形成される各導電性接合材JB1,JB2を含めて、第2半導体素子50Bと第1駆動導電層20A(第2駆動配線22)とを接続する第2接続層を構成する。
 ・上記実施形態において、第1制御用端子84Aおよび第1検出用端子85Aはそれぞれ、樹脂側面74からx方向に突出してもよい。また第2制御用端子84Bおよび第2検出用端子85Bはそれぞれ、樹脂側面73からx方向に突出してもよい。
 ・上記実施形態において、制御用配線41Aおよび検出用配線42Aのそれぞれの配置位置は任意に変更可能である。一例では、検出用配線42Aが制御用配線41Aよりも第2駆動配線22の主配線部22aの近くに配置されてもよい。
 ・上記実施形態において、z方向から視た制御用配線41Aおよび検出用配線42Aの形状はそれぞれ任意に変更可能である。一例では、制御用配線41Aおよび検出用配線42Aのうち少なくとも一方について、第2駆動配線22と絶縁側面12Aとのy方向の間に配置された部分を省略してもよい。
 ・上記実施形態において、制御用配線41Bおよび検出用配線42Bのそれぞれの配置位置は任意に変更可能である。一例では、検出用配線42Bが制御用配線41Bよりも第2駆動導電層20Bの近くに配置されてもよい。
 ・上記実施形態において、第2駆動導電層20Bの構成は任意に変更可能である。一例では、第2駆動導電層20Bは、各第1半導体素子50Aが接続された第1導電部と、各第2半導体素子50Bが接続された第2導電部とに分割された構成であってもよい。この場合、第1導電部と第2導電部とは、導電性の連結部材によって接続されていてもよい。
 ・上記実施形態において、第1半導体素子50Aおよび第2半導体素子50Bの数は任意に変更可能である。第1半導体素子50Aおよび第2半導体素子50Bの数はそれぞれ、半導体装置1の特性に応じて、1個~3個、または5個以上であってもよい。
 ・上記実施形態において、第1接続層60Aおよび第2接続層60Bを省略してもよい。この場合、第1半導体素子50Aは、第2駆動導電層20Bと直接的に接続される。第2半導体素子50Bは、第1駆動導電層20Aの第2駆動配線22と直接的に接続される。なお、第1半導体素子50Aは、はんだやAgペースト等の導電性接合材を介して第2駆動導電層20Bと接続されてもよいし、第2駆動導電層20Bと接触した状態で第2駆動導電層20Bと接続されてもよい。また、第2半導体素子50Bは、はんだやAgペースト等の導電性接合材を介して第1駆動導電層20Aの第2駆動配線22と接続されてもよいし、第2駆動配線22と接触した状態で第2駆動配線22と接続されてもよい。
 ・上記実施形態において、第1半導体素子50Aと第1駆動導電層20Aの第1駆動配線21との間の接合材JAを省略してもよい。この場合、第1半導体素子50Aは、第1駆動配線21と接触した状態で第1駆動配線21と接続されている。
 ・上記実施形態において、第2半導体素子50Bと第2駆動導電層20Bとの間の接合材JBを省略してもよい。この場合、第2半導体素子50Bは、第2駆動導電層20Bと接触した状態で第2駆動導電層20Bに接続されている。
 ・上記実施形態では、第1半導体素子50Aが第2半導体素子50Bよりも第1絶縁部材10A寄りに配置されており、第2半導体素子50Bが第1半導体素子50Aよりも第2絶縁部材10B寄りに配置されていたが、これに限られない。たとえば、第1半導体素子50Aおよび第2半導体素子50Bはそれぞれ、第1絶縁部材10Aと第2絶縁部材10Bとのz方向の間の中央に配置されてもよい。第1半導体素子50Aおよび第2半導体素子50Bをそれぞれ、第1絶縁部材10Aと第2絶縁部材10Bとのz方向の間の中央に配置する構成としては、たとえば、接合材JA,JBや各接続層60A,60Bを省略する構成と、第1駆動配線21の厚さおよび第2駆動導電層20Bの厚さを厚くする構成とが挙げられる。
 ・上記実施形態において、第1半導体素子50Aおよび第2半導体素子50Bの構成はそれぞれ任意に変更可能である。一例では、第1半導体素子50Aの第1素子主面50Asにドレイン電極51A、ソース電極52Aおよびゲート電極53Aが形成されてもよい。この場合、ドレイン電極51Aは、ワイヤまたは帯状の接続部材によって第1駆動導電層20Aの第1駆動配線21と接続されている。また、第2半導体素子50Bの第2素子主面50Bsにドレイン電極51B、ソース電極52Bおよびゲート電極53Bが形成されてもよい。この場合、ドレイン電極51Bは、ワイヤまたは帯状の接続部材によって第2駆動導電層20Bと接続されている。
 ・上記実施形態において、各半導体素子50A,50Bは、ダイオード等のスイッチング素子以外の半導体素子であってもよい。
 1…半導体装置
 10A…第1絶縁部材
 10As…第1絶縁主面
 10Ar…第1絶縁裏面
 10B…第2絶縁部材
 10Bs…第2絶縁主面
 10Br…第2絶縁裏面
 20A…第1駆動導電層
 21…第1駆動配線
 22…第2駆動配線
 23…第3駆動配線
 20B…第2駆動導電層
 40B…制御導電層
 60A…第1接続層
 60B…第2接続層
 50A…第1半導体素子
 50As…第1素子主面
 50Ar…第1素子裏面
 51A…ドレイン電極(第1裏面側駆動電極)
 52A…ソース電極(第1主面側駆動電極)
 50B…第2半導体素子
 50Bs…第2素子主面
 50Br…第2素子裏面
 51B…ドレイン電極(第2裏面側駆動電極)
 52B…ソース電極(第2主面側駆動電極)
 70…封止樹脂
 90…接続部材
 92…端部対向壁(複数の第2半導体素子のうち第2方向の両端の第2半導体素子の一方を第2方向から取り囲む部分)
 93…中間対向壁(複数の第2半導体素子のうち第2方向において隣り合う第2半導体素子の間に位置する部分)
 200…冷却器

Claims (19)

  1.  厚さ方向において互いに反対側を向く第1絶縁主面および第1絶縁裏面を有しており、前記第1絶縁裏面が露出した第1絶縁部材と、
     前記第1絶縁主面上に設けられた第1駆動導電層と、
     前記第1駆動導電層に搭載された第1半導体素子と、
     前記厚さ方向において互いに反対側を向く第2絶縁主面および第2絶縁裏面を有しており、前記第2絶縁裏面が露出し、前記第2絶縁主面が前記第1絶縁主面と前記厚さ方向において対向するように前記第1絶縁部材に対して前記厚さ方向に離間して配置された第2絶縁部材と、
     前記第2絶縁主面上に設けられた第2駆動導電層と、
     前記第2駆動導電層に搭載された第2半導体素子と、
     前記第1絶縁部材および前記第1駆動導電層のうちの少なくとも一方と、前記第2絶縁部材および前記第2駆動導電層のうちの少なくとも一方との間に伝熱経路を形成する接続部材と、
     前記第1半導体素子、前記第2半導体素子および前記接続部材を封止する封止樹脂と、を備え、
     前記接続部材の熱伝導率は、前記封止樹脂の熱伝導率よりも高い
     半導体装置。
  2.  前記接続部材は、前記第2駆動導電層と接続している
     請求項1に記載の半導体装置。
  3.  前記厚さ方向から視て、前記接続部材は、前記第1半導体素子よりも前記第2半導体素子の近くに配置されている
     請求項1または2に記載の半導体装置。
  4.  前記第1半導体素子は、前記厚さ方向において互いに反対側を向く第1素子主面および第1素子裏面を有しており、前記第1素子裏面が前記第1駆動導電層と前記厚さ方向に対向するように配置されており、
     前記第1素子裏面には、第1裏面側駆動電極が設けられており、
     前記第1素子主面には、第1主面側駆動電極が設けられており、
     前記第2半導体素子は、前記厚さ方向において互いに反対側を向く第2素子主面および第2素子裏面を有しており、前記第2素子裏面が前記第2駆動導電層と前記厚さ方向に対向するように配置されており、
     前記第2素子裏面には、第2裏面側駆動電極が設けられており、
     前記第2素子主面には、第2主面側駆動電極が設けられている
     請求項1~3のいずれか一項に記載の半導体装置。
  5.  前記第1駆動導電層は、第1駆動配線および第2駆動配線を有しており、
     前記第1半導体素子は、前記第1裏面側駆動電極が前記第1駆動配線に電気的に接続されるように前記第1駆動配線に搭載されている
     請求項4に記載の半導体装置。
  6.  前記第2半導体素子は、前記第2裏面側駆動電極が前記第2駆動導電層に電気的に接続されるように前記第2駆動導電層に搭載されており、
     前記厚さ方向において前記第2半導体素子と前記第2駆動配線とが互いに離間した状態で対向しており、
     前記第2半導体素子と前記第2駆動配線との間には、前記第2主面側駆動電極と前記第2駆動配線とを電気的に接続する第2接続層が設けられている
     請求項5に記載の半導体装置。
  7.  前記厚さ方向において前記第1半導体素子と前記第2駆動導電層とが互いに離間した状態で対向しており、
     前記第1半導体素子と前記第2駆動導電層との間には、前記第1主面側駆動電極と前記第2駆動導電層とを電気的に接続する第1接続層が設けられている
     請求項6に記載の半導体装置。
  8.  前記厚さ方向と直交する方向のうち互いに直交する2方向を第1方向および第2方向とすると、
     前記第1駆動導電層は、前記第1方向において前記第2駆動配線と隣り合うように形成された第3駆動配線を有しており、
     前記第3駆動配線は、前記第2駆動配線と電気的に絶縁されており、
     前記接続部材は、前記第3駆動配線と前記第2駆動導電層とを接続している
     請求項5~7のいずれか一項に記載の半導体装置。
  9.  前記接続部材は、電気絶縁性を有する材料からなり、前記第1駆動配線と前記第2駆動導電層とを接続している
     請求項5~7のいずれか一項に記載の半導体装置。
  10.  前記第1半導体素子および前記第2半導体素子はそれぞれ、複数個設けられており、
     前記厚さ方向と直交する方向のうち互いに直交する2方向を第1方向および第2方向とすると、
     前記複数の第1半導体素子は、前記第1方向において互いに同じ位置で前記第2方向において互いに離間して配列されており、
     前記複数の第2半導体素子は、前記第1方向において互いに同じ位置で前記第2方向において互いに離間して配列されており、
     前記複数の第1半導体素子および前記複数の第2半導体素子は、前記第1方向において互いに離間して配置されており、
     前記厚さ方向から視て、前記接続部材は、前記第2方向に向けて延びている
     請求項5~9のいずれか一項に記載の半導体装置。
  11.  前記接続部材は、前記第1方向から視て、前記複数の第2半導体素子の全てと重なるように配置されている
     請求項10に記載の半導体装置。
  12.  前記接続部材は、前記第1方向において前記複数の第2半導体素子の全てと隣り合うように配置されている
     請求項11に記載の半導体装置。
  13.  前記第1方向における前記接続部材の大きさは、前記第1方向における前記第2半導体素子の大きさよりも小さい
     請求項10~12のいずれか一項に記載の半導体装置。
  14.  前記接続部材は、前記複数の第2半導体素子のうち前記第2方向の両端の第2半導体素子の一方を前記第2方向から取り囲む部分を有している
     請求項10~13のいずれか一項に記載の半導体装置。
  15.  前記接続部材は、前記複数の第2半導体素子のうち前記第2方向において隣り合う第2半導体素子の間に位置する部分を有している
     請求項10~14のいずれか一項に記載の半導体装置。
  16.  前記接続部材は、スプリング材を含む
     請求項1~13のいずれか一項に記載の半導体装置。
  17.  前記接続部材は、1または複数の柱状のスプリングプローブを含む
     請求項1~13のいずれか一項に記載の半導体装置。
  18.  前記第2絶縁主面上に設けられた制御導電層を有しており、
     前記厚さ方向から視て、前記接続部材は、前記第2半導体素子に対して前記制御導電層とは反対側に配置されている
     請求項1~17のいずれか一項に記載の半導体装置。
  19.  前記第1絶縁部材および前記第2絶縁部材はそれぞれ、セラミックスからなる
     請求項1~18のいずれか一項に記載の半導体装置。
PCT/JP2020/048436 2020-01-21 2020-12-24 半導体装置 WO2021149452A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US17/755,842 US20220384297A1 (en) 2020-01-21 2020-12-24 Semiconductor device
CN202080092851.7A CN114981959A (zh) 2020-01-21 2020-12-24 半导体装置
JP2021573030A JPWO2021149452A1 (ja) 2020-01-21 2020-12-24
DE112020005302.4T DE112020005302T5 (de) 2020-01-21 2020-12-24 Halbleiterbauteil
DE212020000610.5U DE212020000610U1 (de) 2020-01-21 2020-12-24 Halbleiterbauteil

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020007272 2020-01-21
JP2020-007272 2020-01-21

Publications (1)

Publication Number Publication Date
WO2021149452A1 true WO2021149452A1 (ja) 2021-07-29

Family

ID=76992301

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/048436 WO2021149452A1 (ja) 2020-01-21 2020-12-24 半導体装置

Country Status (5)

Country Link
US (1) US20220384297A1 (ja)
JP (1) JPWO2021149452A1 (ja)
CN (1) CN114981959A (ja)
DE (2) DE212020000610U1 (ja)
WO (1) WO2021149452A1 (ja)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004303900A (ja) * 2003-03-31 2004-10-28 Denso Corp 半導体装置
JP2013179229A (ja) * 2012-02-29 2013-09-09 Rohm Co Ltd パワーモジュール半導体装置
JP2014204006A (ja) * 2013-04-05 2014-10-27 三菱電機株式会社 電力用半導体装置
JP2015170605A (ja) * 2014-03-04 2015-09-28 ローム株式会社 半導体装置および半導体装置の製造方法
JP2016039206A (ja) * 2014-08-06 2016-03-22 トヨタ自動車株式会社 半導体装置の製造方法及び同半導体装置
US20180240731A1 (en) * 2017-02-22 2018-08-23 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004303900A (ja) * 2003-03-31 2004-10-28 Denso Corp 半導体装置
JP2013179229A (ja) * 2012-02-29 2013-09-09 Rohm Co Ltd パワーモジュール半導体装置
JP2014204006A (ja) * 2013-04-05 2014-10-27 三菱電機株式会社 電力用半導体装置
JP2015170605A (ja) * 2014-03-04 2015-09-28 ローム株式会社 半導体装置および半導体装置の製造方法
JP2016039206A (ja) * 2014-08-06 2016-03-22 トヨタ自動車株式会社 半導体装置の製造方法及び同半導体装置
US20180240731A1 (en) * 2017-02-22 2018-08-23 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure

Also Published As

Publication number Publication date
JPWO2021149452A1 (ja) 2021-07-29
CN114981959A (zh) 2022-08-30
DE212020000610U1 (de) 2021-12-21
US20220384297A1 (en) 2022-12-01
DE112020005302T5 (de) 2022-11-03

Similar Documents

Publication Publication Date Title
JP7069787B2 (ja) 半導体装置
JP7452597B2 (ja) 半導体装置及びその製造方法
JP5678884B2 (ja) 電力変換装置
CN109599384B (zh) 半导体器件
JP2013069782A (ja) 半導体装置
WO2021261508A1 (ja) 半導体装置
WO2020262212A1 (ja) 半導体装置
WO2020255663A1 (ja) 半導体装置及び半導体装置の製造方法
CN113228265A (zh) 半导体组件的电路构造
CN109427724B (zh) 具有三端子夹具的晶体管封装
WO2021149452A1 (ja) 半導体装置
JP7491043B2 (ja) 半導体モジュール
JP7484156B2 (ja) 半導体装置
JP2021197389A (ja) 半導体装置
JP2021180260A (ja) 半導体装置
WO2022264833A1 (ja) 半導体装置
US20230420341A1 (en) Power module for half-bridge circuit with scalable architecture and improved layout
WO2023149276A1 (ja) 半導体装置
WO2022224935A1 (ja) 半導体装置
US11990391B2 (en) Semiconductor device
WO2022145250A1 (ja) 半導体装置
WO2023199808A1 (ja) 半導体装置
WO2022075003A1 (ja) 半導体装置
KR102611687B1 (ko) 파워모듈
WO2023223802A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20915054

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021573030

Country of ref document: JP

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 20915054

Country of ref document: EP

Kind code of ref document: A1