WO2021143458A1 - 显示驱动器及控制方法、显示控制电路***、电子设备 - Google Patents

显示驱动器及控制方法、显示控制电路***、电子设备 Download PDF

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Publication number
WO2021143458A1
WO2021143458A1 PCT/CN2020/137698 CN2020137698W WO2021143458A1 WO 2021143458 A1 WO2021143458 A1 WO 2021143458A1 CN 2020137698 W CN2020137698 W CN 2020137698W WO 2021143458 A1 WO2021143458 A1 WO 2021143458A1
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Prior art keywords
display
frame
pulse
data
display data
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PCT/CN2020/137698
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English (en)
French (fr)
Inventor
韦育伦
王琨
王安立
汪亮
朱家庆
孙家亮
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20913810.6A priority Critical patent/EP4068256A4/en
Priority to US17/758,935 priority patent/US11935489B2/en
Publication of WO2021143458A1 publication Critical patent/WO2021143458A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
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    • G09G2320/00—Control of display operating conditions
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/08—Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/10—Display system comprising arrangements, such as a coprocessor, specific for motion video images
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
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    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline

Definitions

  • This application relates to the field of electronics and communication technology, and in particular to a display driver and control method, display control circuit system, and electronic equipment.
  • video mode video mode
  • command mode command mode
  • the display data can be transmitted to the display screen in real time according to the refresh rate sequence of the display screen.
  • the command mode the display data is first stored in the buffer, and then the display data is extracted from the buffer and transmitted to the display screen for display. In this way, only when the display image needs to be changed, the display data in the cache needs to be updated.
  • the display data of the dynamic image is more complicated and the processing time is longer.
  • the display cannot be retrieved because it is not stored in the cache in time.
  • the updated display data but the image displayed on the monitor cannot be updated. In this way, it will cause the electronic device to display a dynamic image when the image is stuck.
  • the present application provides a display driver, a control method, a display control circuit system, and an electronic device, which are used in a command mode to reduce the probability of screen freezing when displaying dynamic images.
  • the first aspect of the embodiments of the present application provides a display driver.
  • the display driver is used to drive the display screen for display.
  • the display driver includes a timing control unit, a transceiver unit, and a processing unit.
  • f1 is the first refresh rate of the display screen.
  • the first pulse of the split screen effect signal is used to instruct the host to output the generated Nth frame of display data in the N+1th frame according to the first pulse of the split screen effect signal.
  • N is a positive integer.
  • the transceiver unit is used to receive and send the display data sent by the host.
  • the timing control unit is also used to send the second pulses of S split-screen effect signals when the transceiver unit does not receive the Nth frame of display data at the preset time, and the second pulses of the S split-screen effect signals are used to send the second pulse of the S split-screen effect signals.
  • the duration of N frames is extended by the second preset time T2, and the host is instructed to output the generated Nth frame of display data in the N+1th frame according to the S second pulse of the split screen effect signal; where S is a positive integer . (T1+T2) ⁇ (1/f2); f2 is the second refresh rate of the display screen; the first refresh rate is greater than the second refresh rate.
  • the processing unit is coupled to the transceiver unit, and is used for receiving the Nth frame of display data in the N+1th frame, and controlling the display screen to display the Nth frame of image according to the Nth frame of display data.
  • the time interval between two adjacent first pulses in the split screen effect signal such as the first preset time T1 is beyond the display screen.
  • a first image can be reproduced by the split-screen effect signal.
  • Two pulses delay the duration of the frame to T1+T2, so that the host can complete the generation of display data in the Nth frame, and then control the display screen to display the Nth frame image in the N+1th frame.
  • the display driver will not control the display to repeatedly display the N-1th frame image because it cannot receive the Nth frame image. This can reduce the phenomenon of image freezing and reduce the power consumption of the display screen.
  • the display driver still has not received the Nth frame of display data within the preset time, and the display driver can continue to regenerate the second pulse of the above-mentioned split-screen effect signal until the Nth frame.
  • the host can complete the generation of the Nth frame of display data.
  • the duration after each Nth frame delay needs to match a resolution that the electronic device can support.
  • the display screen includes light emitting diodes.
  • the third preset time T3 is the same as the period of the light-emitting control signal.
  • the light-emitting control signal is used to control the effective light-emitting duration of the light-emitting diode. In this way, when the time of one frame is extended, the refresh rate of the frame will also be reduced.
  • the display screen 10 can be maintained when the resolution changes. The brightness is unchanged.
  • the display driver further includes a frame buffer unit coupled to the transceiver unit, and the frame buffer unit is used to buffer the display data received by the transceiver unit.
  • the processing unit is specifically configured to extract the N-th frame from the frame buffer unit when the timing control unit sends the second pulse of the S-th split-screen effect signal and the transceiver unit does not receive the N-th frame of display data in the N+1th frame. 1 frame of display data, and control the screen to display the N-1 frame image according to the N-1 frame display data.
  • the timing control unit when the timing control unit sends the second pulse of the S-th split-screen effect signal, and the transceiver unit does not receive the N-th frame of display data, the timing control unit of the display driver will start the screen self-refresh mechanism, which can be repeated Display the N-1th frame image to avoid display interruption on the screen.
  • the timing control unit is specifically configured to advance the first pulse of the split screen effect signal or the second pulse of the split screen effect signal in advance by a time change amount ⁇ T each time.
  • the time change ⁇ T is the time difference between the host receiving and sending data.
  • a second aspect of the embodiments of the present application provides a control method of a display driver for driving a display screen for display.
  • the method includes: first, sending a first pulse of a split screen effect signal every first preset time T1;
  • the first preset time T1 1/f1; f1 is the first refresh rate of the display screen.
  • the first pulse of the split screen effect signal is used to instruct the host to output the generated Nth frame of display data in the N+1th frame according to the first pulse of the split screen effect signal.
  • N is a positive integer.
  • the second pulses of S split-screen effect signals are sent, and the second pulses of the S split-screen effect signals are used to extend the duration of the Nth frame.
  • T2 Preset time
  • S is a positive integer
  • f2 is the second refresh rate of the display screen
  • the first refresh rate is greater than the second refresh rate.
  • T1+T2) (1/f2).
  • M ⁇ S, M is a positive integer
  • M ⁇ T3 T2.
  • the technical effect of sending the second pulse of the S split-screen effect signals is the same as that described above, and will not be repeated here.
  • the display screen includes light emitting diodes.
  • the third preset time T3 is the same as the period of the light-emitting control signal.
  • the light-emitting control signal is used to control the effective light-emitting duration of the light-emitting diode.
  • the technical effect of the third preset time T3 is the same as described above, and will not be repeated here.
  • the method further includes in the N+1th frame, when the Nth frame of display data is not received after the second pulse of the Sth split-screen effect signal is sent, extracting the N-1th frame of display data, and according to the The N-1 frame display data controls the display screen to display the N-1 frame image to start the screen self-refresh mechanism to avoid interruption of the displayed image.
  • the method further includes: sending the first pulse of the split screen effect signal or the second pulse of the split screen effect signal in advance by a time change amount ⁇ T each time.
  • the time change ⁇ T is the time difference between the host receiving and sending data.
  • the technical effect of sending the first pulse of the split screen effect signal or the second pulse of the split screen effect signal ahead of time by the amount of change ⁇ T is the same as that described above, and will not be repeated here.
  • a display control circuit system including: a display driver and a host coupled to the display driver.
  • the display driver includes a timing control unit, a transceiver unit, and a processing unit.
  • the timing control unit is used to send a first pulse of the screen splitting effect signal every first preset time T1.
  • the first preset time T1 1/f1.
  • f1 is the first refresh rate of the display screen.
  • the first pulse of the split screen effect signal is used to instruct the host to output the generated Nth frame of display data in the N+1th frame according to the first pulse of the split screen effect signal.
  • N is a positive integer.
  • the transceiver unit is used to receive the display data sent by the host.
  • the timing control unit is also used to send the second pulses of S split screen effect signals when the transceiver unit does not receive the Nth frame of display data at the preset time, and the second pulses of the S split screen effect signals are used to transfer the Nth frame of display data.
  • the duration of the frame is extended by the second preset time T2, and the host is instructed to output the generated Nth frame of display data in the N+1th frame according to the Sth second pulse of the split screen effect signal.
  • S is a positive integer; (T1+T2) ⁇ (1/f2); f2 is the second refresh rate of the display screen.
  • the first refresh rate is greater than the second refresh rate;
  • the processing unit is coupled to the transceiver unit, and is used for receiving the Nth frame of display data in the N+1th frame, and controlling the display screen to display the Nth frame of image according to the Nth frame of display data.
  • the host is used to output the generated Nth frame of display data in the N+1th frame according to the first pulse or the second pulse of the split screen effect signal.
  • the display control circuit system has the same technical effect as the display driver provided in the foregoing embodiment, and will not be repeated here.
  • the technical effect of sending the second pulse of the S split-screen effect signals is the same as that described above, and will not be repeated here.
  • the display screen includes light emitting diodes.
  • the third preset time T3 is the same as the period of the light-emitting control signal; the light-emitting control signal is used to control the effective light-emitting duration of the light-emitting diode.
  • the technical effect of the third preset time T3 is the same as described above, and will not be repeated here.
  • the display driver further includes a frame buffer unit coupled to the transceiver unit, and the frame buffer unit is used to buffer the display data received by the transceiver unit.
  • the processing unit is specifically configured to extract the N-th frame from the frame buffer unit when the timing control unit sends the second pulse of the S-th split-screen effect signal and the transceiver unit does not receive the N-th frame of display data in the N+1th frame. 1 frame of display data, and control the screen to display the N-1 frame image according to the N-1 frame display data. In this way, the screen self-refresh mechanism can be activated to avoid interruption of the displayed image.
  • the timing control unit is specifically configured to advance the first pulse of the split screen effect signal and the second pulse of the split screen effect signal in advance by a time change amount ⁇ T each time.
  • the time change ⁇ T is the time difference between the host receiving and sending data.
  • the technical effect of sending the first pulse of the split screen effect signal or the second pulse of the split screen effect signal ahead of time by the amount of change ⁇ T is the same as that described above, and will not be repeated here.
  • the host includes an image processing unit, a storage unit, and a display engine unit.
  • the image processing unit is used to generate the Nth frame of display data, and when generating the N+1th frame of display data, send the Nth frame of display data.
  • N is a positive integer.
  • the storage unit is coupled to the image processing unit, and is used for storing the Nth frame of display data generated by the image processing unit.
  • the display engine unit is coupled to the display driver and the storage unit, and is used for outputting the Nth frame of display data stored in the storage unit to the display driver in the N+1th frame according to the first pulse or the second pulse of the split screen effect signal .
  • the image processing unit in the host can generate each frame of display image and store it in the storage unit.
  • the display engine unit can send the display image stored in the storage unit to the display driver in the form of a data message when receiving the first pulse or the second pulse of the split screen effect signal, so that the display driver can drive the display according to the display data Display on the screen.
  • an electronic device including a display screen and the above-mentioned display control circuit system.
  • the display driver in the display control circuit system is coupled to the display screen, and is used to drive the display screen for display.
  • the electronic device has the same technical effect as the display driving circuit system provided by the foregoing embodiment, and will not be repeated here.
  • a computer-readable storage medium which stores a computer program, and when the computer program is executed by a processor, any one of the above methods is implemented.
  • the computer-readable storage medium has the same technical effect as the control method of the display driving circuit provided in the foregoing embodiment, and will not be repeated here.
  • FIG. 1a is a schematic structural diagram of a display screen provided by some embodiments of the application.
  • FIG. 1b is a schematic diagram of the structure of a pixel circuit and a light-emitting device in each sub-pixel in FIG. 1a;
  • FIG. 1c is a schematic diagram of a part of the structure of the pixel circuit in FIG. 1b;
  • FIG. 2 is a schematic structural diagram of an electronic device provided by some embodiments of the application.
  • FIG. 3 is a schematic diagram of the structure of the display control circuit system in FIG. 2;
  • FIG. 4 is a schematic diagram of a timing signal of an electronic device provided by related technologies
  • FIG. 5 is a schematic structural diagram of another electronic device provided by some embodiments of the application.
  • FIG. 6 is a schematic diagram of a timing signal of an electronic device provided by some embodiments of the application.
  • FIG. 7 is a schematic diagram of another timing signal of an electronic device provided by some embodiments of the application.
  • FIG. 8 is a schematic diagram of another timing signal of an electronic device provided by some embodiments of the application.
  • FIG. 9 is a schematic diagram of a display driver startup screen self-refresh mechanism provided by some embodiments of the application.
  • FIG. 10 is a schematic diagram of a signal sending manner of an electronic device according to some embodiments of the application.
  • FIG. 11 is a schematic diagram of another timing signal of an electronic device provided by some embodiments of the application.
  • FIG. 12 is a flowchart of a display driver control method provided by some embodiments of the application.
  • 10-display 100-AA area; 101-non-display area; 20-sub-pixel; 201-pixel circuit; 01-electronic equipment; 30-display driver; 301-timing control unit; 302-processing unit; 303-transceiver Unit; 304-frame buffer unit; 40-host; 401-GPU; 402-display engine unit; 403-storage unit; 50-light emitting control circuit.
  • azimuth terms such as “upper”, “lower”, “left”, “right”, etc. may include but are not limited to the directions defined relative to the schematic placement of the components in the drawings. It should be understood that these directions sexual terms can be relative concepts, and they are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the parts in the drawings.
  • Coupled may be an electrical connection method for signal transmission.
  • Coupled should be understood in a broad sense.
  • coupling can be a direct electrical connection or an indirect electrical connection through an intermediary.
  • the embodiments of the present application provide an electronic device.
  • the electronic device includes, for example, a TV, a mobile phone, a tablet computer, a palmtop computer, and a vehicle-mounted computer.
  • the embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic device.
  • the electronic device includes a display screen 10 for displaying images.
  • the display screen 10 may be a liquid crystal display (LCD).
  • the above-mentioned electronic device further includes a backlight module for providing a light source to the display screen 10.
  • the above-mentioned display screen 10 may be an organic light emitting diode (OLED) display screen, which can realize self-luminescence.
  • OLED organic light emitting diode
  • the display screen 10 includes an active display area (AA) 100 and a non-display area 101 located around the AA area 100.
  • the AA area 100 is used to display images.
  • the AA area 100 includes a plurality of sub pixels 20.
  • the above-mentioned multiple sub-pixels 20 in the present application are described by taking the arrangement of matrix as an example.
  • the sub-pixels 20 arranged in a row along the horizontal direction X are referred to as the same row of sub-pixels, and the sub-pixels 20 arranged in a row along the vertical direction Y are referred to as the same row of sub-pixels.
  • a pixel circuit 201 for controlling the sub-pixel 20 to display is provided.
  • the sub-pixel 20 further includes a light-emitting device L coupled to the pixel circuit 201 (as shown in FIG. 1b).
  • the light-emitting device L is an OLED, and its anode (anode, abbreviated as a) is coupled with the pixel circuit 201, and a cathode (cathode, abbreviated as c) is coupled with a voltage terminal VSS.
  • the aforementioned pixel circuit 201 is used to drive the light-emitting device OLED to emit light.
  • the pixel circuit 201 includes a plurality of switching transistors (for example, the transistor M1 and the transistor M2 shown in FIG. 1c) and one driving transistor (for example, the transistor Td shown in FIG. 1c).
  • the aforementioned pixel circuit 201 further includes a capacitor Cst as shown in FIG. 1c.
  • the light-emitting device L is an OLED
  • the light-emitting device L is a current light-emitting device, so by controlling the size of the data voltage Vdata, the size of the drive current I can be controlled, so that after the drive current I flows through the light-emitting device L, the control can be achieved
  • the purpose of the light-emitting device L to emit light.
  • some of the switching transistors in the pixel circuit 201 can control the on and off states of the current path formed between the voltage terminal VDD and the voltage terminal VSS, thereby controlling whether the driving current I is It can flow into the light emitting device L.
  • the gate of the transistor M2 is coupled to the emission control signal EM.
  • the light emission control signal EM is a square wave signal.
  • the duty ratio of the light emission control signal EM can be controlled, thereby controlling the effectiveness of the current path formed between the voltage terminal VDD and the voltage terminal VSS in each frame.
  • the turn-on duration that is, the effective duration of the driving current I flowing through the light-emitting device L, achieves the purpose of controlling the brightness of the light-emitting device L.
  • the electronic device 01 further includes a display control circuit system 02.
  • the display control circuit system 02 includes a display driver 30 as shown in FIG. 2 and a host 40 coupled to the display driver 30.
  • the above-mentioned display driver 30 may be a display driver IC (DDIC).
  • the above-mentioned display driver 30 can be bonded to the display screen 10 through pads provided in the non-display area 101 of the display screen 10.
  • the above-mentioned display driver 30 may use a mobile industry processor interface (MIPI) or other serial/deserial (serial/deserial, SerDes) high-speed interfaces.
  • MIPI mobile industry processor interface
  • SerDes serial/deserial
  • the host 40 may be an integrated circuit, a system on a chip (SoC), an application processor (AP), or a processor.
  • the display driver 30 includes a timing control unit (TCON) 301, a transceiver unit 303, and a processing unit 302 as shown in FIG. 3.
  • TCON timing control unit
  • transceiver unit 303 transceiver unit
  • processing unit 302 processing unit
  • the timing control unit 301 is configured to send a first pulse A of a tearing effect (TE) signal as shown in FIG. 4 every first preset time T1, where the first pulse A is high and the high The level is used as the effective signal of the TE signal.
  • TE tearing effect
  • the above-mentioned first preset time T1 1/f1.
  • f1 is the first refresh rate of the display screen 10.
  • the above-mentioned first refresh rate may be the highest refresh rate of the display screen 10, for example, 120 Hz.
  • N is a positive integer.
  • the aforementioned host 40 includes a graphics processing unit (GPU) 401.
  • the GPU 401 can generate the Nth frame (for example, the first frame) display data through data rendering and programming.
  • the aforementioned host 40 may further include a display engine (display engine) unit 402 and a storage unit 403 coupled to the GPU 401 and the display engine unit 402.
  • the above-mentioned storage unit 403 may be a double-rate synchronous dynamic random access memory (DDR SDRAM), or a system memory (SRAM).
  • DDR SDRAM double-rate synchronous dynamic random access memory
  • SRAM system memory
  • the storage unit 403 is coupled to the GPU 401, and the storage unit 403 is used to store the display data generated by the GPU 401, for example, the above-mentioned first frame display data.
  • the display engine unit 402 is coupled to the storage unit 403.
  • the display engine unit 402 can also be coupled to the timing control unit 301 in the display driver 30 through a high-speed interface, such as the MIPI interface described above.
  • the display engine unit 402 is used to receive the TE signal sent by the timing control unit 301, and according to the TE signal, the display engine unit 402 can extract the Nth frame (for example, the first frame) display data stored in the storage unit 403 and generated by the GPU401 (Indicated by 1 in Figure 4) for data processing, and the data packaged in the display command set (DCS) as the Nth frame (for example, the first frame) data packet is sent to the display driver by the above MIPI interface 30.
  • the Nth frame for example, the first frame
  • DCS display command set
  • the display data generated by each GPU 401 in FIG. 4 (for example, the first frame display data 1) is represented by two rectangles filled with patterns.
  • the first segment of the rectangle table performs data rendering
  • the second segment of rectangles represents the process of GPU401 programming processing.
  • the second frame generated by the GPU401 displays data.
  • the transceiver unit 303 in the display driver 30 may receive the Nth frame (for example, the first frame) DCS data packet sent by the display engine unit 402 through the MIPI interface. Based on this, when the display driver 30 further includes a frame buffer unit 304 coupled to the transceiving unit 303, the transceiving unit 303 may buffer the Nth frame (for example, the first frame) DCS data packet in the frame buffer unit 304 .
  • the processing unit 302 may extract the Nth frame (for example, the 1st frame) DCS data packet from the frame buffer unit 304, and according to the Nth frame (For example, the first frame)
  • the DCS data packet generates the above-mentioned data voltage Vdata for controlling each sub-pixel 20 to display.
  • the aforementioned processing unit 302 may include a data processing unit (process IP) and a source circuit (source circuit).
  • the data processing unit (process IP) can perform data decompression, image processing, image gamma value adjustment, etc. on the DCS data packet.
  • the source circuit (source circuit) can generate the aforementioned data voltage Vdata for controlling each sub-pixel 20 to display according to the data output by the data processing unit (process IP).
  • the timing control unit 301 in the display driver 30 receives the externally input vertical synchronization signal (V-Sync) as shown in FIG. 4 after each time the first pulse A of the TE signal is sent.
  • V-Sync vertical synchronization signal
  • the display driver 30 starts from the first row of sub-pixels 20 and scans the sub-pixels 20 row by row (along the X direction) to turn on some of the transistors in the pixel circuit 201 of each sub-pixel 20, as shown in FIG. 1c.
  • the transistor M1 The transistor M1.
  • the above-mentioned data voltage Vdata generated by the display driver 30 for controlling each sub-pixel 20 to display is transmitted through a data line (DL) as shown in FIG. 3
  • the above-mentioned data voltage Vdata is written to the driving transistor Td through the turned-on transistor M1. Therefore, the driving transistor Td of the pixel circuit 201 can generate the driving current I for driving the light emitting device L to emit light.
  • the display control circuit system 02 of the electronic device may also include a light emission control circuit 50 as shown in FIG. 5.
  • the above-mentioned light emitting control circuit 50 may be integrated in the non-display area 101 of the display screen 10 through the gate driver on array (GOA) technology.
  • the light emission control circuit 50 can provide the light emission control signal EM as shown in FIG. 4 to the gates of some transistors in the pixel circuit 201 of the sub-pixel 20 (for example, the transistor M2 in FIG. 1c) row by row. Therefore, when the light emission control signal EM is at a high level as shown in Fig. 4 (taking a high level as an effective signal as an example), the current path formed between the voltage terminal VDD and the voltage terminal VSS in Fig. 1c is turned on to achieve control The driving current I is the purpose of the effective time flowing into the light emitting device L.
  • the Nth frame of display data generated by GPU401 first.
  • the GPU401 when it generates the N+1th frame of display data, it stores the Nth frame of display data in the storage unit 403.
  • the display engine unit 402 extracts the Nth frame of display data from the storage unit 403, generates the Nth frame of DCS data packet, and sends it to the transceiver unit 303 of the display driver 30 through the MIPI interface.
  • the transceiver unit 303 can buffer the Nth frame of DCS data packet in the frame buffer unit 304.
  • the processing unit 302 extracts the Nth frame DCS data packet from the frame buffer unit 304, and drives the display screen 10 to display the Nth frame image.
  • the timing control unit 301 of the display driver 30 sends the first pulse A of the first TE signal (the first high-level pulse signal as shown in FIG. 4) to the display engine unit 402 of the host 40 , GPU401 generates the first frame of display data within the first frame time.
  • the display engine unit 402 cannot extract the above-mentioned first frame display data from the storage unit 403, so even under the first high level of V-Sync, the sub-pixels 20 in the display screen 10 are scanned line by line.
  • the MIPI interface and the display driver 30 for example, DDIC
  • the light-emitting control signal EM does not send a valid signal
  • the display screen 10 does not perform screen display.
  • the timing control unit 301 of the display driver 30 sends the first pulse A of the second TE signal to the display engine unit 402 of the host 40 (the second high-level pulse signal shown in FIG. 4)
  • the GPU401 generates the first pulse A (the second high-level pulse signal shown in FIG. 4).
  • the first frame of display data is stored in the storage unit 403.
  • the display engine unit 402 extracts the above-mentioned first frame display data from the storage unit 403, generates the first frame DCS data packet, and buffers the first frame DCS data packet 1 in the frame buffer unit 304 through the MIPI interface.
  • the processing unit 302 of the display driver 30 can extract the first frame DCS data packet 1 from the frame buffer unit 304 and generate the data voltage Vdata.
  • the emission control signal EM sends out an effective square wave signal.
  • the sub-pixels 20 in the display screen 10 are scanned line by line, thereby controlling the light-emitting devices L in each sub-pixel 20 to emit light, and the display screen 10 displays the first Frame image.
  • the timing control unit 301 of the display driver 30 sends another first pulse A of the TE signal to the display engine unit 402 of the host 40
  • the GPU401 generates the third frame of display data and displays the second frame at the same time.
  • the data is stored in the storage unit 403.
  • the display engine unit 402 extracts the second frame display data from the storage unit 403, generates the second frame DCS data packet, and buffers the second frame DCS data packet 2 in the frame buffer unit 304 through the MIPI interface.
  • the processing unit 302 of the display driver 30 obtains the second frame DCS data packet 2 from the frame buffer unit 304 after the preset idle time T IDLE to control the display screen 10. Within the frame, the second frame image is displayed.
  • the length of the preset idle time T IDLE is related to the performance and data processing speed of the GPU 401 and the display driver 30. This application does not limit the length of the preset idle time T IDLE , as long as the processing of the display driver 30 can be guaranteed.
  • the unit 302 can control the display screen 10 according to the DCS data packet 2 of the Nth frame (for example, the 2nd frame) obtained from the frame buffer unit 304. It is sufficient to display the Nth frame (for example, the second frame) image normally.
  • the timing control unit 301 of the display driver 30 sends the first pulse A of the third TE signal to the display engine unit 402 of the host 40, and then enters the third frame
  • the GPU401 since in the third frame, the GPU401 is still executing In the operation of generating the display data of the second frame, the display data of the first frame is still buffered in the storage unit 403. Therefore, in the third frame, the display engine unit 402 cannot send the second frame DCS data packet 2 to the transceiver unit 303 of the display driver 30 (such as DDIC) through the MIPI interface, so the MIPI interface is in IDLE in the third frame as shown in FIG. 4 state.
  • the processing unit 302 in the third frame display driver 30 can control the DCS data packet 1 in the first frame buffered in the second frame in the frame buffer unit 304
  • the display screen 10 repeatedly displays the first frame of image.
  • S is a positive integer.
  • the S-th second pulse B of the TE signal outputs the generated display data of the Nth (for example, frame 2) frame (that is, the second frame DCS data packet 2) in the N+1th (for example, frame 3) frame .
  • the duration of the second frame is T1+T2. (T1+T2) ⁇ (1/f2).
  • f2 is the second refresh rate of the display screen 10.
  • the first refresh rate f1 is greater than the second refresh rate f2.
  • the second refresh rate f2 96 Hz.
  • (T1+T2) (8.33ms+T2)
  • 1/f2 10.41ms. Therefore, (8.33ms+T2) ⁇ 10.41ms.
  • the time interval between the second pulse B of the TE signal and the third first pulse A of the TE signal may be the aforementioned second preset time T2.
  • the third high-level pulse of V-Sync will also delay the second preset time T2, so that the second frame can be extended to T1+T2.
  • the GPU401 completes the process of generating the display data of the second frame within the time of T1+T2 (that is, the second frame after the delay processing).
  • the display engine unit 402 can send the second frame DCS data packet 2 through the MIPI interface according to the Sth (for example, the first) second pulse B of the TE signal To the transceiver unit 303, and buffered in the frame buffer unit 304 through the transceiver unit 303.
  • the processing unit 302 of the display driver 30 can control the display screen 10 to display the Nth frame (for example, the second frame) image in the third frame as shown in FIG. 6 according to the second frame DCS data packet 2.
  • the time for GPU401 to generate a frame (for example, the second frame) of display data exceeds, the time interval between two adjacent first pulses in the TE signal, such as the first preset time T1, is beyond the display screen's time.
  • a second pulse B can be regenerated by the TE signal, and the The duration of the frame is delayed to T1+T2, so that the GPU401 can complete the generation of the second frame of display data in the second frame.
  • the processing unit 302 can control the display screen 10 to display the image of the second frame according to the display data of the second frame buffered in the frame buffer unit 304.
  • the display driver 30 for example, DDIC
  • the display screen 10 will not retrieve the image of the first frame from the frame buffer unit 304 because the image of the second frame is not received, and the display screen 10 repeatedly displays the first frame. image. This can reduce the chance of image jamming.
  • the duty cycle of the light emission control signal EM signal can be adjusted to achieve the purpose of adjusting the light emission brightness of the display screen 10. Therefore, in order to ensure the display brightness of the display screen 10 when the resolution changes No change, when the TE signal regenerates a second pulse B, the phase added to the TE signal (hereinafter referred to as the V-Porch phase, with a duration of T2) needs to include an integer multiple of the period T0 of the light emission control signal EM. In this way, the increased V-Porch stage does not change the duty cycle of the light-emitting control signal EM, so that the light-emitting brightness of the display screen 10 can remain unchanged when the resolution changes.
  • a second pulse B is regenerated through the TE signal to extend the Nth frame (for example, the second frame)
  • the duration is described by taking the GPU401 to complete the generation of the display data of the second frame as an example.
  • the transceiver unit 303 of the display driver 30 still has not received the Nth pulse at a preset time (for example, after the aforementioned preset idle time T IDLE).
  • the timing control unit 301 of the display driver 30 may continue to regenerate the second pulse B of the above TE signal until the duration of the Nth frame (for example, the second frame) is extended to enable GPU401 to complete the second Until the frame display data is generated.
  • the time length needs to match a resolution that the electronic device 01 can support.
  • the timing control unit 301 of the display driver 30 may be shown in FIG.
  • the resolution that the electronic device 01 can support includes a maximum resolution of 120 Hz; a minimum resolution of 60 Hz; and an intermediate resolution of 96 Hz.
  • the display engine unit 402 of the host 40 can send the first frame of the DCS data packet 1 through the MIPI interface in the second frame It is transmitted to the display driver 30, and the display driver 30 controls the display screen 10 to display according to the first frame DCS data packet 1.
  • the refresh rate of the frame will also decrease.
  • the timing control unit 301 of the display driver 30 sends the second pulse B of the TE signal to delay the duration of the second frame by T1+T3.
  • the refresh rate of the display screen 10 will be in the second frame, and as the duration of the second frame is extended, the maximum refresh rate is reduced from 120 Hz to the intermediate resolution of 96 Hz.
  • the timing control unit 301 of the display driver 30 does not transmit the second pulse of the TE signal and is in the holding state.
  • the timing control unit 301 of the display driver 30 sends the second pulse B of the TE signal to delay the duration of the second frame by T1+4 ⁇ T3.
  • the refresh rate of the display screen 10 will be in the second frame, and as the duration of the second frame is extended, the maximum refresh rate is reduced from 120 Hz to the minimum resolution of 60 Hz.
  • the GPU401 After the refresh rate of the display screen 10 is reduced to the minimum resolution of 60Hz, and the duration of the second frame is delayed to T1+4 ⁇ T3, as shown in Figure 8, the GPU401 generates the Nth frame (for example, the second frame ) The time to display data will still exceed T1+4 ⁇ T3.
  • the processing unit 302 of the display driver 30 can download from The frame buffer unit 304 extracts the N-1th frame (for example, the first frame) DCS data packet 1, and controls the display screen 10 to display the N-1th frame ( For example, the image of frame 1).
  • the GPU401 generates the Nth frame (for example, the second frame), the display data still cannot be sent to the display driver in the N+1th frame (for example, the third frame) 30.
  • the timing control unit of the display driver 30 301 will start the screen self-refresh (PSR) mechanism, so that the processing unit 302 of the display driver 30 can extract the N-1th frame (for example, the first frame) DCS data packet 1 from the frame buffer unit 304 to control the display
  • the screen 10 displays an image of the N-1th frame (for example, the first frame).
  • the display engine unit 402 can adjust the TE signal according to the first pulse A or the second pulse B of the TE signal.
  • the data generated by the GPU 401 can be sent to the transceiver unit 303 of the display driver 30.
  • ⁇ T time difference
  • the timing control unit 301 may advance by the above-mentioned time change ⁇ T each time (that is, using method 2), and send TE The first pulse of the effect signal or the second pulse of the TE signal.
  • the display engine unit 402 of the host 40 can display data in the second frame.
  • the first frame of DCS data packet 1 is transmitted to the display driver 30 through the MIPI interface, and the display driver 30 controls the display screen 10 to display the first frame of image according to the first frame of DCS data packet 1.
  • the timing control unit 301 of the display driver 30 does not transmit the second pulse of the TE signal and is in the holding state.
  • the timing control unit 301 of the display driver 30 sends the second pulse of the TE signal to delay the duration of the second frame by T1+3 ⁇ T3.
  • the refresh rate of the display screen 10 will be in the second frame, and as the duration of the second frame is extended, the maximum refresh rate is reduced from 96 Hz to the minimum resolution of 60 Hz.
  • the resolutions that can be supported by the electronic device 01 are 120 Hz, 96 Hz, and 60 Hz, or the resolutions that the electronic device 01 can support are: Take 96Hz and 60Hz as an example.
  • the user can also set the period T0 of the light-emitting control signal EM as needed.
  • the resolution supported by the electronic device 01 is not limited to the above-mentioned resolutions.
  • the embodiment of the present application provides a control method of the display driver 30, and the method is used to drive the display screen 10 for display. As shown in Figure 12, the method includes S101 to S103.
  • the first pulse A of the TE signal is used to instruct the host 40 to output the generated Nth frame of display data in the N+1th frame according to the first pulse A of the TE signal.
  • the GPU 401 in the host 40 is used to generate display data for each frame.
  • the display engine unit 402 is used to receive the TE signal sent by the timing control unit 301, and according to the TE signal, store the Nth frame (for example, the first frame) in the storage unit 403 in the N+1th frame (for example, the second frame)
  • the display data is sent to the display driver 30 in the form of a display command message.
  • S is a positive integer. (T1+T2) ⁇ (1/f2).
  • f2 is the second refresh rate of the display screen 10. The first refresh rate f1 is greater than the second refresh rate f2.
  • the display driver 30 cannot receive the second frame DCS data packet 2 in the preset time.
  • the timing control unit 301 of the display driver 30 may send the second pulses B of S TE signals to extend the duration of the Nth (for example, the second frame) frame by the second preset time T2, so that the GPU401 can be After the duration of the second frame is extended to T1+T2, the generation of the display data of the second frame can be completed.
  • the transceiver unit 303 of the display driver 30 still has not received the Nth frame (for example, the second frame) display data (ie, the second frame DCS data packet) within the preset time. 2), the timing control unit 301 of the display driver 30 may continue to regenerate the second pulse of the TE signal until the Nth frame (for example, the second frame) is delayed, so that the GPU401 can complete the generation of the second frame of display data.
  • M ⁇ S, and M is a positive integer.
  • M ⁇ T3 T2.
  • each time before the second pulse B of the TE signal is sent it can be judged whether the time that the second pulse B can extend the Nth frame duration is equal to the period corresponding to a resolution that the electronic device 01 can support. In this way, the length of time after each Nth frame (for example, the second frame) is delayed needs to be matched with a resolution that the electronic device 01 can support.
  • the refresh rate of the frame will also decrease.
  • the timing control unit 301 may advance by a time change ⁇ T each time, and send the first pulse of the TE effect signal or the first pulse of the TE signal.
  • the second pulse is the time difference between the host 40 receiving and sending data.
  • a second pulse B is regenerated by the TE signal, and the duration of the Nth frame (for example, the second frame) is delayed to T1+T2, so that the GPU401 can be completed in the Nth frame (for example, the second frame) Display data generation.
  • the display driver 30 can be caused to control the display screen 10 to display the image of the Nth frame (for example, the 2nd frame).
  • the above method further includes: in the N+1th frame, when the Nth frame (for example, the second frame) display data is not received after the second pulse B of the Sth TE signal is sent, it can be seen from the above that, in the Nth Frame (for example, frame 2), the resolution of the display screen 10 has been reduced to the lowest resolution, such as 60 Hz.
  • the timing control unit 301 of the display driver 30 will start the PSR mechanism, so that the processing unit 302 of the display driver 30 can extract the N-1th frame (for example, the first frame) DCS data packet 1 from the frame buffer unit 304 to control
  • the display screen 10 displays an image of the N-1th frame (for example, the first frame).
  • the transceiver unit 303 of the display driver 30 can receive the display data of the Nth frame (for example, the second frame), avoiding repeated display of the N-1th frame (for example, the first frame) image. Therefore, the timing control unit 301 of the display driver 30 does not activate the PSR mechanism many times, so it can effectively reduce the occurrence of image jamming.
  • an embodiment of the present application provides a computer-readable medium, which stores a computer program.
  • the computer program When the computer program is executed by the processor, the method as described above is realized.
  • the embodiment of the present application provides a computer program product containing instructions. When the computer program product runs on an electronic device, the electronic device is caused to execute the method as described above.
  • the computer-readable medium may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (ROM),
  • ROM read-only memory
  • ROM random access memory
  • RAM random access memory
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • the desired program code in the structural form and any other medium that can be accessed by the computer, but not limited to this.
  • the memory can exist independently and is connected to the processor through a communication bus. The memory can also be integrated with the processor.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • a software program it can be implemented in the form of a computer program product in whole or in part.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.

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Abstract

一种显示驱动器(30)及控制方法、显示控制电路***(02)、电子设备(01)，涉及电子及通信技术领域，用于命令模式下，减小显示动态图像时出现屏幕卡顿现象的几率以及降低显示屏(10)的功耗。显示驱动器(30)的时序控制单元(301)每隔第一预设时间T1发送一个裂屏效应(TE)信号的第一脉冲(A)。时序控制单元(301)当收发单元(303)，未在预设的时间接收第N帧显示数据时，发送S个裂屏效应(TE)信号的第二脉冲(B)，S个裂屏效应(TE)信号的第二脉冲(B)用于将第N帧的时长延长第二预设时间T2，并指示主机(40)根据裂屏效应(TE)信号的第S个第二脉冲(B)，将生成的第N帧显示数据在第N+1帧输出。处理单元(302)在第N+1帧接收第N帧显示数据，并根据第N帧显示数据控制显示屏(10)显示第N帧图像。

Description

显示驱动器及控制方法、显示控制电路***、电子设备
本申请要求于2020年01月17日提交国家知识产权局、申请号为202010054176.0、申请名称为“显示驱动器及控制方法、显示控制电路***、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子及通信技术领域，尤其涉及一种显示驱动器及控制方法、显示控制电路***、电子设备。
背景技术
具有显示功能的电子设备中，图像数据传输至电子设备中的显示屏的方式有两种：视频模式(video mode)和命令模式(command mode)。视频模式中，显示数据可以按照显示屏的刷新率时序，实时传输至显示屏。命令模式中，显示数据先存入缓存(buffer)中，再由缓存中提取显示数据传输至显示屏进行显示。这样一来，只有当需要更改显示图像时，才需要对缓存中的显示数据进行更新。
然而，在采用命令模式的情况下，当电子设备显示较复杂的动态图像时，动态图像的显示数据较为复杂、处理时间较长，从而会因为未及时存入缓存中，使得显示屏无法提取到更新后的显示数据，而无法对显示屏上显示的图像进行更新。这样一来，会使得电子设备显示动态图像时出现图像卡顿现象。
发明内容
本申请提供一种显示驱动器及控制方法、显示控制电路***、电子设备，用于命令模式下，减小显示动态图像时出现屏幕卡顿现象的几率。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种显示驱动器。该显示驱动器用于驱动显示屏进行显示。显示驱动器包括时序控制单元、收发单元以及处理单元。时序控制单元用于每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲；第一预设时间T1＝1/f1。f1为显示屏的第一刷新率。裂屏效应信号的第一脉冲用于指示主机根据裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出。其中，N为正整数。收发单元用于接收并发送主机发送的显示数据。时序控制单元还用于当收发单元，未在预设的时间接收第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个裂屏效应信号的第二脉冲用于将第N帧的时长延长第二预设时间T2，并指示主机根据裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，S为正整数。(T1+T2)≤(1/f2)；f2为显示屏的第二刷新率；第一刷新率大于第二刷新率。处理单元与收发单元耦接，用于在第N+1帧接收第N帧显示数据，并根据第N帧显示数据控制显示屏显示第N帧图像。综上所述，当主机生成一帧，例如第N帧显示数据的时间超过，裂屏效应信号中相邻两个第一脉冲的时间间隔，例如第一预设时间T1时，即超过显示屏正常显示采用的分辨率(例如第一分辨率f1＝120Hz)对应的 每帧图像的时长(例如，T1＝1/f1＝1/120Hz＝8.33ms)时，可以通过裂屏效应信号再生一个第二脉冲，将该帧的时长延时至T1+T2，从而能够使得主机在第N帧内能够完成显示数据的生成，进而在第N+1帧可以控制显示屏显示第N帧的图像。这样一来，在第N+1帧，显示驱动器不会因为接收不到第N帧的图像，而控制显示屏重复显示第N-1帧图像。从而能够减小图像卡顿的现象，以及降低显示屏的功耗。
可选的，时序控制单元具体用于连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送裂屏效应信号的第二脉冲。当发送第S个裂屏效应信号的第二脉冲时，第N帧结束，第N帧的时长(T1+T2)＝(1/f2)。其中，M≥S，M为正整数；M×T3＝T2。这样一来，当裂屏效应信号再生一个第二脉冲后，显示驱动器仍然未在预设的时间接收第N帧显示数据，显示驱动器可以继续再生上述裂屏效应信号的第二脉冲，直至第N帧的时长延时后，能够使得主机完成第N帧显示数据的生成。其中，每次第N帧延时的后的时长需要与电子设备能够支持的一个分辨率相匹配。
可选的，显示屏包括发光二极管。第三预设时间T3与发光控制信号的周期相同。发光控制信号用于控制发光二极管的有效发光时长。这样一来，当一帧的时间延长时，该帧的刷新率也会降低，当第三预设时间T3与发光控制信号的周期相同时，可以使得显示屏10在分辨率发生变化时，保持亮度不变。
可选的，显示驱动器还包括与收发单元耦接的帧缓存单元，帧缓存单元用于对收发单元接收到的显示数据进行缓存。处理单元具体用于在第N+1帧，当时序控制单元发送第S个裂屏效应信号的第二脉冲后，收发单元未接收第N帧显示数据时，从帧缓存单元中提取第N-1帧显示数据，并根据第N-1帧显示数据控制显示屏显示第N-1帧图像。这样一来，当时序控制单元发送第S个裂屏效应信号的第二脉冲后，收发单元未接收第N帧显示数据时，显示驱动器的时序控制单元会启动屏幕自刷新机制，从而可以通过重复显示第N-1帧图像，避免显示屏出现显示中断的现象发生。
可选的，时序控制单元具体用于每次提前一个时间变化量△T，发送裂屏效应信号的第一脉冲或裂屏效应信号的第二脉冲。其中，时间变化量△T为主机接收和发送数据的时间差。从而可以提高整个显示控制电路***处理数据的时效性。
本申请实施例的第二方面，提供一种显示驱动器的控制方法，用于驱动显示屏进行显示，方法包括：首先，每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲；第一预设时间T1＝1/f1；f1为显示屏的第一刷新率。裂屏效应信号的第一脉冲用于指示主机根据裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出。其中，N为正整数。接下来，当未在预设的时间接收第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个裂屏效应信号的第二脉冲用于将第N帧的时长延长第二预设时间T2，并指示主机根据裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出。其中，S为正整数；(T1+T2)≤(1/f2)；f2为显示屏的第二刷新率；第一刷新率大于第二刷新率。接下来，在第N+1帧，接收第N帧显示数据，并根据第N帧显示数据控制显示屏显示第N帧图像。该显示驱动器的控制方法具有与前述实施例提供的显示驱动器相同的技术效果，此处不再赘述。
可选的，在预设的时间之后，未接收第N帧显示数据时，发送S个裂屏效应信号 的第二脉冲包括：连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送裂屏效应信号的第二脉冲。当发送第S个裂屏效应信号的第二脉冲时，第N帧结束，第N帧的时长(T1+T2)＝(1/f2)。其中，M≥S，M为正整数；M×T3＝T2。上述发送S个裂屏效应信号的第二脉冲的技术效果同上所述，此处不再赘述。
可选的，显示屏包括发光二极管。第三预设时间T3与发光控制信号的周期相同。发光控制信号用于控制发光二极管的有效发光时长。第三预设时间T3时长的技术效果同上所述，此处不再赘述。
可选的，方法还包括在第N+1帧，当发送第S个裂屏效应信号的第二脉冲后，未接收第N帧显示数据时，提取第N-1帧显示数据，并根据第N-1帧显示数据控制显示屏显示第N-1帧图像，以启动屏幕自刷新机制，避免显示图像发生中断。
可选的，方法还包括：每次提前一个时间变化量△T，发送裂屏效应信号的第一脉冲或裂屏效应信号的第二脉冲。其中，时间变化量△T为主机接收和发送数据的时间差。提前一个时间变化量△T，发送裂屏效应信号的第一脉冲或裂屏效应信号的第二脉冲的技术效果同上所述，此处不再赘述。
本申请实施例的第三方面，提供一种显示控制电路***，包括：显示驱动器以及与显示驱动器耦接的主机。显示驱动器包括时序控制单元、收发单元以及处理单元。时序控制单元用于每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲。第一预设时间T1＝1/f1。f1为显示屏的第一刷新率。裂屏效应信号的第一脉冲用于指示主机根据裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出。其中，N为正整数。收发单元用于接收主机发送的显示数据。时序控制单元还用于当收发单元未在预设的时间接收第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个裂屏效应信号的第二脉冲用于将第N帧的时长延长第二预设时间T2，并指示主机根据裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出。其中，S为正整数；(T1+T2)≤(1/f2)；f2为显示屏的第二刷新率。第一刷新率大于第二刷新率；处理单元与收发单元耦接，用于在第N+1帧，接收第N帧显示数据，根据第N帧显示数据控制显示屏显示第N帧图像。主机用于根据裂屏效应信号的第一脉冲或第二脉冲，将生成的第N帧显示数据在第N+1帧输出。该显示控制电路***具有与前述实施例提供的显示驱动器相同的技术效果，此处不再赘述。
可选的，时序控制单元具体用于连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送裂屏效应信号的第二脉冲；当发送第S个裂屏效应信号的第二脉冲时，第N帧结束，第N帧的时长(T1+T2)＝(1/f2)。其中，M≥S，M为正整数；M×T3＝T2。上述发送S个裂屏效应信号的第二脉冲的技术效果同上所述，此处不再赘述。
可选的，显示屏包括发光二极管。第三预设时间T3与发光控制信号的周期相同；发光控制信号用于控制发光二极管的有效发光时长。第三预设时间T3时长的技术效果同上所述，此处不再赘述。
可选的，显示驱动器还包括与收发单元耦接的帧缓存单元，帧缓存单元用于对收发单元接收到的显示数据进行缓存。处理单元具体用于在第N+1帧，当时序控制单元发送第S个裂屏效应信号的第二脉冲后，收发单元未接收第N帧显示数据时，从帧缓 存单元中提取第N-1帧显示数据，并根据第N-1帧显示数据控制显示屏显示第N-1帧图像。从而可以启动屏幕自刷新机制，避免显示图像发生中断。
可选的，时序控制单元具体用于每次提前一个时间变化量△T，发送裂屏效应信号的第一脉冲和裂屏效应信号的第二脉冲。其中，时间变化量△T为主机接收和发送数据的时间差。提前一个时间变化量△T，发送裂屏效应信号的第一脉冲或裂屏效应信号的第二脉冲的技术效果同上所述，此处不再赘述。
可选的，主机包括图像处理单元、存储单元以及显示引擎单元。图像处理单元用于生成第N帧显示数据，并在生成第N+1帧显示数据时，发送第N帧显示数据。其中，N为正整数。存储单元与图像处理单元耦接，用于对图像处理单元生成的第N帧显示数据进行存储。显示引擎单元与显示驱动器和存储单元耦接，用于根据裂屏效应信号的第一脉冲或第二脉冲，在第N+1帧将存储于存储单元中的第N帧显示数据输出至显示驱动器。该主机中的图像处理单元可以生成每一帧显示图像，并将其存储于存储单元内。显示引擎单元可以在接收到裂屏效应信号的第一脉冲或者第二脉冲时，将存储单元存储的显示图像以数据报文的形式发送至显示驱动器，从而使得显示驱动器能够根据该显示数据驱动显示屏进行显示。
本申请实施例的第四方面，提供一种电子设备，包括显示屏以及如上所述的显示控制电路***。显示控制电路***中的显示驱动器与显示屏耦接，且用于驱动显示屏进行显示。该电子设备具有与前述实施例提供的显示驱动电路***相同的技术效果，此处不再赘述。
本申请实施例的第五方面，提供一种计算机可读存储介质，其存储有计算机程序，计算机程序被处理器执行时实现如上的任意一种方法。该计算机可读存储介质具有与前述实施例提供的显示驱动电路的控制方法相同的技术效果，此处不再赘述。
附图说明
图1a为本申请的一些实施例提供的一种显示屏的结构示意图；
图1b为图1a中每个亚像素内像素电路和发光器件的结构示意图；
图1c为图1b中像素电路的部分结构示意图；
图2为本申请的一些实施例提供的一种电子设备的结构示意图；
图3为图2中的显示控制电路***的结构示意图；
图4为相关技术提供的电子设备的一种时序信号示意图；
图5为本申请的一些实施例提供的另一种电子设备的结构示意图；
图6为本申请的一些实施例提供的电子设备的一种时序信号示意图；
图7为本申请的一些实施例提供的电子设备的另一种时序信号示意图；
图8为本申请的一些实施例提供的电子设备的另一种时序信号示意图；
图9为本申请的一些实施例提供的显示驱动器启动屏幕自刷新机制的示意图；
图10为本申请的一些实施例提供的电子设备信号发送方式示意图；
图11为本申请的一些实施例提供的电子设备的另一种时序信号示意图；
图12为本申请的一些实施例提供的显示驱动器的控制方法流程图。
附图标记：
10-显示屏；100-AA区；101-非显示区；20-亚像素；201-像素电路；01-电子设备； 30-显示驱动器；301-时序控制单元；302-处理单元；303-收发单元；304-帧缓存单元；40-主机；401-GPU；402-显示引擎单元；403-存储单元；50-发光控制电路。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“耦接”可以是实现信号传输的电性连接的方式。“耦接”应做广义理解，例如，“耦接”可以是直接的电性连接，也可以通过中间媒介间接电性连接。
本申请实施例提供一种电子设备，该电子设备包括例如电视、手机、平板电脑、掌上电脑、车载电脑等。本申请实施例对上述电子设备的具体形式不做特殊限制。如图1a所示，电子设备包括用于显示图像的显示屏10。
在一些实施例中，该显示屏10可以为液晶显示屏(liquid crystal display，LCD)。在此情况下，上述电子设备还包括用于向显示屏10提供光源的背光模组。或者，在另一些实施例中，上述显示屏10可以为有机发光二极管(organic light emitting diode，OLED)显示屏，该OLED显示屏能够实现自发光。
对于上述任意一种显示屏10而言，显示屏10包括有效显示区(active area，AA)100和位于该AA区100周边的非显示区101。AA区100用于显示图像。该AA区100包括多个亚像素(sub pixel)20。为了方便说明，本申请中上述多个亚像素20是以矩阵形式排列为例进行的说明。
需要说明的是，本申请实施例中，沿水平方向X排列成一排的亚像素20称为同一行亚像素，沿竖直方向Y排列成一排的亚像素20称为同一列亚像素。
AA区100中的亚像素20内，设置有用于控制亚像素20进行显示的像素电路201。当上述显示屏10为OLED显示屏时，该亚像素20内还包括与该像素电路201耦接的发光器件L(如图1b所示)。该发光器件L为OLED，其阳极(anode，简称a)与像素电路201耦接，阴极(cathode，简称c)与电压端VSS耦接。上述像素电路201用于驱动发光器件OLED进行发光。
像素电路201包括多个开关晶体管(例如，图1c所示的晶体管M1和晶体管M2)和一个驱动晶体管(例如，图1c所示的晶体管Td)。一些开关晶体管，例如晶体管M1导通时可以将数据电压Vdata写入至驱动晶体管Td，从而使得驱动晶体管Td产生的驱动电流I的大小与上述数据电压Vdata相关。例如，I＝1/2×μ×Cgi×W/L×(Vsg-|Vth|) 2。其中，μ为驱动晶体管M4的载流子迁移率；Cgi为驱动晶体管M4的栅极 与沟道之间的电容；W/L为驱动晶体管M4的宽长比，Vth为驱动晶体管M4的阈值电压。此外，上述像素电路201还包括如图1c所示的电容Cst。
由于发光器件L为OLED时，该发光器件L为电流发光器件，所以通过控制数据电压Vdata的大小，就可以控制驱动电流I的大小，从而在驱动电流I流过发光器件L后，能够达到控制发光器件L发光亮度的目的。
此外，上述像素电路201中一些开关晶体管，例如晶体管M2，在驱动晶体管Td导通后，可以控制电压端VDD与电压端VSS之间形成的电流通路的通、断状态，从而控制驱动电流I是否能够流入到发光器件L。如图1c所示，晶体管M2的栅极与发光控制信号EM相耦接。发光控制信号EM为方波信号。
这样一来，通过脉冲宽度调制(pulse width modulation)方式，可以控制发光控制信号EM的占空比(duty ratio)，从而控制每帧内电压端VDD与电压端VSS之间形成的电流通路的有效导通时长，即驱动电流I流过发光器件L的有效时长，达到控制发光器件L发光亮度的目的。
由上述可知，为了向上述各个亚像素20中的像素电路201提供数据电压Vdata，该电子设备01还包括显示控制电路***02。该显示控制电路***02包括如图2所示的显示驱动器30以及与该显示驱动器30耦接的主机40。
在本申请的一些实施例中，上述显示驱动器30可以为显示驱动集成电路(display driver IC，DDIC)。在此情况下，上述显示驱动器30可以通过设置于显示屏10的非显示区101的焊盘，邦定(bonding)于该显示屏10上。此外，上述显示驱动器30可以通过移动产业处理器接口(mobile industry processor interface，MIPI)或者，其他的串行器/解串器(serial/deserial，SerDes)高速接口。为了方便说明，以下均是以MIPI接口为例进行的说明。与主机40相耦接。此外，在本申请的一些实施例中，上述主机40可以集成电路、片上***(system on a chip，SoC)、应用处理器(application processor，AP)，或处理器。
在此情况下，在上述电子设备采用命令模式传输显示数据的情况下，显示驱动器30包括如图3所示的时序控制单元(timing controlle，TCON)301、收发单元303以及处理单元302。
时序控制单元301用于每隔第一预设时间T1发送如图4所示的一个裂屏效应(tearing effect，TE)信号的第一脉冲A，该第一脉冲A为高电平，该高电平作为TE信号的有效信号。
其中，上述第一预设时间T1＝1/f1。f1为显示屏10的第一刷新率。示例的，上述第一刷新率可以为显示屏10的最高刷新率，例如120Hz。以该第一刷新率f1＝120Hz为例，上述第一预设时间T1＝1/f1＝1/120＝8.33ms。TE信号的第一脉冲A用于指示主机40根据TE信号的第一脉冲A，将生成的第N帧(例如，N＝1为第1帧)显示数据在第N+1帧(例如第2帧)输出。其中，N为正整数。
此外，如图3所示，上述主机40包括图像处理单元(graphics processing unit，GPU)401。GPU401可以通过数据渲染(rendering)和编程(programming)处理，生成第N帧(例如第1帧)显示数据。基于此，上述主机40还可以包括显示引擎(display engine)单元402以及与GPU401和显示引擎单元402耦接的存储单元403。在本申请的一些 实施例中，上述存储单元403可以为双倍速率同步动态随机内存(double data rate synchronous dynamic random access memory，DDR SDRAM)，或者***内存(SRAM)。存储单元403与GPU401耦接，存储单元403用于对GPU401生成的显示数据，例如上述第1帧显示数据进行存储。
此外，显示引擎单元402与存储单元403耦接。并且，该显示引擎单元402还可以通过高速接口，例如上述MIPI接口与显示驱动器30中的时序控制单元301耦接。显示引擎单元402用于接收时序控制单元301发送的TE信号，并根据TE信号，该显示引擎单元402可以提取存储单元403中存储的，由GPU401生成的第N帧(例如第1帧)显示数据(图4中采用①表示)进行数据处理，并将打包到显示命令集(display command set，DCS)中的数据，作为第N帧(例如第1帧)数据包由上述MIPI接口发送至显示驱动器30。
需要说明的是，本申请实施例附图中，例如图4中每个GPU401生成的显示数据(例如第1帧显示数据①)采用两段填充有花纹的矩形表示。GPU401在生成显示数据的过程中，从左至右第一段矩形表进行数据渲染的过程，第二段矩形表示GPU401进行编程处理的过程。
接下来，在第N+1帧(例如N＝1，第2帧)，GPU401生成的第2帧显示数据。显示驱动器30中的收发单元303可以通过MIPI接口接收到显示引擎单元402发送的上述第N帧(例如第1帧)DCS数据包。基于此，在显示驱动器30还包括与收发单元303耦接的帧缓存(frame buffer)单元304时，收发单元303可以将第N帧(例如第1帧)DCS数据包缓存于帧缓存单元304中。
与此同时，在第N+1帧(例如N＝1，第2帧)，处理单元302可以从帧缓存单元304中提取第N帧(例如第1帧)DCS数据包，并根据第N帧(例如第1帧)DCS数据包生成控制各个亚像素20进行显示的上述数据电压Vdata。
在本申请的一些实施例中，上述处理单元302可以包括数据处理单元(process IP)以及源极电路(source circuit)。其中，数据处理单元(process IP)可以对DCS数据包进行数据解压、图像处理、图像伽玛(gamma)值调整等。源极电路(source circuit)可以根据数据处理单元(process IP)输出的数据生成用于控制各个亚像素20进行显示的上述数据电压Vdata。
基于此，显示驱动器30中时序控制单元301会在每次发出TE信号的第一脉冲A后，接收到外部输入的如图4所示的垂直同步信号(V-Sync)。此时，显示驱动器30会从第一行亚像素20开始，逐行(沿X方向)对亚像素20进行扫描，以导通各个亚像素20的像素电路201中的部分晶体管，例如图1c中的晶体管M1。
这样一来，当一行亚像素20被扫描后，显示驱动器30生成的上述用于控制各个亚像素20进行显示的上述数据电压Vdata，通过如图3所示的数据线(data line，DL)传输至每个亚像素20的像素电路201中。上述数据电压Vdata通过导通的晶体管M1写入至驱动晶体管Td。从而能够使得像素电路201的驱动晶体管Td生成用于驱动发光器件L进行发光的驱动电流I。
在此基础上，由上述可知，还可以通过控制驱动电流I流过发光器件L的有效时长，进一步控制发光器件L发光亮度。在此情况下，电子设备的显示控制电路***02 还可以包括如图5所示的发光控制电路50。上述发光控制电路50可以通过阵列基板行驱动(gate driver on array，GOA)技术，集成于显示屏10的非显示区101内。
该发光控制电路50可以逐行向亚像素20的像素电路201中的部分晶体管(例如，图1c中的晶体管M2)的栅极提供如图4所示的发光控制信号EM。从而在发光控制信号EM如图4所示处于高电平(以高电平为有效信号为例)时，将图1c中电压端VDD与电压端VSS之间形成的电流通路导通，达到控制驱动电流I是流入到发光器件L的有效时长的目的。这样一来，显示驱动器30通过MIPI接口获取主机40中显示引擎单元402发送的DCS数据包，可以获得数据电压Vdata，从而可以通过数据电压Vdata，并结合调节发光控制信号EM的占空比，达到控制显示屏10显示第N(例如N＝1)帧图像的目的。
综上所述，GPU401首先生成的第N帧显示数据。接下来，当GPU401生成第N+1帧显示数据的同时，将该第N帧显示数据存储于存储单元403中。与此同时，显示引擎单元402从存储单元403中提取上述第N帧显示数据，生成第N帧DCS数据包，并通过MIPI接口发送至显示驱动器30的收发单元303。收发单元303可以将第N帧DCS数据包缓存于帧缓存单元304中。处理单元302从帧缓存单元304中提取第N帧DCS数据包，并驱动显示屏10显示第N帧图像。
在此情况下，当显示驱动器30的时序控制单元301向主机40的显示引擎单元402发出第一个TE信号的第一脉冲A(如图4所示的第一个高电平脉冲信号)时，GPU401在第1帧时间内，生成第1帧显示数据。此时，显示引擎单元402无法从存储单元403中提取上述第1帧显示数据，因此即使在V-Sync第一次高电平的作用下，显示屏10中的亚像素20被逐行进行扫描，但是由于MIPI接口和显示驱动器30(例如DDIC)处于空闲(IDLE)状态，且发光控制信号EM未发出有效信号，所以显示屏10未进行画面显示。
接下来，显示驱动器30的时序控制单元301向主机40显示引擎单元402发出第二个TE信号的第一脉冲A(如图4所示的第二个高电平脉冲信号)时，GPU401生成第2帧显示数据的同时，将该第1帧显示数据存储于存储单元403中。显示引擎单元402从存储单元403中提取上述第1帧显示数据，生成第1帧DCS数据包，并通过MIPI接口将第1帧DCS数据包①缓存于帧缓存单元304中。显示驱动器30的处理单元302可以从帧缓存单元304中，将第1帧DCS数据包①提取，并生成数据电压Vdata。在如图4所示的第2帧内，发光控制信号EM发出有效的方波信号。此外，在V-Sync第二次高电平的作用下，显示屏10中的亚像素20被逐行进行扫描，从而控制各个亚像素20中的发光器件L进行发光，显示屏10显示第1帧图像。
同理可得，当显示驱动器30的时序控制单元301向主机40的显示引擎单元402发出又一个TE信号的第一脉冲A时，GPU401生成第3帧显示数据的同时，将该第2帧显示数据存储于存储单元403中。显示引擎单元402从存储单元403中提取上述第2帧显示数据，生成第2帧DCS数据包，并通过MIPI接口将第2帧DCS数据包②缓存于帧缓存单元304。与此同时，显示驱动器30的处理单元302在预设空闲时间T IDLE之后，从帧缓存单元304中获得第2帧DCS数据包②，以控制显示屏10，在如图4所示的第3帧内，显示第2帧图像。
需要说明的是，预设空闲时间T IDLE的长短与GPU401以及显示驱动器30的性能、数据处理速度有关，本申请对预设空闲时间T IDLE的长短不做限定，只要能够保证显示驱动器30的处理单元302在第N+1帧(例如第3帧)的预设空闲时间T IDLE之后，根据从帧缓存单元304中获得第N帧(例如第2帧)DCS数据包②，能够控制显示屏10正常显示第N帧(例如第2帧)图像即可。
然而，目前相关技术中，当电子设备显示较复杂的动态图像，例如用户玩大型游戏时，GPU401在一帧内，例如图4所示的第2帧(即T1＝8.33ms内)无法完成第2帧显示数据的生成。因此，在第3帧GPU401无法在生成第3帧显示数据的同时，将第2帧显示数据存储于存储单元403中。所以图4中的第3帧，存储单元403中的数据无法得到更新。
这样一来，当显示驱动器30的时序控制单元301向主机40的显示引擎单元402发送第三个TE信号的第一脉冲A后，进入第3帧时，由于在第3帧，GPU401仍然在执行生成第2帧显示数据的动作，存储单元403中仍然缓存有第1帧显示数据。所以在第3帧，显示引擎单元402无法将第2帧DCS数据包②通过MIPI接口发送至显示驱动器30(例如DDIC)的收发单元303，所以如图4所示MIPI接口在第3帧处于IDLE状态。
在此情况下，如图4所示，在第3帧显示驱动器30(例如DDIC)中的处理单元302可以根据帧缓存单元304中，在第2帧缓存的第1帧DCS数据包①，控制显示屏10重复显示第1帧图像。从而导致电子设备显示复杂图像时，由于相邻两帧重复显示相同的图像，而出现图像卡顿的现象。
为了解决上述问题，当显示驱动器30中的收发单元303未在预设的时间(例如图4中的预设空闲时间T IDLE之后)接收第N帧(例如第2帧)显示数据(即第2帧DCS数据包②)时，本申请实施例提供的显示驱动器30的时序控制单元301可以发送S(例如，S＝1)个TE信号的第二脉冲B(如图6所示)。上述第二脉冲B为高电平，该高电平作为TE信号的有效信号。其中，S为正整数。
如图6所示，S(例如，S＝1)个TE信号的第二脉冲B用于将第N(例如，第2帧)帧的时长延长第二预设时间T2，并指示主机40根据TE信号的第S个第二脉冲B，将生成的第N(例如，第2帧)帧显示数据(即第2帧DCS数据包②)在第N+1(例如，第3帧)帧输出。
在此情况下，第2帧的时长为T1+T2。(T1+T2)≤(1/f2)。f2为显示屏10的第二刷新率。第一刷新率f1大于第二刷新率f2。例如，第一刷新率f1＝120Hz。第二刷新率f2＝96Hz。在此情况下，T1＝1/f1＝8.33ms，(T1+T2)＝(8.33ms+T2)，1/f2＝10.41ms。因此，(8.33ms+T2)≤10.41ms。
这样一来，当电子设备显示较复杂的动态图像时，GPU401如图6所示，在生成第2帧显示数据时，虽然超过了第二个第一预设时间T1(例如，T1＝8.33ms)，但是显示驱动器30的时序控制单元301可以向显示引擎单元402发送一个TE信号的第二脉冲B。TE信号的第二脉冲B与TE信号的第三个第一脉冲A之间的时间间隔可以为上述第二预设时间T2。在此情况下，V-Sync的第三个高电平脉冲也会延时第二预设时间T2，从而能够将第2帧的延长至T1+T2。确保GPU401在T1+T2的时间内(即 经过延时处理的第2帧内)完成生成第2帧显示数据的过程。
在此基础上，由于在第2帧，GPU401已经生成好了第2帧显示数据。因此，在图6所示的第3帧，当GPU401生成第3帧显示数据的同时，可以将上述第2帧显示数据存储于主机40中的存储单元403中。接下来，在如图6所示的在第3帧，显示引擎单元402可以根据TE信号的第S个(例如第1个)第二脉冲B，通过MIPI接口将第2帧DCS数据包②发送至收发单元303，并通过收发单元303缓存于帧缓存单元304内。接下来，显示驱动器30的处理单元302可以根据第2帧DCS数据包②，控制显示屏10在如图6所示的第3帧，显示第N帧(例如第2帧)图像。
综上所述，当GPU401生成一帧(例如第2帧)显示数据的时间超过，TE信号中相邻两个第一脉冲的时间间隔，例如第一预设时间T1时，即超过显示屏的分辨率(例如第一分辨率f1＝120Hz)对应的每帧图像的时长(例如，T1＝1/f1＝1/120Hz＝8.33ms)时，可以通过TE信号再生一个第二脉冲B，将该帧的时长延时至T1+T2，从而能够使得GPU401在第2帧内能够完成第2帧显示数据的生成。进而在第3帧可以使得处理单元302根据帧缓存单元304中缓存的第2帧显示数据，控制显示屏10显示第2帧的图像。这样一来，在第3帧，显示驱动器30(例如DDIC)不会因为接收不到第2帧的图像，而从帧缓存单元304中提取第1帧的图像控制显示屏10重复显示第1帧图像。从而能够减小图像卡顿的几率。
由上述可知，只要GPU401生成一帧显示数据的时间在第一预设时间T1之内时，每帧的时长均为第一预设时间T1，即显示屏10正常显示时的分辨率为1/T1＝120Hz。当GPU401生成一帧(例如第2帧)显示数据的时间超过第一预设时间T1时，可以通过TE信号再生脉冲信号，即一个第二脉冲B，将该帧的时长延时至T1+T2，因此第2帧的分辨率会由1/T1＝120Hz降低至1/(T1+T2)。
此外，由上述可知，可以通过对发光控制信号EM信号的占空比进行调节，以达到调整显示屏10的发光亮度的目的，所以为了在分辨率发生变化的时候，保证显示屏10的显示亮度不变，当TE信号再生一个第二脉冲B时，在TE信号中增加的阶段(以下称为V-Porch阶段，时长为T2)需要包括整数倍的发光控制信号EM的周期T0。这样一来，增加的V-Porch阶段不会改变发光控制信号EM的占空比，从而使得分辨率在发生变化时显示屏10的发光亮度可以保持不变。
上述是以当GPU401生成第N帧(例如第2帧)显示数据的时间超过第一预设时间T1时，通过TE信号再生一个第二脉冲B，延长上述第N帧(例如第2帧)的时长，以使得GPU401完成第2帧显示数据的生成为例进行的说明。
在本申请的另一些实施例中，当TE信号再生一个第二脉冲B后，显示驱动器30的收发单元303，仍然未在预设的时间(例如上述预设空闲时间T IDLE之后)接收第N帧(例如第2帧)显示数据时，显示驱动器30的时序控制单元301可以继续再生上述TE信号的第二脉冲B，直至第N帧(例如第2帧)的时长延至能够使得GPU401完成第2帧显示数据的生成为止。其中，每次第N帧(例如第2帧)延时后的时长需要与电子设备01能够支持的一个分辨率相匹配。
示例的，当GPU401生成第N帧(例如第2帧)显示数据的时间超过第一预设时间T1时，显示驱动器30的时序控制单元301可以如图7所示，连续M次，每次间隔 第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送TE信号的第二脉冲B。其中，M≥S，M为正整数；M×T3＝T2。
示例的，电子设备01能够支持的分辨率有最大分辨率120Hz；最小分辨率60Hz；中间分辨率96Hz。其中，该最大分辨率可以为上述第一分别率f1＝120Hz，第一预设时间T1＝1/f＝8.33ms。
当主机40的GPU401生成第1帧显示数据的时间位于第一预设时间T1内时，由上述可知，主机40的显示引擎单元402可以在第2帧将第1帧DCS数据包①通过MIPI接口传输至显示驱动器30，且该显示驱动器30根据第1帧DCS数据包①控制显示屏10进行显示。
此外，如图7所示，在第2帧，主机40的GPU401生成第2帧显示数据的时间超过了第一预设时间T1，在此情况下，显示驱动器30的时序控制单元301可以先间隔一个第三预设时间T3，判断(T1+T3)是否与第二分辨率(例如中间分辨率96Hz)对应的周期(1/f2＝10.41ms)相同，即判断(T1+T3)是否等于10.41ms。
由上述可知，当一帧的时间延长时，该帧的刷新率也会降低。为了确保显示屏10在分辨率发生变化时，保持亮度不变，第2帧延长的时间，即第三预设时间T3可以与发光控制信号EM的周期T0(T0＝T1/4＝2.08ms)相同。在此情况下，T1+T3＝8.33ms+2.08ms＝10.41ms＝1/f2。此时，显示驱动器30的时序控制单元301发送TE信号的第二脉冲B，以将第2帧的时长延时T1+T3。显示屏10的刷新率会在第2帧，随着第2帧时长的延长由最高刷新率120Hz减小至中间分辨率96Hz。
在此基础上，如图7所示，当GPU401生成第N帧(例如第2帧)显示数据的时间超过T1+T3时，显示驱动器30的时序控制单元301可以再增加一个第三预设时间T3，判断(T1+2×T3)＝(8.33ms+2×2.08ms)＝12.5ms，与第二分辨率(此时，第二分辨率为最小分辨率60Hz)对应的周期(1/f2＝16.67ms)不同。显示驱动器30的时序控制单元301不会发送TE信号的第二脉冲而处于保持状态。
接下来，显示驱动器30的时序控制单元301需要继续增加第三预设时间T3，直至(T1+M×T3)＝(8.33ms+M×2.08ms)＝(8.33ms+4×2.08ms)＝16.67ms，与第二分辨率(此时，第二分辨率为最小分辨率60Hz)对应的周期(1/f2＝16.67ms)相同。
此时，显示驱动器30的时序控制单元301发送TE信号的第二脉冲B，以将第2帧的时长延时T1+4×T3。显示屏10的刷新率会在第2帧，随着第2帧时长的延长由最高刷新率120Hz减小至最小分辨率60Hz。
在此基础上，在显示屏10的刷新率降低至最小分辨率60Hz，第2帧的时长延时至T1+4×T3后，如图8所示，GPU401生成第N帧(例如第2帧)显示数据的时间仍然会超过T1+4×T3。此时，由于显示屏10的刷新率已经降低至最小分辨率60Hz，所以为了确保显示屏10能够显示图像，在第N+1帧(例如第3帧)，显示驱动器30的处理单元302可以从帧缓存单元304中提取第N-1帧(例如第1帧)DCS数据包①，并根据第N-1帧(例如第1帧)DCS数据包①控制显示屏10显示第N-1帧(例如第1帧)的图像。
由上述可知，当GPU401生成第N帧(例如第2帧)显示数据时需要较长的时间时，可以根据显示屏10能够支持的分辨率，显示驱动器30的时序控制单元301可以 发送S个(例如S＝2)的第二脉冲B，以多次(如图9所示为两次)对第N帧(例如第2帧)的时间进行延长，直至显示屏10的刷新率降低至最小分辨率，例如60Hz。
此时，在显示屏10的刷新率已经降低至最小分辨率后，如果GPU401生成第N帧(例如第2帧)显示数据仍然无法在第N+1帧(例如第3帧)发送至显示驱动器30，使得显示驱动器30的收发单元303无法在第N+1帧(例如第3帧)接收到第N帧(例如第2帧)DCS数据包②的情况下，该显示驱动器30的时序控制单元301会启动屏幕自刷新(panel self refresh，PSR)机制，使得显示驱动器30的处理单元302可以从帧缓存单元304中提取第N-1帧(例如第1帧)DCS数据包①，以控制显示屏10显示第N-1帧(例如第1帧)图像。
此外，理想状态下，当显示驱动器30的时序控制单元301向主机40的显示引擎单元402发送上述TE信号后，显示引擎单元402可以根据该TE信号的上述第一脉冲A或第二脉冲B将GPU401生成的数据即可发送至显示驱动器30的收发单元303。然而，受制于主机40自身反应速度的影响，主机40接收和发送数据之间会具有一定的时间差△T。
在此情况下，为了提高整个显示控制电路***02处理数据的时效性，如图10所示，时序控制单元301可以在每次提前一个上述时间变化量△T(即采用方式二)，发送TE效应信号的第一脉冲或TE信号的第二脉冲。
上述是以电子设备01能够支持的分辨率有最大分辨率120Hz；最小分辨率60Hz；中间分辨率96Hz为例，对GPU401生成第N帧(例如第2帧)显示数据的时间超过第一预设时间T1时，显示驱动器30的时序控制单元301发送的TE信号的方式进行的说明。在本申请的另一些实施例中，电子设备01能够支持的分辨率有最大分辨率96Hz；最小分辨率60Hz；其中，该最大分辨率可以为上述第一分辨率f1＝96Hz，第一预设时间T1＝1/f＝10.41ms。
在此情况下，如图11所示，当主机40的GPU401生成第1帧显示数据的时间位于第一预设时间T1时，由上述可知，主机40的显示引擎单元402可以在第2帧将第1帧DCS数据包①通过MIPI接口传输至显示驱动器30，且该显示驱动器30根据第1帧DCS数据包①控制显示屏10显示第1帧图像。
此外，如图11所示，在第2帧，主机40的GPU401生成第2帧显示数据的时间超过了第一预设时间T1，在此情况下，显示驱动器30的时序控制单元301可以先间隔一个第三预设时间T3，判断(T1+T3)是否与第二分辨率(例如中间分辨率96Hz)对应的周期(1/f2＝10.41ms)相同。
以第三预设时间T3与发光控制信号EM的周期T0(T0＝T1/5＝10.41ms/5＝2.08ms)相同为例。T1+T3＝10.41ms+2.08ms＝12.49ms，与第二分辨率(此时，第二分辨率为最小分辨率60Hz)对应的周期(1/f2＝16.67ms)不同。显示驱动器30的时序控制单元301不会发送TE信号的第二脉冲而处于保持状态。
接下来，显示驱动器30的时序控制单元301需要继续增加第三预设时间T3，直至(T1+M×T3)＝(10.41ms+M×2.08ms)＝(10.41ms+3×2.08ms)＝16.67ms，与第二分辨率(此时，第二分辨率为最小分辨率60Hz)对应的周期(1/f2＝16.67ms)相同。
此时，显示驱动器30的时序控制单元301发送TE信号的第二脉冲，以将第2帧 的时长延时T1+3×T3。显示屏10的刷新率会在第2帧，随着第2帧时长的延长由最高刷新率96Hz减小至最小分辨率60Hz。
需要说明的是，上述是以发光控制信号EM的周期T0＝2.08ms为例的情况下，对电子设备01可以支持的分辨率有120Hz、96Hz以及60Hz，或者电子设备01可以支持的分辨率有96Hz以及60Hz为例进行的说明。当然，用户还可以根据需要对发光控制信号EM的周期T0进行设置，当发光控制信号EM的周期T0的数值发生变化后，电子设备01能够支持的分辨率也不限于上述几种分辨率。
本申请实施例提供一种显示驱动器30的控制方法，该方法用于驱动显示屏10进行显示。如图12所示，该方法包括S101～S103。
S101、每隔第一预设时间T1发送一个TE信号的第一脉冲A。第一预设时间T1＝1/f1。f1为显示屏的第一刷新率。TE信号的第一脉冲A用于指示主机40根据TE信号的第一脉冲A，将生成的第N帧显示数据在第N+1帧输出。
其中，N为正整数。上述第一刷新率可以为显示屏10的最高刷新率，例如120Hz。以该第一刷新率f1＝120Hz为例，上述第一预设时间T1＝1/f1＝1/120＝8.33ms。
由上述可知，主机40中的GPU401用于生成每一帧的显示数据。显示引擎单元402用于接收时序控制单元301发送的TE信号，并根据TE信号，在第N+1帧(例如第2帧)将存储于存储单元403中的第N帧(例如第1帧)的显示数据，以显示命令报文的形式发送至显示驱动器30。
S102、当未在预设的时间接收第N帧显示数据时，发送S个TE信号的第二脉冲B，S个TE信号的第二脉冲B用于将第N帧的时长延长第二预设时间T2，并指示主机40根据TE信号的第S个第二脉冲B，将生成的第N帧显示数据在第N+1帧输出。
其中，S为正整数。(T1+T2)≤(1/f2)。f2为显示屏10的第二刷新率。第一刷新率f1大于第二刷新率f2。
示例的，当电子设备显示较复杂的动态图像，例如用户玩大型游戏时，GPU401在一帧内，例如图4所示的第2帧(即T1＝8.33ms内)无法完成第N帧显示数据，(例如第2帧显示数据)的生成。导致显示驱动器30在预设时间无法接收到上述第2帧DCS数据包②。此时，显示驱动器30的时序控制单元301可以发送S个TE信号的第二脉冲B，以将第N(例如，第2帧)帧的时长延长第二预设时间T2，从而能够使得GPU401在第2帧的时长延长至T1+T2后能够完成第2帧显示数据的生成。
这样一来，当TE信号再生一个第二脉冲B后，显示驱动器30的收发单元303，仍然未在预设的时间接收第N帧(例如第2帧)显示数据(即第2帧DCS数据包②)，显示驱动器30的时序控制单元301可以继续再生上述TE信号的第二脉冲，直至第N帧(例如第2帧)的时长延时后，能够使得GPU401完成第2帧显示数据的生成。
基于此，上述S102具体包括：当GPU401生成第N帧(例如第2帧)显示数据的时间超过第一预设时间T1时，显示驱动器30的时序控制单元301可以如图7所示，连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送TE信号的第二脉冲B。其中，M≥S，M为正整数。M×T3＝T2。这样一来，每次发送TE信号的第二脉冲B之前，可以对该第二脉冲B能够将第N帧时长延长的时间是否与电子设备01能够支持的一个分辨率对应的周期相等进行判断，从而可以使得每次第N 帧(例如第2帧)延时后的时长需要与电子设备01能够支持的一个分辨率相匹配。
由上述可知，当一帧的时间延长时，该帧的刷新率也会降低。为了确保显示屏10在分辨率发生变化时，保持亮度不变，每次第2帧延长的时间，即第三预设时间T3可以与发光控制信号EM的周期T0(T0＝T1/4＝2.08ms)相同。
此外，为了提高整个显示控制电路***02处理数据的时效性，如图10所示，时序控制单元301可以在每次提前一个时间变化量△T，发送TE效应信号的第一脉冲或TE信号的第二脉冲。其中，时间变化量△T为主机40接收和发送数据之间的时间差。
S103、在第N+1帧，接收第N帧显示数据，并根据第N帧显示数据控制显示屏10显示第N帧图像。
由上述可知，通过TE信号再生一个第二脉冲B，将第N帧(例如第2帧)的时长延时至T1+T2，从而能够使得GPU401在第N帧(例如第2帧)内能够完成显示数据的生成。进而在第N+1帧(例如第3帧)，可以使得显示驱动器30控制显示屏10显示第N帧(例如第2帧)的图像。
此外，上述方法还包括：在第N+1帧，当发送第S个TE信号的第二脉冲B后，未接收第N帧(例如第2帧)显示数据时，由上述可知，在第N帧(例如第2帧)显示屏10的分辨率已经降低至最低分辨率，例如60Hz。此时，显示驱动器30的时序控制单元301会启动PSR机制，使得显示驱动器30的处理单元302可以从帧缓存单元304中提取第N-1帧(例如第1帧)DCS数据包①，以控制显示屏10显示第N-1帧(例如第1帧)图像。
需要说明的是，当电子设备显示较复杂的动态图像时，显示的大部分时间内，在第S个TE信号的第二脉冲B之前，即显示屏10的分辨率降低至最低分辨率，例如60Hz之前，显示驱动器30的收发单元303就可以接收到第N帧(例如第2帧)显示数据，避免重复显示第N-1帧(例如第1帧)图像。因此，显示驱动器30的时序控制单元301启动PSR机制的次数不多，所以能够有效减小图像卡顿显现发生的几率。
此外，本申请实施例提供一种计算机可读介质，其存储有计算机程序。该计算机程序被处理器执行时实现如上所述的方法。本申请实施例提供一种包含指令的计算机程序产品。当所述计算机程序产品在电子设备上运行时，使得该电子设备执行如上所述的方法。
该计算机可读介质可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，
RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)，或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，通过通信总线与处理器相连接。存储器也可以和处理器集成在一起。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机执行指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用 计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示驱动器，其特征在于，用于驱动显示屏进行显示，所述显示驱动器包括：
    时序控制单元，用于每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲；所述第一预设时间T1＝1/f1；f1为所述显示屏的第一刷新率；所述裂屏效应信号的第一脉冲用于指示主机根据所述裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，N为正整数；
    收发单元，用于接收并发送所述主机发送的显示数据；
    所述时序控制单元还用于当所述收发单元，未在预设的时间接收所述第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个所述裂屏效应信号的第二脉冲用于将所述第N帧的时长延长第二预设时间T2，并指示所述主机根据所述裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出；
    其中，S为正整数；(T1+T2)≤(1/f2)；f2为所述显示屏的第二刷新率；所述第一刷新率大于所述第二刷新率；
    处理单元，与所述收发单元耦接，用于在第N+1帧接收所述第N帧显示数据，并根据所述第N帧显示数据控制所述显示屏显示第N帧图像。
  2. 根据权利要求1所述的显示驱动器，其特征在于，
    所述时序控制单元具体用于连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送所述裂屏效应信号的第二脉冲；当发送第S个裂屏效应信号的第二脉冲时，所述第N帧结束，所述第N帧的时长(T1+T2)＝(1/f2)；
    其中，M≥S，M为正整数；M×T3＝T2。
  3. 根据权利要求2所述的显示驱动器，其特征在于，所述显示屏包括发光二极管；所述第三预设时间T3与发光控制信号的周期相同；所述发光控制信号用于控制所述发光二极管的有效发光时长。
  4. 根据权利要求2所述的显示驱动器，其特征在于，所述显示驱动器还包括与所述收发单元耦接的帧缓存单元，所述帧缓存单元用于对所述收发单元接收到的所述显示数据进行缓存；
    所述处理单元具体用于在第N+1帧，当所述时序控制单元发送第S个裂屏效应信号的第二脉冲后，所述收发单元未接收所述第N帧显示数据时，从所述帧缓存单元中提取第N-1帧显示数据，并根据所述第N-1帧显示数据控制所述显示屏显示第N-1帧图像。
  5. 根据权利要求2所述的显示驱动器，其特征在于，
    所述时序控制单元具体用于每次提前一个时间变化量△T，发送所述裂屏效应信号的第一脉冲或所述裂屏效应信号的第二脉冲；其中，所述时间变化量△T为所述主机接收和发送数据的时间差。
  6. 一种显示驱动器的控制方法，其特征在于，用于驱动显示屏进行显示，所述方法包括：
    每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲；所述第一预设时间T1＝1/f1；f1为所述显示屏的第一刷新率；所述裂屏效应信号的第一脉冲用于指示主机 根据所述裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，N为正整数；
    当未在预设的时间接收所述第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个所述裂屏效应信号的第二脉冲用于将所述第N帧的时长延长第二预设时间T2，并指示所述主机根据所述裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，S为正整数；(T1+T2)≤(1/f2)；f2为所述显示屏的第二刷新率；所述第一刷新率大于所述第二刷新率；
    在第N+1帧，接收所述第N帧显示数据，并根据所述第N帧显示数据控制所述显示屏显示第N帧图像。
  7. 根据权利要求6所述的显示驱动器的控制方法，其特征在于，所述在预设的时间之后，未接收所述第N帧显示数据时，发送S个裂屏效应信号的第二脉冲包括：
    连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送所述裂屏效应信号的第二脉冲；当发送第S个裂屏效应信号的第二脉冲时，所述第N帧结束，所述第N帧的时长(T1+T2)＝(1/f2)；
    其中，M≥S，M为正整数；M×T3＝T2。
  8. 根据权利要求7所述的显示驱动器的控制方法，其特征在于，所述显示屏包括发光二极管；所述第三预设时间T3与发光控制信号的周期相同；所述发光控制信号用于控制所述发光二极管的有效发光时长。
  9. 根据权利要求7所述的显示驱动器的控制方法，其特征在于，所述方法还包括：
    在第N+1帧，当发送第S个裂屏效应信号的第二脉冲后，未接收所述第N帧显示数据时，提取第N-1帧显示数据，并根据所述第N-1帧显示数据控制所述显示屏显示第N-1帧图像。
  10. 根据权利要求7所述的显示驱动器的控制方法，其特征在于，所述方法还包括：
    每次提前一个时间变化量△T，发送所述裂屏效应信号的第一脉冲或所述裂屏效应信号的第二脉冲；其中，所述时间变化量△T为所述主机接收和发送数据的时间差。
  11. 一种显示控制电路***，其特征在于，包括：显示驱动器以及与所述显示驱动器耦接的主机；
    所述显示驱动器包括时序控制单元、收发单元以及处理单元；所述时序控制单元用于每隔第一预设时间T1发送一个裂屏效应信号的第一脉冲；所述第一预设时间T1＝1/f1；f1为显示屏的第一刷新率；所述裂屏效应信号的第一脉冲用于指示主机根据所述裂屏效应信号的第一脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，N为正整数；所述收发单元用于接收所述主机发送的显示数据；所述时序控制单元还用于当所述收发单元未在预设的时间接收所述第N帧显示数据时，发送S个裂屏效应信号的第二脉冲，S个所述裂屏效应信号的第二脉冲用于将所述第N帧的时长延长第二预设时间T2，并指示所述主机根据所述裂屏效应信号的第S个第二脉冲，将生成的第N帧显示数据在第N+1帧输出；其中，S为正整数；(T1+T2)≤(1/f2)；f2为所述显示屏的第二刷新率；所述第一刷新率大于所述第二刷新率；所述处理单元与所述收发单元耦接，用于在第N+1帧，接收所述第N帧显示数据，根据所述第N帧显示 数据控制所述显示屏显示第N帧图像；
    所述主机用于根据所述裂屏效应信号的所述第一脉冲或所述第二脉冲，将生成的第N帧显示数据在第N+1帧输出。
  12. 根据权利要求11所述的显示控制电路***，其特征在于，所述时序控制单元具体用于连续M次，每次间隔第三预设时间T3，判断出(T1+M×T3)＝(1/f2)时，发送所述裂屏效应信号的第二脉冲；当发送第S个裂屏效应信号的第二脉冲时，所述第N帧结束，所述第N帧的时长(T1+T2)＝(1/f2)；
    其中，M≥S，M为正整数；M×T3＝T2。
  13. 根据权利要求12所述的显示控制电路***，其特征在于，所述显示屏包括发光二极管；所述第三预设时间T3与发光控制信号的周期相同；所述发光控制信号用于控制所述发光二极管的有效发光时长。
  14. 根据权利要求12所述的显示控制电路***，其特征在于，所述显示驱动器还包括与所述收发单元耦接的帧缓存单元，所述帧缓存单元用于对所述收发单元接收到的所述显示数据进行缓存；
    所述处理单元具体用于在第N+1帧，当所述时序控制单元发送第S个裂屏效应信号的第二脉冲后，所述收发单元未接收所述第N帧显示数据时，从所述帧缓存单元中提取第N-1帧显示数据，并根据所述第N-1帧显示数据控制所述显示屏显示第N-1帧图像。
  15. 根据权利要求12所述的显示控制电路***，其特征在于，
    所述时序控制单元具体用于每次提前一个时间变化量△T，发送所述裂屏效应信号的第一脉冲和所述裂屏效应信号的第二脉冲；其中，所述时间变化量△T为所述主机接收和发送数据的时间差。
  16. 根据权利要求11所述的显示控制电路***，其特征在于，所述主机包括：
    图像处理单元，用于生成第N帧显示数据，并在生成第N+1帧显示数据时，发送所述第N帧显示数据；
    存储单元，与所述图像处理单元耦接，用于接收所述图像处理单元生成的第N帧显示数据，并进行存储；
    显示引擎单元，与所述显示驱动器和所述存储单元耦接，用于根据所述裂屏效应信号的第一脉冲或第二脉冲，在第N+1帧将存储于所述存储单元中的第N帧显示数据输出至所述显示驱动器。
  17. 一种电子设备，其特征在于，包括显示屏以及如权利要求11-16任一项所述的显示控制电路***；所述显示控制电路***中的显示驱动器与所述显示屏耦接，且用于驱动所述显示屏进行显示。
  18. 一种计算机可读存储介质，其存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求6-10任一项所述的方法。
  19. 一种包含指令的计算机程序产品，其特征在于，当所述计算机程序产品在电子设备上运行时，使得所述电子设备执行如权利要求6-10中任一项所述的方法。
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