WO2021129011A1 - 像素电路的驱动方法、显示面板和显示装置 - Google Patents

像素电路的驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2021129011A1
WO2021129011A1 PCT/CN2020/117990 CN2020117990W WO2021129011A1 WO 2021129011 A1 WO2021129011 A1 WO 2021129011A1 CN 2020117990 W CN2020117990 W CN 2020117990W WO 2021129011 A1 WO2021129011 A1 WO 2021129011A1
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Prior art keywords
transistor
initialization
gate
driving
pixel circuit
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PCT/CN2020/117990
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English (en)
French (fr)
Inventor
赵东方
沈阳
郭子栋
张豪峰
杜哲
李俊峰
葛泳
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云谷（固安）科技有限公司
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Publication of WO2021129011A1 publication Critical patent/WO2021129011A1/zh
Priority to US17/569,309 priority Critical patent/US11688319B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the embodiments of the present application relate to the field of display technology, such as a driving method of a pixel circuit, a pixel circuit, a display panel, and a display device.
  • a display panel usually includes a plurality of pixel circuits and light-emitting devices, and the light-emitting devices are driven to emit light through the pixel circuits to perform display.
  • the display panel in the related art has short-term image retention, which makes the display effect poor.
  • the present application provides a driving method of a pixel circuit, a display panel, and a display device, so as to improve the short-term image sticking phenomenon and improve the display effect.
  • an embodiment of the present application provides a method for driving a pixel circuit.
  • the pixel circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first initialization transistor, a second initialization transistor, and a light emitting device.
  • the compensation transistor is connected to the driver. Between the gate of the transistor and the second electrode of the driving transistor, the second electrode of the driving transistor is connected to the initialization power supply terminal through the first initialization transistor; the data writing transistor is connected between the data voltage input terminal and the first electrode of the driving transistor ; The second initialization transistor is connected between the first signal terminal and the first electrode of the driving transistor; the light emitting device is connected between the second electrode of the driving transistor and the second power supply voltage input terminal;
  • Driving methods include:
  • a turn-on control signal is provided to the gate of the data writing transistor.
  • an embodiment of the present application also provides a display panel, including a pixel circuit
  • the pixel circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first initialization transistor and a second initialization transistor
  • the compensation transistor is connected to the driving transistor
  • the second electrode of the drive transistor is connected to the initialization power supply terminal through the first initialization transistor
  • the data writing transistor is connected between the data voltage input terminal and the first electrode of the drive transistor
  • the second initialization transistor is connected between the first signal terminal and the first electrode of the driving transistor
  • the pixel circuit also includes a first scan line, a second scan line, a third scan line, a fourth scan line, a data line, and a gate driver And data drive;
  • the first scan line is electrically connected to the gate of the first initialization transistor of the pixel circuit
  • the second scan line is electrically connected to the gate of the compensation transistor
  • the third scan line is electrically connected to the gate of the second initialization transistor
  • the fourth The scan line is electrically connected to the gate of the data writing transistor
  • the data line is electrically connected to the data voltage input terminal
  • the first scan line, the second scan line, the third scan line, and the fourth scan line are electrically connected to the output terminal of the gate driver in a one-to-one correspondence, and the data line is electrically connected to the output terminal of the data driver;
  • the gate driver is configured to provide the first pulse signal to the first scan line, the second scan line and the third scan line in the initialization phase, and is configured to provide the first pulse signal to the fourth scan line in the data writing phase;
  • the data driver provides a data voltage to the data line during the data writing phase.
  • an embodiment of the present application also provides a display device, including the display panel provided in the second aspect.
  • the embodiments of the present application provide a driving method for a pixel circuit, a display panel, and a display device.
  • a turn-on control signal is provided to the gate of the first initialization transistor and the gate of the compensation transistor, and to the second initialization transistor.
  • the gate provides a turn-on control signal to provide a fixed voltage to the first signal terminal; so that in the initialization phase, the gate voltage of the driving transistor is the initialization voltage input from the initialization power terminal, and the voltage of the first electrode of the driving transistor is the first signal terminal
  • the fixed input voltage can completely reset the driving transistor.
  • the driving transistor When the gray scale is switched in different frames, no matter whether the gray scale of the previous frame is the same or not, the driving transistor will be restored to the same initial state during the initialization phase of this frame. , Which in turn makes the active layer, gate insulating layer, and the active layer and gate insulating layer inside the driving transistor in the process of gray-scale switching the capture and release of carriers at the interface of the active layer and the gate insulating layer tend to be consistent, so that different gray-scale When switching to the same gray scale, the driving transistors can generate the same driving current, and the light-emitting brightness of the light-emitting device is basically the same, thereby reducing the afterimage phenomenon.
  • FIG. 1 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of another method for driving a pixel circuit according to an embodiment of the present application
  • FIG. 4 is a driving timing diagram of the pixel circuit shown in FIG. 2 provided by an embodiment of the present application;
  • FIG. 5 is another driving timing diagram of the pixel circuit shown in FIG. 2 provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6 provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • a display panel usually includes a plurality of pixel circuits, and the pixel circuit includes a driving transistor that drives the light-emitting device to emit light.
  • the driving transistor controls the light-emitting brightness of the light-emitting device by controlling the driving current flowing through the light-emitting device.
  • the driving current generated by the driving transistor is related to the gate-source voltage difference of the driving transistor. In different display gray scales, the gate-source voltage difference of the driving transistor is different.
  • the difference in the gate-source voltage difference of the driving transistor causes the working state of the driving transistor to be different, which in turn causes the trapping of carriers at the active layer, the gate insulating layer, and the interface between the active layer and the gate insulating layer inside the driving transistor.
  • There is a difference in the degree of release and the degree of release which results in different driving currents of the driving transistors when converting from different gray scales to the same gray scale, which will eventually lead to differences in luminous brightness and form afterimages.
  • the gate of the driving transistor is initialized, the source of the driving transistor is usually in a floating state, so that the change of the gate potential will also cause the change of the source potential, making the reset of the driving transistor insufficient and short-term image retention. still exists.
  • An embodiment of the present application provides a method for driving a pixel circuit, wherein the pixel circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first initialization transistor, a second initialization transistor, and a light emitting device.
  • the compensation transistor is connected to the gate of the driving transistor.
  • the second electrode of the driving transistor is connected to the initialization power supply terminal through the first initialization transistor;
  • the data writing transistor is connected between the data voltage input terminal and the first electrode of the driving transistor;
  • the initialization transistor is connected between the first signal terminal and the first electrode of the driving transistor;
  • the light emitting device is connected between the second electrode of the driving transistor and the second power supply voltage input terminal.
  • FIG. 1 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present application. Referring to FIG. 1, the driving method includes steps 110 to 120.
  • step 110 in the initialization phase, a turn-on control signal is provided to the gate of the first initialization transistor and the gate of the compensation transistor, and a turn-on control signal is provided to the gate of the second initialization transistor, and a fixed signal is provided to the first signal terminal. Voltage.
  • step 120 in the data writing phase, a turn-on control signal is provided to the gate of the data writing transistor.
  • the initialization phase is performed before the data writing phase.
  • a conduction control signal is provided to the gate of the first initialization transistor and the gate of the compensation transistor, so that the first initialization transistor and the compensation transistor are turned on, and the initialization voltage input from the initialization power supply terminal passes through the conduction
  • the first initialization transistor and the compensation transistor are transmitted to the gate of the driving transistor, and then the gate of the driving transistor is initialized.
  • a turn-on signal is provided to the gate of the second initialization transistor, so that the fixed voltage provided by the first signal terminal is transmitted to the first pole of the driving transistor through the turned-on second initialization transistor, wherein the driving transistor
  • the first electrode of the driving transistor can be the source or drain of the driving transistor.
  • the driving transistor when the driving transistor is a P-type transistor, the first electrode of the driving transistor is the source of the driving transistor; when the driving transistor is an N-type transistor In the case, the first pole of the driving transistor is the drain of the driving transistor. That is, in the initialization phase, the gate voltage of the driving transistor is the initialization voltage input from the initialization power terminal, and the voltage of the first electrode of the driving transistor is the fixed voltage input from the first signal terminal. The voltage difference of the first pole of the transistor is fixed, and the driving transistor can be completely reset.
  • the driving transistor in each pixel circuit can be restored to the same state during the initialization phase .
  • the driving transistor will return to the same initial state, so that the internal driving transistor will be restored during the gray-scale switching process.
  • the levels of capture and release of carriers at the active layer, the gate insulating layer, and the interface between the active layer and the gate insulating layer tend to be the same, so that when switching from different gray levels to the same gray level, the driving transistors can produce the same
  • the driving current of the light-emitting device is basically the same, thereby reducing the afterimage phenomenon.
  • a turn-on control signal is provided to the gate of the first initialization transistor and the gate of the compensation transistor, and a turn-on control is provided to the gate of the second initialization transistor.
  • Signal to provide a fixed voltage to the first signal terminal so that in the initialization phase, the gate voltage of the driving transistor is the initialization voltage input from the initialization power terminal, and the voltage of the first electrode of the driving transistor is the fixed voltage input from the first signal terminal.
  • the driving transistor when switching the gray levels in different frames, no matter whether the gray level displayed in the previous frame is the same or not, the driving transistor will be restored to the same initial state during the initialization phase of this frame, thereby making the gray level switching During the process, the active layer, gate insulating layer, and the level of carrier capture and release at the interface between the active layer and the gate insulating layer of the driving transistor tend to be the same, so that when switching from different gray levels to the same gray level , The driving transistor can generate the same driving current, and the light-emitting brightness of the light-emitting device is basically the same, thereby reducing the afterimage phenomenon.
  • the pixel circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first initialization transistor T4, and a second initialization transistor T5 and the light-emitting device D1, the compensation transistor T3 is connected between the gate of the driving transistor T1 and the second electrode of the driving transistor T1, and the second electrode of the driving transistor T1 is connected to the initialization power terminal Vref through the first initialization transistor T4;
  • the input transistor T2 is connected between the data voltage input terminal Vdata and the first electrode of the driving transistor T1; the second initialization transistor T5 is connected between the first signal terminal and the first electrode of the driving transistor T1.
  • the pixel circuit also includes a first light-emitting control transistor T6.
  • the first electrode of the driving transistor T1 is electrically connected to the first power supply voltage input terminal Vdd through the second initialization transistor T5, and the second electrode of the driving transistor T1 is connected to the first light-emitting control transistor T6.
  • the first pole of the light emitting device D1 is electrically connected, and the second pole of the light emitting device D1 is electrically connected to the second power supply voltage input terminal Vss; wherein the first power supply voltage input terminal Vdd is used as the first signal terminal.
  • the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first initialization transistor T4, the second initialization transistor T5, and the first light emission control transistor T6 may be P-type transistors or N-type transistors.
  • the conduction control signal is a low-level signal; when these transistors are N-type transistors, the conduction control signal is a high-level signal.
  • the gate of the compensation transistor T3 is electrically connected to the first scan signal input terminal Scan1 of the pixel circuit
  • the gate of the first initialization transistor T4 is electrically connected to the second scan signal input terminal Scan2 of the pixel circuit
  • the data writing transistor The gate of T2 is electrically connected to the third scan signal input terminal Scan3
  • the gate of the second initialization transistor T5 is electrically connected to the first light emission control signal input terminal EM1
  • the gate of the first light emission control transistor T6 is electrically connected to the second light emission control signal.
  • the input terminal EM2 is electrically connected.
  • these transistors are all P-type transistors, that is, the conduction control signals are all low-level, and the signal input from the first power supply voltage input terminal Vdd is a high-level signal, and the second power supply voltage input terminal Vss is input
  • the signal is a low-level signal as an example for description.
  • FIG. 3 is a flowchart of another method for driving a pixel circuit according to an embodiment of the present application.
  • FIG. 4 is a driving timing diagram of the pixel circuit shown in FIG. 2 according to an embodiment of the present application.
  • the drive timing can be used for Drive the pixel circuit shown in Figure 2.
  • the initialization phase t1 in the above embodiment includes a first initialization phase t11 and a second initialization phase t12.
  • the driving method of the pixel circuit includes steps 111 to 130.
  • step 111 in the first initialization phase t11, a turn-on control signal is provided to the gate of the second initialization transistor T5.
  • a low-level signal is provided to the gate of the second initialization transistor T5, that is, a low-level signal is provided to the first light-emitting control signal input terminal EM1, then the second initialization transistor T5 is turned on, and the first power supply voltage
  • the high-level signal input from the input terminal Vdd is transmitted to the first pole of the driving transistor T1 through the turned-on second initialization transistor T5, so as to reset the first pole of the driving transistor T1.
  • step 112 in the second initialization phase, a turn-on control signal is provided to the gate of the first initialization transistor T4 and the gate of the compensation transistor T3.
  • a low-level signal is provided to the gate of the first initialization transistor T4, that is, a low-level signal is provided to the second scan signal input terminal Scan2, and the first initialization transistor T4 is turned on;
  • a low-level signal is provided to the first scan signal input terminal Scan1, and the compensation transistor T3 is turned on. Therefore, the initialization voltage provided by the initialization power supply terminal Vref passes through the turned-on first initialization transistor T4 and the compensation transistor T3. It is transmitted to the gate of the driving transistor T1 to reset the gate of the driving transistor T1.
  • the first pole of the driving transistor T1 is initialized to the potential input by the first power supply voltage input terminal Vdd, where the potential input by the first power supply voltage input terminal Vdd is fixed
  • the gate of the driving transistor T1 is initialized to the initialization voltage input from the initialization power terminal Vref, that is, after the first initialization phase t11 and the second initialization phase t12, the voltage difference between the gate of the driving transistor T1 and the first electrode is fixed, which can be realized
  • the complete reset of the driving transistor T1 is beneficial to improve the afterimage phenomenon.
  • the second initialization phase t12 is performed after the first initialization phase t11.
  • step 120 in the data writing phase t13, a turn-on control signal is provided to the gate of the data writing transistor T2.
  • the data writing phase t13 is performed after the second initialization phase t12.
  • a low-level signal is provided to the gate of the data writing transistor T2, that is, a low-level signal is provided to the third scan signal input terminal Scan3.
  • the data writing transistor T2 is turned on;
  • the gate of the transistor T3 provides a low-level signal, that is, provides a low-level signal to the first scan signal input terminal Scan1, the compensation transistor T3 is turned on, and the data voltage input from the data voltage input terminal Vdata passes through the turned-on data writing transistor T2
  • the driving transistor T1 and the compensation transistor T3 are written to the gate of the driving transistor T1, wherein the light-emitting brightness of the light-emitting device D1 is related to the magnitude of the data voltage written in the gate of the driving transistor T1.
  • the driving method of the pixel circuit further includes:
  • step 130 in the light-emitting phase t14, a turn-on control signal is provided to the gates of the second initialization transistor T5 and the first light-emitting control transistor T6.
  • a low-level signal is provided to the gates of the second initialization transistor T5 and the first light-emission control transistor T6, so that the second initialization transistor T5 and the first light-emission control transistor T6 are turned on, and the driving transistor T1 drives the light emitting device D1 to emit light. That is, in the pixel circuit structure and driving method provided in this embodiment, the second initialization transistor T5 also plays a role of light emission control, or the light emission control transistor is used as the second initialization transistor T5, which is beneficial to reduce the number of transistors in the pixel circuit. Increase pixel density.
  • the gate of the driving transistor T1 is reset by the first initialization transistor T4 and the compensation transistor T3.
  • the first initialization transistor T4 is electrically connected to the gate of the driving transistor T1 through the compensation transistor T3.
  • Circuit structure which can reduce the leakage path, is beneficial to maintain the gate potential of the driving transistor T1, and thereby is beneficial to improve the display effect.
  • FIG. 5 is another driving timing diagram of the pixel circuit shown in FIG. 2 provided by an embodiment of the present application.
  • the driving timing can be used to drive the pixel circuit shown in FIG. 2. Referring to FIG. 5, in one frame, the first initialization stage t21 Simultaneously with the second initialization phase t22.
  • the first initialization phase t21, the second initialization phase t22, and the initialization phase t2 in FIG. 5 are the same phase.
  • the first initialization phase t21 and the second initialization phase t22 are carried out at the same time, which is beneficial to shorten the driving cycle of each pixel circuit (the driving cycle includes the initialization phase t2, the data writing phase t23, and the light-emitting phase t24), thereby helping to drive high pixel density The pixel circuit in the display panel.
  • the data writing phase t23 and the light emitting phase t24 of the driving sequence shown in FIG. 5 are the same as the data writing phase t13 and the light emitting phase t14 of the pixel circuit in the driving sequence shown in FIG.
  • the driving method of the pixel circuit further includes:
  • a turn-off control signal is provided to the gate of the first light-emitting control transistor T6.
  • the signal provided to the gate of the first light emission control transistor T6 is the signal input to the second light emission control signal input terminal EM2.
  • a high-level signal is provided to the gate of the first light-emitting control transistor T6, so that in the first initialization stage, the first light-emitting control transistor T6 is turned off.
  • the second initialization transistor T5 since the second initialization transistor T5 is turned on during the first initialization phase, the high-level signal input from the first power supply voltage input terminal Vdd is transmitted to the first pole of the driving transistor T1; to the compensation transistor T3 The signal input to the gate is a high-level signal, so the compensation transistor T3 is turned off. Due to the storage effect of the storage capacitor, the gate of the driving transistor T1 maintains the data voltage of the previous frame.
  • the data voltage of the gate of the driving transistor T1 is the data voltage corresponding to any gray scale
  • the first electrode voltage of the driving transistor T1 is the voltage input from the first power supply voltage input terminal Vdd, so the gate of the driving transistor T1 and the driving transistor T1 are first
  • the voltage difference between the poles is usually smaller than its threshold voltage, which in turn causes the driving transistor T1 to turn on.
  • the driving method provided in this embodiment by providing a turn-off control signal to the gate of the first light-emitting control transistor T6 in the first initialization stage, the first light-emitting control transistor T6 is turned off in the first initialization stage, thereby avoiding the A display failure caused by the light emission of the light-emitting device D1 during the initialization phase.
  • the second initialization transistor T5 is turned on, and the high-level signal input from the first power supply voltage input terminal Vdd is transmitted to the first pole of the driving transistor T1; the first initialization transistor T4 and the compensation transistor T3 are turned on, and the initialization voltage input from the initialization power terminal Vref is transmitted to the gate of the driving transistor T1. Because the initialization voltage is usually low, the voltage difference between the gate of the driving transistor T1 and the first electrode of the driving transistor T1 is usually less than Its threshold voltage, in turn, turns on the driving transistor T1.
  • the first light-emitting control transistor T6 is turned off in the first initialization stage, thereby avoiding the A display failure caused by the light emission of the light-emitting device D1 during the initialization phase.
  • the pixel circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first initialization transistor T4, and a second initialization transistor.
  • the transistor T5 and the light emitting device D1 is connected between the gate of the driving transistor T1 and the second electrode of the driving transistor T1, and the second electrode of the driving transistor T1 is connected to the initialization power terminal Vref through the first initialization transistor T4;
  • the writing transistor T2 is connected between the data voltage input terminal Vdata and the first electrode of the driving transistor T1;
  • the second initialization transistor T5 is connected between the first signal terminal and the first electrode of the driving transistor T1; the second electrode of the light emitting device D1
  • the pole is connected to the second power supply voltage input terminal Vss.
  • the pixel circuit further includes a first light emission control transistor T6 and a second light emission control transistor T7.
  • the first electrode of the driving transistor T1 is electrically connected to the first power supply voltage input terminal Vdd through the first light emission control transistor T6, and the second electrode of the driving transistor T1
  • the second light emitting control transistor T7 is electrically connected to the first electrode of the light emitting device D1, and the second electrode of the light emitting device D1 is electrically connected to the second power supply voltage input terminal Vss; wherein, the first signal terminal and the second light emitting control transistor T7 The grid is electrically connected.
  • the first signal terminal is electrically connected to the gate of the second light-emitting control transistor T7, that is, the signal input from the first signal terminal is used as a control signal to control the turn-on or turn-off of the second light-emitting control transistor T7, or to control the second light-emitting control transistor T7.
  • the second light-emitting control signal input terminal EM2 through which the two light-emitting control transistors T7 are turned on or off serves as the first signal terminal.
  • the gate of the compensation transistor T3 is electrically connected to the first scan signal input terminal Scan1 of the pixel circuit
  • the gate of the first initialization transistor T4 is electrically connected to the second scan signal input terminal Scan2 of the pixel circuit
  • the data writing transistor The gate of T2 is electrically connected to the third scanning signal input terminal Scan3
  • the gate of the first emission control transistor T6 is electrically connected to the first emission control signal input terminal EM1
  • the gate of the second emission control transistor T7 is electrically connected to the second emission control
  • the signal input terminal EM2 is electrically connected
  • the gate of the second initialization transistor T5 is electrically connected to the second scan signal input terminal Scan2.
  • the control method of the pixel circuit also includes:
  • a turn-off control signal is provided to the gate of the second light-emitting control transistor T7. Provides another way to completely reset the drive transistor.
  • FIG. 7 is a driving timing diagram of the pixel circuit shown in FIG. 6 provided by an embodiment of the present application.
  • a low-level signal is provided to the gate of the second initialization transistor T5, namely A low-level signal is input to the second scan signal input terminal Scan2, the second initialization transistor T5 is turned on, and the high-level signal provided to the first signal terminal (the second light-emitting control signal input terminal EM2) passes through the turned-on second initialization
  • the transistor T5 is transmitted to the first pole of the driving transistor T1 to realize the initialization of the first pole of the driving transistor T1.
  • the second light-emitting control transistor T7 is turned off according to the high-level signal input from its gate.
  • a low-level signal is provided to the gate of the first initialization transistor T4, that is, a low-level signal is input to the second scan signal input terminal Scan2, and the first initialization transistor T4 is turned on;
  • the first scan signal input terminal Scan1 provides a low-level signal, the first initialization transistor T4 and the compensation transistor T3 are turned on to reset the gate of the driving transistor T1, and then the initialization phase t31 is implemented
  • the complete reset of the driving transistor T1 is beneficial to improve the residual image.
  • a low-level signal is provided to the gate of the data writing transistor T2, that is, a low-level signal is provided to the third scan signal input terminal Scan3, and the data writing transistor T2 is turned on; and the gate of the compensation transistor T3 is turned on.
  • a low-level signal that is, provides a low-level signal to the first scan signal input terminal Scan1
  • the compensation transistor T3 is turned on, so that the data voltage input from the data voltage input terminal Vdata is driven by the turned-on data writing transistor T2
  • the transistor T1 and the compensation transistor T3 are written to the gate of the driving transistor T1 to realize the writing of the data voltage and the compensation of the gate voltage of the driving transistor T1.
  • a low-level signal is provided to the gate of the first light-emitting control transistor T6, that is, a low-level signal is provided to the first light-emitting control signal input terminal EM1, and the first light-emitting control transistor T6 is turned on;
  • the gate of the control transistor T7 provides a low-level signal, that is, a low-level signal is provided to the second light-emission control signal input terminal EM2, the second light-emission control transistor T7 is turned on, and the driving transistor T1 drives the light-emitting device D1 to emit light.
  • the driving method of the pixel circuit further includes:
  • a turn-off control signal is provided to the gate of the first light-emitting control transistor T6.
  • a turn-off control signal is provided to the gate of the first light-emitting control transistor T6, so that the signals provided to the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are the same at each stage, and then
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T7 can be connected to the same control signal line of the display panel, which is beneficial to reduce the number of wiring in the display panel.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a third initialization transistor T8, and the third initialization transistor T8 is connected to the initialization power terminal Vref and the light emitting device D1.
  • the driving method also includes:
  • a turn-on control signal is provided to the gate of the third initialization transistor T8.
  • the gate of the third initialization transistor T8 is electrically connected to the second scan signal input terminal Scan2.
  • the driving timing shown in FIGS. 4 and 5 is also applicable to the pixel circuit shown in FIG. 8.
  • a low-level signal is provided to the gate of the third initialization transistor T8, that is, a low-level signal is provided to the second scan signal input terminal Scan2, and the third initialization transistor T8 is turned on, thereby enabling the The initialization of the first pole of the light emitting device D1 avoids the influence of the residual charge on the first pole of the light emitting device D1 on the display effect, and improves the display effect.
  • the pixel circuit provided by any of the foregoing embodiments of the present application further includes a storage capacitor Cst, which further stores the gate potential of the driving transistor, so that the potential of the driving transistor can be well maintained during the light-emitting phase.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 10 includes the pixel circuit 100 provided by any embodiment of the present application.
  • the pixel circuit 100 includes a driving transistor, a data writing transistor, a compensation transistor, a first initialization transistor, and a second initialization transistor.
  • the compensation transistor is connected between the gate of the driving transistor and the second electrode of the driving transistor.
  • the first initialization transistor is connected to the initialization power supply terminal; the data writing transistor is connected between the data voltage input terminal and the first electrode of the driving transistor; the second initialization transistor is connected between the first signal terminal and the first electrode of the driving transistor
  • the pixel circuit 100 also includes a first scan line S1, a second scan line S2, a third scan line S3, a fourth scan line S4, a data line, a gate driver 200, and a data driver 300.
  • the first scan line S1 is electrically connected to the gate of the first initialization transistor of the pixel circuit
  • the second scan line S2 is electrically connected to the gate of the compensation transistor
  • the third scan line S3 is electrically connected to the gate of the second initialization transistor.
  • the fourth scan line S4 is electrically connected to the gate of the data writing transistor
  • the data lines (D1, D2, D3, D4...) are electrically connected to the data voltage input terminal.
  • the first scan line S1, the second scan line S2, the third scan line S3, and the third scan line S4 are electrically connected to the output terminal of the gate driver 200 in a one-to-one correspondence, and the data line is electrically connected to the output terminal of the data driver 300.
  • the gate driver 200 is configured to provide the first pulse signal to the first scan line S1 and the second scan line S2 in the initialization phase, and to provide the first pulse signal to the third scan line S3, and to provide the first pulse signal to the third scan line S3 in the data writing phase.
  • the fourth scan line S4 provides the first pulse signal.
  • the data driver 300 is configured to provide a data voltage to the data line during the data writing phase.
  • the first pulse signal may be a control signal for turning on a transistor corresponding to the first pulse signal in the pixel circuit. For example, when the transistor type corresponding to the first pulse signal in the pixel circuit is P-type, the first pulse signal is low. Level pulse signal.
  • the gate driver 200 may include a scan driver that outputs a scan pulse signal and a light emission control pulse driver that outputs a light emission control pulse.
  • the display panel includes the pixel circuit shown in FIG. 2 and FIG. 8, and the third scan line S3 connected to the gate of the second initialization transistor may be electrically connected to the light emission control pulse driver.
  • the display panel includes the pixel circuit shown in FIG.
  • the scan line and the third scan line may be scan lines that provide the same scan pulse signal, or the first scan line and the third scan line may be combined into the same scan line to reduce the number of wiring.
  • the gate driver provides the first pulse signal to the first scan line and the second scan line, and provides the first pulse signal to the third scan line in the initialization stage, and
  • the data writing stage provides the first pulse signal to the fourth scan line;
  • the data driver provides the data voltage to the data line during the data writing stage, which can completely reset the driving transistor.
  • the driving transistors will all return to the same initial state, so that the active layer, gate insulating layer, and active layer inside the driving transistor during the gray scale switching process
  • the degree of capture and release of carriers at the interface of the gate insulating layer tends to be the same, so that when switching from different gray scales to the same gray scale, the driving transistor can generate the same driving current, and the light-emitting brightness of the light-emitting device is basically the same. Reduce the afterimage phenomenon.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 1 provided by the embodiment of the present application includes any of the foregoing embodiments of the present application.
  • the display device may be a mobile phone as shown in FIG. 10, or may be a computer, a television, a smart wearable display device, etc., which is not limited in the embodiment of the present application.

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Abstract

一种像素电路的驱动方法、显示面板和显示装置，像素电路包括驱动晶体管、数据写入晶体管、补偿晶体管、第一初始化晶体管、第二初始化晶体管和发光器件，补偿晶体管连接于驱动晶体管的栅极和驱动晶体管的第二极之间，驱动晶体管的第二极通过第一初始化晶体管连接至初始化电源端；第二初始化晶体管连接于第一信号端和驱动晶体管的第一极之间；像素电路的驱动方法包括初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号，向第二初始化晶体管的栅极提供导通控制信号，向第一信号端提供固定电压（步骤110）；数据写入阶段，向数据写入晶体管的栅极提供导通控制信号（步骤120）。

Description

像素电路的驱动方法、显示面板和显示装置
本申请要求在2019年12月26日提交中国专利局、申请号为201911367990.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如像素电路的驱动方法及像素电路、显示面板和显示装置。
背景技术
随着显示技术的发展，人们对显示效果的要求也越来越高。
显示面板中，通常包括多个像素电路和发光器件，通过像素电路驱动发光器件发光来进行显示。
然而相关技术中的显示面板中存在短期残影的情况，使得显示效果较差。
发明内容
本申请提供一种像素电路的驱动方法、显示面板和显示装置，以改善短期残影现象，提高显示效果。
第一方面，本申请实施例提供了一种像素电路的驱动方法，像素电路包括驱动晶体管、数据写入晶体管、补偿晶体管、第一初始化晶体管、第二初始化晶体管和发光器件，补偿晶体管连接于驱动晶体管的栅极和驱动晶体管的第二极之间，驱动晶体管的第二极通过第一初始化晶体管连接至初始化电源端；数据写入晶体管连接于数据电压输入端与驱动晶体管的第一极之间；第二初始化晶体管连接于第一信号端和驱动晶体管的第一极之间；发光器件连接于驱动晶体管的第二极与第二电源电压输入端之间；
驱动方法包括：
初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控 制信号，以及向第二初始化晶体管的栅极提供导通控制信号，向第一信号端提供固定电压；
数据写入阶段，向数据写入晶体管的栅极提供导通控制信号。
第二方面，本申请实施例还提供了一种显示面板，包括像素电路，像素电路包括驱动晶体管，数据写入晶体管、补偿晶体管、第一初始化晶体管和第二初始化晶体管，补偿晶体管连接于驱动晶体管的栅极和驱动晶体管的第二极之间，驱动晶体管的第二极通过第一初始化晶体管连接至初始化电源端；数据写入晶体管连接于数据电压输入端与驱动晶体管的第一极之间；第二初始化晶体管连接于第一信号端和驱动晶体管的第一极之间；像素电路还包括第一扫描线、第二扫描线、第三扫描线、第四扫描线、数据线、栅极驱动器和数据驱动器；
其中，第一扫描线与像素电路的第一初始化晶体管的栅极电连接，第二扫描线与补偿晶体管的栅极电连接，第三扫描线与第二初始化晶体管的栅极电连接，第四扫描线与数据写入晶体管的栅极电连接，数据线与数据电压输入端电连接；
第一扫描线、第二扫描线、第三扫描线和第四扫描线分别与栅极驱动器的输出端一一对应电连接，数据线与数据驱动器的输出端电连接；
栅极驱动器设置为在初始化阶段，向第一扫描线、第二扫描线和第三扫描线提供第一脉冲信号，以及设置为在数据写入阶段向第四扫描线提供第一脉冲信号；
数据驱动器在数据写入阶段，向数据线提供数据电压。
第三方面，本申请实施例还提供了一种显示装置，包括第二方面提供的显示面板。
本申请实施例提供了像素电路的驱动方法、显示面板和显示装置，通过在初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号，以及向第二初始化晶体管的栅极提供导通控制信号，向第一信号端提供固定电压；使得在初始化阶段，驱动晶体管的栅极电压为初始化电源端输入的初 始化电压，驱动晶体管的第一极的电压为第一信号端输入的固定电压，可以实现对驱动晶体管的完全复位，则在不同帧进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的初始化阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，发光器件的发光亮度基本一致，进而减轻残影现象。
附图说明
图1是本申请一实施例提供的一种像素电路的驱动方法的流程图；
图2是本申请一实施例提供的一种像素电路的结构示意图；
图3是本申请一实施例提供的另一种像素电路的驱动方法的流程图；
图4是本申请一实施例提供的图2所示的像素电路的一种驱动时序图；
图5是本申请一实施例提供的图2所示的像素电路的另一种驱动时序图；
图6是本申请一实施例提供的另一种像素电路的结构示意图；
图7是本申请一实施例提供图6所示的像素电路的驱动时序图；
图8是本申请一实施例提供的又一种像素电路的结构示意图；
图9是本申请一实施例提供的一种显示面板的结构示意图；
图10是本申请一实施例提供的一种显示装置的结构示意图。
具体实施方式
一种显示面板中存在短期残影的情况，例如显示面板中原来显示不同灰阶的发光器件向同一灰阶切换时发光亮度不同，使得显示效果较差。经发明人研究发现，显示面板通常包括多个像素电路，像素电路包括驱动发光器件发光的驱动晶体管，驱动晶体管通过控制流过发光器件的驱动电流来控制发光器件的发光亮度。驱动晶体管产生的驱动电流大小与驱动晶体管的栅源电压差相关， 不同显示灰阶下，驱动晶体管的栅源电压差大小不同。驱动晶体管栅源电压差的不同，使得驱动晶体管的工作状态存在差异，进而使得在驱动晶体管内部的有源层、栅极绝缘层以及有源层和栅极绝缘层的界面处载流子的捕获和释放程度存在差异，导致由不同灰阶向同一灰阶转换时，驱动晶体管的驱动电流大小不同，最终导致发光亮度的差异，形成残影。并且，对驱动晶体管栅极进行初始化时，驱动晶体管的源极通常处于浮置状态，进而使得栅极电位的改变也会引起源极电位的改变，使得驱动晶体管的复位不充分，短期残影现象仍然存在。
本申请实施例提供一种像素电路的驱动方法，其中，像素电路包括驱动晶体管、数据写入晶体管、补偿晶体管、第一初始化晶体管、第二初始化晶体管和发光器件，补偿晶体管连接于驱动晶体管的栅极和驱动晶体管的第二极之间，驱动晶体管的第二极通过第一初始化晶体管连接至初始化电源端；数据写入晶体管连接于数据电压输入端与驱动晶体管的第一极之间；第二初始化晶体管连接于第一信号端和驱动晶体管的第一极之间；发光器件连接于驱动晶体管的第二极与第二电源电压输入端之间。
图1是本申请一实施例提供的一种像素电路的驱动方法的流程图，参考图1，驱动方法包括步骤110至步骤120。
在步骤110中，初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号，以及向第二初始化晶体管的栅极提供导通控制信号，向第一信号端提供固定电压。
在步骤120中，数据写入阶段，向数据写入晶体管的栅极提供导通控制信号。
可选的，一帧内，初始化阶段在数据写入阶段之前进行。
示例性的，在初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号，使得第一初始化晶体管和补偿晶体管导通，初始化电源端输入的初始化电压通过导通的第一初始化晶体管和补偿晶体管传输至驱动晶 体管的栅极，进而对驱动晶体管的栅极进行初始化。并且，在初始化阶段，向第二初始化晶体管的栅极提供导通信号，进而使得第一信号端提供的固定电压通过导通的第二初始化晶体管传输至驱动晶体管的第一极，其中，驱动晶体管的第一极可以是驱动晶体管的源极或漏极，示例性的，在驱动晶体管为P型晶体管的情况下，驱动晶体管的第一极是驱动晶体管的源极；在驱动晶体管为N型晶体管的情况下，驱动晶体管的第一极是驱动晶体管的漏极。即在初始化阶段，驱动晶体管的栅极电压为初始化电源端输入的初始化电压，驱动晶体管的第一极的电压为第一信号端输入的固定电压，即在初始化阶段，驱动晶体管的栅极和驱动晶体管的第一极的电压差固定，可以实现对驱动晶体管的完全复位，因此在包括多个像素电路的显示面板中，每个像素电路中的驱动晶体管在初始化阶段都可以被恢复为相同的状态，则在不同帧中进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的初始化阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，则发光器件的发光亮度基本一致，进而减轻残影现象。
本申请实施例提供的像素电路的驱动方法，通过在初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号，以及向第二初始化晶体管的栅极提供导通控制信号，向第一信号端提供固定电压；使得在初始化阶段，驱动晶体管的栅极电压为初始化电源端输入的初始化电压，驱动晶体管的第一极的电压为第一信号端输入的固定电压，可以实现对驱动晶体管的完全复位，则在不同帧进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的初始化阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，发光器件的发光亮度基本一致，进而减轻残 影现象。
图2是本申请一实施例提供的一种像素电路的结构示意图，参考图2，该像素电路包括驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一初始化晶体管T4、第二初始化晶体管T5和发光器件D1，补偿晶体管T3连接于驱动晶体管T1的栅极和驱动晶体管T1的第二极之间，驱动晶体管T1的第二极通过第一初始化晶体管T4连接至初始化电源端Vref；数据写入晶体管T2连接于数据电压输入端Vdata与驱动晶体管T1的第一极之间；第二初始化晶体管T5连接于第一信号端和驱动晶体管T1的第一极之间。
像素电路还包括第一发光控制晶体管T6，驱动晶体管T1的第一极通过第二初始化晶体管T5与第一电源电压输入端Vdd电连接，驱动晶体管T1的第二极通过第一发光控制晶体管T6与发光器件D1的第一极电连接，发光器件D1的第二极与第二电源电压输入端Vss电连接；其中，第一电源电压输入端Vdd作为第一信号端。
示例性的，驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一初始化晶体管T4、第二初始化晶体管T5和第一发光控制晶体管T6可以是P型晶体管，也可以是N型晶体管。在这些晶体管为P型晶体管的情况下，导通控制信号为低电平信号；在这些晶体管为N型晶体管的情况下，导通控制信号为高电平信号。可选的，补偿晶体管T3的栅极与像素电路的第一扫描信号输入端Scan1电连接，第一初始化晶体管T4的栅极与像素电路的第二扫描信号输入端Scan2电连接，数据写入晶体管T2的栅极与第三扫描信号输入端Scan3电连接，第二初始化晶体管T5的栅极与第一发光控制信号输入端EM1电连接，第一发光控制晶体管T6的栅极与第二发光控制信号输入端EM2电连接。以下实施例均以这些晶体管均为P型晶体管，即导通控制信号均为低电平，并以第一电源电压输入端Vdd输入的信号为高电平信号，第二电源电压输入端Vss输入的信号为低电平信号为例进行说明。
图3是本申请一实施例提供的另一种像素电路的驱动方法的流程图，图4是本申请一实施例提供的图2所示像素电路的一种驱动时序图，该驱动时序可用于驱动图2所示像素电路。参考图2、图3和图4，上述实施例中初始化阶段t1包括第一初始化阶段t11和第二初始化阶段t12。
像素电路的驱动方法包括步骤111至步骤130。
在步骤111中，在第一初始化阶段t11，向第二初始化晶体管T5的栅极提供导通控制信号。
在第一初始化阶段，向第二初始化晶体管T5的栅极提供低电平信号，即向第一发光控制信号输入端EM1提供低电平信号，则第二初始化晶体管T5导通，第一电源电压输入端Vdd输入的高电平信号通过导通的第二初始化晶体管T5传输至驱动晶体管T1的第一极，进而实现对驱动晶体管T1第一极的复位。
在步骤112中，在第二初始化阶段，向第一初始化晶体管T4的栅极和补偿晶体管T3的栅极提供导通控制信号。
在第二初始化阶段，向第一初始化晶体管T4的栅极提供低电平信号，即向第二扫描信号输入端Scan2提供低电平信号，第一初始化晶体管T4导通；向补偿晶体管T3的栅极提供低电平信号，即向第一扫描信号输入端Scan1提供低电平信号，补偿晶体管T3导通，故初始化电源端Vref提供的初始化电压通过导通的第一初始化晶体管T4和补偿晶体管T3传输至驱动晶体管T1的栅极，实现对驱动晶体管T1栅极的复位。
因此，在第一初始化阶段t11和第二初始化阶段t12过后，驱动晶体管T1的第一极被初始化为第一电源电压输入端Vdd输入的电位，其中第一电源电压输入端Vdd输入的电位为固定电位，驱动晶体管T1的栅极被初始化为初始化电源端Vref输入的初始化电压，即第一初始化阶段t11和第二初始化阶段t12后驱动晶体管T1的栅极和第一极的电压差固定，可以实现对驱动晶体管T1的完全复位，进而有利于改善残影现象。可选的，一帧内，第二初始化阶段t12在第一 初始化阶段t11之后进行。
在步骤120中，数据写入阶段t13，向数据写入晶体管T2的栅极提供导通控制信号。其中数据写入阶段t13在第二初始化阶段t12之后进行。
示例性的，在数据写入阶段t13，向数据写入晶体管T2的栅极提供低电平信号，即向第三扫描信号输入端Scan3提供低电平信号数据写入晶体管T2导通；向补偿晶体管T3的栅极提供低电平信号，即向第一扫描信号输入端Scan1提供低电平信号，补偿晶体管T3导通，数据电压输入端Vdata输入的数据电压通过导通的数据写入晶体管T2、驱动晶体管T1和补偿晶体管T3写入到驱动晶体管T1的栅极，其中发光器件D1的发光亮度与驱动晶体管T1栅极写入的数据电压大小相关。
参考图1-图4，该像素电路的驱动方法还包括：
在步骤130中，在发光阶段t14，向第二初始化晶体管T5和第一发光控制晶体管T6的栅极提供导通控制信号。
示例性的，在发光阶段t14，向第二初始化晶体管T5和第一发光控制晶体管T6的栅极提供低电平信号，进而使得第二初始化晶体管T5和第一发光控制晶体管T6导通，驱动晶体管T1驱动发光器件D1发光。即本实施例提供的像素电路结构和驱动方法中，第二初始化晶体管T5还起到发光控制的作用，或者说将发光控制晶体管作为第二初始化晶体管T5，有利于减少像素电路中晶体管的数量，提高像素密度。
本实施例，通过第一初始化晶体管T4和补偿晶体管T3实现对驱动晶体管T1栅极的复位，体现在像素电路中的结构时第一初始化晶体管T4通过补偿晶体管T3与驱动晶体管T1的栅极电连接，进而使得像素电路中只有一条漏电路径，相对于通过第一初始化晶体管T4直接对驱动晶体管T1栅极进行初始化的像素电路结构(即第一初始化晶体管T4直接与驱动晶体管T1栅极电连接的像素电路结构)，可以减少漏电路径，有利于驱动晶体管T1栅极电位的保持，进 而有利于提高显示效果。
图5是本申请一实施例提供的图2所示像素电路的另一种驱动时序图，该驱动时序可用于驱动图2所示像素电路，参考图5，一帧内，第一初始化阶段t21与第二初始化阶段t22同时进行。
示例性的，图5中第一初始化阶段t21、第二初始化阶段t22和初始化阶段t2为同一阶段。第一初始化阶段t21与第二初始化阶段t22同时进行，有利于缩短每个像素电路的驱动周期(驱动周期包括初始化阶段t2、数据写入阶段t23和发光阶段t24)，进而有利于驱动高像素密度的显示面板中的像素电路。图5所示驱动时序的数据写入阶段t23和发光阶段t24与图4所示驱动时序中数据写入阶段t13和发光阶段t14像素电路的工作过程一致，在此不再赘述。
参考图4和图5，该像素电路的驱动方法还包括：
在第一初始化阶段(图4中t11，图5中t21)，向第一发光控制晶体管T6的栅极提供关断控制信号。
参考图2、图4和图5，其中向第一发光控制晶体管T6栅极提供的信号即为向第二发光控制信号输入端EM2输入的信号。示例性的，在第一初始化阶段，向第一发光控制晶体管T6的栅极提供高电平信号，进而使得在第一初始化阶段，第一发光控制晶体管T6关断。
对于图4所示驱动时序，因在第一初始化阶段，第二初始化晶体管T5导通，第一电源电压输入端Vdd输入的高电平信号传输至驱动晶体管T1的第一极；向补偿晶体管T3栅极输入的信号为高电平信号，因此补偿晶体管T3关断，由于存储电容的存储作用，驱动晶体管T1的栅极保持上一帧的数据电压。驱动晶体管T1栅极的数据电压为任一灰阶对应的数据电压，驱动晶体管T1的第一极电压为第一电源电压输入端Vdd输入的电压，因此驱动晶体管T1栅极与驱动晶体管T1第一极的电压差通常小于其阈值电压，进而使得驱动晶体管T1导通。本实施例提供的驱动方法中，通过在第一初始化阶段向第一发光控制晶体管T6的 栅极提供关断控制信号，使得第一发光控制晶体管T6在第一初始化阶段关断，进而避免在第一初始化阶段发光器件D1发光带来的显示不良。
对于图5所示驱动时序，因在第一初始化阶段，第二初始化晶体管T5导通，第一电源电压输入端Vdd输入的高电平信号传输至驱动晶体管T1的第一极；第一初始化晶体管T4和补偿晶体管T3导通，初始化电源端Vref输入的初始化电压传输至驱动晶体管T1的栅极，因初始化电压通常较低，因此驱动晶体管T1栅极与驱动晶体管T1第一极的电压差通常小于其阈值电压，进而使得驱动晶体管T1导通。本实施例提供的驱动方法中，通过在第一初始化阶段向第一发光控制晶体管T6的栅极提供关断控制信号，使得第一发光控制晶体管T6在第一初始化阶段关断，进而避免在第一初始化阶段发光器件D1发光带来的显示不良。
图6是本申请一实施例提供的另一种像素电路的结构示意图，参考图6，该像素电路包括驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一初始化晶体管T4、第二初始化晶体管T5和发光器件D1，补偿晶体管T3连接于驱动晶体管T1的栅极和驱动晶体管T1的第二极之间，驱动晶体管T1的第二极通过第一初始化晶体管T4连接至初始化电源端Vref；数据写入晶体管T2连接于数据电压输入端Vdata与驱动晶体管T1的第一极之间；第二初始化晶体管T5连接于第一信号端和驱动晶体管T1的第一极之间；发光器件D1的第二极与第二电源电压输入端Vss连接。
像素电路还包括第一发光控制晶体管T6、第二发光控制晶体管T7，驱动晶体管T1的第一极通过第一发光控制晶体管T6与第一电源电压输入端Vdd电连接，驱动晶体管T1的第二极通过第二发光控制晶体管T7与发光器件D1的第一极电连接，发光器件D1的第二极与第二电源电压输入端Vss电连接；其中，第一信号端与第二发光控制晶体管T7的栅极电连接。
参考图6，第一信号端与第二发光控制晶体管T7的栅极电连接，即第一信号端输入的信号作为控制第二发光控制晶体管T7导通或关断的控制信号，或者 说控制第二发光控制晶体管T7导通或关断的第二发光控制信号输入端EM2作为第一信号端。可选的，补偿晶体管T3的栅极与像素电路的第一扫描信号输入端Scan1电连接，第一初始化晶体管T4的栅极与像素电路的第二扫描信号输入端Scan2电连接，数据写入晶体管T2的栅极与第三扫描信号输入端Scan3电连接，第一发光控制晶体管T6的栅极与第一发光控制信号输入端EM1电连接，第二发光控制晶体管T7的栅极与第二发光控制信号输入端EM2电连接，第二初始化晶体管T5的栅极与第二扫描信号输入端Scan2电连接。
像素电路的控制方法还包括：
在初始化阶段，向第二发光控制晶体管T7的栅极提供关断控制信号。提供了另一种可实现驱动晶体管的完全复位的方式。
图7是本申请一实施例提供的图6所示的像素电路的驱动时序图，参考图6和图7，在初始化阶段t31，向第二初始化晶体管T5的栅极提供低电平信号，即向第二扫描信号输入端Scan2输入低电平信号，第二初始化晶体管T5导通，向第一信号端(第二发光控制信号输入端EM2)提供的高电平信号通过导通的第二初始化晶体管T5传输至驱动晶体管T1的第一极，实现对驱动晶体管T1第一极的初始化。同时第二发光控制晶体管T7根据其栅极输入的高电平信号而关断。并且，在初始化阶段，向第一初始化晶体管T4的栅极提供低电平信号，即向第二扫描信号输入端Scan2输入低电平信号，第一初始化晶体管T4导通；向补偿晶体管T3的栅极提供低电平信号，即第一扫描信号输入端Scan1提供低电平信号，第一初始化晶体管T4和补偿晶体管T3导通，实现对驱动晶体管T1栅极的复位，进而在初始化阶段t31实现了对驱动晶体管T1的完全复位，有利于改善残影。
在数据写入阶段t32，向数据写入晶体管T2的栅极提供低电平信号，即向第三扫描信号输入端Scan3提供低电平信号，数据写入晶体管T2导通；向补偿晶体管T3栅极提供低电平信号，即向第一扫描信号输入端Scan1提供低电平信号，补偿晶体管T3导通，进而使得数据电压输入端Vdata输入的数据电压通过 导通的数据写入晶体管T2、驱动晶体管T1和补偿晶体管T3写入到驱动晶体管T1的栅极，实现数据电压的写入和对驱动晶体管T1栅极电压的补偿。
在发光阶段t33，向第一发光控制晶体管T6的栅极提供低电平信号，即向第一发光控制信号输入端EM1提供低电平信号，第一发光控制晶体管T6导通；向第二发光控制晶体管T7的栅极提供低电平信号，即向第二发光控制信号输入端EM2提供低电平信号，第二发光控制晶体管T7导通，驱动晶体管T1驱动发光器件D1发光。
参考图6和图7，可选的，像素电路的驱动方法还包括：
在初始化阶段t31，向第一发光控制晶体管T6的栅极提供关断控制信号。
示例性的，在初始化阶段，向第一发光控制晶体管T6的栅极提供关断控制信号，使得在各阶段向第一发光控制晶体管T6和第二发光控制晶体管T7栅极提供的信号相同，进而使得向第一发光控制晶体管T6的栅极和第二发光控制晶体管T7的栅极可以连接于显示面板的同一条控制信号线，进而有利于减少显示面板中的布线数量。
图8是本申请一实施例提供的又一种像素电路的结构示意图，参考图8，该像素电路还包括第三初始化晶体管T8，第三初始化晶体管T8连接于初始化电源端Vref与发光器件D1的第一极之间；驱动方法还包括：
在初始化阶段，向第三初始化晶体管T8的栅极提供导通控制信号。
参考图8，第三初始化晶体管T8的栅极与第二扫描信号输入端Scan2电连接，图4和图5所示驱动时序同样适用于图8所示像素电路。示例性的，在初始化阶段，向第三初始化晶体管T8的栅极提供低电平信号，即向第二扫描信号输入端Scan2提供低电平信号，第三初始化晶体管T8导通，进而可以实现对发光器件D1第一极的初始化，避免发光器件D1第一极残留电荷对显示效果的影响，提升显示效果。
需要说明的是，本申请上述任意实施例提供的像素电路中，还包括存储电 容Cst，进而存储驱动晶体管的栅极电位，使得发光阶段驱动晶体管电位可以得到良好保持。
本申请实施例还提供了一种显示面板，图9是本申请一实施例提供的一种显示面板的结构示意图，参考图9，该显示面板10包括本申请任意实施例提供的像素电路100，像素电路100包括驱动晶体管、数据写入晶体管、补偿晶体管、第一初始化晶体管和第二初始化晶体管，补偿晶体管连接于驱动晶体管的栅极和驱动晶体管的第二极之间，驱动晶体管的第二极通过第一初始化晶体管连接至初始化电源端；数据写入晶体管连接于数据电压输入端与驱动晶体管的第一极之间；第二初始化晶体管连接于第一信号端和驱动晶体管的第一极之间；像素电路100还包括第一扫描线S1、第二扫描线S2、第三扫描线S3、第四扫描线S4、数据线、栅极驱动器200和数据驱动器300。
其中，第一扫描线S1与像素电路的第一初始化晶体管的栅极电连接，第二扫描线S2与补偿晶体管的栅极电连接，第三扫描线S3与第二初始化晶体管的栅极电连接，第四扫描线S4与数据写入晶体管的栅极电连接，数据线(D1、D2、D3、D4……)与数据电压输入端电连接。
第一扫描线S1、第二扫描线S2、第三扫描线S3和第三扫描线S4分别与栅极驱动器200的输出端一一对应电连接，数据线与数据驱动器300的输出端电连接。
栅极驱动器200设置为在初始化阶段，向第一扫描线S1和第二扫描线S2提供第一脉冲信号，以及向第三扫描线S3提供第一脉冲信号，以及设置为在数据写入阶段向第四扫描线S4提供第一脉冲信号。
数据驱动器300设置为在数据写入阶段，向数据线提供数据电压。
其中，第一脉冲信号可以是使像素电路中与第一脉冲信号对应的晶体管导通的控制信号，例如像素电路中与第一脉冲信号对应的晶体管类型为P型时，第一脉冲信号为低电平脉冲信号。
示例性的，栅极驱动器200可以包括输出扫描脉冲信号的扫描驱动器和输出发光控制脉冲的发光控制脉冲驱动器。示例性的，显示面板包括图2和图8所示像素电路，与第二初始化晶体管的栅极连接的第三扫描线S3可与发光控制脉冲驱动器电连接。
需要说明的是，对于图6所示像素电路，因第二初始化晶体管和第一初始化晶体管均与第二扫描信号输入端电连接，因此显示面板包括图6所示像素电路，显示面板中第一扫描线和第三扫描线可以是提供相同扫描脉冲信号的扫描线，或者将第一扫描线和第三扫描线合并为同一条扫描线，以减少布线数量。
本申请实施例提供的像素电路的驱动方法，通过栅极驱动器在初始化阶段，向第一扫描线和第二扫描线提供第一脉冲信号，以及向第三扫描线提供第一脉冲信号，以及在数据写入阶段向第四扫描线提供第一脉冲信号；数据驱动器在数据写入阶段，向数据线提供数据电压，可以实现对驱动晶体管的完全复位，则在不同帧进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的初始化阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，发光器件的发光亮度基本一致，进而减轻残影现象。
本申请实施例还提供了一种显示装置，图10是本申请一实施例提供的一种显示装置的结构示意图，参考图10，本申请实施例提供的显示装置1包括本申请上述任意实施例提供的显示面板10。显示装置可以为图10所示的手机，也可以为电脑、电视机、智能穿戴显示装置等，本申请实施例对此不作限定。

Claims (19)

  1. 一种像素电路的驱动方法，所述像素电路包括驱动晶体管、数据写入晶体管、补偿晶体管、第一初始化晶体管、第二初始化晶体管和发光器件，所述补偿晶体管连接于所述驱动晶体管的栅极和所述驱动晶体管的第二极之间，所述驱动晶体管的第二极通过所述第一初始化晶体管连接至初始化电源端；所述数据写入晶体管连接于数据电压输入端与所述驱动晶体管的第一极之间；所述第二初始化晶体管连接于第一信号端和所述驱动晶体管的第一极之间；所述发光器件连接于所述驱动晶体管的第二极与第二电源电压输入端之间；
    所述驱动方法包括：
    初始化阶段，向所述第一初始化晶体管的栅极和所述补偿晶体管的栅极提供导通控制信号，以及向所述第二初始化晶体管的栅极提供导通控制信号，向所述第一信号端提供固定电压；
    数据写入阶段，向所述数据写入晶体管的栅极提供导通控制信号。
  2. 根据权利要求1所述的像素电路的驱动方法，其中，所述像素电路还包括第一发光控制晶体管，所述驱动晶体管的第一极通过所述第二初始化晶体管与第一电源电压输入端电连接，所述驱动晶体管的第二极通过所述第一发光控制晶体管与所述发光器件的第一极电连接，所述发光器件的第二极与所述第二电源电压输入端电连接；其中，所述第一电源电压输入端作为所述第一信号端；
    所述初始化阶段包括第一初始化阶段和第二初始化阶段，
    在所述第一初始化阶段，向所述第二初始化晶体管的栅极提供导通控制信号；
    在所述第二初始化阶段，向第一初始化晶体管的栅极和补偿晶体管的栅极提供导通控制信号。
  3. 根据权利要求2所述的像素电路的驱动方法，其中，一帧内，所述第二初始化阶段在所述第一初始化阶段之后进行。
  4. 根据权利要求2所述的像素电路的驱动方法，其中，一帧内，所述第一初始化阶段与所述第二初始化阶段同时进行。
  5. 根据权利要求2所述的像素电路的驱动方法，还包括：
    在所述第一初始化阶段，向所述第一发光控制晶体管的栅极提供关断控制信号。
  6. 根据权利要求1所述的像素电路的驱动方法，其中，所述像素电路还包括第一发光控制晶体管、第二发光控制晶体管，所述驱动晶体管的第一极通过所述第一发光控制晶体管与第一电源电压输入端电连接，所述驱动晶体管的第二极与通过所述第二发光控制晶体管与所述发光器件的第一极电连接，所述发光器件的第二极与所述第二电源电压输入端电连接；其中，所述第一信号端与所述第二发光控制晶体管的栅极电连接；
    所述像素电路的控制方法还包括：
    在初始化阶段，向所述第二发光控制晶体管的栅极提供关断控制信号。
  7. 根据权利要求6所述的像素电路的驱动方法，还包括：
    在所述初始化阶段，向所述第一发光控制晶体管的栅极提供关断控制信号。
  8. 根据权利要求1所述的像素电路的驱动方法，其中，所述像素电路还包括第三初始化晶体管，所述第三初始化晶体管连接于所述初始化电源端与所述发光器件的第一极之间；所述驱动方法还包括：
    在所述初始化阶段，向所述第三初始化晶体管的栅极提供导通控制信号。
  9. 根据权利要求1所述的像素电路的驱动方法，其中，一帧内，所述初始化阶段在所述数据写入阶段之前进行。
  10. 根据权利要求1所述的像素电路的驱动方法，其中，所述驱动晶体管的第一极为所述驱动晶体管源极或漏极，在所述驱动晶体管为P型晶体管的情况下，所述驱动晶体管的第一极是所述驱动晶体管的源极；在所述驱动晶体管为N型晶体管的情况下，所述驱动晶体管的第一极是所述驱动晶体管的漏极。
  11. 根据权利要求2所述的像素电路的驱动方法，其中，所述补偿晶体管的栅极与所述像素电路的第一扫描信号输入端电连接，所述第一初始化晶体管的栅极与所述像素电路的第二扫描信号输入端电连接，所述数据写入晶体管的 栅极与第三扫描信号输入端电连接，所述第二初始化晶体管的栅极与第一发光控制信号输入端电连接，所述第一发光控制晶体管的栅极与第二发光控制信号输入端电连接。
  12. 根据权利要求2所述的像素电路的驱动方法，还包括：
    在发光阶段，向所述第二初始化晶体管和所述第一发光控制晶体管的栅极提供导通控制信号。
  13. 根据权利要求1-12所述的像素电路的驱动方法，其中，所述像素电路还包括存储电容，所述存储电容设置为存储所述驱动晶体管的栅极电位，以在发光阶段保持所述驱动晶体管的栅极电位。
  14. 根据权利要求6所述的像素电路的驱动方法，其中，所述补偿晶体管的栅极与所述像素电路的第一扫描信号输入端电连接，所述第一初始化晶体管的栅极与所述像素电路的第二扫描信号输入端电连接，所述数据写入晶体管的栅极与第三扫描信号输入端电连接，所述第一发光控制晶体管的栅极与第一发光控制信号输入端电连接，所述第二发光控制晶体管的栅极与第二发光控制信号输入端电连接，所述第二初始化晶体管的栅极与所述第二扫描信号输入端电连接。
  15. 一种显示面板，包括像素电路，所述像素电路包括驱动晶体管，数据写入晶体管、补偿晶体管、第一初始化晶体管和第二初始化晶体管，所述补偿晶体管连接于所述驱动晶体管的栅极和所述驱动晶体管的第二极之间，所述驱动晶体管的第二极通过所述第一初始化晶体管连接至初始化电源端；所述数据写入晶体管连接于数据电压输入端与所述驱动晶体管的第一极之间；所述第二初始化晶体管连接于第一信号端和所述驱动晶体管的第一极之间；所述像素电路还包括第一扫描线、第二扫描线、第三扫描线、第四扫描线、数据线、栅极驱动器和数据驱动器；
    其中，所述第一扫描线与所述像素电路的所述第一初始化晶体管的栅极电连接，所述第二扫描线与所述补偿晶体管的栅极电连接，所述第三扫描线与所 述第二初始化晶体管的栅极电连接，所述第四扫描线与所述数据写入晶体管的栅极电连接，所述数据线与所述数据电压输入端电连接；
    所述第一扫描线、所述第二扫描线、所述第三扫描线和所述第四扫描线分别与所述栅极驱动器的输出端一一对应电连接，所述数据线与所述数据驱动器的输出端电连接；
    所述栅极驱动器设置为在初始化阶段，向所述第一扫描线、所述第二扫描线和所述第三扫描线提供第一脉冲信号，以及设置为在数据写入阶段向所述第四扫描线提供第一脉冲信号；
    所述数据驱动器在所述数据写入阶段，向所述数据线提供数据电压。
  16. 根据权利要求15所述的显示面板，其中，所述第一脉冲信号为所述像素电路中与所述第一脉冲信号对应的晶体管导通的控制信号，在所述像素电路中与所述第一脉冲信号对应的晶体管为P型晶体管的情况下，所述第一脉冲信号为低电平脉冲信号。
  17. 根据权利要求15所述的显示面板，其中，所述栅极驱动器包括输出扫描脉冲信号的扫描驱动器和输出发光控制脉冲的发光控制脉冲驱动器。
  18. 根据权利要求17所述的显示面板，其中，所述第三扫描线与所述发光控制脉冲驱动器电连接。
  19. 一种显示装置，包括权利要求15所述的显示面板。
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