WO2021007769A1 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2021007769A1
WO2021007769A1 PCT/CN2019/096139 CN2019096139W WO2021007769A1 WO 2021007769 A1 WO2021007769 A1 WO 2021007769A1 CN 2019096139 W CN2019096139 W CN 2019096139W WO 2021007769 A1 WO2021007769 A1 WO 2021007769A1
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Prior art keywords
flat layer
layer
via hole
base substrate
switch unit
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PCT/CN2019/096139
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English (en)
French (fr)
Inventor
李峰
方业周
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001057.4A priority Critical patent/CN110520976B/zh
Priority to US16/768,168 priority patent/US11889721B2/en
Priority to PCT/CN2019/096139 priority patent/WO2021007769A1/zh
Publication of WO2021007769A1 publication Critical patent/WO2021007769A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/163—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor
    • G02F2001/1635—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor the pixel comprises active switching elements, e.g. TFT
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate usually includes a base substrate and a thin film transistor (English: Thin Film Transistor; TFT for short) on the base substrate, a flat layer, and a pixel electrode.
  • TFT Thin Film Transistor
  • the pixel electrode is connected to the drain of the TFT through a via hole on the flat layer.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the technical solution is as follows:
  • a method for manufacturing a display substrate including:
  • the switch unit including an output electrode
  • a flat layer is formed on the side of the switch unit away from the base substrate, and the flat layer has flat layer via holes in the area corresponding to the output electrode.
  • the orthographic projection is located in the orthographic projection area of the output electrode on the base substrate;
  • a pixel electrode is formed on the side of the flat layer away from the switch unit, and the pixel electrode is in contact with the output electrode through the flat layer via hole.
  • etching the surface of the region corresponding to the flat layer via on the output electrode includes:
  • the surface of the output electrode corresponding to the flat layer via hole is etched.
  • the method further includes:
  • the forming a flat layer on the side of the switch unit away from the base substrate includes:
  • the step of using the flat layer as a mask to etch the surface of the output electrode corresponding to the flat layer via hole includes:
  • planarization layer as a mask, overetch the area on the passivation layer exposed by the planarization layer vias to form the passivation layer vias on the passivation layer, and perform a correction to the output
  • the electrode is etched on the surface of the area corresponding to the flat layer via hole, the passivation layer via hole communicates with the flat layer via hole, and the orthographic projection of the passivation layer via hole on the base substrate Located in the orthographic projection area of the flat layer via on the base substrate;
  • the forming a pixel electrode on a side of the flat layer away from the switch unit, the pixel electrode being in contact with the output electrode through the flat layer via hole includes:
  • a pixel electrode is formed on a side of the flat layer away from the switch unit, and the pixel electrode is in contact with the output electrode through the flat layer via hole and the passivation layer via hole.
  • the two mutually connected opening surfaces of the planar layer via hole and the passivation layer via hole overlap.
  • the step of using the flat layer as a mask to over-etch areas on the passivation layer exposed by the flat layer vias includes:
  • an area on the passivation layer exposed by the flat layer via hole is over-etched through a dry etching process.
  • the output electrode is exposed through the flat layer via hole, and the flat layer is used as a mask to etch the surface of the output electrode corresponding to the flat layer via hole, including :
  • the surface of the area on the output electrode exposed by the flat layer via hole is etched by a wet etching process.
  • the method further includes:
  • the target time is less than or equal to 30 minutes.
  • the switch unit is a thin film transistor
  • the forming the switch unit on the base substrate includes:
  • a gate electrode, a gate insulating layer, an active layer, and a source-drain layer are formed on the base substrate, the source-drain layer includes a source electrode and a drain electrode, and the output electrode is the drain electrode.
  • the method further includes: sequentially forming an insulating layer and a common electrode on a side of the pixel electrode away from the flat layer.
  • the common electrode is a plate electrode
  • the pixel electrode is a strip electrode
  • a display substrate is provided, which is manufactured by using the method described in any one of the above aspects, including:
  • a switch unit located on the base substrate includes an output electrode, the output electrode has a groove on a side away from the base substrate, and the depth of the groove is 50-300 angstroms;
  • the projection is located in the orthographic projection area of the output electrode on the base substrate;
  • the pixel electrode located on the side of the flat layer away from the switch unit is in contact with the bottom surface of the groove through the flat layer via hole.
  • the display substrate further includes:
  • the insulating layer and the common electrode on the side of the pixel electrode away from the flat layer in a direction away from the pixel electrode;
  • the switch unit is a thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain, and the output electrode is the drain.
  • the common electrode is a plate electrode
  • the pixel electrode is a strip electrode
  • a display device including the display substrate of any one of the above-mentioned other aspects.
  • FIG. 1 is a method flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a method flowchart of another method for manufacturing a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a switch unit formed on a base substrate provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a passivation layer formed on the side of the switch unit away from the base substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram after forming a flat layer on the side of the passivation layer away from the base substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a passivation layer exposed through a flat layer via hole after being overetched according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram after forming a pixel electrode on a side of a flat layer away from a switch unit according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram after forming an insulating layer and a common electrode on a side of a pixel electrode away from a flat layer according to an embodiment of the present disclosure
  • FIG. 9 is a method flowchart of yet another method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a flat layer formed on the side of the switch unit away from the base substrate provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram after etching the surface of the area corresponding to the flat layer via hole on the output electrode according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of another pixel electrode formed on the side of the flat layer away from the switching unit provided by an embodiment of the present disclosure
  • FIG. 13 is another schematic diagram of an insulating layer and a common electrode formed on the side of the pixel electrode away from the flat layer according to an embodiment of the present disclosure.
  • the display substrate usually includes a base substrate and a TFT, a flat layer and a pixel electrode on the base substrate.
  • the TFT includes a gate, a gate insulating layer, an active layer, a source and a drain, and the flat layer has a The pixel electrode is connected to the drain through the via hole.
  • air media such as water vapor and/or oxygen in the air usually oxidize the source and drain of the TFT, causing a metal oxide film to form on the surface of the source and drain, resulting in the final display substrate.
  • the contact resistance between the pixel electrode and the drain is relatively large, the switching characteristics of the TFT are poor, and the power consumption of the display substrate is relatively large.
  • the manufacturing method thereof, and the display device provided by the embodiments of the present disclosure by etching the surface of the output electrode of the switch unit (for example, the drain of the TFT) corresponding to the flat layer via hole, the On the oxidized part of the surface of the region corresponding to the flat layer via hole, the pixel electrode is in contact with the output electrode through the flat layer via hole, so that the contact resistance between the pixel electrode and the output electrode is small, the switching characteristic of the switching unit is better, and the function of the display substrate Low consumption.
  • the switch unit for example, the drain of the TFT
  • FIG. 1 shows a method flow chart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • the method may include the following steps:
  • a switch unit is formed on a base substrate, and the switch unit includes an output electrode.
  • a flat layer is formed on the side of the switch unit away from the base substrate.
  • the flat layer has flat layer vias in the area corresponding to the output electrode.
  • the orthographic projection of the flat layer via on the base substrate is located on the output electrode on the liner. In the orthographic projection area on the base substrate.
  • step 103 the surface of the area corresponding to the flat layer via on the output electrode is etched.
  • a pixel electrode is formed on the side of the flat layer away from the switch unit, and the pixel electrode contacts the output electrode through the flat layer via hole.
  • the output electrode of the switch unit corresponding to the flat layer via hole is etched, the output electrode and the flat layer can be removed.
  • the pixel electrode is in contact with the output electrode through the flat layer via hole, so that the contact resistance between the pixel electrode and the output electrode is small, the switching characteristic of the switch unit is better, and the power consumption of the display substrate is lower.
  • FIG. 2 shows a method flowchart of another method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • the method may include the following steps:
  • a switch unit is formed on a base substrate, and the switch unit includes an output electrode.
  • the switch unit may include a control electrode, a semiconductor layer, an input electrode and an output electrode, the input electrode and the output electrode are not in contact, and the input electrode and the output electrode are respectively in contact with the semiconductor layer.
  • the switching unit may be a TFT, which may be a top-gate TFT or a bottom-gate TFT. Both the top-gate TFT and the bottom-gate TFT include a gate, a gate insulating layer, an active layer, a source, and The drain, source and drain are not in contact, and the source and drain are in contact with the active layer respectively.
  • the gate when the switching unit is a TFT, the gate may be a control electrode, the active layer may be a semiconductor layer, the source may be an input electrode, and the drain may be an output electrode.
  • FIG. 3 shows a schematic diagram of a switch unit 11 formed on a base substrate 10 according to an embodiment of the present disclosure.
  • This FIG. 3 takes the switch unit 11 as a bottom-gate TFT as an example for illustration.
  • the switch unit 11 includes a gate 111, a gate insulating layer 112, an active layer 113, a source 114 and a drain 115, the source 114 and the drain 115 are not in contact, and the source 114 and the drain 115 are respectively It is in contact with the active layer 113, where the parts on the active layer 113 that are in contact with the source 114 and the parts that are in contact with the drain 115 have been treated as conductors.
  • the gate 111 can be a control electrode, and the source 114 can be an input
  • the electrode, the drain 115 may be an output electrode.
  • the gate 111, the gate insulating layer 112, the active layer 113, and the source-drain layer are sequentially distributed along the direction away from the base substrate 10.
  • the switch unit 11 is a bottom gate. Type TFT.
  • the materials of the gate 111, the source 114, and the drain 115 may be metal materials or alloy materials.
  • the material of the gate 111 may be metal Mo (Chinese: Mo), metal Cu (Chinese: copper). ) Or metal Al (Chinese: Aluminum), or the material of the gate 111 can be metal Mo, metal Cu, or metal Al alloy; the material of the source 114 and the drain 115 Usually the same.
  • the material of the source 114 and the drain 115 can be one of metal Ti (Chinese: titanium), metal Mo, metal Cu, or metal Al, or the source 114 and drain 115 The material can be metal Ti (Chinese: titanium), metal Mo, metal Cu, or metal Al.
  • the material of the gate insulating layer 112 can be a transparent insulating material.
  • the material of the gate insulating layer 112 can be One of SiO 2 (Chinese: silicon dioxide), SiOx (Chinese: silicon oxide), SiNx (Chinese: silicon nitride), Al 2 O 3 (Chinese: alumina) or SiOxNx (Chinese: silicon oxynitride)
  • the material of the active layer 113 may be a semiconductor material, for example, the material of the active layer 113 may be oxide (English: Oxide), a-Si (Chinese: amorphous silicon) or p-Si ( Chinese: One of polysilicon, the oxide can be indium gallium zinc oxide (English: Indium Gallium Zinc Oxide; abbreviation: IGZO) active layer or indium tin zinc oxide (English: Indium Tin Zinc Oxide; abbreviation: ITZO) ).
  • Forming the switch unit 11 on the base substrate 10 may include: firstly, forming a metal Al material layer on the base substrate 10 by any of sputtering or thermal evaporation, and processing the metal Al material layer through a patterning process Obtain the gate 111; then, using SiO 2 as the material, a gate insulating layer 112 is formed on the side of the gate 111 away from the base substrate 10 by any of the processes such as deposition, coating or sputtering; then, by deposition IGZO material layer is formed on the side of the gate insulating layer 112 away from the base substrate 10 in any of the processes such as coating or sputtering.
  • the IGZO material layer is processed through a patterning process to obtain the active layer 113, and the active layer 113 is obtained by doping
  • the miscellaneous process conducts a conductive process on the active layer 113 that is in contact with the source and drain to be formed; finally, the active layer 113 is far away from the base substrate by any of sputtering or thermal evaporation.
  • a metal Ti material layer is formed on one side of 10, and the metal Ti material layer is processed through a patterning process to obtain the source electrode 114 and the drain electrode 115.
  • the deposition process may be, for example, plasma enhanced chemical vapor deposition (English: Plasma Enhanced Chemical Vapor Deposition; abbreviated as: PECVD).
  • a passivation layer is formed on the side of the switch unit away from the base substrate.
  • FIG. 4 shows a schematic diagram of a passivation layer 12 formed on a side of the switch unit 11 away from the base substrate 10 according to an embodiment of the present disclosure, and the passivation layer 12 covers the switch unit 11.
  • the material of the passivation layer 12 may be one or a combination of SiOx, SiNx, or SiOxNx.
  • the passivation layer 12 is formed on the side of the switch unit 11 away from the base substrate 10 by any of the processes such as deposition, coating, or sputtering.
  • a flat layer is formed on the side of the passivation layer away from the base substrate.
  • the flat layer has flat layer vias in the area corresponding to the output electrode.
  • the orthographic projection of the flat layer via on the base substrate is located on the output electrode. In the orthographic projection area on the base substrate, the area on the passivation layer corresponding to the output electrode is exposed through the flat layer via hole.
  • FIG. 5 shows a schematic diagram of a flat layer 13 formed on the side of the passivation layer 12 away from the base substrate 10 according to an embodiment of the present disclosure.
  • the flat layer 13 is connected to the drain 115 (that is, The corresponding area of the output electrode) has a flat layer via 131.
  • the orthographic projection of the flat layer via 131 on the base substrate 10 is located in the orthographic projection area of the drain 115 on the base substrate 10.
  • the passivation layer 12 and the drain The corresponding area 115 is exposed through the flat layer via 131.
  • the flat layer via 131 may be a cylindrical via, a quadrangular prism via, or a truncated truncated via, which is not limited in the embodiment of the present disclosure.
  • the material of the flat layer 13 may be an organic transparent material or an inorganic transparent material
  • the organic transparent material may be an organic resin
  • the inorganic transparent material may be one or more of SiOx, SiNx, Al 2 O 3 or SiOxNx. Kind of combination.
  • a resin material layer is formed on the side of the passivation layer 12 away from the base substrate 10 through any of the processes of deposition, magnetron sputtering, or thermal evaporation, and then the resin The material layer is sequentially exposed and developed to form a flat layer via 131 on the resin material layer. Finally, the resin material layer with the flat layer via 131 is cured to obtain the flat layer 13. Wherein, curing the resin material layer can remove the water vapor in the resin material layer, and prevent the water vapor in the finally formed flat layer from affecting the output electrode (that is, the drain 115) of the switch unit 11.
  • step 204 using the planarization layer as a mask, the areas exposed by the planarization layer vias on the passivation layer are over-etched to form the passivation layer vias on the passivation layer, and the output electrode is connected to the planarization layer.
  • the surface of the corresponding area of the via hole is etched.
  • the area exposed by the flat layer vias on the passivation layer is over-etched, and the passivation layer vias can be formed on the passivation layer, and the output electrodes can be connected with the flat layer vias.
  • a groove is formed on the surface of the corresponding area, and the depth of the groove may be 50-300 angstroms.
  • the passivation layer via is in communication with the flat layer via, and the orthographic projection of the passivation layer via on the base substrate is located in the orthographic projection area of the flat layer via on the base substrate.
  • the passivation layer via hole may be a cylindrical via hole, a quadrangular prism via hole or a truncated cone via hole, which is not limited in the embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of the passivation layer 12 exposed by the flat layer via 131 after being etched according to an embodiment of the present disclosure, with the flat layer 13 as a mask.
  • the area on the passivation layer 12 exposed by the flat layer via 131 is over-etched by a dry etching process.
  • the area exposed by the flat layer via 131 on the passivation layer 12 is over-etched, and the passivation layer via 121 can be formed on the passivation layer 12.
  • the passivation layer via 121 is in communication with the flat layer via 131, and the orthographic projection of the passivation layer via 121 on the base substrate 10 is located in the orthographic projection area of the flat layer via 131 on the base substrate 10.
  • the two communicating opening surfaces of the passivation layer via hole 121 and the planarization layer via hole 131 overlap each other, so the alignment accuracy of the passivation layer via hole 121 and the planarization layer via hole 131 is high, and dislocation is not easy to occur.
  • the depth of the groove formed by the etching is usually 50-100 angstroms.
  • a pixel electrode is formed on the side of the flat layer away from the switching unit, and the pixel electrode contacts the output electrode through the flat layer via hole and the passivation layer via hole.
  • FIG. 7 shows a schematic diagram after the pixel electrode 14 is formed on the side of the flat layer 13 away from the switch unit 11 according to an embodiment of the present disclosure.
  • the pixel electrode 14 contacts the drain 115 (that is, the output electrode) through the planarization layer via 131 and the passivation layer via 121, and specifically contacts the bottom surface of the groove on the drain 115 Contact, the pixel electrode 14 may be a strip electrode.
  • the material of the pixel electrode 14 may be a transparent conductive material, and the transparent conductive material may be indium tin oxide (English: Indium Tin Oxide; abbreviation: ITO), indium zinc oxide (English: Indium Zinc Oxide; abbreviation: IZO) or One or a combination of aluminum-doped zinc oxide (English: Aluminum-doped Zinc Oxide; abbreviation: ZnO:Al).
  • ITO Indium Tin Oxide
  • IZO indium zinc oxide
  • ZnO Aluminum-doped Zinc Oxide
  • an ITO material layer can be formed on the side of the flat layer 13 away from the switch unit 11 by any of deposition, magnetron sputtering, or thermal evaporation, and the ITO material layer can be processed through a patterning process to obtain the pixel electrode 14.
  • step 206 an insulating layer and a common electrode are sequentially formed on the side of the pixel electrode away from the flat layer.
  • FIG. 8 shows a schematic diagram of an insulating layer 15 and a common electrode 16 formed in sequence on the side of the pixel electrode 14 away from the flat layer 13 provided by an embodiment of the present disclosure.
  • the insulating layer 15 covers the pixel electrode.
  • the common electrode 16 may be a plate electrode.
  • the material of the insulating layer 15 may be a transparent insulating material.
  • the material of the insulating layer 15 may be one or a combination of SiO 2 , SiOx, SiNx, Al 2 O 3 or SiOxNx, and the material of the common electrode 16 It may be a transparent conductive material.
  • the material of the common electrode 16 may be one or a combination of ITO, IZO, or ZnO:Al.
  • forming the insulating layer 15 and the common electrode 16 on the side of the pixel electrode 14 away from the flat layer 13 may include: first, by deposition, In any of the processes such as coating or sputtering, a layer of SiO 2 is deposited on the side of the pixel electrode 14 away from the flat layer 13 as the insulating layer 15; then, by any of the processes such as deposition, magnetron sputtering, or thermal evaporation One is to form an ITO material layer on the side of the insulating layer 15 away from the flat layer 13, and process the ITO material layer through a patterning process to obtain the common electrode 16.
  • the structure shown in FIG. 8 may be a display substrate, but the display substrate shown in FIG. 8 is only exemplary and cannot be used to limit the display substrate actually manufactured in the embodiment of the present disclosure, except
  • the display substrate may also include structures such as gate lines and data lines.
  • the gate lines are usually connected to the gate and the data lines are usually connected to the source, which will not be repeated in the embodiments of the present application.
  • the output electrode and the flat layer can be removed.
  • the pixel electrode is in contact with the output electrode through the flat layer via hole, so that the contact resistance between the pixel electrode and the output electrode is small, the switching characteristic of the switch unit is better, and the power consumption of the display substrate is lower.
  • the surface of the output electrode corresponding to the flat layer via hole is etched using the flat layer as a mask, the manufacturing process of the display substrate can be simplified.
  • the passivation layer and the planarization layer are manufactured by two patterning processes. Due to the limitation of manufacturing accuracy, the vias on the passivation layer and the planarization layer are prone to misalignment, resulting in pixel electrodes The contact surface with the drain electrode is small or even unable to contact, resulting in insufficient driving of the pixel electrode by the TFT, and even unable to drive the pixel electrode.
  • the passivation layer via is formed by using the flat layer as a mask, the passivation layer via and the flat layer via can be self-aligned, and the passivation layer via and the flat layer via are aligned
  • the accuracy is high, so it can avoid the misalignment of the flat layer via hole and the passivation layer via hole, and ensure the effective contact between the pixel electrode and the output electrode, thereby avoiding the situation that the switching unit does not drive the pixel electrode or even cannot drive the pixel electrode.
  • the solutions provided by the embodiments of the present disclosure can meet the requirements of the display substrate for high frequency and low power consumption.
  • FIG. 9 shows a method flowchart of still another method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • the method may include the following steps:
  • a switch unit is formed on a base substrate, and the switch unit includes an output electrode.
  • step 201 of the embodiment shown in FIG. 2 For the structure of the switch unit and the implementation process of step 301, reference may be made to step 201 of the embodiment shown in FIG. 2 and the accompanying drawings corresponding to step 201, which are not repeated in the embodiment of the present disclosure.
  • a flat layer is formed on the side of the switch unit away from the base substrate, and the flat layer has flat layer via holes in the area corresponding to the output electrode, and the output electrode is exposed through the flat layer via hole.
  • FIG. 10 shows a schematic diagram of a flat layer 13 formed on the side of the switch unit 11 away from the base substrate 10 according to an embodiment of the present disclosure.
  • the flat layer 13 is connected to the output electrode (ie It is the drain 115)
  • the corresponding area has a flat layer via 131, the orthographic projection of the flat layer via 131 on the base substrate 10 is located in the orthographic projection area of the output electrode on the base substrate 10, and the output electrode passes through the flat layer via 131 nudity.
  • forming the flat layer 13 on the side of the switch unit 11 away from the base substrate 10 may include: first, using organic resin as a material, in the switch unit by any of deposition, magnetron sputtering, or thermal evaporation. 11 A resin material layer is formed on the side away from the base substrate 10, and then the resin material layer is sequentially exposed and developed to form a flat layer via 131 on the resin material layer. Finally, the flat layer via 131 is formed on the resin material layer. The resin material layer is cured for the target time period to obtain the flat layer 13.
  • the target duration may be less than or equal to 30 minutes, for example, the target duration may be 8 minutes, 10 minutes, 15 minutes, 20 minutes, etc.
  • curing the resin material layer can remove the water vapor in the resin material layer, and prevent the water vapor in the finally formed flat layer from affecting the output electrode of the switch unit 11 (that is, the drain 115).
  • the longer the curing time of the resin material layer the more thoroughly the water vapor in the resin material layer is removed.
  • the target duration can be controlled to be less than or equal to 30 minutes to reduce the degree of oxidation of the output electrode, thereby reducing the impact of the curing process on the output electrode.
  • step 303 using the flat layer as a mask, the surface of the area exposed by the flat layer via holes on the output electrode is etched.
  • a groove can be formed on the output electrode exposed by the flat layer via, and the depth of the groove can be It is 50-300 angstroms, and the actual depth of the groove is related to etching parameters such as etching process and etching time.
  • FIG. 11 shows a schematic diagram of an output electrode (that is, the drain 115) corresponding to the flat layer via 131 after etching according to an embodiment of the present disclosure.
  • the surface of the area exposed by the flat layer via 131 on the drain 115 can be etched by a wet etching process, and a groove is formed on the surface of the area exposed by the flat layer via 131 on the drain 115 (Fig. 11 Not shown).
  • the depth of the groove formed by the etching is generally 200-300 angstroms.
  • the structure shown in FIG. 10 can be placed in an etching solution, and under the protection of the flat layer 13, the surface of the exposed area of the drain 115 through the flat layer via 131 chemically reacts with the etching solution to cause the leakage
  • the oxidized portion of the surface of the electrode 115 exposed through the flat layer via 131 is etched away, and a groove is formed on the drain 115 on the surface of the exposed area through the flat layer via 131.
  • a pixel electrode is formed on the side of the flat layer away from the switch unit, and the pixel electrode contacts the output electrode through the flat layer via hole.
  • FIG. 12 is another schematic diagram of a pixel electrode 14 formed on the side of the flat layer 13 away from the switch unit 11 provided by an embodiment of the present disclosure.
  • the pixel electrode 14 passes through the flat layer via hole and the output electrode (that is, The bottom surface of the groove on the drain 115) is in contact with each other, and the pixel electrode 14 may be a strip electrode.
  • step 305 an insulating layer and a common electrode are sequentially formed on the side of the pixel electrode away from the flat layer.
  • FIG. 13 is another schematic diagram provided by an embodiment of the present disclosure after an insulating layer 15 and a common electrode 16 are sequentially formed on the side of the pixel electrode 14 away from the flat layer 13.
  • step 304 to step 305 For the implementation process of the foregoing step 304 to step 305, reference may be made to step 205 to step 206 of the embodiment shown in FIG. 2, which will not be repeated in the embodiment of the present disclosure.
  • the structure shown in FIG. 13 may be a display substrate, but the display substrate shown in FIG. 13 is only exemplary and cannot be used to limit the display substrate actually manufactured in the embodiment of the present disclosure, except
  • the display substrate may also include structures such as gate lines and data lines.
  • the gate lines are usually connected to the gate and the data lines are usually connected to the source, which will not be repeated in the embodiments of the present application.
  • the output electrode and the flat layer can be removed.
  • the pixel electrode is in contact with the output electrode through the flat layer via hole, so that the contact resistance between the pixel electrode and the output electrode is small, the switching characteristic of the switch unit is better, and the power consumption of the display substrate is lower.
  • the surface of the output electrode corresponding to the flat layer via hole is etched using the flat layer as a mask, the manufacturing process of the display substrate can be simplified.
  • the one patterning process involved includes photoresist coating, exposure, development, etching, and photoresist stripping.
  • the material layer (such as ITO material layer )
  • the processing includes: first, coating a layer of photoresist on the material layer (such as ITO material layer) to form a photoresist layer, and then using a mask to expose the photoresist layer so that the photoresist layer is formed
  • the fully exposed area and the non-exposed area are then processed by a development process to completely remove the photoresist in the fully exposed area, and all the photoresist in the non-exposed area is retained.
  • the material layer (such as ITO material The area corresponding to the fully exposed area on the layer) is etched, and finally, the photoresist in the non-exposed area is stripped to obtain a corresponding structure (for example, the pixel electrode 14).
  • the photoresist is a positive photoresist as an example.
  • the process of one patterning process can refer to the description in this paragraph, and the embodiments of the present disclosure will not be omitted here. Repeat.
  • a display substrate which may be a display substrate as shown in FIG. 8 or FIG. 13.
  • the display substrate includes a base substrate 10; a switch unit 11 located on the base substrate 10, the switch unit 11 includes an output electrode, and the side of the output electrode away from the base substrate 10 has a groove (Neither shown in FIGS. 8 and 13), the depth of the groove may be 50-300 angstroms; the flat layer 13 located on the side of the switch unit 11 away from the base substrate 10, and the area on the flat layer 13 corresponding to the output electrode It has flat layer vias (not shown in FIGS.
  • the orthographic projection of the flat layer vias on the base substrate 10 is located in the orthographic projection area of the output electrode on the base substrate 10; located on the flat layer 13
  • the pixel electrode 14 on the side away from the switch unit 11 is in contact with the bottom surface of the groove on the output electrode through the flat layer via hole, and the groove is obtained by etching the side of the output electrode away from the base substrate 10 .
  • the switch unit 11 may be a TFT.
  • the TFT may be a top-gate TFT or a bottom-gate TFT. Both the top-gate TFT and the bottom-gate TFT include a gate, a gate insulating layer, an active layer, and a source.
  • the output electrode of the switch unit 11 may be the drain.
  • the embodiment of the present disclosure takes the switch unit 11 as a bottom-gate TFT as an example for description. As shown in FIG. 8 and FIG. 13, the switch unit 11 includes gates 111 sequentially distributed along a direction away from the base substrate 10.
  • the gate insulating layer 112, the active layer 113, the source drain layer, the source drain layer includes a source 114 and a drain 115
  • the output electrode of the switch unit 11 may be the drain 115
  • the bottom surface of the groove is in contact, that is, in the display substrate shown in FIGS. 8 and 13, the pixel electrode 14 is in contact with the bottom surface of the groove on the drain 115.
  • the display substrate may further include a passivation layer 12, the passivation layer 12 is located between the switching unit 11 and the flat layer 13, and the passivation layer 12 is connected to the output electrode (also The corresponding area of the drain 115) has a passivation layer via hole (not marked in FIG. 8), the passivation layer via hole is connected to the flat layer via hole, and the passivation layer via hole is located on the base substrate 10
  • the projection is located in the orthographic projection area of the flat layer via hole on the base substrate 10.
  • the pixel electrode 14 passes through the flat layer via hole and the passivation layer via hole to contact the recess on the output electrode (that is, the drain 115) of the switch unit 11 The bottom surface of the groove touches.
  • the two interconnected opening surfaces on the flat layer via and the passivation layer via overlap, so that the alignment accuracy of the flat layer via and the passivation layer via is higher. , Can ensure the effective contact of the pixel electrode and the output electrode.
  • the display substrate may further include an insulating layer 15 and a common electrode 16 located on the side of the pixel electrode 14 away from the flat layer 13 in a direction away from the pixel electrode 14.
  • the common electrode 16 is a plate electrode
  • the pixel electrode 14 is a strip electrode
  • the insulating layer 15 can keep the pixel electrode 14 and the common electrode 16 insulated.
  • the groove is obtained by etching the side of the output electrode away from the base substrate Etching can remove the oxidized part of the output electrode on the side away from the base substrate. Therefore, the bottom surface of the groove is not oxidized. Therefore, the contact resistance between the pixel electrode and the output electrode is small, and the switching characteristics of the switching unit are better. The power consumption of the substrate is low.
  • embodiments of the present disclosure also provide a display device, which includes the display substrate provided in the above-mentioned embodiments.
  • the display device may be any product or component with display function.
  • the display device may be electronic paper, mobile phone, tablet computer, television, notebook computer, display, digital photo frame, navigator, watch or bracelet.

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Abstract

本公开提供一种显示基板及其制造方法、显示装置，属于显示技术领域，该方法包括：在衬底基板上形成开关单元；在开关单元远离衬底基板的一侧形成平坦层，平坦层上与输出电极对应区域具有平坦层过孔，平坦层过孔在衬底基板上的正投影位于输出电极在衬底基板上的正投影区域内；对输出电极上与平坦层过孔对应区域的表面进行刻蚀；在平坦层远离开关单元的一侧形成像素电极，像素电极通过平坦层过孔与输出电极接触。本公开可以减小输出电极与像素电极的接触电阻，提升开关单元的开关特性。本公开用于显示基板制造。

Description

显示基板及其制造方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其制造方法、显示装置。
背景技术
显示基板通常包括衬底基板以及位于衬底基板上的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)、平坦层和像素电极，像素电极通过平坦层上的过孔与TFT的漏极连接。
发明内容
本公开实施例提供了一种显示基板及其制造方法、显示装置。所述技术方案如下：
一方面，提供一种显示基板的制造方法，包括：
在衬底基板上形成开关单元，所述开关单元包括输出电极；
在所述开关单元远离所述衬底基板的一侧形成平坦层，所述平坦层上与所述输出电极对应区域具有平坦层过孔，所述平坦层过孔在所述衬底基板上的正投影位于所述输出电极在所述衬底基板上的正投影区域内；
对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀；
在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极通过所述平坦层过孔与所述输出电极接触。
可选地，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀。
可选地，在所述开关单元远离所述衬底基板的一侧形成平坦层之前，所述方法还包括：
在所述开关单元远离所述衬底基板的一侧形成钝化层；
所述在所述开关单元远离所述衬底基板的一侧形成平坦层，包括：
在所述钝化层远离所述开关单元的一侧形成平坦层，所述钝化层上与所述输出电极对应区域通过所述平坦层过孔裸露；
所述以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
以所述平坦层为掩膜，对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻，以在所述钝化层上形成钝化层过孔，并对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，所述钝化层过孔与所述平坦层过孔连通，所述钝化层过孔在所述衬底基板上的正投影位于所述平坦层过孔在所述衬底基板上的正投影区域内；
所述在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极通过所述平坦层过孔与所述输出电极接触，包括：
在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极通过所述平坦层过孔和所述钝化层过孔与所述输出电极接触。
可选地，所述平坦层过孔和所述钝化层过孔上相互连通的两个开口面重合。
可选地，所述以所述平坦层为掩膜，对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻，包括：
以所述平坦层为掩膜，通过干法刻蚀工艺对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻。
可选地，所述输出电极通过所述平坦层过孔裸露，所述以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
以所述平坦层为掩膜，通过湿法刻蚀工艺对所述输出电极上通过所述平坦层过孔裸露的区域的表面进行刻蚀。
可选地，在所述开关单元远离所述衬底基板的一侧形成平坦层之后，所述方法还包括：
对所述平坦层固化目标时长，所述目标时长小于或者等于30分钟。
可选地，所述开关单元为薄膜晶体管，
所述在衬底基板上形成开关单元，包括：
在所述衬底基板上形成栅极、栅绝缘层、有源层和源漏极层，所述源漏极层包括源极和漏极，所述输出电极为所述漏极。
可选地，所述方法还包括：在所述像素电极远离所述平坦层的一侧依次形 成绝缘层和公共电极。
可选地，所述公共电极为板状电极，所述像素电极为条状电极。
另一方面，提供一种显示基板，所述显示基板采用上述一方面任一所述的方法制成，包括：
衬底基板；
位于所述衬底基板上的开关单元，所述开关单元包括输出电极，所述输出电极远离所述衬底基板的一面具有凹槽，所述凹槽的深度为50～300埃；
位于所述开关单元远离所述衬底基板一侧的平坦层，所述平坦层上与所述输出电极对应区域具有平坦层过孔，所述平坦层过孔在所述衬底基板上的正投影位于所述输出电极在所述衬底基板上的正投影区域内；
位于所述平坦层远离所述开关单元一侧的像素电极，所述像素电极通过所述平坦层过孔与所述凹槽的底面接触。
可选地，所述显示基板还包括：
位于所述开关单元与所述平坦层之间的钝化层，所述钝化层上与所述输出电极对应区域具有钝化层过孔，所述钝化层过孔与所述平坦层过孔连通，所述平坦层过孔和所述钝化层过孔上相互连通的两个开口面重合，所述钝化层过孔在所述衬底基板上的正投影位于所述平坦层过孔在所述衬底基板上的正投影区域内，所述像素电极通过所述平坦层过孔和所述钝化层过孔与所述凹槽的底面接触；
沿远离所述像素电极的方向位于所述像素电极远离所述平坦层一侧的绝缘层和公共电极；
其中，所述开关单元为薄膜晶体管，包括栅极、栅绝缘层、有源层、源极和漏极，所述输出电极为所述漏极。
可选地，所述公共电极为板状电极，所述像素电极为条状电极。
再一方面，提供一种显示装置，包括上述另一方面任一所述的显示基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的制造方法的方法流程图；
图2是本公开实施例提供的另一种显示基板的制造方法的方法流程图；
图3是本公开实施例提供的一种在衬底基板上形成开关单元后的示意图；
图4是本公开实施例提供的一种在开关单元远离衬底基板的一侧形成钝化层后的示意图；
图5是本公开实施例提供的一种在钝化层远离衬底基板的一侧形成平坦层后的示意图；
图6是本公开实施例提供的一种对钝化层上通过平坦层过孔裸露的部分进行过刻后的示意图；
图7是本公开实施例提供的一种在平坦层远离开关单元的一侧形成像素电极后的示意图；
图8是本公开实施例提供的一种在像素电极远离平坦层的一侧形成绝缘层和公共电极后的示意图；
图9是本公开实施例提供的再一种显示基板的制造方法的方法流程图；
图10是本公开实施例提供的一种在开关单元远离衬底基板的一侧形成平坦层后的示意图；
图11是本公开实施例提供的一种对输出电极上与平坦层过孔对应区域的表面进行刻蚀后的示意图；
图12是本公开实施例提供的另一种在平坦层远离开关单元的一侧形成像素电极后的示意图；
图13是本公开实施例提供的另一种在像素电极远离平坦层的一侧形成绝缘层和公共电极后的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
目前处于物联网大时代，显示行业以及传感器行业等半导体电子信息行业起着举足轻重的作用。在显示行业中，显示基板通常包括衬底基板以及位于衬底基板上的TFT、平坦层和像素电极，TFT包括栅极、栅绝缘层、有源层、源极和漏极，平坦层具有过孔，像素电极通过该过孔与漏极连接。在制造平坦层的过程中，空气中的水汽和/或氧气等空气介质通常会氧化TFT的源极和漏极， 使得源极和漏极的表面形成金属氧化膜，导致最终制成的显示基板中，像素电极与漏极的接触电阻较大，TFT的开关特性较差，显示基板的功耗较大。
本公开实施例提供的显示基板及其制造方法、显示装置，通过对开关单元的输出电极(例如TFT的漏极)上与平坦层过孔对应区域的表面进行刻蚀，可以去除输出电极上与平坦层过孔对应区域的表面的被氧化的部分，像素电极通过平坦层过孔与输出电极接触，从而像素电极与输出电极的接触电阻较小，开关单元的开关特性较好，显示基板的功耗较低。
请参考图1，其示出了本公开实施例提供的一种显示基板的制造方法的方法流程图，参见图1，该方法可以包括以下几个步骤：
在步骤101中，在衬底基板上形成开关单元，开关单元包括输出电极。
在步骤102中，在开关单元远离衬底基板的一侧形成平坦层，平坦层上与输出电极对应区域具有平坦层过孔，平坦层过孔在衬底基板上的正投影位于输出电极在衬底基板上的正投影区域内。
在步骤103中，对输出电极上与平坦层过孔对应区域的表面进行刻蚀。
在步骤104中，在平坦层远离开关单元的一侧形成像素电极，像素电极通过平坦层过孔与输出电极接触。
综上所述，本公开实施例提供的显示基板的制造方法，由于对开关单元的输出电极上与平坦层过孔对应区域的表面进行了刻蚀，因此可以去除该输出电极上与平坦层过孔对应区域的表面被氧化的部分，像素电极通过平坦层过孔与输出电极接触，从而像素电极与输出电极的接触电阻较小，开关单元的开关特性较好，显示基板的功耗较低。
请参考图2，其示出了本公开实施例提供的另一种显示基板的制造方法的方法流程图，参见图2，该方法可以包括以下几个步骤：
在步骤201中，在衬底基板上形成开关单元，开关单元包括输出电极。
其中，开关单元可以包括控制电极、半导体层、输入电极和输出电极，输入电极和输出电极不接触，输入电极和输出电极分别与半导体层接触。示例地，开关单元可以是TFT，该TFT可以是顶栅型TFT或者底栅型TFT，无论顶栅型TFT还是底栅型TFT，均包括栅极、栅绝缘层、有源层、源极和漏极，源极和漏极不接触，且源极和漏极分别与有源层接触。在本公开实施例中，当开关单 元为TFT时，栅极可以是控制电极，有源层可以是半导体层，源极可以是输入电极，漏极可以是输出电极。
示例地，请参考图3，其示出了本公开实施例提供的一种在衬底基板10上形成开关单元11后的示意图，该图3以开关单元11为底栅型TFT为例进行说明。参见图3，该开关单元11包括栅极111、栅绝缘层112、有源层113、源极114和漏极115，源极114与漏极115不接触，且源极114和漏极115分别与有源层113接触，其中，有源层113上与源极114接触的部位以及与漏极115接触的部位均进行了导体化处理，栅极111可以为控制电极，源极114可以为输入电极，漏极115可以为输出电极。如图3所示，栅极111、栅绝缘层112、有源层113和源漏极层(图3中未标出)沿远离衬底基板10的方向依次分布，该开关单元11为底栅型TFT。
其中，栅极111、源极114和漏极115这三者的材料均可以为金属材料或合金材料，例如，栅极111的材料可以为金属Mo(中文：钼)、金属Cu(中文：铜)或金属Al(中文：铝)中的一种金属材料，或者，栅极111的材料可以为金属Mo、金属Cu或金属Al中的多种的合金材料；源极114和漏极115的材料通常相同，例如，源极114和漏极115的材料均可以为金属Ti(中文：钛)、金属Mo、金属Cu或金属Al中的一种金属材料，或者，源极114和漏极115的材料均可以为金属Ti(中文：钛)、金属Mo、金属Cu或金属Al中的多种的合金材料；栅绝缘层112的材料可以为透明绝缘材料，例如，栅绝缘层112的材料可以为SiO 2(中文：二氧化硅)、SiOx(中文：氧化硅)、SiNx(中文：氮化硅)、Al 2O 3(中文：氧化铝)或SiOxNx(中文：氮氧化硅)中的一种或者多种的组合，有源层113的材料可以为半导体材料，例如，有源层113的材料可以为氧化物(英文：Oxide)、a-Si(中文：非晶硅)或p-Si(中文：多晶硅)中的一种，氧化物可以为铟镓锌氧化物(英文：Indium Gallium Zinc Oxide；简称：IGZO)有源层或铟锡锌氧化物(英文：Indium Tin Zinc Oxide；简称：ITZO)。
示例地，以栅极111的材料为金属Al，栅绝缘层112的材料为SiO 2，有源层113的材料为IGZO，源极114和漏极115的材料均为金属Ti为例，则在衬底基板10上形成开关单元11可以包括：首先，通过溅射或热蒸发等工艺中的任一种在衬底基板10上形成金属Al材质层，通过一次构图工艺对金属Al材质层进行处理得到栅极111；接着，以SiO 2为材料，通过沉积、涂敷或溅射等工艺中的任一种在栅极111远离衬底基板10的一侧形成栅绝缘层112；然后，通过 沉积、涂敷或溅射等工艺中的任一种在栅绝缘层112远离衬底基板10的一侧形成IGZO材质层，通过一次构图工艺对IGZO材质层进行处理得到有源层113，并通过掺杂等工艺对有源层113上与待形成的源极和漏极接触的部位进行导体化处理；最后，通过溅射或热蒸发等工艺中的任一种在有源层113远离衬底基板10的一侧形成金属Ti材质层，通过一次构图工艺对金属Ti材质层进行处理得到源极114和漏极115。其中，沉积工艺例如可以是等离子体增强化学气相沉积法(英文：Plasma Enhanced Chemical Vapor Deposition；简称：PECVD)。
在步骤202中，在开关单元远离衬底基板的一侧形成钝化层。
请参考图4，其示出了本公开实施例提供的一种在开关单元11远离衬底基板10的一侧形成钝化层12后的示意图，钝化层12覆盖开关单元11。可选地，钝化层12的材料可以为SiOx、SiNx或SiOxNx中的一种或者多种的组合。示例地，以SiOx为材料，通过沉积、涂敷或溅射等工艺中的任一种在开关单元11远离衬底基板10的一侧形成钝化层12。
在步骤203中，在钝化层远离衬底基板的一侧形成平坦层，平坦层上与输出电极对应区域具有平坦层过孔，平坦层过孔在衬底基板上的正投影位于输出电极在衬底基板上的正投影区域内，钝化层上与输出电极对应区域通过平坦层过孔裸露。
请参考图5，其示出了本公开实施例提供的一种在钝化层12远离衬底基板10的一侧形成平坦层13后的示意图，平坦层13上与漏极115(也即是输出电极)对应区域具有平坦层过孔131，平坦层过孔131在衬底基板10上的正投影位于漏极115在衬底基板10上的正投影区域内，钝化层12上与漏极115对应区域通过该平坦层过孔131裸露。其中，平坦层过孔131可以为圆柱状过孔、四棱柱状过孔或圆台状过孔，本公开实施例对此不做限定。可选地，平坦层13的材料可以为有机透明材料或无机透明材料，该有机透明材料可以为有机树脂，该无机透明材料可以为SiOx、SiNx、Al 2O 3或SiOxNx中的一种或者多种的组合。
示例地，首先，以有机树脂为材料，通过沉积、磁控溅射或热蒸发等工艺中的任一种在钝化层12远离衬底基板10的一侧形成树脂材质层，然后，对树脂材质层依次进行曝光和显影，从而在树脂材质层上形成平坦层过孔131，最后，对形成有平坦层过孔131的树脂材质层进行固化得到平坦层13。其中，对树脂材质层进行固化可以去除树脂材质层中的水汽，避免最终形成的平坦层中的水汽影响开关单元11中的输出电极(也即是漏极115)。
在步骤204中，以平坦层为掩膜，对钝化层上通过平坦层过孔裸露的区域进行过刻，以在钝化层上形成钝化层过孔，并对输出电极上与平坦层过孔对应区域的表面进行刻蚀。
其中，以平坦层为掩膜，对钝化层上通过平坦层过孔裸露的区域进行过刻，可以在钝化层上形成钝化层过孔，且可以在输出电极上与平坦层过孔对应区域的表面形成凹槽，该凹槽的深度可以为50～300埃。钝化层过孔与平坦层过孔连通，且钝化层过孔在衬底基板上的正投影位于平坦层过孔在衬底基板上的正投影区域内。钝化层过孔可以为圆柱状过孔、四棱柱状过孔或圆台状过孔，本公开实施例对此不做限定。
示例地，请参考图6，其示出了本公开实施例提供的一种对钝化层12上通过平坦层过孔131裸露的区域进行过刻后的示意图，以平坦层13为掩膜，通过干法刻蚀工艺对钝化层12上通过平坦层过孔131裸露的区域进行过刻。如图6所示，以平坦层13为掩膜，对钝化层12上通过平坦层过孔131裸露的区域进行过刻，可以在钝化层12上形成钝化层过孔121，且可以去除输出电极(也即是漏极115)上与平坦层过孔131对应区域的表面被氧化的部分，去除输出电极上与平坦层过孔131对应区域的表面被氧化的部分后，可以在输出电极上与平坦层过孔131对应区域的表面形成凹槽(图6中未标出)。该钝化层过孔121与平坦层过孔131连通，且该钝化层过孔121在衬底基板10上的正投影位于平坦层过孔131在衬底基板10上的正投影区域内，该钝化层过孔121和平坦层过孔131上相互连通的两个开口面重合，因此钝化层过孔121与平坦层过孔131的对位精度较高，不容易出现错位。本公开实施例中，当通过干法刻蚀工艺对漏极115上通过平坦层过孔131裸露的区域的表面进行刻蚀时，刻蚀形成的凹槽的深度通常为50～100埃。
在步骤205中，在平坦层远离开关单元的一侧形成像素电极，像素电极通过平坦层过孔和钝化层过孔与输出电极接触。
示例地，请参考图7，其示出了本公开实施例提供的一种在平坦层13远离开关单元11的一侧形成像素电极14后的示意图。参见图7并结合图6，像素电极14通过平坦层过孔131和钝化层过孔121与漏极115(也即是输出电极)接触，且具体是与漏极115上的凹槽的底面接触，该像素电极14可以为条状电极。
其中，该像素电极14的材料可以为透明导电材料，该透明导电材料可以为氧化铟锡(英文：Indium Tin Oxide；简称：ITO)、氧化铟锌(英文：Indium Zinc  Oxide；简称：IZO)或掺铝氧化锌(英文：Aluminum-doped Zinc Oxide；简称：ZnO:Al)中的一种或者多种的组合。示例地，可以通过沉积、磁控溅射或热蒸发等工艺中的任一种在平坦层13远离开关单元11的一侧形成ITO材质层，通过一次构图工艺对ITO材质层进行处理得到像素电极14。
在步骤206中，在像素电极远离平坦层的一侧依次形成绝缘层和公共电极。
示例地，请参考图8，其示出了本公开实施例提供的一种在像素电极14远离平坦层13的一侧依次形成绝缘层15和公共电极16后的示意图，绝缘层15覆盖像素电极14，公共电极16可以为板状电极。
其中，绝缘层15的材料可以为透明绝缘材料，例如，绝缘层15的材料可以为SiO 2、SiOx、SiNx、Al 2O 3或SiOxNx中的一种或者多种的组合，公共电极16的材料可以为透明导电材料，例如，公共电极16的材料可以为ITO、IZO或ZnO:Al中的一种或者多种的组合。
示例地，以绝缘层15的材料为SiO 2，公共电极16的材料ITO为例，在像素电极14远离平坦层13的一侧依次形成绝缘层15和公共电极16可以包括：首先，通过沉积、涂敷或溅射等工艺中的任一种在像素电极14远离平坦层13的一侧沉积一层SiO 2作为绝缘层15；然后，通过沉积、磁控溅射或热蒸发等工艺中的任一种在绝缘层15远离平坦层13的一侧形成ITO材质层，通过一次构图工艺对ITO材质层进行处理得到公共电极16。
本领域技术人员容易理解，图8示出的可以是显示基板的结构，但是该图8示出的显示基板仅仅是示例性的，并不能用于限定本公开实施例实际制造的显示基板，除图8示出的结构外，显示基板还可以包括栅线和数据线等结构，栅线通常与栅极连接，数据线通常与源极连接，本申请实施例在此不再赘述。
综上所述，本公开实施例提供的显示基板的制造方法，由于对开关单元的输出电极上与平坦层过孔对应区域的表面进行了刻蚀，因此可以去除该输出电极上与平坦层过孔对应区域的表面被氧化的部分，像素电极通过平坦层过孔与输出电极接触，从而像素电极与输出电极的接触电阻较小，开关单元的开关特性较好，显示基板的功耗较低。此外，由于是以平坦层为掩膜对输出电极上与平坦层过孔对应区域的表面进行刻蚀的，因此可以简化显示基板的制造工艺。
在发明人所知的技术中，钝化层和平坦层是通过两次构图工艺制造的，受制造精度的限制，钝化层上的过孔和平坦层的过孔容易出现错位，导致像素电极与漏极的接触面较小甚至无法接触，从而导致TFT对像素电极的驱动不足， 甚至无法驱动像素电极。在本公开实施例中，钝化层过孔是以平坦层为掩膜形成的，钝化层过孔与平坦层过孔能够自对位，钝化层过孔与平坦层过孔的对位精度较高，因此可以避免平坦层过孔与钝化层过孔错位，保证像素电极与输出电极有效接触，从而避免开关单元对像素电极驱动不足，甚至无法驱动像素电极的情况发生。本公开实施例提供的方案可以满足显示基板对高频及低功耗的需求。
请参考图9，其示出了本公开实施例提供的再一种显示基板的制造方法的方法流程图，参见图9，该方法可以包括以下步骤：
在步骤301中，在衬底基板上形成开关单元，开关单元包括输出电极。
该开关单元的结构以及该步骤301的实现过程可以参考图2所示实施例的步骤201以及该步骤201对应的附图，本公开实施例在此不再赘述。
在步骤302中，在开关单元远离衬底基板的一侧形成平坦层，平坦层上与输出电极对应区域具有平坦层过孔，输出电极通过平坦层过孔裸露。
示例地，请参考图10，其示出了本公开实施例提供的一种在开关单元11远离衬底基板10的一侧形成平坦层13后的示意图，平坦层13上与输出电极(也即是漏极115)对应区域具有平坦层过孔131，平坦层过孔131在衬底基板10上的正投影位于输出电极在衬底基板10上的正投影区域内，输出电极通过平坦层过孔131裸露。
示例地，在开关单元11远离衬底基板10的一侧形成平坦层13可以包括：首先，以有机树脂为材料，通过沉积、磁控溅射或热蒸发等工艺中的任一种在开关单元11远离衬底基板10的一侧形成树脂材质层，然后，对树脂材质层依次进行曝光和显影，从而在树脂材质层上形成平坦层过孔131，最后，对形成有平坦层过孔131的树脂材质层固化目标时长得到平坦层13。其中，该目标时长可以小于或等于30分钟，例如该目标时长可以为8分钟、10分钟、15分钟或者20分钟等。
其中，对树脂材质层进行固化可以去除树脂材质层中的水汽，避免最终形成的平坦层中的水汽影响开关单元11的输出电极(也即是漏极115)。本领域技术人员容易理解，对树脂材质层固化的时长越长，树脂材质层中的水汽被去除地越彻底，但是，在本实施例中，由于对形成有平坦层过孔131的树脂材质层固化的过程中，输出电极暴露在空气中，可能会被空气氧化，因此可以控制目 标时长小于或等于30分钟，以降低输出电极被氧化的程度，从而降低固化过程对输出电极的影响。
在步骤303中，以平坦层为掩膜，对输出电极上通过平坦层过孔裸露的区域的表面进行刻蚀。
其中，以平坦层为掩膜，对输出电极上通过平坦层过孔裸露的区域的表面进行刻蚀，可以在输出电极上通过平坦层过孔裸露的区域形成凹槽，该凹槽的深度可以为50～300埃，该凹槽的实际深度与刻蚀工艺以及刻蚀时长等刻蚀参数相关。
示例地，请参考图11，其示出了本公开实施例提供的一种对输出电极(也即是漏极115)上与平坦层过孔131对应区域进行刻蚀后的示意图。可以通过湿法刻蚀工艺对漏极115上通过平坦层过孔131裸露的区域的表面进行刻蚀，在漏极115上通过平坦层过孔131裸露的区域的表面形成凹槽(图11中未示出)。本公开实施例中，当通过湿法刻蚀工艺对漏极115上通过平坦层过孔131裸露的区域的表面进行刻蚀时，刻蚀形成的凹槽的深度通常为200～300埃。
示例地，可以将图10所示的结构放置在刻蚀液中，在平坦层13的保护下，漏极115上通过平坦层过孔131裸露区域的表面与刻蚀液发生化学反应，使漏极115上通过平坦层过孔131裸露区域的表面被氧化的部分被刻蚀掉，在漏极115上通过平坦层过孔131裸露区域的表面形成凹槽。
在步骤304中，在平坦层远离开关单元的一侧形成像素电极，像素电极通过平坦层过孔与输出电极接触。
示例地，图12是本公开实施例提供的另一种在平坦层13远离开关单元11的一侧形成像素电极14后的示意图，该像素电极14通过平坦层过孔与输出电极(也即是漏极115)上的凹槽的底面接触，该像素电极14可以为条状电极。
在步骤305中，在像素电极远离平坦层的一侧依次形成绝缘层和公共电极。
示例地，图13是本公开实施例提供的另一种在像素电极14远离平坦层13的一侧依次形成绝缘层15和公共电极16后的示意图。
上述步骤304至步骤305的实现过程可以参考图2所示实施例的步骤205至步骤206，本公开实施例在此不再赘述。
本领域技术人员容易理解，图13示出的可以是显示基板的结构，但是该图13示出的显示基板仅仅是示例性的，并不能用于限定本公开实施例实际制造的显示基板，除图13示出的结构外，显示基板还可以包括栅线和数据线等结构， 栅线通常与栅极连接，数据线通常与源极连接，本申请实施例在此不再赘述。
综上所述，本公开实施例提供的显示基板的制造方法，由于对开关单元的输出电极上与平坦层过孔对应区域的表面进行了刻蚀，因此可以去除该输出电极上与平坦层过孔对应区域的表面被氧化的部分，像素电极通过平坦层过孔与输出电极接触，从而像素电极与输出电极的接触电阻较小，开关单元的开关特性较好，显示基板的功耗较低。此外，由于是以平坦层为掩膜对输出电极上与平坦层过孔对应区域的表面进行刻蚀的，因此可以简化显示基板的制造工艺。
本公开实施例提供的显示基板的制造方法中，所涉及的一次构图工艺包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，通过一次构图工艺对材质层(例如ITO材质层)进行处理包括：首先，在材质层(例如ITO材质层)上涂覆一层光刻胶形成光刻胶层，接着，采用掩膜版对光刻胶层进行曝光，使得光刻胶层形成完全曝光区和非曝光区，然后，采用显影工艺处理，使完全曝光区的光刻胶被完全去除，非曝光区的光刻胶全部保留，之后，采用刻蚀工艺对材质层(例如ITO材质层)上完全曝光区对应的区域进行刻蚀，最后，剥离非曝光区的光刻胶得到相应的结构(例如像素电极14)。这里是以光刻胶为正性光刻胶为例进行说明的，当光刻胶为负性光刻胶时，一次构图工艺的过程可以参考本段的描述，本公开实施例在此不再赘述。
本公开实施例提供的显示基板的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
基于同样的发明构思，本公开实施例还提供了一种显示基板，该显示基板可以为如图8或图13所示的显示基板。如图8和图13所示，该显示基板包括衬底基板10；位于衬底基板10上的开关单元11，该开关单元11包括输出电极，该输出电极远离衬底基板10的一面具有凹槽(图8和图13中均未标出)，该凹槽的深度可以为50～300埃；位于开关单元11远离衬底基板10一侧的平坦层13，平坦层13上与输出电极对应区域具有平坦层过孔(图8和图13中均未标出)，平坦层过孔在衬底基板10上的正投影位于输出电极在衬底基板10上的正投影 区域内；位于平坦层13远离开关单元11一侧的像素电极14，像素电极14通过平坦层过孔与输出电极上的凹槽的底面接触，该凹槽是通过对输出电极远离衬底基板10的一面进行刻蚀得到的。
可选地，开关单元11可以为TFT，该TFT可以是顶栅型TFT或者底栅型TFT，无论顶栅型TFT还是底栅型TFT，均包括栅极、栅绝缘层、有源层、源极和漏极，开关单元11的输出电极可以为该漏极。示例地，本公开实施例以开关单元11为底栅型TFT为例进行说明，则如图8和图13所示，该开关单元11包括沿远离衬底基板10的方向依次分布的栅极111、栅绝缘层112、有源层113、源漏极层，源漏极层包括源极114和漏极115，开关单元11的输出电极可以为该漏极115，像素电极14与输出电极上的凹槽的底面接触，也即是，在如图8和图13所示的显示基板中，像素电极14与漏极115上的凹槽的底面接触。
可选地，如图8所示，该显示基板还可以包括钝化层12，钝化层12位于开关单元11与平坦层13之间，钝化层12上与开关单元11的输出电极(也即是漏极115)对应区域具有钝化层过孔(图8中未标出)，该钝化层过孔与平坦层过孔连通，该钝化层过孔在衬底基板10上的正投影位于平坦层过孔在衬底基板10上的正投影区域内，像素电极14通过平坦层过孔和钝化层过孔与开关单元11的输出电极(也即是漏极115)上的凹槽的底面接触。
可选地，如图8所示，平坦层过孔和钝化层过孔上相互连通的两个开口面重合，这样一来，平坦层过孔和钝化层过孔的对位精度较高，可以保证像素电极与输出电极有效接触。
可选地，如图8和图13所示，该显示基板还可以包括：沿远离像素电极14的方向位于像素电极14远离平坦层13一侧的绝缘层15和公共电极16。其中，公共电极16为板状电极，像素电极14为条状电极，绝缘层15可以使像素电极14和公共电极16保持绝缘。
综上所述，本公开实施例提供的显示基板，由于像素电极与开关单元的输出电极上的凹槽的底面接触，该凹槽是通过对该输出电极远离衬底基板的一面刻蚀得到的，刻蚀可以去除该输出电极远离衬底基板的一面上被氧化的部分，因此凹槽的底面未被氧化，因此像素电极与输出电极的接触电阻较小，开关单元的开关特性较好，显示基板的功耗较低。
基于同样的发明构思，本公开实施例还提供了一种显示装置，该显示装置 包括上述实施例提供的显示基板。该显示装置可以是任何具有显示功能的产品或者部件，例如，该显示装置可以是电子纸、手机、平板电脑、电视机、笔记本电脑、显示器、数码相框、导航仪、手表或手环等。
本公开实施例中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或者”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (12)

  1. 一种显示基板的制造方法，包括：
    在衬底基板上形成开关单元，所述开关单元包括输出电极；
    在所述开关单元远离所述衬底基板的一侧形成平坦层，所述平坦层上与所述输出电极对应区域具有平坦层过孔，所述平坦层过孔在所述衬底基板上的正投影位于所述输出电极在所述衬底基板上的正投影区域内；
    对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀；
    在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极通过所述平坦层过孔与所述输出电极接触。
  2. 根据权利要求1所述的方法，其中，
    对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
    以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀。
  3. 根据权利要求2所述的方法，其中，
    在所述开关单元远离所述衬底基板的一侧形成平坦层之前，所述方法还包括：
    在所述开关单元远离所述衬底基板的一侧形成钝化层；
    所述在所述开关单元远离所述衬底基板的一侧形成平坦层，包括：
    在所述钝化层远离所述开关单元的一侧形成平坦层，所述钝化层上与所述输出电极对应区域通过所述平坦层过孔裸露；
    所述以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
    以所述平坦层为掩膜，对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻，以在所述钝化层上形成钝化层过孔，并对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，所述钝化层过孔与所述平坦层过孔连通，所述钝化层过孔在所述衬底基板上的正投影位于所述平坦层过孔在所述衬底基板上的正投影区域内；
    所述在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极 通过所述平坦层过孔与所述输出电极接触，包括：
    在所述平坦层远离所述开关单元的一侧形成像素电极，所述像素电极通过所述平坦层过孔和所述钝化层过孔与所述输出电极接触。
  4. 根据权利要求3所述的方法，其中，
    所述平坦层过孔和所述钝化层过孔上相互连通的两个开口面重合。
  5. 根据权利要求3或4所述的方法，其中，
    所述以所述平坦层为掩膜，对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻，包括：
    以所述平坦层为掩膜，通过干法刻蚀工艺对所述钝化层上通过所述平坦层过孔裸露的区域进行过刻。
  6. 根据权利要求2所述的方法，其中，
    所述输出电极通过所述平坦层过孔裸露，所述以所述平坦层为掩膜，对所述输出电极上与所述平坦层过孔对应区域的表面进行刻蚀，包括：
    以所述平坦层为掩膜，通过湿法刻蚀工艺对所述输出电极上通过所述平坦层过孔裸露的区域的表面进行刻蚀。
  7. 根据权利要求6所述的方法，其中，
    在所述开关单元远离所述衬底基板的一侧形成平坦层之后，所述方法还包括：
    对所述平坦层固化目标时长，所述目标时长小于或者等于30分钟。
  8. 根据权利要求1至7任一所述的方法，其中，
    所述开关单元为薄膜晶体管，
    所述在衬底基板上形成开关单元，包括：
    在所述衬底基板上形成栅极、栅绝缘层、有源层和源漏极层，所述源漏极层包括源极和漏极，所述输出电极为所述漏极。
  9. 根据权利要求1至8任一所述的方法，其中，所述方法还包括：
    在所述像素电极远离所述平坦层的一侧依次形成绝缘层和公共电极。
  10. 一种显示基板，所述显示基板采用权利要求1至9任一所述的方法制成，包括：
    衬底基板；
    位于所述衬底基板上的开关单元，所述开关单元包括输出电极，所述输出电极远离所述衬底基板的一面具有凹槽，所述凹槽的深度为50～300埃；
    位于所述开关单元远离所述衬底基板一侧的平坦层，所述平坦层上与所述输出电极对应区域具有平坦层过孔，所述平坦层过孔在所述衬底基板上的正投影位于所述输出电极在所述衬底基板上的正投影区域内；
    位于所述平坦层远离所述开关单元一侧的像素电极，所述像素电极通过所述平坦层过孔与所述凹槽的底面接触。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：
    位于所述开关单元与所述平坦层之间的钝化层，所述钝化层上与所述输出电极对应区域具有钝化层过孔，所述钝化层过孔与所述平坦层过孔连通，所述平坦层过孔和所述钝化层过孔上相互连通的两个开口面重合，所述钝化层过孔在所述衬底基板上的正投影位于所述平坦层过孔在所述衬底基板上的正投影区域内，所述像素电极通过所述平坦层过孔和所述钝化层过孔与所述凹槽的底面接触；
    沿远离所述像素电极的方向位于所述像素电极远离所述平坦层一侧的绝缘层和公共电极；
    其中，所述开关单元为薄膜晶体管，包括栅极、栅绝缘层、有源层、源极和漏极，所述输出电极为所述漏极。
  12. 一种显示装置，包括权利要求10或11所述的显示基板。
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