WO2021003929A1 - 一种可减少goa级数的电路及显示装置 - Google Patents

一种可减少goa级数的电路及显示装置 Download PDF

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Publication number
WO2021003929A1
WO2021003929A1 PCT/CN2019/117485 CN2019117485W WO2021003929A1 WO 2021003929 A1 WO2021003929 A1 WO 2021003929A1 CN 2019117485 W CN2019117485 W CN 2019117485W WO 2021003929 A1 WO2021003929 A1 WO 2021003929A1
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Prior art keywords
gate signal
goa
circuit
input terminal
secondary output
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PCT/CN2019/117485
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English (en)
French (fr)
Inventor
江志雄
蒙艳红
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Tcl华星光电技术有限公司
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Priority to US16/616,971 priority Critical patent/US10916172B2/en
Publication of WO2021003929A1 publication Critical patent/WO2021003929A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technology, and more specifically, to a circuit and a display device capable of reducing the number of GOA stages.
  • GOA Gate Driver on Array, array substrate row drive
  • the existing GOA circuit technology has defects, and a circuit that can reduce the number of GOA stages is needed to improve it.
  • the invention provides a circuit and a display device that can reduce the number of GOA levels, realizes a narrow frame design, and solves the problems existing in the existing cabinet opening technology.
  • the present invention provides a circuit capable of reducing the number of GOA stages, including one to multiple stages of GOA sub-circuits.
  • Each stage of the GOA sub-circuit includes a gate signal input terminal, a primary output terminal, one or more secondary output terminals, and one to A plurality of branching devices respectively corresponding to one or more of the secondary output terminals;
  • the gate signal input terminal and the primary output terminal are respectively connected to a branch node, one end of one or more of the branch devices is respectively connected to the branch node, and the other end of one or more of the branch devices Are respectively connected to one or more corresponding secondary output terminals.
  • the shunt device is a switching thin film transistor.
  • the shunt node is implemented by a threshold splitter, so that the gate signal at the gate signal input terminal is divided into multiple output gate signals.
  • the number of one or more secondary output terminals included in each stage of the GOA sub-circuit is n
  • the number of one or more branching devices is n n
  • one or more of the secondary output terminals include a first secondary output terminal, a second secondary output terminal,...the i-th secondary output terminal...the nth secondary output terminal, and one or more of the secondary output terminals
  • the way device includes the first branch device, the second branch device,...the i-th branch device...the n-th branch device.
  • the opening time of the i-th splitting device is the time when the threshold of the gate signal input terminal connected to itself is opened i/(n+1), and the i-th splitting device
  • the closing time of the circuit device is the time (i+1)/(n+1) of the gate signal input terminal connected to itself, so that the gate signal of the i-th secondary output terminal is higher than the gate signal of the gate signal input terminal connected to itself Delay one self-gate signal i/(n+1) time.
  • the gate signal of the i+1-th splitting device is delayed by the time of its own gate signal 1/(n+1) from the gate signal of the i-th splitting device.
  • the number of stages of the GOA sub-circuits of one or more stages is m, and then the GOA sub-circuits of one or more stages include the first-stage GOA sub-circuit and the second-stage GOA.
  • Sub-circuit...j-th GOA sub-circuit ...m-th GOA sub-circuit.
  • the gate signal at the gate signal input terminal of the j+1-th GOA sub-circuit is delayed by one self-gate signal from the gate signal input terminal of the j-th GOA sub-circuit time.
  • the signal at the gate signal input terminal is the same as the signal at the primary output terminal.
  • the present invention also provides a display device including the above-mentioned circuit capable of reducing the number of GOA stages.
  • the present invention provides a display including the above-mentioned display panel.
  • the present invention reduces the number of GOA circuit stages to one-Nth of the original, so as to more rationally use the area of the GOA circuit and reduce GOA levels to achieve a narrow frame design.
  • FIG. 1 is a schematic diagram of the occupied area of a single-stage GOA 4k panel in the prior art
  • FIG. 2 is a schematic diagram of the occupied area of a single-stage GOA with an 8k panel in the prior art
  • Figure 3 is a schematic diagram of a threshold output gate signal in the prior art
  • FIG. 4 is a circuit diagram that can reduce the number of GOA stages provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of waveforms of the primary output terminal, the switching thin film transistor, and the secondary output terminal provided by an embodiment of the present invention.
  • FIG. 4 is a circuit diagram that can reduce the number of GOA stages according to an embodiment of the present invention.
  • the circuit that can reduce the number of GOA stages includes one to multiple stages of GOA sub-circuits 10, and each stage of the GOA sub-circuits 10 includes The gate signal input terminal 1, the primary output terminal 2, one or more secondary output terminals 3, and one or more shunt devices 4 corresponding to one or more secondary output terminals 3, respectively.
  • the shunt device 4 is preferably a switching thin film transistor, that is, a switch TFT.
  • the circuit that can reduce the number of GOA stages includes a two-stage GOA sub-circuit 10.
  • the gate signal input terminal 1 is G(n) on the left
  • the original stage The output terminal 2 is G(n) on the right
  • the first secondary output terminal 3 is G(n+1)
  • the second secondary output terminal 3 is G(n+2)
  • the first shunt device 4 is SW(1)
  • the second shunt device 4 is SW(2).
  • G(n) on the left and G(n) on the right are connected by shunt node 5, and one end of SW(1) is connected to One end of SW(2) is also connected to the shunt node 5 respectively.
  • the shunt node 5 is implemented by a gate demux (Gate demux), so that the gate signal of the gate signal input terminal 1 Divided into multiple output gate signals, that is, G(n) is divided into G(n+1) and G(n+2) through two switch TFTs, while maintaining G(n) output.
  • G(n) gate signal input terminal 1 Divided into multiple output gate signals, that is, G(n) is divided into G(n+1) and G(n+2) through two switch TFTs, while maintaining G(n) output.
  • the other end of SW(1) is connected to G(n+1), and the other end of SW(2) is connected to G(n+2).
  • the gate signal input terminal 1 is G(n+3) on the left
  • the primary output terminal 2 is G(n+3) on the right
  • the first secondary output Terminal 3 is G(n+4)
  • the second secondary output terminal 3 is G(n+5)
  • the first shunt device 4 is SW(1)
  • the second shunt device 4 is SW(2 ).
  • the number of GOA circuit stages can be reduced to 1/3 of the original.
  • FIG. 5 is a waveform diagram of the primary output terminal 2, the switching thin film transistor, and the secondary output terminal 3 provided by an embodiment of the present invention.
  • the gate signal input terminal 1G(n) and the two shunt devices 4SW (n) The high and low potentials are the same, 28V and -6V respectively;
  • the turn-on time of the switching thin film transistor SW(1) is the time when the gate is turned on 1/3, and the turn-off is the time when the gate is turned on 2/3;
  • the turn-on time of the thin film transistor SW(2) is the time when the gate is opened 2/3, and the turn-off is the time when the gate is closed.
  • the first secondary output terminal 3 divided by the gate signal input terminal 1G(n) is G(n+1), and the start and end time of the G(n+1) gate signal is just the gate
  • the signal input terminal 1G(n) is delayed by 1/3 of its threshold time, that is to say, the time when the G(n) gate is turned on by 1/3 of the G(n) threshold (gate) of the switching thin film transistor SW(1) is turned on.
  • the gate signal opening time of the gate signal input terminal G(n+3) is exactly one G(n) delay.
  • the threshold time and duration are the same, and so on for G(n+4) and G(n+5).
  • the figure also shows the waveform of G(n+6).
  • the gate signal input terminal G(n+6) ) Is just the time for which G(n+3) delays one of its thresholds, and the duration is the same, that is, GOA subcircuit 10 can be expanded according to the actual situation. If only the GOA stages need to be reduced by half, Only one switch TFT is needed; if you need to reduce the GOA to 1/4, you need three switch TFTs, and so on.
  • the GOA DEMUX (demultiplexer-threshold splitter) circuit provided by the present invention can solve the problem of unreasonable use of space caused by excessive circuit stages, and thus can not realize the problem of narrow frame. After passing through the threshold splitter, The output gate waveform is consistent with the prior art. Therefore, under the condition that the performance of the present invention remains unchanged, the number of stages of the GOA circuit is reduced to one-Nth of the original, and the area of the GOA circuit is more rationally used.
  • the present invention also provides a display device including the above-mentioned circuit capable of reducing the number of GOA stages.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种可减少GOA级数的电路及显示装置，该电路包括一至多级GOA子电路（10），每级GOA子电路（10）均包括门信号输入端（1）、原级输出端（2）、一至多个次级输出端（3）及一至多个分别与一至多个次级输出端（3）对应的分路装置（4）；门信号输入端（1）及原级输出端（2）分别连接于分路节点（5），一至多个分路装置（4）的一端分别连接于分路节点（5），一至多个分路装置（4）的另一端分别连接于一至多个分别与之对应的次级输出端（3）。通过将GOA电路级数降低为原来的N分之一，更加合理地利用GOA电路的面积，从而实现窄边框设计。

Description

一种可减少GOA级数的电路及显示装置 技术领域
本发明涉及显示器技术领域，更具体地说，涉及一种可减少GOA级数的电路及显示装置。
 背景技术
随着人们对显示器画面精细度的要求越来越高，显示器的分辨率从FHD（Full High Definition，全高清）、UD（Ultra High Definition，超高清），进而到8K甚至16K，gate（门）的级数也成倍的增长着，对于GOA(Gate Driver on Array，阵列基板行驱动)技术而言，留给GOA布线的宽度就越来越小，为了把GOA所有的功能模块都设计进去，只能加长GOA的布线区域，如图1-2所示，现有技术中，采用相同尺寸的面板实现4K分辨率或者8K分辨率时，从单级GOA占用面积的对比可以看出，面积形状受限，空间分布不合理，现有GOA电路不利于实现窄边框，参见图3，现有技术中，每一级gate门信号都需要单独的一级GOA电路做输出，如此会造成整个电路的占用长度过长。
 技术问题
现有技术中，采用相同尺寸的面板实现4K分辨率或者8K分辨率时，从单级GOA占用面积的对比可以看出，面积形状受限，空间分布不合理，现有GOA电路不利于实现窄边框，参见图3，现有技术中，每一级gate门信号都需要单独的一级GOA电路做输出，如此会造成整个电路的占用长度过长。
因此，现有GOA电路技术存在缺陷，需要一种可减少GOA级数的电路加以改进。
 技术解决方案
本发明提供了一种可减少GOA级数的电路及显示装置，实现窄边框设计，解决了现有开柜技术中存在的问题。
本发明提供了一种可减少GOA级数的电路，包括一至多级GOA子电路，每级所述GOA子电路均包括门信号输入端、原级输出端、一至多个次级输出端及一至多个分别与一至多个所述次级输出端对应的分路装置；
所述门信号输入端及所述原级输出端分别连接于分路节点，一至多个所述分路装置的一端分别连接于所述分路节点，一至多个所述分路装置的另一端分别连接于一至多个分别与之对应的次级输出端。
在本发明所述的可减少GOA级数的电路中，所述分路装置为开关薄膜晶体管。
在本发明所述的可减少GOA级数的电路中，所述分路节点采用门限分路器实现，从而使门信号输入端的门信号分为多路输出门信号。
在本发明所述的可减少GOA级数的电路中，每级所述GOA子电路所包括一至多个所述次级输出端的个数为n，一至多个所述分路装置的个数为n，则一至多个所述次级输出端包括第1次级输出端、第2次级输出端、……第i次级输出端……第n次级输出端，一至多个所述分路装置包括第1分路装置、第2分路装置、……第i分路装置……第n分路装置。
在本发明所述的可减少GOA级数的电路中，所述第i分路装置的开启时间为自身连接的门信号输入端的门限开启i/(n+1)的时间，所述第i分路装置的关闭时间为自身所连接的门信号输入端的门限开启(i+1)/(n+1)的时间，从而使第i次级输出端的门信号比自身连接的门信号输入端的门信号延迟一个自身门信号i/(n+1)的时间。
在本发明所述的可减少GOA级数的电路中，第i+1分路装置的门信号比第i级分路装置的门信号延迟一个自身门信号1/(n+1)的时间。
在本发明所述的可减少GOA级数的电路中，一至多级所述GOA子电路的级数为m，则一至多级所述GOA子电路包括第1级GOA子电路、第2级GOA子电路、……第j级GOA子电路……第m级GOA子电路。
在本发明所述的可减少GOA级数的电路中，第j+1级GOA子电路的门信号输入端的门信号比第j级GOA子电路的门信号输入端的门信号延迟一个自身门信号的时间。
在本发明所述的可减少GOA级数的电路中，所述门信号输入端的信号与所述原级输出端的信号相同。
另一方面，本发明还提供一种显示装置，包括如上所述的可减少GOA级数的电路。
本发明提供一种显示器，包括上述所述的显示面板。
 有益效果
解决高分辨率机种的GOA电路占用长度过长、不利于窄边框设计的问题，本发明通过将GOA电路级数降低为原来的N分之一，更加合理地利用GOA电路的面积，减小GOA级数，从而实现窄边框设计。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的4k面板单级GOA占用面积的示意图；
图2为现有技术的8k面板单级GOA占用面积的示意图；
图3为现有技术的门限输出门信号的示意图；
图4为本发明实施例提供的一种可减少GOA级数的电路图；
图5为本发明实施例提供的原级输出端、开关薄膜晶体管及次级输出端的波形示意图。
元件标号说明：
1           门信号输入端
2         原级输出端
3         次级输出端
4         分路装置
5         分路节点
10        GOA子电路
 本发明的最佳实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
参见图4，图4为本发明实施例提供的一种可减少GOA级数的电路图，该可减少GOA级数的电路包括一至多级GOA子电路10，每级所述GOA子电路10均包括门信号输入端1、原级输出端2、一至多个次级输出端3及一至多个分别与一至多个所述次级输出端3对应的分路装置4。其中，所述分路装置4优选为开关薄膜晶体管，即swich TFT。
在图4所示的实施例中，该可减少GOA级数的电路包括两级GOA子电路10，第一级子电路10中，门信号输入端1为左侧的G(n)，原级输出端2为右侧的G(n)，第一个次级输出端3为G(n+1)，第二个次级输出端3为G(n+2)，第一个分路装置4为SW(1)，第二个分路装置4为SW(2)，左侧的G(n)与右侧的G(n)通过分路节点5连接，而SW(1)的一端及SW(2)的一端也分别连接于该分路节点5，因此为了解决分路问题，所述分路节点5采用门限分路器（Gate demux）实现，从而使门信号输入端1的门信号分为多路输出门信号，即通过2个swich TFT将G(n)分出G(n+1)和G(n+2)，同时保持G(n)输出。SW(1)的另一端连接于G(n+1)，SW(2)的另一端连接于G(n+2)。
类似的，第二级GOA子电路10中，门信号输入端1为左侧的G(n+3)，原级输出端2为右侧的G(n+3)，第一个次级输出端3为G(n+4)，第二个次级输出端3为G(n+5)，第一个分路装置4为SW(1)，第二个分路装置4为SW(2)。
本实施例中，设置2个swich TFT，则可以将GOA电路级数降低为原来的1/3。
参见图5，图5为本发明实施例提供的原级输出端2、开关薄膜晶体管及次级输出端3的波形示意图，门信号输入端1G(n)与两个分路装置4SW (n) 的高电位和低电位相同，分别为28V和-6V；开关薄膜晶体管SW(1)的开启时间为门限(gate)开启1/3时的时间，关闭为gate开启2/3时的时间；开关薄膜晶体管SW(2)的开启时间为门限(gate)开启2/3时的时间，关闭为门限(gate)关闭的时间。从图中还可以看出，通过门信号输入端1G(n)分出来的第一个次级输出端3为G(n+1)，G(n+1)门信号的起止时间刚好为门信号输入端1G(n)往后推延其门限时间1/3，也就是说，通过开关薄膜晶体管SW(1)的在G(n)门限(gate)开启1/3时的时间开启，在G(n)开启2/3时的时间关闭，即可实现G(n+1)门信号；同样的，第二个次级输出端3为G(n+2)，G(n+2)门信号的起止时间刚好为门信号输入端1G(n)往后推延其门限时间2/3，通过开关薄膜晶体管SW(2)实现输出G(n+2)。
由于图4示出的实施例通过增设两个swich TFT实现，因此在第二级子电路10中，门信号输入端G(n+3)的门信号开启时间刚好为G(n)推延其一个门限的时间，持续时间则相同，以此类推G(n+4)及G(n+5)，图中还示出G(n+6)的波形图，门信号输入端G(n+6)的门信号开启时间刚好为G(n+3)推延其一个门限的时间，持续时间则相同，即实际中可根据情况进行拓展GOA子电路10，若只需要将GOA级数缩减一半，只需一个swich TFT即可；若需要将GOA缩减到1/4，则需要3个swich TFT，以此类推。
本发明提供的GOA DEMUX（demultiplexer-解复用器，门限分路器）电路，可以解决电路级数过多而造成空间利用不合理，从而不能实现窄边框的问题，经过门限分路器后，输出的gate 波形图与现有技术一致，因此在本发明在性能不变的情况下，将GOA电路级数降低为原来的N分之一，更加合理地利用GOA电路的面积。
此外，本发明还提供一种显示装置，包括如上所述的可减少GOA级数的电路。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (19)

  1. 一种可减少GOA级数的电路，其中，包括一至多级GOA子电路，每级所述GOA子电路均包括门信号输入端、原级输出端、一至多个次级输出端及一至多个分别与一至多个所述次级输出端对应的分路装置，所述分路装置为开关薄膜晶体管；
    所述门信号输入端及所述原级输出端分别连接于分路节点，一至多个所述分路装置的一端分别连接于所述分路节点，一至多个所述分路装置的另一端分别连接于一至多个分别与之对应的次级输出端，所述分路节点采用门限分路器实现，从而使门信号输入端的门信号分为多路输出门信号。
  2. 一种可减少GOA级数的电路，其中，包括一至多级GOA子电路，每级所述GOA子电路均包括门信号输入端、原级输出端、一至多个次级输出端及一至多个分别与一至多个所述次级输出端对应的分路装置；
    所述门信号输入端及所述原级输出端分别连接于分路节点，一至多个所述分路装置的一端分别连接于所述分路节点，一至多个所述分路装置的另一端分别连接于一至多个分别与之对应的次级输出端。
  3. 根据权利要求2所述的可减少GOA级数的电路，其中，所述分路装置为开关薄膜晶体管。
  4. 根据权利要求2所述的可减少GOA级数的电路，其中，所述分路节点采用门限分路器实现，从而使门信号输入端的门信号分为多路输出门信号。
  5. 根据权利要求2所述的可减少GOA级数的电路，其中，每级所述GOA子电路所包括一至多个所述次级输出端的个数为n，一至多个所述分路装置的个数为n，则一至多个所述次级输出端包括第1次级输出端、第2次级输出端、……第i次级输出端……第n次级输出端，一至多个所述分路装置包括第1分路装置、第2分路装置、……第i分路装置……第n分路装置。
  6. 根据权利要求5所述的可减少GOA级数的电路，其中，所述第i分路装置的开启时间为自身连接的门信号输入端的门限开启i/(n+1)的时间，所述第i分路装置的关闭时间为自身所连接的门信号输入端的门限开启(i+1)/(n+1)的时间，从而使第i次级输出端的门信号比自身连接的门信号输入端的门信号延迟一个自身门信号i/(n+1)的时间。
  7. 根据权利要求5所述的可减少GOA级数的电路，其中，第i+1分路装置的门信号比第i级分路装置的门信号延迟一个自身门信号1/(n+1)的时间。
  8. 根据权利要求2所述的可减少GOA级数的电路，其中，一至多级所述GOA子电路的级数为m，则一至多级所述GOA子电路包括第1级GOA子电路、第2级GOA子电路、……第j级GOA子电路……第m级GOA子电路。
  9. 根据权利要求8所述的可减少GOA级数的电路，其中，第j+1级GOA子电路的门信号输入端的门信号比第j级GOA子电路的门信号输入端的门信号延迟一个自身门信号的时间。
  10. 根据权利要求2所述的可减少GOA级数的电路，其中，所述门信号输入端的信号与所述原级输出端的信号相同。
  11. 一种显示装置，其中，所述显示装置包括可减少GOA级数的电路；所述可减少GOA级数的电路包括一至多级GOA子电路，每级所述GOA子电路均包括门信号输入端、原级输出端、一至多个次级输出端及一至多个分别与一至多个所述次级输出端对应的分路装置；
    所述门信号输入端及所述原级输出端分别连接于分路节点，一至多个所述分路装置的一端分别连接于所述分路节点，一至多个所述分路装置的另一端分别连接于一至多个分别与之对应的次级输出端。
  12. 根据权利要求1所述的显示装置，其中，所述分路装置为开关薄膜晶体管。
  13. 根据权利要求1所述的显示装置，其中，所述分路节点采用门限分路器实现，从而使门信号输入端的门信号分为多路输出门信号。
  14. 根据权利要求1所述的显示装置，其中，每级所述GOA子电路所包括一至多个所述次级输出端的个数为n，一至多个所述分路装置的个数为n，则一至多个所述次级输出端包括第1次级输出端、第2次级输出端、……第i次级输出端……第n次级输出端，一至多个所述分路装置包括第1分路装置、第2分路装置、……第i分路装置……第n分路装置。
  15. 根据权利要求4所述的显示装置，其中，所述第i分路装置的开启时间为自身连接的门信号输入端的门限开启i/(n+1)的时间，所述第i分路装置的关闭时间为自身所连接的门信号输入端的门限开启(i+1)/(n+1)的时间，从而使第i次级输出端的门信号比自身连接的门信号输入端的门信号延迟一个自身门信号i/(n+1)的时间。
  16. 根据权利要求4所述的显示装置，其中，第i+1分路装置的门信号比第i级分路装置的门信号延迟一个自身门信号1/(n+1)的时间。
  17. 根据权利要求1所述的显示装置，其中，一至多级所述GOA子电路的级数为m，则一至多级所述GOA子电路包括第1级GOA子电路、第2级GOA子电路、……第j级GOA子电路……第m级GOA子电路。
  18. 根据权利要求7所述的显示装置，其中，第j+1级GOA子电路的门信号输入端的门信号比第j级GOA子电路的门信号输入端的门信号延迟一个自身门信号的时间。
  19. 根据权利要求1所述的显示装置，其中，所述门信号输入端的信号与所述原级输出端的信号相同。
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