WO2020133654A1 - 阵列基板、显示面板以及显示面板的控制方法 - Google Patents

阵列基板、显示面板以及显示面板的控制方法 Download PDF

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Publication number
WO2020133654A1
WO2020133654A1 PCT/CN2019/075635 CN2019075635W WO2020133654A1 WO 2020133654 A1 WO2020133654 A1 WO 2020133654A1 CN 2019075635 W CN2019075635 W CN 2019075635W WO 2020133654 A1 WO2020133654 A1 WO 2020133654A1
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Prior art keywords
layer
film transistor
liquid crystal
thin film
ito
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Application number
PCT/CN2019/075635
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English (en)
French (fr)
Inventor
程薇
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武汉华星光电技术有限公司
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Priority to US16/476,089 priority Critical patent/US10739654B2/en
Publication of WO2020133654A1 publication Critical patent/WO2020133654A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1334—Constructional arrangements; Manufacturing methods based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1347—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

Definitions

  • Embodiments of the present application provide an array substrate, a display panel, and a display panel control method to improve the contrast of the display panel.
  • An array substrate including:
  • An array layer the array layer is disposed on the substrate layer, the array layer includes a plurality of first thin film transistors;
  • a flat layer, the flat layer is disposed on the array layer;
  • a first insulating layer, the first insulating layer is disposed on the flat layer;
  • a metal layer, the metal layer is disposed on the first insulating layer
  • a second insulating layer, the second insulating layer is located on the first insulating layer
  • a common electrode layer, the common electrode layer is located on the second insulating layer and electrically connected to the metal layer;
  • a passivation layer, the passivation layer is provided on the common electrode layer;
  • a first ITO layer is located on the passivation layer, the first ITO layer is electrically connected to the first source and drain of the first thin film transistor;
  • the array layer further includes a plurality of second thin film transistors, and a second ITO layer and a polymer dispersed liquid crystal layer are further provided on the first insulating layer and between the second insulating layer, and the second ITO A layer is provided on the first insulating layer, the polymer dispersed liquid crystal layer is provided on the second ITO layer, the second ITO layer is electrically connected to the second source and drain of the second thin film transistor, And it is electrically insulated from the first source and drain of the first thin film transistor.
  • the array substrate further includes a light-shielding layer, the light-shielding layer is disposed on the substrate layer, the light-shielding layer includes a plurality of light-shielding portions, and the light-shielding portion is located on the first Below a first source drain of a thin film transistor and a second source drain of the second thin film transistor.
  • the array substrate includes a first through hole, the first through hole passes through the passivation layer, the common electrode layer, the second insulating layer, the first insulating layer and In a flat layer, the first through hole is located above the first source and drain of the first thin film transistor.
  • the first ITO layer covers the surface of the passivation layer and the surface of the array substrate facing the first through hole, and the first ITO layer passes through a part or The first through hole is completely filled and electrically connected with the first source and drain of the first thin film transistor.
  • the array substrate includes a second through hole, the second through hole passes through the first insulating layer and the flat layer, and the second through hole is located in the Above the second source and drain of the second thin film transistor.
  • the second ITO layer covers part of the surface of the first insulating layer and the surface of the array substrate facing the second through hole, and the second ITO layer passes The second through hole is partially or completely filled and electrically connected to the second source and drain of the second thin film transistor.
  • the polymer dispersed liquid crystal layer includes a polymer matrix and liquid crystal molecules, and the liquid crystal molecules are dispersed in the polymer matrix.
  • a display panel including:
  • the array substrate includes:
  • An array layer the array layer is disposed on the substrate layer, the array layer includes a plurality of first thin film transistors;
  • a flat layer, the flat layer is disposed on the array layer;
  • a first insulating layer, the first insulating layer is disposed on the flat layer;
  • a metal layer, the metal layer is disposed on the first insulating layer
  • a second insulating layer, the second insulating layer is located on the first insulating layer
  • a common electrode layer, the common electrode layer is located on the second insulating layer and electrically connected to the metal layer;
  • a passivation layer, the passivation layer is provided on the common electrode layer;
  • a first ITO layer is located on the passivation layer, the first ITO layer is electrically connected to the first source and drain of the first thin film transistor;
  • the array layer further includes a plurality of second thin film transistors, and a second ITO layer and a polymer dispersed liquid crystal layer are further provided on the first insulating layer and between the second insulating layer, and the second ITO A layer is provided on the first insulating layer, the polymer dispersed liquid crystal layer is provided on the second ITO layer, the second ITO layer is electrically connected to the second source and drain of the second thin film transistor, And electrically insulated from the first source and drain of the first thin film transistor;
  • a color filter substrate, the color filter substrate is located on a side of the array substrate away from the substrate layer;
  • a liquid crystal portion the liquid crystal portion is located between the array substrate and the color filter substrate, the liquid crystal portion includes a plurality of liquid crystal cells, the polymer dispersed liquid crystal layer includes a plurality of polymer dispersed liquid crystal cells, each liquid crystal cell corresponds and covers One polymer dispersed liquid crystal cell, one liquid crystal cell and one corresponding polymer dispersed liquid crystal cell correspond to one sub-pixel.
  • the array substrate further includes a light-shielding layer, the light-shielding layer is disposed on the substrate layer, the light-shielding layer includes a plurality of light-shielding portions, and the light-shielding portions are located on the first Below a first source drain of a thin film transistor and a second source drain of the second thin film transistor.
  • the array substrate includes a first through hole, the first through hole passes through the passivation layer, the common electrode layer, the second insulating layer, the first insulating layer and In a flat layer, the first through hole is located above the first source and drain of the first thin film transistor.
  • the first ITO layer covers the surface of the passivation layer and the surface of the array substrate facing the first through hole, and the first ITO layer passes through a part or The first through hole is completely filled and electrically connected with the first source and drain of the first thin film transistor.
  • the array substrate includes a second through hole, the second through hole passes through the first insulating layer and the flat layer, and the second through hole is located Above the second source and drain of the second thin film transistor.
  • the second ITO layer covers part of the surface of the first insulating layer and the surface of the array substrate facing the second through hole, and the second ITO layer passes The second through hole is partially or completely filled and electrically connected to the second source and drain of the second thin film transistor.
  • the metal layer includes a plurality of metal lines, and the metal lines are located above the first source and drain of the first thin film transistor.
  • the polymer dispersed liquid crystal layer includes a polymer matrix and liquid crystal molecules, and the liquid crystal molecules are dispersed in the polymer matrix.
  • the color filter substrate further includes a third ITO layer, and the third ITO layer faces the liquid crystal portion.
  • the display panel further includes a backlight module, and the backlight module is disposed on a side of the array substrate away from the color filter substrate.
  • a control method of a display panel including:
  • the color filter substrate further includes a third ITO layer, and the third ITO layer faces the liquid crystal portion;
  • the first thin-film transistor and the second thin-film transistor corresponding to the sub-pixel are turned off.
  • the present application provides an array substrate, a display panel, and a display panel control method.
  • the array substrate includes a substrate layer, an array layer, a flat layer, a first insulating layer, a metal layer, a second insulating layer, a common electrode layer, a passivation layer, and a first ITO layer
  • the array layer includes a plurality of first thin film transistors And a plurality of second thin film transistors
  • the first ITO layer is electrically connected to the first source and drain of the first thin film transistor
  • the second ITO layer is electrically connected to the second source and drain of the second thin film transistor, and electrically insulated from the first source and drain of the first thin film transistor, so
  • the display panel includes the array substrate, the color filter substrate, and the liquid crystal portion.
  • the color filter substrate also includes a third ITO layer.
  • the corresponding sub-pixel is turned on.
  • the first thin-film transistor and the second thin-film transistor when any of the sub-pixels needs low-brightness display, turn on the first thin-film transistor corresponding to the sub-pixel, and turn off the second thin film corresponding to the sub-pixel A transistor, when any of the sub-pixels needs to be displayed in a dark state, the first thin-film transistor and the second thin-film transistor corresponding to the sub-pixel are turned off, so that each sub-pixel has high brightness, low brightness and dark
  • There are three display modes so without increasing the brightness of the backlight module, that is, without increasing the power consumption of the backlight module, the contrast of the display panel is improved.
  • FIG. 1 is a schematic structural diagram of a first implementation manner of an array substrate provided by this application.
  • FIG. 2 is a schematic structural diagram of a second implementation manner of an array substrate provided by this application.
  • FIG. 3 is a schematic structural diagram of a polymer-dispersed liquid crystal cell of a polymer-dispersed liquid crystal layer of an array substrate provided by this application.
  • FIG. 6 is a schematic structural diagram of a liquid crystal cell of a liquid crystal portion of a display panel provided by this application.
  • FIG. 7 is a schematic structural diagram of a first use state of a display panel provided by this application.
  • FIG. 8 is a schematic structural diagram of a second usage state of a display panel provided by this application.
  • FIG. 9 is a schematic structural diagram of a third usage state of the display panel provided by the present application.
  • the present application provides an array substrate 10.
  • the array substrate 10 includes a substrate layer 11, an array layer 12, a flat layer 13, a first insulating layer 14, a metal layer 15, a second insulating layer 16, a common electrode layer 17, a passivation layer 18, and a first ITO layer 19.
  • the substrate layer 11 may be a glass substrate or a substrate formed of organic materials.
  • the array substrate 10 further includes a light shielding layer 21.
  • the light shielding layer 21 is disposed on the substrate layer 11.
  • the light-shielding layer 21 includes a plurality of light-shielding portions 211.
  • the array layer 12 is disposed on the substrate layer 11.
  • the array layer 12 includes several first thin film transistors 121 and several second thin film transistors 122.
  • the first thin film transistor 121 has a first source and drain 1211.
  • the second thin film transistor 122 has a second source and drain 1221.
  • the light shielding layer 21 is located between the substrate layer 11 and the array layer 12.
  • the light shielding portion 211 is located below the first source and drain 1211 of the first thin film transistor 121 and the second source and drain 1221 of the second thin film transistor 122.
  • the flat layer 13 is disposed on the array layer 12.
  • the first insulating layer 14 is disposed on the flat layer 13.
  • the metal layer 15 is disposed on the first insulating layer 14.
  • the second insulating layer 16 is located on the first insulating layer 14.
  • the second insulating layer 16 covers the first insulating layer 14 and the metal layer 15.
  • the common electrode layer 17 is located on the second insulating layer 16 and is electrically connected to the metal layer 15.
  • the metal layer 15 includes several metal lines 151.
  • the metal line 151 is located above the first source and drain 1211 of the first thin film transistor 121 to reduce the shielding of light by the metal line 151.
  • the metal wire 151 may use copper.
  • the passivation layer 18 is disposed on the common electrode layer 17.
  • the first ITO layer 19 is located on the passivation layer 18.
  • the first ITO layer 19 is electrically connected to the first source and drain 1211 of the first thin film transistor 121.
  • the array substrate 10 includes a plurality of first through holes 10a.
  • Each of the first through holes 10 a passes through the passivation layer 18, the common electrode layer 17, the second insulating layer 16, the first insulating layer 14 and the flat layer 13.
  • Each of the first through holes 10 a is located above the first source and drain 1211 of the first thin film transistor 121.
  • the first ITO layer 19 covers the surface 18a of the passivation layer 18 and the surface 10a1 of the array substrate 10 facing the first through hole 10a.
  • the first ITO layer 19 is electrically connected to the first source and drain 1211 of the first thin film transistor 121 by partially or completely filling the first through hole 10a. Referring to FIG.
  • the first ITO layer 19 is partially filled in the first through hole 10 a, so that the first source and drain electrodes 1211 of the first thin film transistor 121 are electrically connected.
  • the first ITO layer 19 completely fills the first through hole 10 a, so that the first source and drain electrodes 1211 of the first thin film transistor 121 are electrically connected.
  • the upper surface 19a of the first ITO layer 19 is a flat surface.
  • a second ITO layer 22 and a polymer dispersed liquid crystal layer 23 are also provided between the first insulating layer 14 and the second insulating layer 16.
  • the second ITO layer 22 is disposed on the first insulating layer 14.
  • the polymer dispersed liquid crystal layer 23 is disposed on the second ITO layer 22.
  • the second ITO layer 22 is electrically connected to the second source and drain 1221 of the second thin film transistor 122 and electrically insulated from the first source and drain 1211 of the first thin film transistor 121.
  • the polymer dispersed liquid crystal layer 23 includes a polymer matrix 231 and liquid crystal molecules 232 dispersed in the polymer matrix 231.
  • the precursor of the polymer matrix 231 may be provided first, and then the liquid crystal molecules 232 are dispersed in the precursor, and then the precursor containing the liquid crystal molecules is set by spraying or inkjet printing, etc. On the second ITO layer 22, the polymer dispersed liquid crystal layer 23 is formed.
  • the array substrate 10 includes second through holes 10b.
  • the second through hole 10b passes through the first insulating layer 14 and the flat layer 13.
  • the second through hole 10b is located above the second source and drain 1221 of the second thin film transistor 122.
  • the second ITO layer 22 covers part of the surface 14a of the first insulating layer 14 and the surface 10b1 of the array substrate 10 facing the second through hole 10b.
  • the second ITO layer 22 is partially or completely filled
  • the second through hole 10b is electrically connected to the second source and drain 1221 of the second thin film transistor 122.
  • the present application also provides a display panel 30.
  • the display panel 30 includes the array substrate 10 as described above, and further includes a color filter substrate 31 and a liquid crystal portion 32.
  • the color filter substrate 31 is located on the side of the array substrate 10 away from the substrate layer 11.
  • the liquid crystal portion 32 is located between the array substrate 10 and the color filter substrate 31.
  • the liquid crystal portion 32 includes a plurality of liquid crystal cells 321.
  • the polymer dispersed liquid crystal layer 23 includes a plurality of polymer dispersed liquid crystal cells 23a. Each liquid crystal cell 321 corresponds to and covers one of the polymer dispersed liquid crystal cells 23a.
  • One liquid crystal cell 321 and one corresponding polymer dispersed liquid crystal cell 23a correspond to one sub-pixel 30a.
  • the color filter substrate 31 further includes a third ITO layer 311.
  • the third ITO layer 311 faces the liquid crystal portion 32.
  • the first thin film transistor 121 By turning on the first thin film transistor 121 to control the voltage generated between the first ITO layer 19 and the third ITO layer 311, the direction of the liquid crystal molecules of the liquid crystal portion 32 is rotated, so that light can pass through the liquid crystal ⁇ 32.
  • the first thin film transistor 121 By turning off the first thin film transistor 121 to control the voltage elimination between the first ITO layer 19 and the third ITO layer 311, the direction of the liquid crystal molecules of the liquid crystal portion 32 is restored, so that the liquid crystal portion 32 blocks light To prevent light from passing through the liquid crystal portion 32.
  • the second thin film transistor 122 By turning on the second thin film transistor 122 to control the voltage generated between the second ITO layer 22 and the common electrode layer 17, the direction of the liquid crystal molecules of the polymer dispersed liquid crystal layer 23 is rotated so that light can pass through ⁇ Polymer-dispersed liquid crystal layer 23.
  • the second thin film transistor 122 By turning off the second thin film transistor 122 to control the voltage elimination between the second ITO layer 22 and the common electrode layer 17, the direction of the liquid crystal molecules of the polymer dispersed liquid crystal layer 23 is restored, so that the polymer is dispersed
  • the liquid crystal layer 23 blocks light and prevents light from passing through the polymer dispersed liquid crystal layer 23.
  • the present application also provides a control method of the display panel 30.
  • the method includes:
  • A. Provide a display panel 30.
  • the display panel 30 is as described above and will not be repeated here.
  • the first thin film transistor 121 corresponding to the sub-pixel 30a is turned on to place the first ITO layer 19 and the third ITO layer A voltage is generated between 311 to deflect the direction of the liquid crystal molecules of the liquid crystal portion 32 to transmit light
  • the second thin film transistor 122 corresponding to the sub-pixel 30a is turned on between the second ITO layer 22 and the common electrode layer 17 A voltage is generated to deflect the direction of the liquid crystal molecules of the polymer dispersed liquid crystal layer 23 to transmit light.
  • the first thin film transistor 121 corresponding to the sub-pixel 30a is turned off to place the first ITO layer 19 and the third ITO layer
  • the voltage between 311 is eliminated to restore the direction of the liquid crystal molecules of the liquid crystal portion 32 to shield the light
  • the second thin film transistor 122 corresponding to the sub-pixel 30a is turned off to be between the second ITO layer 22 and the common electrode layer 17
  • the voltage is eliminated to restore the direction in which the liquid crystal molecules of the polymer dispersed liquid crystal layer 23 are shielded from light.
  • the present application provides an array substrate, a display panel, and a display panel control method.
  • the array substrate includes a substrate layer, an array layer, a flat layer, a first insulating layer, a metal layer, a second insulating layer, a common electrode layer, a passivation layer, and a first ITO layer
  • the array layer includes a plurality of first thin film transistors And a plurality of second thin film transistors
  • the first ITO layer is electrically connected to the first source and drain of the first thin film transistor
  • the second ITO layer is electrically connected to the second source and drain of the second thin film transistor, and electrically insulated from the first source and drain of the first thin film transistor, so
  • the display panel includes the array substrate, the color filter substrate, and the liquid crystal portion.
  • the color filter substrate also includes a third ITO layer.
  • the corresponding sub-pixel is turned on.
  • the first thin-film transistor and the second thin-film transistor when any of the sub-pixels needs low-brightness display, turn on the first thin-film transistor corresponding to the sub-pixel and turn off the second thin film corresponding to the sub-pixel A transistor, when any of the sub-pixels needs to be displayed in a dark state, the first thin-film transistor and the second thin-film transistor corresponding to the sub-pixel are turned off, so that each sub-pixel has high brightness, low brightness and dark
  • There are three display modes so without increasing the brightness of the backlight module, that is, without increasing the power consumption of the backlight module, the contrast of the display panel is improved.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Dispersion Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

一种阵列基板(10)，包括阵列层(12)、第一绝缘层(14)、第二绝缘层(16)和第一ITO层(19)，阵列层(12)包括第一薄膜晶体管(121)和第二薄膜晶体管(122)，第一ITO层(19)与第一薄膜晶体管(121)电连接，在第一绝缘层(14)上和第二绝缘层(16)之间还设置有第二ITO层(22)和聚合物分散液晶层(23)，第二ITO层(22)与第二薄膜晶体管(122)电连接、且与第一薄膜晶体管(121)电绝缘。

Description

阵列基板、显示面板以及显示面板的控制方法 技术领域
本申请涉及电子设备领域，具体涉及一种阵列基板、显示面板以及显示面板的控制方法。
 背景技术
在显示领域，高对比度一直以来是研究者的研究方向，目前，通常是通过提高亮度来改善对比度的，但是，对背光模组的亮度提升会使得整个显示面板电量的损耗增加，因此，如何在不提升背光模组的亮度的前提下，提供一种阵列基板、显示面板以及显示面板的控制方法以提升显示面板的对比度是目前亟待解决的问题。
 技术问题
本申请实施例提供一种阵列基板、显示面板以及显示面板的控制方法，以提升显示面板的对比度。
 技术解决方案
一种阵列基板，包括：
衬底层；
阵列层，所述阵列层设置于所述衬底层上，所述阵列层包括若干第一薄膜晶体管；
平坦层，所述平坦层设置于所述阵列层上；
第一绝缘层，所述第一绝缘层设置于所述平坦层上；
金属层，所述金属层设置于所述第一绝缘层上；
第二绝缘层，所述第二绝缘层位于所述第一绝缘层上；
公共电极层，所述公共电极层位于所述第二绝缘层上、并与所述金属层电连接；
钝化层，所述钝化层设置于所述公共电极层上；以及
第一ITO层，所述第一ITO层位于所述钝化层上，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接；
其中，所述阵列层还包括若干第二薄膜晶体管，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层设置于所述第一绝缘层上，所述聚合物分散液晶层设置于所述第二ITO层上，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘。
在本申请实施例所提供的阵列基板中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底层上，所述遮光层包括若干遮光部，所述遮光部位于所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二源漏极的下方。
在本申请实施例所提供的阵列基板中，所述阵列基板包括第一通孔，所述第一通孔穿过所述钝化层、公共电极层、第二绝缘层、第一绝缘层和平坦层，所述第一通孔位于所述第一薄膜晶体管的第一源漏极的上方。
在本申请实施例所提供的阵列基板中，所述第一ITO层覆盖所述钝化层的表面和所述阵列基板朝向所述第一通孔的表面，所述第一ITO层通过部分或者完全填充所述第一通孔与所述第一薄膜晶体管的第一源漏极电连接。
在本申请实施例所提供的阵列基板中，所述阵列基板包括第二通孔，所述第二通孔穿过所述第一绝缘层和所述平坦层，所述第二通孔位于所述第二薄膜晶体管的第二源漏极的上方。
在本申请实施例所提供的阵列基板中，所述第二ITO层覆盖部分所述第一绝缘层的表面和所述阵列基板朝向所述第二通孔的表面，所述第二ITO层通过部分或者完全填充所述第二通孔与所述第二薄膜晶体管的第二源漏极电连接。
在本申请实施例所提供的阵列基板中，所述金属层包括若干金属线，所述金属线位于所述第一薄膜晶体管的第一源漏极的上方。
在本申请实施例所提供的阵列基板中，所述聚合物分散液晶层包括聚合物基体和液晶分子，所述液晶分子分散于所述聚合物基体内。
一种显示面板，包括：
阵列基板，所述阵列基板包括：
衬底层；
阵列层，所述阵列层设置于所述衬底层上，所述阵列层包括若干第一薄膜晶体管；
平坦层，所述平坦层设置于所述阵列层上；
第一绝缘层，所述第一绝缘层设置于所述平坦层上；
金属层，所述金属层设置于所述第一绝缘层上；
第二绝缘层，所述第二绝缘层位于所述第一绝缘层上；
公共电极层，所述公共电极层位于所述第二绝缘层上、并与所述金属层电连接；
钝化层，所述钝化层设置于所述公共电极层上；以及
第一ITO层，所述第一ITO层位于所述钝化层上，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接；
其中，所述阵列层还包括若干第二薄膜晶体管，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层设置于所述第一绝缘层上，所述聚合物分散液晶层设置于所述第二ITO层上，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘；
彩膜基板，所述彩膜基板位于所述阵列基板远离所述衬底层的一侧；以及
液晶部，所述液晶部位于所述阵列基板和彩膜基板之间，所述液晶部包括若干液晶单元，所述聚合物分散液晶层包括若干聚合物分散液晶单元，每一液晶单元对应并覆盖一个所述聚合物分散液晶单元，一个液晶单元和一个与其所对应的聚合物分散液晶单元对应一个子像素。
在本申请实施例所提供的显示面板中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底层上，所述遮光层包括若干遮光部，所述遮光部位于所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二源漏极的下方。
在本申请实施例所提供的显示面板中，所述阵列基板包括第一通孔，所述第一通孔穿过所述钝化层、公共电极层、第二绝缘层、第一绝缘层和平坦层，所述第一通孔位于所述第一薄膜晶体管的第一源漏极的上方。
在本申请实施例所提供的显示面板中，所述第一ITO层覆盖所述钝化层的表面和所述阵列基板朝向所述第一通孔的表面，所述第一ITO层通过部分或者完全填充所述第一通孔与所述第一薄膜晶体管的第一源漏极电连接。
在本申请实施例所提供的显示面板中，所述阵列基板包括第二通孔，所述第二通孔穿过所述第一绝缘层和所述平坦层，所述第二通孔位于所述第二薄膜晶体管的第二源漏极的上方。
在本申请实施例所提供的显示面板中，所述第二ITO层覆盖部分所述第一绝缘层的表面和所述阵列基板朝向所述第二通孔的表面，所述第二ITO层通过部分或者完全填充所述第二通孔与所述第二薄膜晶体管的第二源漏极电连接。
在本申请实施例所提供的显示面板中，所述金属层包括若干金属线，所述金属线位于所述第一薄膜晶体管的第一源漏极的上方。
在本申请实施例所提供的显示面板中，所述聚合物分散液晶层包括聚合物基体和液晶分子，所述液晶分子分散于所述聚合物基体内。
在本申请实施例所提供的显示面板中，所述彩膜基板还包括第三ITO层，所述第三ITO层朝向所述液晶部。
在本申请实施例所提供的显示面板中，所述显示面板还包括背光模组，所述背光模组设置于所述阵列基板远离所述彩膜基板的一侧。
一种显示面板的控制方法，包括：
提供一如前所述的显示面板，所述彩膜基板还包括第三ITO层，所述第三ITO层朝向所述液晶部；
当任一所述子像素需要高亮显示时，开启所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管；
当任一所述子像素需要低亮显示时，开启所述子像素对应的所述第一薄膜晶体管，同时关闭所述子像素对应的所述第二薄膜晶体管；以及
当任一所述子像素需要暗态显示时，关闭所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管。
 有益效果
本申请提供了一种阵列基板、显示面板以及显示面板的控制方法。所述阵列基板包括衬底层、阵列层、平坦层、第一绝缘层、金属层、第二绝缘层、公共电极层、钝化层和第一ITO层，所述阵列层包括若干第一薄膜晶体管和若干第二薄膜晶体管，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘，所述显示面板包括所述阵列基板、彩膜基板和液晶部，所述彩膜基板还包括第三ITO层，当任一所述子像素需要高亮显示时，开启所述子像素对应的所述第一薄膜晶体管和第二薄膜晶体管，当任一所述子像素需要低亮显示时，开启所述子像素对应的所述第一薄膜晶体管，同时关闭所述子像素对应的所述第二薄膜晶体管，当任一所述子像素需要暗态显示时，关闭所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管，从而使得每一子像素具有高亮、低亮和暗态三种显示模式，因此，在不提升背光模组的亮度的前提下，也即在不增加背光模组的电量消耗的前提下，提升了显示面板的对比度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请所提供的阵列基板的第一种实施方式的结构示意图。
图2为本申请所提供的阵列基板的第二种实施方式的结构示意图。
图3为本申请所提供的阵列基板的聚合物分散液晶层的聚合物分散液晶单元结构示意图。
图4为本申请所提供的显示面板的第一种实施方式的结构示意图。
图5为本申请所提供的显示面板的第二种实施方式的结构示意图。
图6为本申请所提供的显示面板的液晶部的液晶单元的结构示意图。
图7为本申请所提供的显示面板的第一种使用状态的结构示意图。
图8为本申请所提供的显示面板的第二种使用状态的结构示意图。
图9为本申请所提供的显示面板的第三种使用状态的结构示意图。
 本发明的实施方式
请参阅图1，本申请提供一种阵列基板10。所述阵列基板10包括衬底层11、阵列层12、平坦层13、第一绝缘层14、金属层15、第二绝缘层16、公共电极层17、钝化层18和第一ITO层19。
所述衬底层11可以为玻璃基板，也可以为有机材料形成的基板。所述阵列基板10还包括遮光层21。所述遮光层21设置于所述衬底层11上。所述遮光层21包括若干遮光部211。所述阵列层12设置于所述衬底层11上。所述阵列层12包括若干第一薄膜晶体管121和若干第二薄膜晶体管122。所述第一薄膜晶体管121具有第一源漏极1211。所述第二薄膜晶体管122具有第二源漏极1221。所述遮光层21位于所述衬底层11和所述阵列层12之间。所述遮光部211位于所述第一薄膜晶体管121的第一源漏极1211和所述第二薄膜晶体管122的第二源漏极1221的下方。
所述平坦层13设置于所述阵列层12上。所述第一绝缘层14设置于所述平坦层13上。所述金属层15设置于所述第一绝缘层14上。所述第二绝缘层16位于所述第一绝缘层14上。所述第二绝缘层16覆盖所述第一绝缘层14和所述金属层15。所述公共电极层17位于所述第二绝缘层16上、并与所述金属层15电连接。所述金属层15包括若干金属线151。所述金属线151位于所述第一薄膜晶体管121的第一源漏极1211的上方，以减少所述金属线151对光线的遮挡。所述金属线151可以采用铜。所述钝化层18设置于所述公共电极层17上。所述第一ITO层19位于所述钝化层18上，所述第一ITO层19与所述第一薄膜晶体管121的第一源漏极1211电连接。
所述阵列基板10包括若干第一通孔10a。每一所述第一通孔10a穿过所述钝化层18、公共电极层17、第二绝缘层16、第一绝缘层14和平坦层13。每一所述第一通孔10a位于一个所述第一薄膜晶体管121的第一源漏极1211的上方。所述第一ITO层19覆盖所述钝化层18的表面18a和所述阵列基板10朝向所述第一通孔10a的表面10a1。所述第一ITO层19通过部分或者完全填充所述第一通孔10a与所述第一薄膜晶体管121的第一源漏极1211电连接。请参阅图1，所述第一ITO层19部分填充于所述第一通孔10a，以使得所述第一薄膜晶体管121的第一源漏极1211电连接。请参阅图2，所述第一ITO层19完全填充所述第一通孔10a，以使得所述第一薄膜晶体管121的第一源漏极1211电连接。所述第一ITO层19的上表面19a为一平坦表面。
在所述第一绝缘层14和所述第二绝缘层16之间还设置有第二ITO层22和聚合物分散液晶层23。所述第二ITO层22设置于所述第一绝缘层14上。所述聚合物分散液晶层23设置于所述第二ITO层22上。所述第二ITO层22与所述第二薄膜晶体管122的第二源漏极1221电连接、且与所述第一薄膜晶体管121的第一源漏极1211电绝缘。请参阅图3，所述聚合物分散液晶层23包括聚合物基体231和分散于所述聚合物基体231内的液晶分子232。在制备过程中，可以先提供所述聚合物基体231的前驱体，然后将液晶分子232分散于所述前驱体中，随后采用喷涂或者喷墨打印等方式，将包含有液晶分子的前驱体设置于所述第二ITO层22上，从而形成所述聚合物分散液晶层23。
所述阵列基板10包括第二通孔10b。所述第二通孔10b穿过所述第一绝缘层14和所述平坦层13。所述第二通孔10b位于所述第二薄膜晶体管122的第二源漏极1221的上方。所述第二ITO层22覆盖部分所述第一绝缘层14的表面14a和所述阵列基板10朝向所述第二通孔10b的表面10b1，所述第二ITO层22通过部分或者完全填充所述第二通孔10b与所述第二薄膜晶体管122的第二源漏极1221电连接。
请参阅图4，本申请还提供一种显示面板30。所述显示面板30包括如前所述的阵列基板10，还包括一彩膜基板31和一液晶部32。所述彩膜基板31位于所述阵列基板10远离所述衬底层11的一侧。所述液晶部32位于所述阵列基板10和彩膜基板31之间。请参阅图5，所述液晶部32包括若干液晶单元321。请参阅图3，所述聚合物分散液晶层23包括若干聚合物分散液晶单元23a。每一液晶单元321对应并覆盖一个所述聚合物分散液晶单元23a。一个液晶单元321和一个与其所对应的聚合物分散液晶单元23a对应一个子像素30a。
所述彩膜基板31还包括第三ITO层311。所述第三ITO层311朝向所述液晶部32。通过开启所述第一薄膜晶体管121以控制所述第一ITO层19和第三ITO层311之间产生电压，从而转动所述液晶部32的液晶分子的方向，使得光线可以透过所述液晶部32。通过关闭所述第一薄膜晶体管121以控制所述第一ITO层19和第三ITO层311之间消除电压，从而恢复所述液晶部32的液晶分子的方向，使得所述液晶部32遮挡光线，避免光线透过所述液晶部32。通过开启所述第二薄膜晶体管122以控制所述第二ITO层22和公共电极层17之间产生电压，从而转动所述聚合物分散液晶层23的液晶分子的方向，使得光线可以透过所述聚合物分散液晶层23。通过关闭所述第二薄膜晶体管122以控制所述第二ITO层22和公共电极层17之间消除电压，从而恢复所述聚合物分散液晶层23的液晶分子的方向，使得所述聚合物分散液晶层23遮挡光线，避免光线透过所述聚合物分散液晶层23。
请参阅图6，所述显示面板30还可以包括背光模组33。所述背光模组33作为所述显示面板30的光源。所述背光模组33可以设置于所述阵列基板10远离所述彩膜基板31的一侧。所述背光模组33还可以设置于所述彩膜基板31远离所述阵列基板10的一侧。
请参阅图7-9，本申请还提供一种显示面板30的控制方法。所述方法包括：
A、提供一显示面板30。
所述显示面板30如前所述，在此不再赘述。
B、当任一所述子像素30a需要高亮显示时，开启所述子像素30a对应的所述第一薄膜晶体管121和所述第二薄膜晶体管122。
请参阅图7，当任一所述子像素30a需要高亮显示时，开启所述子像素30a对应的所述第一薄膜晶体管121以在所述第一ITO层19和所述第三ITO层311之间产生电压以偏转液晶部32的液晶分子的方向以透光，同时开启所述子像素30a对应的所述第二薄膜晶体管122以在第二ITO层22和所述公共电极层17之间产生电压以偏转聚合物分散液晶层23的液晶分子的方向以透光。
C、当任一所述子像素30a需要低亮显示时，开启所述子像素30a对应的所述第一薄膜晶体管121，同时关闭所述子像素30a对应的所述第二薄膜晶体管122。
请参阅图8，当任一所述子像素30a需要低亮显示时，开启所述子像素30a对应的所述第一薄膜晶体管121以在所述第一ITO层19和所述第三ITO层311之间产生电压以偏转液晶部32的液晶分子的方向以透光，同时关闭所述子像素30a对应的所述第二薄膜晶体管122以在第二ITO层22和所述公共电极层17之间消除电压以恢复聚合物分散液晶层23的液晶分子的方向以遮光。
D、当任一所述子像素30a需要暗态显示时，关闭所述子像素30a对应的所述第一薄膜晶体管121和所述第二薄膜晶体管122。
请参阅图9，当任一所述子像素30a需要暗态显示时，关闭所述子像素30a对应的所述第一薄膜晶体管121以在所述第一ITO层19和所述第三ITO层311之间消除电压以恢复液晶部32的液晶分子的方向以遮光，同时关闭所述子像素30a对应的所述第二薄膜晶体管122以在第二ITO层22和所述公共电极层17之间消除电压以恢复聚合物分散液晶层23的液晶分子的方向以遮光。
本申请提供了一种阵列基板、显示面板以及显示面板的控制方法。所述阵列基板包括衬底层、阵列层、平坦层、第一绝缘层、金属层、第二绝缘层、公共电极层、钝化层和第一ITO层，所述阵列层包括若干第一薄膜晶体管和若干第二薄膜晶体管，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘，所述显示面板包括所述阵列基板、彩膜基板和液晶部，所述彩膜基板还包括第三ITO层，当任一所述子像素需要高亮显示时，开启所述子像素对应的所述第一薄膜晶体管和第二薄膜晶体管，当任一所述子像素需要低亮显示时，开启所述子像素对应的所述第一薄膜晶体管，同时关闭所述子像素对应的所述第二薄膜晶体管，当任一所述子像素需要暗态显示时，关闭所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管，从而使得每一子像素具有高亮、低亮和暗态三种显示模式，因此，在不提升背光模组的亮度的前提下，也即在不增加背光模组的电量消耗的前提下，提升了显示面板的对比度。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施例进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施例及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种阵列基板，其中，包括：
    衬底层；
    阵列层，所述阵列层设置于所述衬底层上，所述阵列层包括若干第一薄膜晶体管；
    平坦层，所述平坦层设置于所述阵列层上；
    第一绝缘层，所述第一绝缘层设置于所述平坦层上；
    金属层，所述金属层设置于所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层位于所述第一绝缘层上；
    公共电极层，所述公共电极层位于所述第二绝缘层上、并与所述金属层电连接；
    钝化层，所述钝化层设置于所述公共电极层上；以及
    第一ITO层，所述第一ITO层位于所述钝化层上，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接；
    其中，所述阵列层还包括若干第二薄膜晶体管，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层设置于所述第一绝缘层上，所述聚合物分散液晶层设置于所述第二ITO层上，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底层上，所述遮光层包括若干遮光部，所述遮光部位于所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二源漏极的下方。
  3. 如权利要求1所述的阵列基板，其中，所述阵列基板包括第一通孔，所述第一通孔穿过所述钝化层、公共电极层、第二绝缘层、第一绝缘层和平坦层，所述第一通孔位于所述第一薄膜晶体管的第一源漏极的上方。
  4. 如权利要求3所述的阵列基板，其中，所述第一ITO层覆盖所述钝化层的表面和所述阵列基板朝向所述第一通孔的表面，所述第一ITO层通过部分或者完全填充所述第一通孔与所述第一薄膜晶体管的第一源漏极电连接。
  5. 如权利要求1所述的阵列基板，其中，所述阵列基板包括第二通孔，所述第二通孔穿过所述第一绝缘层和所述平坦层，所述第二通孔位于所述第二薄膜晶体管的第二源漏极的上方。
  6. 如权利要求5所述的阵列基板，其中，所述第二ITO层覆盖部分所述第一绝缘层的表面和所述阵列基板朝向所述第二通孔的表面，所述第二ITO层通过部分或者完全填充所述第二通孔与所述第二薄膜晶体管的第二源漏极电连接。
  7. 如权利要求1所述的阵列基板，其中，所述金属层包括若干金属线，所述金属线位于所述第一薄膜晶体管的第一源漏极的上方。
  8. 如权利要求1所述的阵列基板，其中，所述聚合物分散液晶层包括聚合物基体和液晶分子，所述液晶分子分散于所述聚合物基体内。
  9. 一种显示面板，其中，包括：
    阵列基板，所述阵列基板包括：
    衬底层；
    阵列层，所述阵列层设置于所述衬底层上，所述阵列层包括若干第一薄膜晶体管；
    平坦层，所述平坦层设置于所述阵列层上；
    第一绝缘层，所述第一绝缘层设置于所述平坦层上；
    金属层，所述金属层设置于所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层位于所述第一绝缘层上；
    公共电极层，所述公共电极层位于所述第二绝缘层上、并与所述金属层电连接；
    钝化层，所述钝化层设置于所述公共电极层上；以及
    第一ITO层，所述第一ITO层位于所述钝化层上，所述第一ITO层与所述第一薄膜晶体管的第一源漏极电连接；
    其中，所述阵列层还包括若干第二薄膜晶体管，在所述第一绝缘层上和所述第二绝缘层之间还设置有第二ITO层和聚合物分散液晶层，所述第二ITO层设置于所述第一绝缘层上，所述聚合物分散液晶层设置于所述第二ITO层上，所述第二ITO层与所述第二薄膜晶体管的第二源漏极电连接、且与所述第一薄膜晶体管的第一源漏极电绝缘；
    彩膜基板，所述彩膜基板位于所述阵列基板远离所述衬底层的一侧；以及
    液晶部，所述液晶部位于所述阵列基板和彩膜基板之间，所述液晶部包括若干液晶单元，所述聚合物分散液晶层包括若干聚合物分散液晶单元，每一液晶单元对应并覆盖一个所述聚合物分散液晶单元，一个液晶单元和一个与其所对应的聚合物分散液晶单元对应一个子像素。
  10. 如权利要求9所述的显示面板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底层上，所述遮光层包括若干遮光部，所述遮光部位于所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二源漏极的下方。
  11. 如权利要求9所述的显示面板，其中，所述阵列基板包括第一通孔，所述第一通孔穿过所述钝化层、公共电极层、第二绝缘层、第一绝缘层和平坦层，所述第一通孔位于所述第一薄膜晶体管的第一源漏极的上方。
  12. 如权利要求9所述的显示面板，其中，所述第一ITO层覆盖所述钝化层的表面和所述阵列基板朝向所述第一通孔的表面，所述第一ITO层通过部分或者完全填充所述第一通孔与所述第一薄膜晶体管的第一源漏极电连接。
  13. 如权利要求9所述的显示面板，其中，所述阵列基板包括第二通孔，所述第二通孔穿过所述第一绝缘层和所述平坦层，所述第二通孔位于所述第二薄膜晶体管的第二源漏极的上方。
  14. 如权利要求13所述的显示面板，其中，所述第二ITO层覆盖部分所述第一绝缘层的表面和所述阵列基板朝向所述第二通孔的表面，所述第二ITO层通过部分或者完全填充所述第二通孔与所述第二薄膜晶体管的第二源漏极电连接。
  15. 如权利要求9所述的显示面板，其中，所述金属层包括若干金属线，所述金属线位于所述第一薄膜晶体管的第一源漏极的上方。
  16. 如权利要求10所述的显示面板，其中，所述聚合物分散液晶层包括聚合物基体和液晶分子，所述液晶分子分散于所述聚合物基体内。
  17. 如权利要求9所述的显示面板，其中，所述彩膜基板还包括第三ITO层，所述第三ITO层朝向所述液晶部。
  18. 如权利要求9所述的显示面板，其中，所述显示面板还包括背光模组，所述背光模组设置于所述阵列基板远离所述彩膜基板的一侧。
  19. 一种显示面板的控制方法，其中，包括：
    提供一如权利要求9所述的显示面板，所述彩膜基板还包括第三ITO层，所述第三ITO层朝向所述液晶部；
    当任一所述子像素需要高亮显示时，开启所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管；
    当任一所述子像素需要低亮显示时，开启所述子像素对应的所述第一薄膜晶体管，同时关闭所述子像素对应的所述第二薄膜晶体管；以及
    当任一所述子像素需要暗态显示时，关闭所述子像素对应的所述第一薄膜晶体管和所述第二薄膜晶体管。
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