WO2020098032A1 - 显示面板的制程方法、显示面板及显示装置 - Google Patents

显示面板的制程方法、显示面板及显示装置 Download PDF

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Publication number
WO2020098032A1
WO2020098032A1 PCT/CN2018/120482 CN2018120482W WO2020098032A1 WO 2020098032 A1 WO2020098032 A1 WO 2020098032A1 CN 2018120482 W CN2018120482 W CN 2018120482W WO 2020098032 A1 WO2020098032 A1 WO 2020098032A1
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Prior art keywords
light
shielding layer
substrate
line
layer
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PCT/CN2018/120482
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English (en)
French (fr)
Inventor
杨春辉
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惠科股份有限公司
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Priority to US17/042,841 priority Critical patent/US11561442B2/en
Publication of WO2020098032A1 publication Critical patent/WO2020098032A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present application relates to the field of display technology, and in particular, to a manufacturing method of a display panel, a display panel, and a display device.
  • Flat panel displays include thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal (TFT-LCD) and organic light-emitting diode (Organic Light-Emitting Diode, OLED) displays, etc.
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display controls the rotation direction of the liquid crystal molecules to refract the light from the backlight to produce a picture, which has many advantages such as a thin body, power saving, no radiation and so on.
  • the display panel of the display includes an array substrate and a color filter substrate.
  • the array substrate and the color filter substrate are prone to deviation from the cell during the cell alignment, resulting in light leakage.
  • the technical problem to be solved by the present application is to provide a manufacturing method of a display panel, a display panel and a display device to prevent light leakage of the display panel.
  • the present application provides a display panel formed with a display area and a peripheral area.
  • the display panel includes: a first substrate and a second substrate, the first substrate and the second substrate are provided to a box; a plurality of pixel units are provided On the first substrate; a plurality of data lines and scanning lines are provided on the first substrate between two adjacent pixel units; a plurality of color resisters are provided on the pixels corresponding to the first substrate Above the unit;
  • the first substrate includes a first light-shielding layer formed between two adjacent pixel units, which can block the data line or the scanning line;
  • the display area includes an opening Area and non-opening area, the first light-shielding layer is only provided in the non-opening area of the display area;
  • the second substrate includes a second light-shielding layer corresponding to the first light-shielding layer; each of the data The line and the scanning line are blocked by at least one of the first light-shielding layer and the second light-shielding layer.
  • the present application provides a first light-shielding layer on the first substrate, a second light-shielding layer on the second substrate, and the first light-shielding layer and the second The light shielding layer is provided correspondingly.
  • the first light shielding layer on the first substrate can shield the portion of the first substrate that needs to be shielded
  • the second light shielding layer on the second substrate can The portion of the second substrate that needs to be shielded is shielded from light, which can avoid light leakage caused by the deviation of the structure that needs to be shielded from the portion of the first substrate or the second substrate due to an error in the cell and the shielding layer.
  • FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel unit according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another pixel unit according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another pixel unit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of section A-A 'of an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a cross section of another display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a cross section of another display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a cross section of another display panel according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a cross section of another display panel according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a cross section of a thin film transistor switch according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a first substrate manufacturing method according to an embodiment of the present application.
  • FIG. 13 is a flowchart of a method for manufacturing a first substrate according to an embodiment of the present application.
  • FIG. 14 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
  • 16 is a schematic diagram of a cross section of another thin film transistor switch according to an embodiment of the present application.
  • Exemplary color resists are produced on the array substrate side (COA).
  • the COA array substrate has a first metal layer / amorphous silicon layer / second metal layer / passivation layer / red color resister / green color Eight processes of resist / blue color resist / flat layer / transparent conductive film:
  • the first metal layer is the first process: generating the gate and the common electrode line; the amorphous silicon layer is the second process: generating the semiconductor layer; the second metal layer is the third process: generating the source and drain;
  • the passivation layer is the fourth process: the protective layer of the second metal layer; the red, green, and blue color resists are the fifth, sixth, and seventh processes: the color resist layer; the transparent conductive film is the eighth process : Pixel electrode.
  • Eight masks are required.
  • the color filter substrate has two processes: black matrix layer and interstitial particles. Two masks are required.
  • the black matrix layer process of the color filter substrate functions to block the scattered light of the liquid crystal layer and prevent color mixing between sub-pixels. And prevent the ambient light from irradiating the TFT channel; shield the light leakage caused by the disorder of the liquid crystal guidance caused by the disturbance of the electric field near the data line and the scan line.
  • an embodiment of the present application discloses a display panel 110 including a first substrate 120 and a second substrate 140 disposed on a box with the first substrate 120; A plurality of pixel units 124 on the first substrate 120; a plurality of data lines 121 and scanning lines 221 disposed on the first substrate 120 between two adjacent pixel units 124; disposed above the pixel units 124 corresponding to the first substrate 120 A plurality of color resists 129; the first substrate 120 includes a first light-shielding layer 123; the display area 111 includes an opening area 113 and a non-opening area 114, and the first light-shielding layer 123 is formed between two adjacent pixel units 124 to block the data lines 121 or scan line 221, the first light-shielding layer 123 is only disposed in the non-opening area 114 of the display area 111; the second substrate 140 includes a second light-shielding layer 141 corresponding to the first light-shielding
  • the first substrate 120 is an array substrate on which the color resist 129 is provided on the array side, and the second substrate 140 is a common substrate; the pixel unit 124 and the corresponding color resist 129 together form a pixel.
  • the light shielding layer that blocks the data line 121 or the scanning line 221 may be all disposed on the second substrate 140. This design may cause misalignment when the first substrate 120 and the second substrate 140 are aligned with each other.
  • the light-shielding layer does not have the effect of blocking the data line 121 or the scanning line 221, thereby causing a problem of light leakage. For this problem, if only the light-shielding layer provided on the second substrate 140 is widened or lengthened, the display panel 110 is effective If the light transmission area is reduced, the light transmittance will be reduced, which will affect the display effect of the display panel 110.
  • the first A first light-shielding layer 123 is provided between two adjacent pixel electrodes 125 of the substrate 120, regardless of whether the first light-shielding layer 123 is corresponding to the data line 121 and the scanning line 221, since the first light-shielding layer 123 can Achieve a more accurate effect of blocking the data line 121 or the scanning line 221, which can improve the problem of light leakage when the first substrate 120 and the second substrate 140 are misaligned.
  • the first light-shielding layer 123 is also located adjacent to Between the two color resists, it can be the same layer as the color resist, or it can be a different layer from the color resist.
  • first light-shielding layer 123 and the color resist are in the same layer, they are located between two adjacent color resists. It can block the gap between the two color resists, it can also prevent the adjacent two color resists from mixing, and it can also make the color resist layer flat; when the first light-shielding layer 123 and the color resist different layers, it can play a role in blocking the two
  • the gap between the color resists prevents light leakage, and also provides a standing position for the support layer between the first substrate 120 and the second substrate 140.
  • Each data line 121 and scan line 221 are blocked by at least one of the first light-shielding layer 123 and the second light-shielding layer 141.
  • the present application provides a first light-shielding layer 123 on the first substrate 120, a second light-shielding layer 141 on the second substrate 140, and the first A light-shielding layer 123 and a second light-shielding layer 141 are provided correspondingly.
  • the first light-shielding layer 123 on the first substrate 120 can shield the portion of the first substrate 120 that needs to be shielded
  • the second light shielding layer 141 on the second substrate 140 can shield the portion of the second substrate 140 that needs to be shielded, which can avoid the structure and shielding of the portion of the first substrate 120 or the second substrate 140 that needs to be shielded due to the box error The light leakage caused by the shift of the layer.
  • the pixel unit 124 includes a first pixel unit 130 and a data line 121 disposed outside the first pixel unit 130; the first pixel unit 130 includes a first thin film transistor switch 138 and a first pixel electrode 131, And a first common electrode line 132 disposed outside the first pixel electrode 131, the first common electrode line 132 and the first pixel electrode 131 are on different layers and partially overlap; the first common electrode line 132 is disposed on the data line 121 On one side, a first gap 133 is provided between the first common electrode line 132 and the data line 121; the first pixel electrode 131 is via-connected to the source 151 or the drain 152 of the first thin film transistor switch 138; the first light-shielding layer 123 blocks the data line 121, the first gap 133, the first common electrode line 132, and extends beyond the edge of the first common electrode line 132 near the first pixel electrode 131.
  • the first pixel electrode 131 is formed of a transparent conductive film
  • the first thin film transistor switch 138 corresponds to the thin film transistor switch under the first pixel unit 130 in FIG. 2 and FIG. 3.
  • the first light-shielding layer 123 blocks the data line 121, the first gap 133, the first common electrode line 132, and extends beyond the edge of the first common electrode line 132 to the first pixel electrode 131, wherein the first common electrode line 132 Partial overlap between the first pixel electrode 131 and the first pixel electrode 131 will produce an electric field shielding effect.
  • the liquid crystal in the overlap area will not deflect, in order to avoid the overlapping area of the first common electrode line 132 and the first pixel electrode 131 Dark or bright lines appear on the display, and the overlapping area needs to be blocked by a light-shielding layer, so the first light-shielding layer 123 blocks the first common electrode line 132 and extends beyond the edge of the first common electrode line 132 to the first pixel electrode 131; the first The gap 133 is easily blocked by the misalignment of the first substrate 120 and the second substrate 140 to prevent light leakage. Therefore, the first light-shielding layer 123 blocks the first gap 133 between the first common electrode line 132 and the data line 121 , Can avoid the above problems.
  • the pixel unit 124 includes a second pixel unit 134 adjacent to the first pixel unit 130, the second pixel unit 134 includes a second pixel electrode 135, and the data line 121 is disposed between the first pixel electrode 131 and the second Between the pixel electrodes 135; the second pixel unit 134 further includes a line 136 disposed between the first pixel electrode 131 and the second pixel electrode 135, the second common electrode line 136 and the second pixel electrode 135 are on different layers, and part overlap;
  • the second common electrode line 136 is disposed on the side of the data line 121 away from the first common electrode line 132, and a second gap 137 is provided between the second common electrode line 136 and the data line 121; the first light shielding layer 123 also blocks the second The gap 137, the second common electrode line 136, and beyond the edge of the second common electrode line 136 close to the second pixel electrode 135.
  • the first common electrode line 132 and the second common electrode line 136 are respectively provided on both sides of the data line 121, and a first gap 133 is provided between the first common electrode line 132 and the data line 121, and the second common electrode line A second gap 137 is provided between the electrode line 136 and the data line 121.
  • the first light shielding layer 123 also blocks the second gap 137
  • the second common The electrode line 136 extends beyond the edge of the first common electrode line 132 near the first pixel electrode 131 and the edge of the second common electrode line 136 near the second pixel electrode 135. This design can effectively block the first pixel unit 130 and the first The position where the two pixel unit 134 may leak light and the position where display unevenness occurs due to electric field shielding or other reasons.
  • first common electrode line 132 and the second common electrode line 136 are a small section of the corresponding pixel unit 124 of the common electrode on the first substrate 120, and are connected to each other.
  • the first thin film transistor switch 138 includes a gate 150, a gate insulating layer 153, an amorphous silicon layer 154, a source 151 and a drain 152 provided in the same layer, and a first passivation layer 155;
  • the color resist 129 includes a first color resist 1291 formed over the first passivation layer 155; a first light-shielding layer 123 is formed at the gap between the first color resist 1291 and the adjacent color resist 129
  • the first pixel electrode 131 is formed above the first color resist 1291, and is partially stacked on the upper surface of the first light-shielding layer 123 near the first pixel electrode 131.
  • the first light-shielding layer 123 is provided at the gap between the first color resist 1291 and the adjacent color resist 129, and the common electrode is formed in the next process of the first light-shielding layer 123.
  • the first light-shielding layer 123 In addition to preventing light leakage, it can also serve as a flat layer, between flat pixel electrodes 125, and gaps between adjacent color resists 129.
  • the first pixel electrode 131 is partially stacked on the upper surface of the first light-shielding layer 123 near the first pixel electrode 131, which can ensure that the first pixel electrode 131 and the first common electrode partially overlap to generate a shielded electric field, improving the first pixel electrode 131 and The problem of uneven display brightness in the area close to the first common electrode.
  • the pixel unit 124 further includes a second pixel unit 134, and the second pixel unit 134 includes a second thin film transistor switch 139;
  • the second thin film transistor switch 139 includes a gate 150, a gate insulating layer 153, The crystalline silicon layer 154, the source electrode 151 and the drain electrode 152 provided in the same layer, and the second passivation layer 156;
  • the color resist 129 further includes a second color resist 1292; the second color resist 1292 is formed above the second passivation layer 156, and the first light-shielding layer 123 is formed at the gap between the first color resist 1291 and the second color resist 1292
  • the second pixel electrode 135 is formed above the second color resist 1292, and is partially stacked on the upper surface of the first light-shielding layer 123 near the second pixel electrode 135.
  • the second thin film transistor switch 139 corresponds to the thin film transistor switch under 2 or the second pixel unit 134 in FIG. 3.
  • the first light-shielding layer 123 is provided at the gap between the first color resist 1291 and the second color resist 1292, and the common electrode is formed in the next process of the first light-shielding layer 123.
  • it can also serve as a flat layer between flat pixel electrodes 125 and gaps between adjacent color resists 129.
  • the second pixel electrode 135 is partially stacked on the upper surface of the first light-shielding layer 123 near the second pixel electrode 135, which can ensure that the second pixel electrode 135 and the second common electrode partially overlap to generate a shielded electric field, improving the second pixel electrode 135 and The problem of uneven display brightness in the area near the second common electrode.
  • the first light-shielding layer 123 shields the data lines 121 and the scanning lines 221 in a one-to-one correspondence; the second light-shielding layer 141 and all data lines 121 and the scanning The lines 221 correspond to the shielding settings one by one; the first light shielding layer 123 and the second light shielding layer 141 are correspondingly disposed; the first light shielding layer 123 and the second light shielding layer 141 have the same shape and size.
  • the positions of the first light-shielding layer 123 and the second light-shielding layer 141 are correspondingly set, and all data lines 121 and scanning lines 221 can be double-shielded, which avoids the process of the first substrate 120 and the second substrate 140 in the box
  • the misalignment causes data lines 121 or scan lines 221 or other structures to be unblocked and leak light.
  • the first light-shielding layer 123 and the second light-shielding layer 141 have the same shape and size, and the same light mask can be used to prepare the first light-shielding layer 123 and the second light-shielding layer 141 under the advancement of the light-shielding effect, which reduces one mask and saves costs .
  • the first light-shielding layer 123 and the second light-shielding layer 141 generally require the same shape and size, but there may be differences in the manufacturing process, but even if there is a slight difference in shape and size, as long as the shape and size difference does not exceed the threshold, it is considered to be the same.
  • the difference from the above embodiment is that the data line 121 and the scanning line 221 are respectively provided corresponding to the pixel unit 124; the first light-shielding layer 123 blocks the first part of the data line 121 or the scanning line 221 therein; The two light shielding layers 141 block the second part of the data line 121 or the scanning line 221 therein; at least a part of the first part and the second part are different.
  • the data line 121 and the scanning line 221 are blocked by the first light-shielding layer 123 and / or the second light-shielding layer 141.
  • the first light-shielding layer 123 blocks the first part of the data line 121 or the scanning line 221.
  • the second light shielding layer 141 blocks the second part of the data line 121 or the scanning line 221 is one of the cases, and may also include a part of the data line 121 or the scanning line 221 is only blocked by the first light shielding layer 123, the other part of the data line 121 Or, the scan line 221 is only blocked by the second light shielding layer 141, and a part of the data line 121 or the scan line 221 is blocked by both light shielding layers at the same time.
  • This design can reduce the total area of the light-shielding layer and save raw materials.
  • the first substrate 120 is provided with multiple data lines 121 and scanning lines 221. The structure is complicated. If too many light-shielding layers are provided on the first substrate 120 The yield of the product, so the use of complementary occlusion methods can avoid the above drawbacks.
  • the first substrate 120 includes a plurality of pixel units 124, and the data lines 121 and the scanning lines 221 are respectively disposed corresponding to the pixel units 124.
  • the pixel units 124 include thin film transistor switches 126 connected to the scanning lines 221;
  • the second substrate 140 includes a second light shielding layer 141; the first light shielding layer 123 shields the data line 121; the second light shielding layer 141 shields the scanning line 221 and the thin film transistor switch 126.
  • the thin film transistor switch 126 is generally provided on the scanning line 221, and the width of the place where the thin film transistor switch 126 is provided may be the same as the width of the scanning line 221 or may be wider than the width of the scanning line 221; if the thin film transistor is provided When the width of the switch 126 is wider than that of the scan line 221, the second light-shielding layer 141 is widened corresponding to the scan line 221 to block the thin film transistor switch 126.
  • the light leakage at the data line 121 may be serious.
  • the structure in which the common electrode line is disposed between the pixel electrodes 125 has serious light leakage.
  • the first light-shielding layer 123 can effectively reduce light leakage.
  • the light leakage at the corresponding scan line 221 is slightly less, and due to the dense wiring on the array substrate side, additional structures may cause a decrease in product yield. Therefore, caution is required.
  • Unnecessary structures such as a light-shielding layer, are provided on the color film substrate side to improve Product yield; in this solution, the second light-shielding layer 141 can be disposed at the second substrate 140 to reduce the structure on the side of the first substrate 120 while ensuring good light leakage, thereby improving the display panel 110 Yield.
  • the material of the first light shielding layer is the same as the material of the second light shielding layer. In this scheme, the process is saved and time and effort are saved.
  • a manufacturing method of the display panel 110 including: S131: forming a first substrate of a first substrate;
  • S132 forming a thin film transistor switch excluding the pixel electrode on the first substrate; at the same time, forming a data line and a scanning line beside the thin film transistor switch;
  • S134 Form a pixel electrode and a first light-shielding layer to block the data line and / or the scanning line above the color resist, respectively, to obtain a first substrate;
  • S135 forming a second substrate that blocks the data line and the scanning line and the second light-shielding layer;
  • a method for manufacturing a display panel including: S141: forming a first substrate of a first substrate, forming a gate on the first substrate, The scanning line connected to the same layer as the gate and the common electrode line;
  • S143 forming a source electrode and a drain electrode arranged in the same layer above the amorphous silicon layer, and a data line connected to the source electrode or the drain electrode;
  • a method for manufacturing a display panel including: S151: referring to FIG. A in FIG. 12, on a first substrate Forming a gate, a scan line connected to the same layer as the gate, and a common electrode line;
  • S152 Referring to FIG. 12 in FIG. 12, forming a gate insulating layer and an amorphous silicon layer above the gate;
  • S153 Referring to FIG. 12 in FIG. 12, a source electrode and a drain electrode provided in the same layer are formed above the amorphous silicon layer, and a data line connected to the source electrode or the drain electrode is formed.
  • a passivation layer is formed over the source and drain, and a transparent conductive film partially overlapping with the common electrode line to obtain a thin film transistor switch;
  • a first light-shielding layer that blocks the data line and the scanning line is formed on the pixel electrode and between two adjacent color resists to obtain a first substrate;
  • the first light-shielding layer blocks the data line, the common electrode line, and the edge of the pixel electrode beyond the common electrode line, and does not cover the scan line;
  • the second light-shielding layer is formed between some color resists
  • the second light-shielding layer corresponds to the scanning line and blocks the scanning line.
  • the present application discloses a display device 100, including any of the above display panels 110.
  • TN panel Transmission Nematic, twisted nematic panel
  • IPS panel In-PaneSwitcing, plane conversion
  • VA panel Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology

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Abstract

一种显示面板的制程方法、显示面板（110）及显示装置，显示面板（110）包括：第一基板（120）和第二基板（140），第一基板（120）和第二基板（140）对盒设置；多个像素单元（124），设置在第一基板（120）上；多个数据线（121）和扫描线（221），设置在第一基板（120），相邻两个像素单元（124）之间；多个色阻（129），设置在第一基板（120）对应的像素单元（124）的上方；第一基板（120）包括形成在相邻两个像素单元（124）之间、用于遮挡数据线（121）或扫描线（221）的第一遮光层（123）；显示区（111）包括开口区（113）和非开口区（114），第一遮光层（123）仅设置在显示区（111）的非开口区（114）；第二基板（140）包括与第一遮光层（123）对应设置的第二遮光层（141）；每条数据线（121）和扫描线（221）至少被第一遮光层（123）和第二遮光层（141）中的一种所遮挡。该方案可以防止显示面板漏光、提高显示面板良率。

Description

显示面板的制程方法、显示面板及显示装置
本申请要求于2018年11月14日提交中国专利局，申请号为CN201811350597.7，申请名称为“一种显示面板的制程方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的制程方法、显示面板及显示装置。
背景技术
应当理解的是，这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光源的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。
显示器的显示面板包括阵列基板和彩膜基板，在显示面板的制造过程中，阵列基板和彩膜基板在对盒时中易产生对盒偏差，导致漏光现象。
发明内容
本申请所要解决的技术问题是提供了一种显示面板的制程方法、显示面板及显示装置，以防止显示面板漏光。
本申请提供了一种显示面板，形成有显示区和***区，显示面板包括：第一基板和第二基板，所述第一基板和所述第二基板对盒设置；多个像素单元，设置在所述第一基板上；多个数据线和扫描线，设置在所述第一基板，相邻两个像素单元之间；多个色阻，设置在所述第一基板对应的所述像素单元的上方；所述第一基板包括第一遮光层，所述第一遮光层形成在相邻两个所述像素单元之间，可以遮挡所述数据线或扫描线；所述显示区包括开口区和非开口区，所述第一遮光层仅设置在所述显示区的非开口区；所述第二基板包括与所述第一遮光层对应设置的第二遮光层；每条所述数据线和扫描线至少被所述第一遮光层和第二遮光层中的一种所遮挡。
相对于仅在第一基板或第二基板上设置遮光层的方案，本申请在第一基板上设置第一遮光层，在第二基板上设置第二遮光层，且第一遮光层和第二遮光层对应设置，在第一基板和 第二基板对盒时，第一基板上的第一遮光层可以对第一基板上需要遮光的部分遮光，第二基板上的第二遮光层可以对第二基板上需要遮光的部分遮光，可以避免因对盒误差使第一基板或第二基板上的部分需要遮光的结构与遮光层发生偏移产生的漏光。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示装置的示意图；
图2是本申请实施例一种显示面板的截面示意图；
图3是本申请实施例一种像素单元的示意图；
图4是本申请实施例另一种像素单元的示意图；
图5是本申请实施例另一种像素单元的示意图；
图6是本申请实施例截面A-A’的示意图；
图7是本申请实施例另一种显示面板的截面的示意图；
图8是本申请实施例另一种显示面板的截面的示意图；
图9是本申请实施例另一种显示面板的截面的示意图；
图10是本申请实施例另一种显示面板的截面的示意图；
图11是本申请实施例一种薄膜电晶体开关的截面的示意图；
图12是本申请实施例一种第一基板制程方法的示意图；
图13是本申请实施例一种第一基板制程方法的流程图；
图14是本申请实施例一种显示面板制程方法的流程图；
图15是本申请实施例另一种显示面板制程方法的流程图；
图16是本申请实施例另一种薄膜电晶体开关的截面的示意图。
具体实施方式
范例性的色阻做在阵列基板侧(color on array，COA)的生产过程，COA阵列基板有第一金属层/非晶硅层/第二金属层/钝化层/红色色阻/绿色色阻/蓝色色阻/平坦层/透明导电薄膜八道制程：
第一金属层为第一道制程：产生栅极及公共电极线；非晶硅层为第二道制程：产生半导体层；第二金属层为第三道制程：产生有源极和漏极；钝化层为第四道制程：第二金属层的 保护层；红色色阻/绿色色阻/蓝色色阻为第五、六、七制程：为色阻层；透明导电薄膜为第八道制程：为像素电极。需要八道光罩，彩膜基板有黑色矩阵层和间隙粒子两道制程，需要两道光罩，其中彩膜基板的黑色矩阵层制程的作用为：遮挡液晶层杂乱散射光，防止亚像素之间混色和防止环境光照射到TFT沟道；遮蔽由于数据线与扫描线附近电场紊乱导致的液晶导向紊乱所引起的漏光。
但在实际生产制程中，特别是阵列基板和彩膜基板对盒组立过程中极易导致黑色矩阵层与阵列基板上的公共电极的错位，进而导致公共电极与数据线之间漏光，这对产品良率的提升有极大影响。增大黑色矩阵层的宽度，固然可以起到作用，但对产品穿透率有副作用。为了在保证穿透率的前提下，迫切需要新的像素架构设计。
下面参考附图和实施例对本申请作说明。
如图2至图11和图16所示，本申请实施例公布了一种显示面板110，包括第一基板120和与第一基板120对盒设置的第二基板140；设置在第一基板120上的多个像素单元124；设置在第一基板120上、相邻两个像素单元124之间的多个数据线121和扫描线221；设置在第一基板120对应的像素单元124的上方的多个色阻129；第一基板120包括第一遮光层123；显示区111包括开口区113和非开口区114，第一遮光层123形成在相邻两个像素单元124之间、遮挡数据线121或扫描线221，第一遮光层123仅设置在显示区111的非开口区114；第二基板140包括与第一遮光层123对应设置的第二遮光层141；每条数据线121和扫描线221至少被第一遮光层123和第二遮光层141中的一种所遮挡。
具体的，第一基板120为色阻129设在阵列侧的阵列基板，第二基板140为公共基板；像素单元124和对应的色阻129共同组成像素。
示例性的方案，该遮挡数据线121或扫描线221的遮光层可能全部设置在第二基板140上，这种设计可能会在第一基板120和第二基板140对盒时，由于错位而使得遮光层没有起到遮挡数据线121或扫描线221的效果，从而出现漏光的问题，针对该问题若仅仅是将设置在第二基板140上的遮光层加宽或加长，则显示面板110的有效透光面积将减小，则光透过率也就减小，会影响到显示面板110的显示效果；本方案中，不仅在第二基板140侧设置有第二遮光层141，还在第一基板120的相邻的两个像素电极125之间设有第一遮光层123，无论该第一遮光层123是否与数据线121和扫描线221一一对应设置，由于该第一遮光层123可以达到较为精准的遮挡数据线121或扫描线221的效果，因而可以改善当第一基板120和第二基板140错位时，漏光的问题，除此之外，第一遮光层123还位于相邻的两个色阻的之间，可以是和色阻同一层，还可以与色阻不同层，第一遮光层123和色阻同层时，则是位于相邻的两个色阻之间，既可以遮挡两个色阻之间的间隙，也可以防止相邻的两个色阻发生混色，还可以使色阻层平坦化；第一遮光层123和色阻不同层时，能起到遮挡两个色阻之间 的间隙防止漏光的作用，还能为第一基板120和第二基板140之间的支撑层提供站立的位置。
其中，每条数据线121和扫描线221至少被第一遮光层123和第二遮光层141中的一种所遮挡包括三种情况，其一是所有的数据线121或扫描线221同时被两种遮光层遮挡；其二是，一部分数据线121或扫描线221被第一遮光层123遮挡，另一部分被第二遮光层141遮挡；其三是，一部分数据线121或扫描线221被第一遮光层123遮挡，另一部分被第二遮光层141遮挡，还一部分被两种遮光层遮挡，每条数据线121和扫描线221至少被第一遮光层123和第二遮光层141中的一种所遮挡即可。
相对于仅在第一基板120或第二基板140上设置遮光层的方案，本申请在第一基板120上设置第一遮光层123，在第二基板140上设置第二遮光层141，且第一遮光层123和第二遮光层141对应设置，在第一基板120和第二基板140对盒时，第一基板120上的第一遮光层123可以对第一基板120上需要遮光的部分遮光，第二基板140上的第二遮光层141可以对第二基板140上需要遮光的部分遮光，可以避免因对盒误差使第一基板120或第二基板140上的部分需要遮光的结构与遮光层发生偏移产生的漏光。
在一实施例中，像素单元124包括第一像素单元130、以及设置在第一像素单元130外侧的数据线121；第一像素单元130包括第一薄膜电晶体开关138、第一像素电极131，以及设置在第一像素电极131外侧的第一公共电极线132，第一公共电极线132与第一像素电极131在不同层、且部分交叠；第一公共电极线132设置在数据线121的一侧，第一公共电极线132和数据线121之间设置第一间隙133；第一像素电极131与第一薄膜电晶体开关138的源极151或漏极152过孔连接；第一遮光层123遮挡数据线121、第一间隙133、第一公共电极线132，并超出第一公共电极线132靠近第一像素电极131的边缘。
具体的，第一像素电极131由透明导电薄膜形成，第一薄膜电晶体开关138对应2和图3图中第一像素单元130下方的薄膜电晶体开关。
本方案中，第一遮光层123遮挡数据线121、第一间隙133、第一公共电极线132，并超出第一公共电极线132靠近第一像素电极131的边缘，其中第一公共电极线132与第一像素电极131在不同层且部分交叠会产生电场屏蔽效应，对应的，该交叠区域的液晶不会发生偏转，为避免第一公共电极线132与第一像素电极131交叠区显示出现暗纹或亮纹，该交叠区需要用遮光层遮挡，故第一遮光层123遮挡第一公共电极线132并超出第一公共电极线132靠近第一像素电极131的边缘；第一间隙133易因第一基板120和第二基板140对盒错位而遮挡不到出现漏光的问题，因此，第一遮光层123遮挡第一公共电极线132和数据线121之间的第一间隙133，可以避免上述问题出现。
在一实施例中，像素单元124包括与第一像素单元130相邻的第二像素单元134，第二像素单元134包括第二像素电极135，数据线121设置在第一像素电极131和第二像素电极 135之间；第二像素单元134还包括设置在第一像素电极131和第二像素电极135之间的线136，第二公共电极线136与第二像素电极135在不同层、且部分交叠；
第二公共电极线136设置在数据线121远离第一公共电极线132的一侧，第二公共电极线136和数据线121之间设置有第二间隙137；第一遮光层123还遮挡第二间隙137、第二公共电极线136，并超出第二公共电极线136靠近第二像素电极135的边缘。
本方案中，第一公共电极线132和第二公共电极线136分别设在数据线121的两侧，且第一公共电极线132和数据线121之间设置有第一间隙133，第二公共电极线136和数据线121之间设置有第二间隙137，第一遮光层123除了遮挡第一间隙133、数据线121、第一公共电极线132外，还遮挡第二间隙137、第二公共电极线136，并分别超出第一公共电极线132靠近第一像素电极131的边缘和第二公共电极线136靠近第二像素电极135的边缘，该设计可以有效的遮挡第一像素单元130和第二像素单元134的可能漏光的位置以及因电场屏蔽或其他原因出现显示不均的位置。
具体的，第一公共电极线132和第二公共电极线136是第一基板120上的公共电极的对应像素单元124的一小段，互相是连通的。
在一实施例中，第一薄膜电晶体开关138包括栅极150、栅极绝缘层153、非晶硅层154、同层设置的源极151和漏极152，以及第一钝化层155；色阻129包括第一色阻1291，第一色阻1291形成在第一钝化层155的上方；第一遮光层123形成在第一色阻1291和相邻的色阻129之间的间隙处；第一像素电极131形成在第一色阻1291上方，并部分堆叠在第一遮光层123靠近第一像素电极131的上表面。
本方案中，第一遮光层123设置第一色阻1291和相邻的色阻129之间的间隙处，公共电极在第一遮光层123的下一制程形成，如此，该第一遮光层123除了防止漏光之外，还可以作为平坦层，平坦像素电极125之间，以及相邻色阻129之间的间隙处。另外，第一像素电极131部分堆叠在第一遮光层123靠近第一像素电极131的上表面，可以保证第一像素电极131和第一公共电极部分重合产生屏蔽电场，改善第一像素电极131和第一公共电极靠近的区域的显示亮度不均的问题。
在一实施例中，像素单元124还包括第二像素单元134，第二像素单元134包括第二薄膜电晶体开关139；第二薄膜电晶体开关139包括栅极150、栅极绝缘层153、非晶硅层154、同层设置的源极151和漏极152，以及第二钝化层156；
色阻129还包括第二色阻1292；第二色阻1292形成在第二钝化层156的上方，第一遮光层123形成在第一色阻1291和第二色阻1292之间的间隙处；第二像素电极135形成在第二色阻1292上方，并部分堆叠在第一遮光层123靠近第二像素电极135的上表面。
具体的，第二薄膜电晶体开关139对应2或图3图中第二像素单元134下方的薄膜电晶 体开关。
本方案中，第一遮光层123设置第一色阻1291和第二色阻1292之间的间隙处，公共电极在第一遮光层123的下一制程形成，如此，该第一遮光层123除了防止漏光之外，还可以作为平坦层，平坦像素电极125之间，以及相邻色阻129之间的间隙处。另外，第二像素电极135部分堆叠在第一遮光层123靠近第二像素电极135的上表面，可以保证第二像素电极135和第二公共电极部分重合产生屏蔽电场，改善第二像素电极135和第二公共电极靠近的区域的显示亮度不均的问题。
作为本申请的另一实施例，与上述实施例不同在于，第一遮光层123与所有的数据线121和扫描线221一一对应遮挡设置；第二遮光层141与所有的数据线121和扫描线221一一对应遮挡设置；第一遮光层123和第二遮光层141对应设置；第一遮光层123和第二遮光层141的形状及尺寸相同。
本方案中，第一遮光层123和第二遮光层141的位置对应设置，可以对所有的数据线121和扫描线221双重遮挡，避免了第一基板120和第二基板140对盒过程中发生错位引起数据线121或扫描线221或其他结构没有被挡住而漏光。
第一遮光层123和第二遮光层141的形状大小一致，在保证遮光作用的提前下还能共用同一光罩制备第一遮光层123和第二遮光层141，减少一个光罩，节省了成本。设计时第一遮光层123和第二遮光层141一般要求形状大小一致，但制程中可能会存在差异，但即便形状大小有少许差异，只要形状大小差异不超出阈值，则认为相同。
作为本申请的另一实施例，与上述实施例不同在于，数据线121和扫描线221分别与像素单元124对应设置；第一遮光层123遮挡其中的第一部分数据线121或扫描线221；第二遮光层141遮挡其中的第二部分的数据线121或扫描线221；第一部分和第二部分至少有一部分不同。
本方案中，数据线121和扫描线221被第一遮光层123和/或第二遮光层141遮挡包括多种情况；第一遮光层123遮挡其中的第一部分数据线121或扫描线221，第二遮光层141遮挡其中的第二部分的数据线121或扫描线221是其中一种情况，还可以包括其中一部分数据线121或扫描线221仅被第一遮光层123遮挡，另一部分数据线121或扫描线221仅被第二遮光层141，还一部分数据线121或扫描线221同时被两种遮光层遮挡的情况。该设计可以减少遮光层的总面积，节省原料，且第一基板120上设有多条数据线121和扫描线221，结构复杂，若再第一基板120上再设置太多的遮光层会降低产品的良率，故采用互补的遮挡方法可以避免以上弊端。
在一实施例中，第一基板120包括多个像素单元124，数据线121和扫描线221，分别与像素单元124对应设置，像素单元124包括与扫描线221连接的薄膜电晶体开关126；第 二基板140包括第二遮光层141；第一遮光层123遮挡数据线121；第二遮光层141遮挡扫描线221和薄膜电晶体开关126。
具体的，薄膜电晶体开关126一般设置在扫描线221上，设置薄膜电晶体开关126的地方的宽度可能与扫描线221的宽度一致，也可能宽于扫描线221的宽度；若设置薄膜电晶体开关126的地方的宽度宽于扫描线221的宽度时，则第二遮光层141对应扫描线221处进行加宽以遮挡薄膜电晶体开关126。
本方案中，数据线121处的漏光情况可能较为严重，特别是公共电极线设置在像素电极125之间的架构漏光严重，在此设置第一遮光层123，可以有效减少漏光。对应扫描线221处漏光情况稍少，而由于阵列基板侧布线密集，额外增加结构可能引起产品良率降低问题故而需谨慎，不必要的结构，比如遮光层，设置在彩膜基板侧有利于提高产品良率；本方案，则可以将第二遮光层141设置在第二基板140处，以在保证较好的防漏光的情况下，减少第一基板120侧的结构，从而提高显示面板110的良率。
在一实施例中，第一遮光层的材料与第二遮光层的材料相同。本方案中，节省制程，省时省力。
作为本申请的另一实施例，参考图13所示，公开了一种显示面板110的制程方法，包括：S131：形成第一基板的第一基底；
S132：在第一基底上形成不包括像素电极的薄膜电晶体开关；同时，在薄膜电晶体开关旁形成数据线和扫描线；
S133：在薄膜电晶体开关的上方形成色阻；
S134：在色阻的上方分别形成像素电极，以及遮挡数据线和/或扫描线的第一遮光层，得到第一基板；
S135：形成遮挡数据线和扫描线和第二遮光层的第二基板；
S136：对盒固定第一基板和第二基板，使得第二遮光层对应遮挡数据线和扫描线。
作为本申请的另一实施例，参考图11和图14所示，公开了一种显示面板的制程方法，包括：S141：形成第一基板的第一基底，在第一基底上形成栅极、与栅极同层且连接的扫描线，以及公共电极线；
S142：在栅极上方形成栅极绝缘层、非晶硅层；
S143：在非晶硅层的上方形成同层设置的源极和漏极，以及与源极或漏极连接的数据线；
S144：在源极和漏极上方形成钝化层，以及与公共电极线部分交叠的透明导电薄膜得到薄膜电晶体开关；
S145：在薄膜电晶体开关的上方形成色阻；
S146：在相邻的两个色阻之间形成遮挡数据线和扫描线的第一遮光层；
S147：在色阻和第一遮光层上形成像素电极得到第一基板；
S148：形成遮挡数据线和扫描线和第二遮光层的第二基板；
S149：对盒固定第一基板和第二基板，使得第二遮光层对应遮挡数据线和扫描线221。
作为本申请的另一实施例，参考图11、图12和图15所示，公开了一种显示面板的制程方法，包括：S151：参考图12中的图a所示，在第一基底上形成栅极、与栅极同层且连接的扫描线，以及公共电极线；
S152：参考图12中的图b所示，在栅极上方形成栅极绝缘层、非晶硅层；
S153：参考图12中的图c所示，在非晶硅层的上方形成同层设置的源极和漏极，以及与源极或漏极连接的数据线；
S154：参考图12中的图d所示，在源极和漏极上方形成钝化层，以及与公共电极线部分交叠的透明导电薄膜得到薄膜电晶体开关；
S155：参考图12中的图e所示，在薄膜电晶体开关的上方形成色阻；
S156：参考图12中的图f所示，在色阻上形成像素电极；
S157：参考图12中的图g所示，在像素电极上，且在相邻的两个色阻之间形成遮挡数据线和扫描线的第一遮光层得到第一基板；
S158：形成遮挡数据线和扫描线和第二遮光层的第二基板；
S159：对盒固定第一基板和第二基板，使得第二遮光层对应遮挡数据线和扫描线。
作为本申请的另一实施例，与上述实施例不同在于，第一遮光层遮挡数据线、公共电极线，以及超出公共电极线靠近像素电极的边缘，不遮扫描线；
第二遮光层，形成在部分色阻之间；
对盒时，使得第二遮光层与扫描线对应，遮挡扫描线。
作为本申请的另一实施例，参考图1所示，本申请公开了一种显示装置100，包括以上***示面板110。
需要说明的是，本申请中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本申请，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛TN面板(Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PaneSwitcing，平面转换)、VA面板(Multi-domain Vertica Aignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，形成有显示区和***区，包括：
    第一基板；
    第二基板，与所述第一基板对盒设置；
    多个像素单元，设置在所述第一基板上；
    多个数据线和扫描线，设置在所述第一基板上，相邻两个像素单元之间；
    多个色阻，设置在所述第一基板对应的所述像素单元的上方；
    所述第一基板包括第一遮光层；所述第一遮光层形成在相邻两个所述像素单元之间，可以遮挡所述数据线或扫描线；
    所述显示区包括开口区和非开口区，所述第一遮光层仅设置在所述非开口区；
    所述第二基板包括与所述第一遮光层对应设置的第二遮光层；
    每条所述数据线和扫描线至少被所述第一遮光层和所述第二遮光层中的一种所遮挡。
  2. 如权利要求1所述的一种显示面板，其中，所述像素单元包括第一像素单元，以及设置在所述第一像素单元外侧的所述数据线；
    所述第一像素单元包括第一薄膜电晶体开关、第一像素电极，以及设置在第一像素电极外侧的第一公共电极线，所述第一公共电极线与所述第一像素电极在不同层、且部分交叠；
    所述第一公共电极线设置在所述数据线的一侧，所述第一公共电极线和所述数据线之间设置第一间隙；
    所述第一像素电极与所述第一薄膜电晶体开关的源极或漏极过孔连接；
    所述第一遮光层遮挡所述数据线、第一间隙和第一公共电极线，并超出所述第一公共电极线靠近所述第一像素电极的边缘。
  3. 如权利要求2所述的一种显示面板，其中，所述像素单元包括与所述第一像素单元相邻的第二像素单元，所述第二像素单元包括第二像素电极，所述数据线设置在所述第一像素电极和第二像素电极之间；
    所述第二像素单元还包括设置在所述第一像素电极和第二像素电极之间的第二公共电极线，所述第二公共电极线与所述第二像素电极在不同层、且部分交叠；
    所述第二公共电极线设置在所述数据线远离所述第一公共电极线的一侧，所述第二公共电极线和数据线之间设置有第二间隙；
    所述第一遮光层还遮挡所述第二间隙、第二公共电极线，并超出所述第二公共电极线靠近所述第二像素电极的边缘。
  4. 如权利要求1所述的一种显示面板，其中，第一基板为色阻设在阵列基板,第二基板为公共基板。
  5. 如权利要求1所述的一种显示面板，其中，所述第一遮光层和所述第二遮光层的材质相同。
  6. 如权利要求2所述的一种显示面板，其中，所述第一像素电极由透明导电薄膜形成。
  7. 如权利要求2所述的一种显示面板，其中，所述第一薄膜电晶体开关对应第一像素单元下方的薄膜电晶体开关。
  8. 如权利要求2所述的一种显示面板，其中，所述像素单元和对应的所述色阻组成像素。
  9. 如权利要求3所述的一种显示面板，其中，所述第一公共电极线和所述第二公共电极线是所述第一基板上的公共电极的对应像素单元的一小段，互相是连通的。
  10. 如权利要求3所述的一种显示面板，其中，所述第一薄膜电晶体开关包括栅极、栅极绝缘层、非晶硅层、同层设置的源极和漏极，以及第一钝化层；
    所述色阻包括第一色阻，所述第一色阻形成在所述第一钝化层的上方；
    所述第一遮光层形成在所述第一色阻和相邻的色阻之间的间隙处；
    所述第一像素电极形成在所述第一色阻上方，并部分堆叠在所述第一遮光层靠近第一像素电极的上表面。
  11. 如权利要求10所述的一种显示面板，其中，所述第二像素单元包括第二薄膜电晶体开关；
    所述第二薄膜电晶体开关包括栅极、栅极绝缘层、非晶硅层、同层设置的源极和漏极，以及第二钝化层；
    所述色阻还包括第二色阻；
    所述第二色阻形成在所述第二钝化层的上方，所述第一遮光层形成在所述第一色阻和第二色阻之间的间隙处；
    所述第二像素电极形成在所述第二色阻上方，并部分堆叠在所述第一遮光层靠近第二像素电极的上表面。
  12. 如权利要求1所述的一种显示面板，其中，所述第一遮光层与所有的所述数据线和扫描线一一对应遮挡设置；所述第二遮光层与所有的所述数据线和扫描线一一对应遮挡设置；
    所述第一遮光层和第二遮光层对应设置；
    所述第一遮光层和第二遮光层的形状及尺寸相同。
  13. 如权利要求1所述的一种显示面板，其中，所述数据线和扫描线分别与所述像素单元对应设置；
    所述第一遮光层遮挡其中的第一部分所述数据线；
    所述第二遮光层遮挡其中的第二部分的所述数据线；
    所述第一部分和第二部分至少有一部分不同。
  14. 如权利要求1所述的一种显示面板，其中，所述数据线和扫描线分别与所述像素单元对应设置；
    所述第一遮光层遮挡其中的第一部分所述扫描线；
    所述第二遮光层遮挡其中的第二部分的所述扫描线；
    所述第一部分和第二部分至少有一部分不同。
  15. 如权利要求13所述的一种显示面板，其中，所述像素单元包括与所述扫描线连接的薄膜电晶体开关；
    所述第二基板包括第二遮光层；
    所述第一遮光层遮挡数据线；
    所述第二遮光层遮挡所述扫描线和薄膜电晶体开关。
  16. 一种显示面板的制程方法，包括：
    形成第一基板的基底；
    在所述基底上形成不包括像素电极的薄膜电晶体开关；同时，在所述薄膜电晶体开关旁形成数据线和扫描线；
    在所述薄膜电晶体开关的上方形成色阻；
    在所述色阻的上方分别形成像素电极、以及遮挡所述数据线和扫描线的第一遮光层，得到第一基板；
    形成遮挡所述数据线和扫描线的第二遮光层，得到第二基板；
    对盒固定所述第一基板和第二基板，使得所述第二遮光层对应遮挡所述数据线和扫描线。
  17. 如权利要求16所述的一种显示面板的制程方法，其中，包括：
    形成第一基板的第一基底，在所述第一基底上形成栅极、与栅极同层且连接的扫描线，以及公共电极线；
    在所述栅极上方形成栅极绝缘层、非晶硅层；
    在所述非晶硅层的上方形成同层设置的源极和漏极，以及与源极或漏极连接的数据线；
    在所述源极和漏极上方形成钝化层，以及与公共电极线部分交叠的透明导电薄膜得到薄膜电晶体开关；
    在所述薄膜电晶体开关的上方形成色阻；
    在相邻的两个色阻之间形成遮挡数据线和扫描线的第一遮光层；
    在所述色阻和所述第一遮光层上形成像素电极得到第一基板；
    形成遮挡数据线和扫描线和第二遮光层的第二基板；
    对盒固定所述第一基板和第二基板，使得所述第二遮光层对应遮挡所述数据线和扫描线。
  18. 如权利要求16所述的一种显示面板的制程方法，其中，包括所述第一遮光层遮挡数据线、公共电极线，以及超出公共电极线靠近像素电极的边缘，不遮扫描线；
    所述第二遮光层，形成在部分色阻之间；
    对盒时，使得所述第二遮光层与扫描线对应，遮挡扫描线。
  19. 一种显示装置，所述显示装置包括显示面板，所述显示面板形成有显示区和***区，所述显示面板包括：
    第一基板；
    第二基板，与所述第一基板对盒设置；
    多个像素单元，设置在所述第一基板上；
    多个数据线和扫描线，设置在所述第一基板上，相邻两个像素单元之间；
    多个色阻，设置在所述第一基板对应的所述像素单元的上方；
    所述第一基板包括第一遮光层；所述第一遮光层形成在相邻两个所述像素单元之间，可以遮挡所述数据线或扫描线；
    所述显示区包括开口区和非开口区，所述第一遮光层仅设置在所述非开口区；
    所述第二基板包括与所述第一遮光层对应设置的第二遮光层；
    每条所述数据线和扫描线至少被所述第一遮光层和所述第二遮光层中的一种所遮挡。。
  20. 如权利要求19所述的一种显示装置，其中，所述第一遮光层与所有的所述数据线和扫描线一一对应遮挡设置；所述第二遮光层与所有的所述数据线和扫描线一一对应遮挡设置；
    所述第一遮光层和第二遮光层对应设置；
    所述第一遮光层和第二遮光层的形状及尺寸相同。
PCT/CN2018/120482 2018-11-14 2018-12-12 显示面板的制程方法、显示面板及显示装置 WO2020098032A1 (zh)

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