WO2020087806A1 - 外延基板及其制造方法 - Google Patents

外延基板及其制造方法 Download PDF

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Publication number
WO2020087806A1
WO2020087806A1 PCT/CN2019/075758 CN2019075758W WO2020087806A1 WO 2020087806 A1 WO2020087806 A1 WO 2020087806A1 CN 2019075758 W CN2019075758 W CN 2019075758W WO 2020087806 A1 WO2020087806 A1 WO 2020087806A1
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boss
substrate
epitaxial
substrate body
area
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PCT/CN2019/075758
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English (en)
French (fr)
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郭恩卿
邢汝博
黄秀颀
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昆山工研院新型平板显示技术中心有限公司
昆山国显光电有限公司
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Publication of WO2020087806A1 publication Critical patent/WO2020087806A1/zh
Priority to US17/191,997 priority Critical patent/US20210193634A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • This application relates to the field of display technology, and in particular to an epitaxial substrate and a manufacturing method thereof.
  • Micro-LED Micro Light Emitting Diode
  • Micro-LED display technology has the advantages of high brightness, high response speed, low power consumption, long life, etc., making Micro-LED display technology a research hotspot of new generation display technology, but Micro-LED LED display technology is not yet mature, and many technical problems still need to be resolved.
  • the main problem solved by the present application is to provide an epitaxial substrate and a manufacturing method thereof, which can improve the success rate of alignment between the epitaxial substrate and the driving substrate.
  • an epitaxial substrate including: a substrate body; a plurality of bosses arranged in an array on the substrate body; and a plurality of contact electrodes corresponding to the bosses
  • the top of the; planarization layer, covering the boss and the substrate body is not covered by the boss, wherein the planarization layer is provided with a first through hole corresponding to the boss, so that the contact electrode is exposed through the first through hole
  • Multiple pads are arranged on the planarization layer in an array and are electrically connected to the corresponding contact electrodes through the first through holes.
  • the area of the pads projected vertically on the substrate body is larger than that of the contact electrodes on the substrate body The area of the vertical projection.
  • the vertical projection of the pad on the substrate body completely covers the vertical projection of the contact electrode on the substrate body.
  • the vertical projection of the pad on the substrate body completely covers the vertical projection of the boss on the substrate body, and the area of the vertical projection of the pad on the substrate body is larger than the area of the vertical projection of the boss on the substrate body.
  • the area of the vertical projection of the pad on the substrate body is at least twice the area of the vertical projection of the boss on the substrate body.
  • the area of the pad is between twice and four times the area of the boss.
  • the area of the pad is between two and three times the area of the boss.
  • the pad is arranged in a T shape, and includes an epitaxial portion provided on the planarization layer and a connection portion provided in the first through hole and used to electrically connect the epitaxial portion and the contact electrode
  • the projection completely covers the vertical projection of the connection portion and the first through hole on the substrate body, and the area of the vertical projection of the extension portion on the substrate body is larger than the area of the vertical projection of the connection portion and the first through hole on the substrate body.
  • the cross-sectional area of the epitaxial portion gradually decreases in a direction away from the substrate body.
  • the cross-sectional area of the epitaxial portion is equal everywhere in the direction away from the substrate body.
  • the epitaxial substrate further includes a passivation layer, the passivation layer is interposed between the boss and the planarization layer, and a second through hole allowing contact electrode exposure is provided.
  • the passivation layer is silicon nitride or silicon oxide or a stacked structure of silicon nitride and silicon oxide.
  • the boss is an electroluminescent element.
  • the boss is Micro LED.
  • the size of the boss along the direction perpendicular to the light exit is between 1 ⁇ m and 100 ⁇ m, and the size along the light exit direction is between 0.5 ⁇ m and 10 ⁇ m.
  • the substrate body includes a substrate and an epitaxial layer formed on the substrate.
  • the material of the substrate is sapphire material or silicon.
  • the material of the epitaxial layer is gallium nitride.
  • the boss is an LED light-emitting unit, and the boss includes a light-emitting layer and N-type semiconductor layers and P-type semiconductor layers on both sides of the light-emitting layer.
  • Another technical solution adopted by the present application is to provide a method for manufacturing an epitaxial substrate.
  • the method includes: providing a substrate body; forming a plurality of bosses arranged in an array on the substrate body; A contact electrode is correspondingly formed on the top of the boss; a planarization layer is covered on the region of the boss and the substrate body not covered by the boss, and a first through hole corresponding to the boss is formed on the planarization layer to make the contact electrode pass The first through holes are exposed; a plurality of pads arranged in an array are formed on the planarization layer, wherein each pad is electrically connected to the corresponding contact electrode through the corresponding first through hole, and the pad is on the substrate body
  • the area of the vertical projection is larger than the area of the vertical projection of the contact electrode on the substrate body.
  • the method further includes: forming a passivation layer on the boss, and forming a second pass on the passivation layer that allows the exposed contact electrode hole.
  • the epitaxial substrate of the present application includes: a substrate body; a plurality of bosses arranged on the substrate body in an array; a plurality of contact electrodes corresponding to the tops of the bosses; a planarization layer covering the bosses and the substrate body On the area covered by the boss, the planarizing layer is provided with a first through hole corresponding to the boss, so that the contact electrode is exposed through the first through hole; a plurality of pads are arranged on the planarizing layer in an array , And is electrically connected to the corresponding contact electrode through the first through hole, wherein the area of the vertical projection of the pad on the substrate body is larger than the area of the vertical projection of the contact electrode on the substrate body.
  • the pad is connected to the corresponding contact electrode, when the drive substrate is aligned with the epitaxial substrate, it can be aligned with the pad array.
  • the area of the pad can be The design area is larger than the contact electrode area. Since the pad area is larger than the contact electrode area, the difficulty of aligning with the pad is reduced, which can improve the alignment success rate of the epitaxial substrate and the driving substrate; the epitaxial substrate structure makes the driving substrate
  • the allowable error range of para-bonding can be increased by at least 10%, depending on the change of the duty ratio of the boss on the epitaxial substrate. When the duty ratio of the boss on the epitaxial substrate is 10%, the allowable error range can be increased to Close to 10 times, so the improvement effect is remarkable.
  • FIG. 1 is a schematic structural diagram of an epitaxial substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an epitaxial substrate according to an embodiment of the present application after removing a pad and a contact electrode;
  • FIG. 3 is a schematic flowchart of a method for manufacturing an exceptionally extended substrate of the present application
  • FIG. 4 is a schematic diagram of the process S11-S16 for implementing an exceptionally extended substrate in this application;
  • FIG. 5 is a schematic diagram of the process S17-S18 for implementing the exception extension substrate in this application.
  • FIG. 1 is a schematic structural diagram of an epitaxial substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the structure of the epitaxial substrate after removing the pad and the contact electrode according to an embodiment of the present application.
  • the epitaxial substrate includes: a substrate body 11, a plurality of bosses 12, a plurality of contact electrodes 13, a planarization layer 14, and a plurality of pads 15.
  • the substrate body 11 may include a substrate and an epitaxial layer formed on the substrate.
  • the material of the substrate may be sapphire material, silicon, or the like.
  • the material of the epitaxial layer may be gallium nitride (GaN).
  • the plurality of bosses 12 are arranged on the substrate body 11 in an array.
  • the boss 12 may be an LED light emitting unit.
  • the boss 12 may include at least a light-emitting layer and N-type semiconductor layers and P-type semiconductor layers on both sides of the light-emitting layer.
  • the boss 12 may be an electroluminescence element, that is, an element that can emit light when energized.
  • the boss 12 may be a Micro LED.
  • the dimension of the boss 12 along the direction perpendicular to the light exit direction (for example, the lateral dimension in the figure) is between 1 ⁇ m and 100 ⁇ m, and the size along the light exit direction (eg, the longitudinal dimension in the figure) is between 0.5 ⁇ m and 10 Between microns.
  • the boss 12 may also be an OLED (Organic Light-Emitting Diode) light emitting unit. It should be understood that the boss 12 may be other light-emitting units, which is not limited in the embodiment of the present application.
  • OLED Organic Light-Emitting Diode
  • the boss 12 is connected to the driving current or voltage through the contact electrode 13.
  • the contact electrodes 13 correspond to the bosses 12 one-to-one.
  • the contact electrode 13 is correspondingly disposed on the top of the boss 12.
  • the contact electrode 13 is in electrical contact with the corresponding boss 12.
  • the planarization layer 14 covers the boss 12 and the area of the substrate body 11 not covered by the boss 12.
  • the planarization layer 14 is provided with a first through hole h1 corresponding to the boss 12 so that the contact electrode 13 is exposed through the first through hole h1.
  • a plurality of pads 15 are arranged on the planarization layer 14 in an array, and are electrically connected to the corresponding contact electrodes 13 through the first through holes h1.
  • the pad 15 is used for alignment bonding with a corresponding driving circuit on a driving substrate.
  • the area of the vertical projection of the pad 15 on the substrate body 11 is larger than the area of the vertical projection of the contact electrode 13 on the substrate body 11.
  • the vertical projection of the pad 15 on the substrate body 11 completely covers the vertical projection of the contact electrode 13 on the substrate body 11.
  • the design of the planarization layer 14 makes The area of the pad 15 can be designed to be larger than the area of the contact electrode 13, since the area of the pad 15 is larger than the area of the contact electrode 13, compared with the direct alignment with the contact electrode 13, the alignment with the pad 15 array can be The difficulty of alignment is reduced, so that the alignment success rate of the epitaxial substrate and the driving substrate can be improved.
  • the design of the planarization layer 14 can prevent the pad 15 from causing short circuit or static electricity problems.
  • the vertical projection of the pad 15 on the substrate body 11 completely covers the vertical projection of the boss 12 on the substrate body 11.
  • the area of the vertical projection of the pad 15 on the substrate body 11 is further larger than the area of the vertical projection of the boss 12 on the substrate body 11.
  • the vertical projection of the pad 15 on the substrate body 11 completely covers the vertical projection of the boss 12 on the substrate body 11, and the projection area of the pad 15 is larger than the projection area of the boss 12.
  • the lateral space between two adjacent bosses 12 is utilized to increase the contact area of the pad 15.
  • the area of the vertical projection of the pad 15 on the substrate body 11 is at least twice the area of the vertical projection of the boss 12 on the substrate body 11.
  • the area of the pad 15 is between twice and four times the area of the boss 12, so that the pixel density will not be affected while ensuring the success rate of the alignment between the epitaxial substrate and the driving substrate. display effect.
  • the area of the pad 15 is between two and three times the area of the boss 12. In this case, the display effect can be better guaranteed.
  • the pad 15 is arranged in a T shape.
  • the pad 15 may include the epitaxial portion 151 and the connection portion 152.
  • the connection portion 152 is vertically connected to the extension portion 151.
  • the connection portion 152 is provided perpendicular to the surface of the substrate body 11, and the extension portion 151 is provided parallel to the surface of the substrate body 11.
  • the epitaxial portion 151 is provided on the planarization layer 14.
  • the connection portion 152 is provided in the first through hole h1.
  • the connection portion 152 is used to electrically connect the epitaxial portion 151 and the contact electrode 13.
  • the vertical projection of the epitaxial portion 151 on the substrate body 11 completely covers the vertical projection of the connection portion 152 and the first through hole h1 on the substrate body 11.
  • the area of the vertical projection of the epitaxial portion 151 on the substrate body 11 is further larger than the area of the vertical projection of the connection portion 152 and the first through hole h1 on the substrate body 11.
  • the cross-sectional area of the epitaxial portion 151 is equal everywhere in the direction away from the substrate body 11. In this way, the area of the contact surface on the side of the pad 15 away from the substrate body 11 can be maximized.
  • the cross-sectional area of the epitaxial portion may gradually decrease in the direction away from the substrate body 11. In this way, the contact area between the pad 15 and the planarization layer 14 can be increased, and the bonding of the pad 15 and the planarization layer 14 can be made stronger.
  • the epitaxial substrate may further include a passivation layer 16, which is interposed between the boss 12 and the planarization layer 14.
  • the passivation layer 16 is provided with a second through hole h2 allowing the contact electrode 13 to be exposed.
  • the material of the passivation layer 16 may be silicon nitride (SiN x ) or silicon oxide (SiO x ) or a stacked structure of silicon nitride (SiN x ) and silicon oxide (SiO x ).
  • providing the passivation layer 16 can protect the boss 12 and prevent the planarization layer 14 directly disposed on the boss 12 from eroding the boss 12.
  • FIG. 3 is a schematic flow chart of a method for manufacturing an extended substrate according to the present application.
  • FIG. 4 is a schematic diagram of the process S11-S16 for implementing an exceptionally extended substrate in this application.
  • FIG. 5 is a schematic diagram of the process S17-S18 for implementing the exception extension substrate in this application.
  • the method for manufacturing an epitaxial substrate may include the following steps:
  • Step S11 Provide a substrate body.
  • the substrate body 11 may include a substrate and an epitaxial layer formed on the substrate.
  • the material of the substrate may be sapphire material, silicon, or the like.
  • the material of the epitaxial layer may be gallium nitride (GaN).
  • Step S12 forming a plurality of bosses arranged in an array on the substrate body.
  • the boss 12 is formed on the surface of the epitaxial layer away from the substrate.
  • the boss 12 may be an LED light emitting unit.
  • the boss 12 may include at least a light-emitting layer and N-type semiconductor layers and P-type semiconductor layers on both sides of the light-emitting layer.
  • the boss 12 may be a Micro LED.
  • the size of the boss 12 along the direction perpendicular to the light exit direction (such as the lateral dimension in the figure) is between 1 micron and 100 micrometers, and the size along the light exit direction (such as the longitudinal dimension in the figure) is between 0.5 micron and 10 micrometers between.
  • the boss 12 may also be an OLED (Organic Light-Emitting Diode) light emitting unit. It should be understood that the boss 12 may be other electroluminescent elements, which is not limited in the embodiments of the present application.
  • OLED Organic Light-Emitting Diode
  • the specific steps of forming a plurality of bosses 12 arranged in an array on the substrate body 11 may be: forming a whole layer of boss material layer on the substrate body 11; etching the whole boss material layer A plurality of bosses 12 arranged in an array are formed.
  • forming a whole layer of the boss material layer on the substrate body 11 may be: growing each layer of the LED on the epitaxial layer through epitaxial growth.
  • etching a whole boss material layer to form a plurality of bosses 12 arranged in an array may specifically be: photolithography, ICP (inductively coupled plasma) etching, etc. Semiconductor technology.
  • step 12a may be included: forming a passivation layer 16 on the side wall of the boss 12 and a partial area of the top wall of the boss 12, and forming a third layer on the passivation layer 16 that allows the contact electrode to be exposed Two through holes h2.
  • the method for forming the passivation layer 16 may be vapor deposition, such as physical vapor deposition or chemical vapor deposition, and may specifically be PECVD (Plasma Enhanced Chemical Vapor Deposition).
  • Step S13 correspondingly forming a contact electrode on the top of the boss.
  • the boss 12 is connected to the driving current or voltage through the contact electrode 13.
  • the contact electrode 13 is formed on the boss by a metal lift off (stripping) process or an EB / Sputter (electron beam / sputtering), photolithography, or etching process.
  • the contact electrode 13 is formed in the second through hole h2.
  • Step S14 Cover the planarization layer on the boss and the area of the substrate body that is not covered by the boss.
  • the planarization layer 14 is formed by a deposition process on the regions of the boss 12 and the substrate body 11 that are not covered by the boss 12.
  • the specific deposition method may be physical vapor deposition or chemical vapor deposition.
  • Step S15 forming a first through hole corresponding to the boss in the planarization layer, so that the contact electrode is exposed through the first through hole.
  • a first through hole h1 corresponding to the boss 12 is formed on the planarization layer 14 so that the contact electrode 13 is exposed through the first through hole h1.
  • the formation of the planarization layer 12 and the first through hole h1 may be achieved by a photolithography process using a polymer planarization material of photosensitive properties.
  • Step S16 forming a plurality of pads arranged in an array on the planarization layer, wherein each pad is electrically connected to a corresponding contact electrode through a corresponding first through hole, and the pad is vertically projected on the substrate body The area is larger than the area of the vertical projection of the contact electrode on the substrate body.
  • a plurality of pads 15 arranged in an array are formed on the planarization layer 14.
  • the planarization layer 14 For the relationship between the area of the pad 15 and the contact electrode 13 and the boss 12, please refer to the description of the above embodiment for details, which will not be repeated here.
  • Step S17 Align the bonding pad with the corresponding driving element on the driving substrate.
  • the plurality of pads 15 arranged in an array and the plurality of drive elements 22 on the drive substrate 21 are aligned and bonded, so that the plurality of pads 15 arranged in an array and the plurality of drive elements 22 on the drive substrate 21 One to one electrical connection.
  • Step S18 The substrate body is removed, and a common electrode is formed on the side of the boss away from the pad.
  • the substrate body 11 is removed, and a whole layer of common electrode 23 is formed on the side of the boss 12 away from the pad 15. All the bosses 12 share a common electrode 23, and the other electrode of the boss 12 is connected to different driving elements 22.
  • the epitaxial substrate of the present application includes: a substrate body; a plurality of bosses arranged on the substrate body in an array; a plurality of contact electrodes corresponding to the tops of the bosses; a planarization layer covering the bosses and the substrate body On the area covered by the boss, the planarizing layer is provided with a first through hole corresponding to the boss, so that the contact electrode is exposed through the first through hole; a plurality of pads are arranged on the planarizing layer in an array , And is electrically connected to the corresponding contact electrode through the first through hole, wherein the area of the vertical projection of the pad on the substrate body is larger than the area of the vertical projection of the contact electrode on the substrate body.
  • the pad is connected to the corresponding contact electrode, when the drive substrate is aligned with the epitaxial substrate, it can be aligned with the pad array.
  • the area of the pad can be The design has a larger area than the contact electrode. Since the pad area is larger than the contact electrode area, the difficulty of aligning with the pad is reduced, which can improve the alignment success rate of the epitaxial substrate and the driving substrate; the epitaxial substrate structure makes the driving
  • the allowable error range of substrate alignment bonding can be increased by at least 10%, depending on the change of the duty ratio of the boss on the epitaxial substrate. When the duty ratio of the boss on the epitaxial substrate is 10%, the allowable error range can be increased It is close to 10 times, so the lifting effect is remarkable.

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  • Electroluminescent Light Sources (AREA)

Abstract

本申请公开了一种外延基板，该外延基板包括：基板主体；多个凸台，以阵列方式排布于基板主体上；多个接触电极，对应设置于凸台的顶部；平坦化层，覆盖于凸台和基板主体未被凸台覆盖的区域上，其中平坦化层设置有与凸台对应的第一通孔，以使得接触电极经第一通孔外露；多个焊盘，以阵列方式排布于平坦化层上，并通过第一通孔电连接至对应的接触电极，其中焊盘在基板主体上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。本申请还公开了一种外延基板的制造方法。通过上述方式，本申请能够提高外延基板与驱动基板的对位成功率。

Description

外延基板及其制造方法 【技术领域】
本申请涉及显示技术领域，具体涉及一种外延基板及其制造方法。
【背景技术】
近年来半导体照明技术日趋成熟，成本不断下降，产业规模趋于饱和，这为LED显示技术的发展提供了较好的技术支持。
Micro-LED(Micro Light Emitting Diode，微型发光二极体)具有高亮度、高响应速度、低功耗、长寿命等优点，使得Micro-LED显示技术成为新一代显示技术的研究热点，但是Micro-LED显示屏技术还不成熟，许多技术问题仍有待解决。
由于Micro-LED尺寸极小，其电极层、钝化层等图形尺寸更小，给对位键合的精度及工艺控制带来很大的挑战，不利于对位键合的成功率。
【发明内容】
本申请主要解决的问题是提供一种外延基板及其制造方法，能够提高外延基板与驱动基板的对位成功率。
为解决上述技术问题，本申请采用的技术方案是：提供一种外延基板，包括：基板主体；多个凸台，以阵列方式排布于基板主体上；多个接触电极，对应设置于凸台的顶部；平坦化层，覆盖于凸台和基板主体未被凸台覆盖的区域上，其中，平坦化层设置有与凸台对应的第一通孔，以使得接触电极经第一通孔外露；多个焊盘，以阵列方式排布于平坦化层上，并通过第一通孔电连接至对应的接触电极，焊盘在基板主体上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。
其中，焊盘在基板主体上的垂直投影完全覆盖接触电极在基板主体上的垂直投影。
其中，焊盘在基板主体上的垂直投影完全覆盖凸台在基板主体上的垂直投影，且焊盘在基板主体上的垂直投影的面积大于凸台在基板主体上的垂直投影 的面积。
其中，焊盘在基板主体上的垂直投影的面积至少为凸台在基板主体上的垂直投影的面积的两倍。
其中，焊盘的面积为凸台的面积的两倍至四倍之间。
其中，焊盘的面积为凸台的面积的两倍至三倍之间。
其中，焊盘呈T字形设置，且包括设置于平坦化层上的外延部以及设置于第一通孔内且用于电连接外延部和接触电极的连接部，外延部在基板主体上的垂直投影完全覆盖连接部和第一通孔在基板主体上的垂直投影，且外延部在基板主体上的垂直投影的面积大于连接部和第一通孔在基板主体上的垂直投影的面积。
其中，外延部的横截面积在远离基板主体的方向上逐渐减小。
其中，外延部的横截面积在远离基板主体的方向上处处相等。
其中，外延基板进一步包括钝化层，钝化层介于凸台和平坦化层之间，且设置有允许接触电极外露的第二通孔。
其中，钝化层为氮化硅或者氧化硅或者氮化硅和氧化硅的层叠结构。
其中，凸台为电致发光元件。
其中，凸台为Micro LED。
其中，凸台沿垂直于出光方向的尺寸在1微米-100微米之间，沿出光方向的尺寸在0.5微米-10微米之间。
其中，基板主体包括衬底和形成在衬底上的外延层。
其中，衬底的材料为蓝宝石材料或硅。
其中，外延层的材料为氮化镓。
其中，凸台为LED发光单元，凸台包括发光层以及位于发光层两侧的N型半导体层和P型半导体层。
为解决上述技术问题，本申请采用的另一技术方案是：提供一种外延基板的制造方法，该方法包括：提供一基板主体；在基板主体上形成以阵列方式排布的多个凸台；在凸台的顶部对应形成接触电极；在凸台和基板主体未被凸台覆盖的区域上覆盖平坦化层，并在平坦化层形成与凸台对应的第一通孔，以使得接触电极经第一通孔外露；在平坦化层上形成以阵列方式排布的多个焊盘，其中每个焊盘通过对应的第一通孔电连接至对应的接触电极，焊盘在基板主体 上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。
其中，在凸台和基板主体经凸台外露的区域上覆盖平坦化层的步骤之前，进一步包括：在凸台上形成钝化层，并在钝化层上形成允许接触电极外露的第二通孔。
本申请的外延基板包括：基板主体；多个凸台，以阵列方式排布于基板主体上；多个接触电极，对应设置于凸台的顶部；平坦化层，覆盖于凸台和基板主体未被凸台覆盖的区域上，其中平坦化层设置有与凸台对应的第一通孔，以使得接触电极经第一通孔外露；多个焊盘，以阵列方式排布于平坦化层上，并通过第一通孔电连接至对应的接触电极，其中焊盘在基板主体上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。通过上述方式，由于设置焊盘与对应的接触电极连接，在驱动基板与该外延基板进行对位时，可以与焊盘阵列对位即可，通过平坦化层的设计，使得焊盘的面积能够设计的比接触电极的面积大，由于焊盘面积比接触电极面积大，降低与焊盘对位的难度，从而可以提高外延基板与驱动基板的对位成功率；该外延基板结构使得与驱动基板对位键合所允许的误差范围能提高至少10％，视外延基板上凸台的占空比变化而变化，在外延基板上凸台的占空比为10％时，误差允许范围可提升至接近10倍，因此提升效果显著。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请实施例的外延基板的结构示意图；
图2本申请实施例的外延基板移除焊盘和接触电极后的结构示意图；
图3是本申请实施例外延基板的制造方法的流程示意图；
图4是本申请实施例外延基板的制程S11-S16的示意图；
图5是本申请实施例外延基板的制程S17-S18的示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请结合参阅图1和图2，图1是本申请实施例的外延基板的结构示意图。图2是本申请实施例的外延基板移除焊盘和接触电极后的结构示意图。
在本实施例中，外延基板包括：基板主体11、多个凸台12、多个接触电极13、平坦化层14、多个焊盘15。
基板主体11可以包括衬底和形成在衬底上的外延层。衬底的材料可以是蓝宝石材料、硅等。外延层的材料可以是氮化镓(GaN)。
多个凸台12以阵列方式排布于基板主体11上。凸台12可以为LED发光单元。
例如，凸台12至少可包括发光层以及位于发光层两侧的N型半导体层和P型半导体层。
例如，凸台12可以为电致发光元件，即通电时可以发光的元件。例如，凸台12可以是Micro LED。可选地，凸台12的沿垂直于出光方向的尺寸(例如图中的横向尺寸)在1微米-100微米之间，沿出光方向的尺寸(例如图中的纵向尺寸)在0.5微米-10微米之间。
凸台12也可以为OLED(Organic Light-Emitting Diode)发光单元。应理解，凸台12可以为其他发光单元，本申请实施例对此不做限定。
凸台12通过接触电极13接入驱动电流或者电压。
接触电极13与凸台12一一对应。接触电极13对应设置于凸台12的顶部。 接触电极13与对应的凸台12电接触。
平坦化层14覆盖于凸台12和基板主体11未被凸台12覆盖的区域上。
平坦化层14上设置有与凸台12对应的第一通孔h1，以使得接触电极13经第一通孔h1外露。
多个焊盘15以阵列方式排布于平坦化层14上，并通过第一通孔h1电连接至对应的接触电极13。
可选地，焊盘15用于与对应的一驱动基板上的驱动电路进行对位键合。
焊盘15在基板主体11上的垂直投影的面积大于接触电极13在基板主体11上的垂直投影的面积。
可选地，焊盘15在基板主体11上的垂直投影完全覆盖接触电极13在基板主体11上的垂直投影。
通过上述方式，由于焊盘15在基板主体11上的垂直投影完全覆盖接触电极13在基板主体11上的垂直投影，便于接触电极13与焊盘15的电连接，设计的接触结构不会占用外延基板的横向尺寸，由于设置焊盘15与对应的接触电极13连接，在驱动基板与该外延基板进行对位时，可以与焊盘15阵列对位即可，通过平坦化层14的设计，使得焊盘15的面积能够设计的比接触电极13的面积大，由于焊盘15的面积比接触电极13的面积大，相较于与接触电极13的直接对位，与焊盘15阵列对位可以降低对位的难度，从而可以提高外延基板与驱动基板的对位成功率。另外，平坦化层14的设计可以防止焊盘15引起短路或者静电的问题。
可选地，焊盘15在基板主体11上的垂直投影完全覆盖凸台12在基板主体11上的垂直投影。焊盘15在基板主体11上的垂直投影的面积进一步大于凸台12在基板主体11上的垂直投影的面积。
通过上述方式，进一步设置焊盘15在基板主体11上的垂直投影完全覆盖凸台12在基板主体11上的垂直投影，并且使得焊盘15的投影面积比凸台12的投影面积大，可以进一步地提高对位成功率，且不会占用额外的基板主体11 的横向尺寸，利用了相邻两凸台12之间的横向空间来增大焊盘15的接触面积。
可选地，焊盘15在基板主体11上的垂直投影的面积至少为凸台12在基板主体11上的垂直投影的面积的两倍。
通过上述方式，进一步通过设置焊盘15的面积为凸台12的面积的两倍以上，保证外延基板与驱动基板的对位成功率。
优选地，焊盘15的面积为凸台12的面积的两倍至四倍之间，从而可以在保证外延基板与驱动基板的对位成功率的情况下，不会对像素密度产生影响，保证显示效果。
更为优选地，焊盘15的面积为凸台12的面积的两倍至三倍之间。在这种情况下，能够较好的保证显示效果。
可选地，焊盘15呈T字形设置。具体而言，焊盘15可包括外延部151和连接部152。连接部152与外延部151垂直连接。例如，连接部152垂直于基板主体11的表面设置，外延部151平行于基板主体11的表面设置。
外延部151设置于平坦化层14上。连接部152设置于第一通孔h1内，连接部152用于电连接外延部151和接触电极13。
可选地，外延部151在基板主体11上的垂直投影完全覆盖连接部152和第一通孔h1在基板主体11上的垂直投影。
可选地，外延部151在基板主体11上的垂直投影的面积进一步大于连接部152和第一通孔h1在基板主体11上的垂直投影的面积。
如图1所示，在本实施例中，外延部151的横截面积在远离基板主体11的方向上处处相等。通过这种方式，可以将焊盘15远离基板主体11一侧的接触面面积最大化。
在其他实施例中，外延部的横截面积在远离基板主体11的方向上还可以是逐渐减小。通过这种方式，可以提高焊盘15与平坦化层14的接触面积，使焊盘15与平坦化层14的结合更加牢固。
可选地，外延基板还可以进一步包括钝化层16，钝化层16介于凸台12和 平坦化层14之间，钝化层16设置有允许接触电极13外露的第二通孔h2。
可选地，钝化层16的材料可以是氮化硅(SiN x)或者氧化硅(SiO x)或者氮化硅(SiN x)和氧化硅(SiO x)的层叠结构。
通过上述方式，设置钝化层16可以对凸台12进行保护，避免直接设置在凸台12上的平坦化层14对凸台12产生侵蚀。
请参阅图3、图4以及图5，图3是本申请实施例外延基板的制造方法的流程示意图。图4是本申请实施例外延基板的制程S11-S16的示意图。图5是本申请实施例外延基板的制程S17-S18的示意图。在本实施例中，外延基板的制造方法可以包括以下步骤：
步骤S11：提供一基板主体。
其中，基板主体11可以包括衬底和形成在衬底上的外延层。衬底的材料可以是蓝宝石材料、硅等。外延层的材料可以是氮化镓(GaN)。
步骤S12：在基板主体上形成以阵列方式排布的多个凸台。
其中，凸台12形成在外延层远离衬底的一侧表面上。凸台12可以为LED发光单元。例如，凸台12至少可包括发光层以及位于发光层两侧的N型半导体层和P型半导体层。例如，凸台12可以为Micro LED。可选地，凸台12沿垂直于出光方向的尺寸(例如图中的横向尺寸)在1微米-100微米之间，沿出光方向的尺寸(例如图中的纵向尺寸)在0.5微米-10微米之间。
凸台12也可以为OLED(Organic Light-Emitting Diode)发光单元。应理解，凸台12可以为其他电致发光元件，本申请实施例对此不做限定。
在基板主体11上形成以阵列方式排布的多个凸台12的具体步骤可以为：在基板主体11上形成一整层的凸台材料层；对一整层的凸台材料层进行蚀刻处理形成以阵列方式排布的多个凸台12。
可选地，在基板主体11上形成一整层的凸台材料层可以为：通过磊晶在外延层上生长出LED的各层。
可选地，对一整层的凸台材料层进行蚀刻处理形成以阵列方式排布的多个 凸台12具体可以为：采用光刻、ICP(inductively coupled plasma，感应耦合等离子体)刻蚀等半导体工艺。
可选地，步骤S12之后可以包括步骤12a：在凸台12侧壁上和凸台12的顶壁的部分区域上形成钝化层16，并在钝化层16上形成允许接触电极外露的第二通孔h2。形成钝化层16的方式可以为气相沉积，例如物理气相沉积或者化学气相沉积，具体可以为PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)。
步骤S13：在凸台的顶部对应形成接触电极。
其中，凸台12通过接触电极13接入驱动电流或者电压。通过金属lift off(剥离)工艺或者EB/Sputter(电子束/溅射)、光刻、刻蚀工艺在凸台之上形成接触电极13。
可选地，接触电极13形成在第二通孔h2中。
步骤S14：在凸台和基板主体未被凸台覆盖的区域上覆盖平坦化层。
例如，在凸台12和基板主体11未被凸台12覆盖的区域上通过沉积工艺形成平坦化层14。具体的沉积方式可以是物理气相沉积或者化学气相沉积。
步骤S15：在平坦化层形成与凸台对应的第一通孔，以使得接触电极经第一通孔外露。
其中，在平坦化层14上形成与凸台12对应的第一通孔h1，以使得接触电极13经第一通孔h1外露。平坦化层12和第一通孔h1的形成可采用光敏性质的聚合物平坦化材料通过光刻工艺实现。
步骤S16：在平坦化层上形成以阵列方式排布的多个焊盘，其中每个焊盘通过对应的第一通孔电连接至对应的接触电极，焊盘在基板主体上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。
其中，在平坦化层14上形成以阵列方式排布的多个焊盘15。焊盘15与接触电极13和凸台12的面积大小关系具体参见上文实施例的描述，此处不再赘述。
步骤S17：将焊盘与驱动基板上的对应驱动元件进行对位键合。
例如，将阵列排布的多个焊盘15与驱动基板21上的多个驱动元件22进行对位键合，使得阵列排布的多个焊盘15与驱动基板21上的多个驱动元件22一一对应电连接。
步骤S18：移除基板主体，并在凸台远离焊盘的一侧形成公共电极。
其中，移除基板主体11，并在凸台12远离焊盘15的一侧形成一整层公共电极23。所有的凸台12共用公共电极23，凸台12另一电极连接不同的驱动元件22。
本申请的外延基板包括：基板主体；多个凸台，以阵列方式排布于基板主体上；多个接触电极，对应设置于凸台的顶部；平坦化层，覆盖于凸台和基板主体未被凸台覆盖的区域上，其中平坦化层设置有与凸台对应的第一通孔，以使得接触电极经第一通孔外露；多个焊盘，以阵列方式排布于平坦化层上，并通过第一通孔电连接至对应的接触电极，其中焊盘在基板主体上的垂直投影的面积大于接触电极在基板主体上的垂直投影的面积。通过上述方式，由于设置焊盘与对应的接触电极连接，在驱动基板与该外延基板进行对位时，可以与焊盘阵列对位即可，通过平坦化层的设计，使得焊盘的面积能够设计的比接触电极的面积大，由于焊盘面积比接触电极面积大，降低了与焊盘对位的难度，从而可以提高外延基板与驱动基板的对位成功率；该外延基板结构使得与驱动基板对位键合所允许的误差范围能提高至少10％，视外延基板上凸台的占空比变化而变化，在外延基板上凸台的占空比为10％时，误差允许范围可提升至接近10倍，因此提升效果显著。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种外延基板，包括：
    基板主体；
    多个凸台，以阵列方式排布于所述基板主体上；
    多个接触电极，对应设置于所述凸台的顶部；
    平坦化层，覆盖于所述凸台和所述基板主体未被所述凸台覆盖的区域上，其中，所述平坦化层设置有与所述凸台对应的第一通孔，以使得所述接触电极经所述第一通孔外露；
    多个焊盘，以阵列方式排布于所述平坦化层上，并通过所述第一通孔电连接至对应的所述接触电极，所述焊盘在所述基板主体上的垂直投影的面积大于所述接触电极在所述基板主体上的垂直投影的面积。
  2. 根据权利要求1所述的外延基板，其中，所述焊盘在所述基板主体上的垂直投影完全覆盖所述接触电极在所述基板主体上的垂直投影。
  3. 根据权利要求2所述的外延基板，其中，所述焊盘在所述基板主体上的垂直投影完全覆盖所述凸台在所述基板主体上的垂直投影，且所述焊盘在所述基板主体上的垂直投影的面积大于所述凸台在所述基板主体上的垂直投影的面积。
  4. 根据权利要求2所述的外延基板，其中，所述焊盘在所述基板主体上的垂直投影的面积至少为所述凸台在所述基板主体上的垂直投影的面积的两倍。
  5. 根据权利要求4所述的外延基板，其中，所述焊盘的面积为所述凸台的面积的两倍至四倍之间。
  6. 根据权利要求5所述的外延基板，其中，所述焊盘的面积为所述凸台的面积的两倍至三倍之间。
  7. 根据权利要求1所述的外延基板，其中，所述焊盘呈T字形设置，且包括设置于所述平坦化层上的外延部以及设置于所述第一通孔内且用于电连接所述外延部和所述接触电极的连接部，所述外延部在所述基板主体上的垂直投影完全覆盖所述连接部和所述第一通孔在所述基板主体上的垂直投影，且所述外延部在所述基板主体上的垂直投影的面积大于所述连接部和所述第一通孔在所述基板主体上的垂直投影的面积。
  8. 根据权利要求7所述的外延基板，其中，所述外延部的横截面积在远离 所述基板主体的方向上逐渐减小。
  9. 根据权利要求7所述的外延基板，其中，所述外延部的横截面积在远离所述基板主体的方向上处处相等。
  10. 根据权利要求1所述的外延基板，其中，所述外延基板进一步包括钝化层，所述钝化层介于所述凸台和所述平坦化层之间，且设置有允许所述接触电极外露的第二通孔。
  11. 根据权利要求10所述的外延基板，其中，所述钝化层为氮化硅或者氧化硅或者氮化硅和氧化硅的层叠结构。
  12. 根据权利要求1所述的外延基板，其中，所述凸台为电致发光元件。
  13. 根据权利要求12所述的外延基板，其中，所述凸台为Micro LED。
  14. 根据权利要求12所述的外延基板，其中，所述凸台沿垂直于出光方向的尺寸在1微米-100微米之间，沿所述出光方向的尺寸在0.5微米-10微米之间。
  15. 根据权利要求1所述的外延基板，其中，所述基板主体包括衬底和形成在所述衬底上的外延层。
  16. 根据权利要求15所述的外延基板，其中，所述衬底的材料为蓝宝石材料或硅。
  17. 根据权利要求15所述的外延基板，其中，所述外延层的材料为氮化镓。
  18. 根据权利要求12所述的外延基板，其中，所述凸台为LED发光单元，所述凸台包括发光层以及位于所述发光层两侧的N型半导体层和P型半导体层。
  19. 一种外延基板的制造方法，其中，所述方法包括：
    提供一基板主体；
    在所述基板主体上形成以阵列方式排布的多个凸台；
    在所述凸台的顶部对应形成接触电极；
    在所述凸台和所述基板主体未被所述凸台覆盖的区域上覆盖平坦化层，并在所述平坦化层形成与所述凸台对应的第一通孔，以使得所述接触电极经所述第一通孔外露；
    在所述平坦化层上形成以阵列方式排布的多个焊盘，每个所述焊盘通过对应的所述第一通孔电连接至对应的所述接触电极，所述焊盘在所述基板主体上的垂直投影的面积大于所述接触电极在所述基板主体上的垂直投影的面积。
  20. 根据权利要求19所述的方法，其中，所述在所述凸台和所述基板主体未被所述凸台覆盖的区域上覆盖平坦化层的步骤之前，进一步包括：
    在所述凸台上形成钝化层，并在所述钝化层上形成允许所述接触电极外露的第二通孔。
PCT/CN2019/075758 2018-10-31 2019-02-21 外延基板及其制造方法 WO2020087806A1 (zh)

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