WO2020244030A1 - 一种led芯片结构 - Google Patents

一种led芯片结构 Download PDF

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WO2020244030A1
WO2020244030A1 PCT/CN2019/096295 CN2019096295W WO2020244030A1 WO 2020244030 A1 WO2020244030 A1 WO 2020244030A1 CN 2019096295 W CN2019096295 W CN 2019096295W WO 2020244030 A1 WO2020244030 A1 WO 2020244030A1
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negative electrode
electrode layer
substrate
light
chip
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PCT/CN2019/096295
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French (fr)
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龚文
邵鹏睿
张雨晨
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深圳市晶台股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer

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  • the invention relates to the technical field of semiconductor light-emitting devices, in particular to an LED chip structure.
  • Light-emitting diodes are a common light-emitting device.
  • the size and functions of light-emitting diodes have undergone tremendous changes from their birth to the present.
  • LED displays With the continuous expansion of LED applications, LED displays have gradually been applied to high-end applications such as business meetings, theaters, and stages. In the scene, higher requirements are put forward for LED display devices, forcing LED display devices to develop in the direction of small pitch and high density.
  • the current LED chip size greatly restricts the size of LED devices, so optimizing the LED chip structure has become an urgent solution for the industry The problem.
  • the present invention improves the chip structure through integrated technology and involves an all-in-one chip structure, which can greatly reduce the chip size, effectively reduce the distance of LED display, increase display density, and improve display quality.
  • An LED chip structure includes a substrate, a negative electrode layer is provided on the substrate, at least three light-emitting layers are provided on the negative electrode layer, and at least three light-emitting layers are provided with a positive electrode layer to form at least three light-emitting layers. At least three light-emitting points are independently controlled, the upper surface of the positive electrode layer on at least three light-emitting points is provided with a positive electrode, and the negative electrode layer is provided with a negative electrode.
  • the substrate is an integrated structure.
  • the negative electrode layer includes a separated structure or an integrated structure.
  • Non-common-polarity chips use a separate structure of the negative electrode layer, and common-polarity chips use an integrated structure of the negative electrode layer.
  • the separated structure of the negative electrode layer is: at least three of the negative electrode layers are evenly arranged on the surface of the substrate, at least three of the light-emitting layers are respectively arranged on at least three of the negative electrode layers, at least Each of the three negative electrode layers is provided with a negative electrode.
  • the number of light-emitting layers is equal to the number of negative electrode layers.
  • the light-emitting layer covers 2/3-3/4 area of the surface of the negative electrode layer.
  • the space can be used reasonably.
  • the integrated structure of the negative electrode layer is that the negative electrode layer covers the entire surface of the substrate, and the negative electrode layer is provided with a negative electrode.
  • At least three of the light-emitting layers are evenly arranged on the surface of the negative electrode layer.
  • the positive electrode layer covers the entire surface of the light-emitting layer.
  • the present invention is equipped with multiple independently controlled light-emitting points on the same substrate of the chip through integration technology, and can be divided into two structures of common pole and non-common pole at the same time, to achieve an all-in-one chip structure improvement, and can greatly reduce
  • the chip size effectively reduces the pitch of the LED display, increases the display density, and improves the display quality.
  • Figure 1 is a schematic diagram of the common pole structure of a formal integrated chip
  • Figure 2 is a schematic diagram of a non-common pole structure of a formal integrated chip
  • Figure 3 is a schematic diagram of the structure of a vertically integrated chip
  • Figure 4 is a schematic diagram of the common pole structure of the flip-chip integrated chip
  • Figure 5 is a schematic diagram of the non-common pole structure of the flip-chip integrated chip
  • the present invention adopts the method of etching the epitaxial wafer to make the chip, wherein the epitaxial wafer includes a substrate, the entire surface of the substrate is covered with the negative electrode layer 2 through deposition, and then the entire surface of the negative electrode layer 2 is covered with a light-emitting layer through deposition 3. Finally, the positive electrode layer 4 is covered by deposition on the entire surface of the light-emitting layer 3, which is combined into a four-layered rectangular epitaxial wafer as the etching basis of the chip.
  • the substrate in the present invention includes a sapphire substrate 1 and a metal substrate 7, the negative electrode layer 2 adopts an N-GaN layer, the light emitting layer 3 adopts a multiple quantum well light emitting layer, and the positive electrode layer 4 adopts a P-GaN layer.
  • the chips in the present invention include a front-mounted integrated chip, a vertical integrated chip, and a flip-chip integrated chip.
  • the present invention will be further described in detail below with reference to embodiments and specific implementation methods.
  • this embodiment is a specific manufacturing process of a common-polar formally mounted integrated chip
  • the common pole type formal integrated chip can be obtained by cutting.
  • the common-polar front-mounted integrated chip in this embodiment is directly fixed on the substrate by die-bonding glue, and the negative electrode 6 and the three positive electrodes 5 on it are bonded by gold wires to realize the conduction between the chip and the circuit of the substrate. .
  • this embodiment is a specific manufacturing process of a non-common pole type formal integrated chip
  • the light-emitting points are etched to the upper surface of the negative electrode layer 2 through an etching process, so that the light-emitting layer 3 and the positive electrode layer 4 have a missing corner.
  • the area of the light-emitting layer 3 covering the negative electrode layer 2 is 3/4;
  • the non-common-polar front-mounted integrated chip in this embodiment is directly fixed on the substrate by die-bonding glue, and the three negative electrodes 6 and three positive electrodes 5 on it are bonded by gold wires to realize the circuit between the chip and the substrate.
  • this embodiment is a specific manufacturing process of a vertically integrated chip
  • the vertical integrated chip can be obtained through the cutting process.
  • the vertical integrated chip in this embodiment is directly fixed on the substrate by die-bonding glue.
  • the metal substrate 7 can be used as the negative electrode to be directly welded to the circuit of the substrate.
  • the three positive electrodes 5 are welded by gold wires to achieve Conduction of chip and substrate circuit.
  • this embodiment is similar to Embodiment 1, except that the stacking sequence of the negative electrode layer 2, the light emitting layer 3, and the positive electrode layer 4 in the epitaxial wafer is changed so that they are reversed. It is installed under the sapphire substrate 1, the three positive electrodes 5 are made into squares, and the negative electrode 6 is made into long strips to fit the mounting position of the substrate, and a common-polar flip-chip integrated chip can be obtained.
  • the common-pole flip-chip integrated chip in this embodiment is directly embedded in the corresponding circuit position of the substrate and thermally welded by the electrode end, so that the chip and the substrate circuit can be connected.
  • this embodiment is similar to embodiment 2, and the stacking sequence of the negative electrode layer 2, the light emitting layer 3 and the positive electrode layer 4 in the epitaxial wafer used is changed so that they are flip-chip mounted under the sapphire substrate 1.
  • the area of the light-emitting layer 3 covering the negative electrode layer 2 is 2/3, and the remaining 1/3 area of the negative electrode layer 2 is provided with a negative electrode 6.
  • the three positive electrodes 5 and three negative electrodes 6 are all made into squares to fit the substrate You can obtain non-common-polar flip-chip integrated chips at the installation position of the
  • the non-common-polar flip-chip integrated chip in this embodiment is directly embedded in the corresponding circuit position of the substrate and thermally welded by the electrode end, so that the chip and the substrate circuit can be connected.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

本发明涉及半导体发光器件技术领域，尤其涉及一种LED芯片结构，包括衬底，包括衬底，所述衬底上设置有负极层，所述负极层上设置有至少三个发光层，至少三个所述发光层上均设置有正极层，形成至少三个分别独立控制的发光点，至少三个发光点上的所述正极层上表面均设有正极电极，所述负极层设有负极电极。本发明通过集成技术改进芯片结构，涉及多合一的芯片结构，可以极大的缩小芯片尺寸，有效的降低LED显示的间距，提高显示密度，提升显示质量。

Description

一种LED芯片结构 技术领域
本发明涉及半导体发光器件技术领域，尤其涉及一种LED芯片结构。
背景技术
发光二极管是一种常见的发光器件，发光二极管的从诞生到现在尺寸和功能发生了巨大的变化，随着LED应用领域的不断扩展，LED显示逐渐的应用到了商务会议、影院、舞台等高端使用场景中，对LED显示器件提出了更高的要求，迫使LED显示器件向小间距高密度方向发展，现行的LED芯片尺寸极大的制约了LED器件的尺寸，因此优化LED芯片结构成为行业亟待解决的问题。
发明内容
本发明通过集成技术改进芯片结构,涉及多合一的芯片结构，可以极大的缩小芯片尺寸，有效的降低LED显示的间距，提高显示密度，提升显示质量。
本发明的技术方案为：
一种LED芯片结构，包括衬底，所述衬底上设置有负极层，所述负极层上设置有至少三个发光层，至少三个所述发光层上均设置有正极层，形成至少三个分别独立控制的发光点，至少三个发光点上的所述正极层上表面均设有正极电极，所述负极层设有负极电极。
进一步，所述衬底为一体式结构。
进一步，所述负极层包括分离式结构或一体式结构。
非共极式的芯片采用分离式结构的负极层，共极式的芯片采用一体式结构的负极层。
进一步，所述负极层的分离式结构为：至少三个所述负极层间隔均匀设置在所述衬底的表面，至少三个所述发光层分别设置在至少三个所述负极层上，至少三个所述负极层均设有负极电极。
在分离式结构中，发光层的个数与负极层的个数相等。
进一步，所述发光层覆盖所述负极层表面的2/3—3/4面积。
为在每个分离式的负极层上留有位置设置负极电极，合理利用空间。
进一步，所述负极层的一体式结构为：所述负极层覆盖于整个所述衬底的表面，所述负极层设有一个负极电极。
进一步，至少三个所述发光层间隔均匀设置在所述负极层的表面。
进一步，所述正极层覆盖整个所述发光层的表面。
本发明的有益效果为：
本发明通过集成技术在芯片的同一衬底上设有多个独立控制的发光点，同时可分为共极与非共极两种结构，实现多合一的芯片结构改进，可以极大的缩小芯片尺寸，有效的降低LED显示的间距，提高显示密度，提升显示质量。
附图说明
图1是正装集成芯片的共极结构示意图；
图2是正装集成芯片的非共极结构示意图；
图3是垂直集成芯片的结构示意图；
图4是倒装集成芯片的共极结构示意图；
图5是倒装集成芯片的非共极结构示意图；
图中：1-蓝宝石衬底、2-负极层、3-发光层、4-正极层、5-正极电极、6-负极电极、7-金属衬底。
具体实施方式
附图仅用于示例性说明，不能理解为对本专利的限制；为了更好说明本实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。附图中描述位置关系仅用于示例性说明，不能理解为对本专利的限制。
本发明采用刻蚀外延片的方式进行制作芯片，其中，外延片包括衬底，衬底的整个表面通过沉积作用覆盖上负极层2，然后在负极层2的整个表面通过沉积作用覆盖上发光层3，最后在发光层3的整个表面通过沉积作用覆盖上正极层4，组合为一具有4层结构的长方体外延片作为芯片的刻蚀基础。
本发明中的衬底包括蓝宝石衬底1和金属衬底7，负极层2采用N-GaN层，发光层3采用多量子阱发光层，正极层4采用P-GaN层。
本发明中的芯片包括正装集成芯片、垂直集成芯片和倒装集成芯片，下面 结合实施例和具体实施方法对本发明作进一步详细的说明。
实施例1：
如图1所示，本实施例为共极式正装集成芯片的具体制作过程；
首先准备一块用蓝宝石衬底1的外延片，按特定图形通过刻蚀外延层至负极层2上表面，使其在负极层2的表面上形成三个独立控制的发光点；
然后在三个独立的正极层4上分别沉积一层金作为正极电极5；
再在负极层2沉积一层金作为负极电极6；
最后通过切割即可获得共极式正装集成芯片。
本实施例中的共极式正装集成芯片是直接通过固晶胶固定在基板上，其上的负极电极6与三个正极电极5利用金线进行焊线操作，实现芯片与基板电路的导通。
实施例2：
如图2所示，本实施例为非共极式正装集成芯片的具体制作过程；
首先准备一块用蓝宝石衬底1的外延片，按特定图形通过刻蚀外延层至衬底的上表面，使其在衬底的表面上形成三个独立控制的发光点；
接着再通过刻蚀工艺刻蚀发光点至负极层2上表面，使发光层3和正极层4均有缺角，此时，发光层3覆盖负极层2的面积为3/4；
然后在三个独立的正极层4上分别沉积一层金作为正极电极5；
再在缺角处的三个独立的负极层2上分别沉积一层金作为负极电极6；
最后通过切割工艺即可获得非共极式正装集成芯片。
本实施例中的非共极式正装集成芯片是直接通过固晶胶固定在基板上，其上的三个负极电极6与三个正极电极5利用金线进行焊线操作，实现芯片与基板电路的导通。
实施例3：
如图3所示，本实施例为垂直集成芯片的具体制作过程；
首先准备一块用金属衬底7的外延片，通过刻蚀外延层至衬底的上表面，使其在衬底的表面上形成三个独立控制的发光点；
然后在三个独立的正极层4上分别沉积一层金作为正极电极5；
通过切割工艺即可获得垂直集成芯片。
本实施例中的垂直集成芯片是直接通过固晶胶固定在基板上，其金属衬底7可作为负极电极直接焊接在基板的电路上，三个正极电极5利用金线进行焊线操作，实现芯片与基板电路的导通。
实施例4：
如图4所示，本实施例与对实施例1类似，所不同之处在于，其所采用的外延片中的负极层2、发光层3和正极层4堆叠顺序做出变化，使它们倒装在蓝宝石衬底1下，同时将三个正极电极5做成方形、负极电极6做成长条形以契合基板的安装位置，即可获得共极式倒装集成芯片。
本实施例中的共极式倒装集成芯片通过电极端直接嵌入基板的相应电路位置上并热熔焊接，即可实现芯片与基板电路的导通。
实施例5：
如图5所示，本实施例与实施例2类似，其所采用的外延片中的负极层2、发光层3和正极层4堆叠顺序做出变化，使它们倒装在蓝宝石衬底1下，同时使发光层3覆盖负极层2的面积为2/3，负极层2剩余的1/3面积设置负极电极6，将三个正极电极5和三个负极电极6均做成方形以契合基板的安装位置，即可获得非共极式倒装集成芯片。
本实施例中的非共极式倒装集成芯片通过电极端直接嵌入基板的相应电路位置上并热熔焊接，即可实现芯片与基板电路的导通。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (8)

  1. 一种LED芯片结构，其特征在于，包括衬底，所述衬底上设置有负极层，所述负极层上设置有至少三个发光层，至少三个所述发光层上均设置有正极层，形成至少三个分别独立控制的发光点，至少三个发光点上的所述正极层上表面均设有正极电极，所述负极层设有负极电极。
  2. 根据权利要求1所述的一种LED芯片结构，其特征在于，所述衬底为一体式结构。
  3. 根据权利要求1所述的一种LED芯片结构，其特征在于，所述负极层包括分离式结构或一体式结构。
  4. 根据权利要求3所述的一种LED芯片结构，其特征在于，所述负极层的分离式结构为：至少三个所述负极层间隔均匀设置在所述衬底的表面，至少三个所述发光层分别设置在至少三个所述负极层上，至少三个所述负极层均设有负极电极。
  5. 根据权利要求4所述的一种LED芯片结构，其特征在于，所述发光层覆盖所述负极层表面的2/3—3/4面积。
  6. 根据权利要求3所述的一种LED芯片结构，其特征在于，所述负极层的一体式结构为：所述负极层覆盖于整个所述衬底的表面，所述负极层设有一个负极电极。
  7. 根据权利要求6所述的一种LED芯片结构，其特征在于，至少三个所述发光层间隔均匀设置在所述负极层的表面。
  8. 根据权利要求5或7所述的一种LED芯片结构，其特征在于，所述正极层覆盖整个所述发光层的表面。
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CN110518033A (zh) * 2019-09-29 2019-11-29 深圳市晶台股份有限公司 一种集成全彩发光芯片结构
TWI824614B (zh) * 2022-07-11 2023-12-01 友達光電股份有限公司 顯示面板

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