WO2022252476A1 - 发光器件、发光基板和发光器件的制作方法 - Google Patents

发光器件、发光基板和发光器件的制作方法 Download PDF

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Publication number
WO2022252476A1
WO2022252476A1 PCT/CN2021/125522 CN2021125522W WO2022252476A1 WO 2022252476 A1 WO2022252476 A1 WO 2022252476A1 CN 2021125522 W CN2021125522 W CN 2021125522W WO 2022252476 A1 WO2022252476 A1 WO 2022252476A1
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Prior art keywords
semiconductor layer
layer
light
opening
emitting
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PCT/CN2021/125522
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English (en)
French (fr)
Inventor
秦斌
彭宽军
刘伟星
张方振
董学
彭***
滕万鹏
李小龙
孙双
陈婉芝
袁广才
贾倩
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京东方科技集团股份有限公司
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Priority to US18/263,567 priority Critical patent/US20240088328A1/en
Priority to EP21943828.0A priority patent/EP4270496A1/en
Priority to JP2023574117A priority patent/JP2024521208A/ja
Publication of WO2022252476A1 publication Critical patent/WO2022252476A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a light emitting device, a light emitting substrate and a method for manufacturing the light emitting device.
  • Light-emitting diode (Light-Emitting Diode, LED) display refers to the traditional LED array, miniaturization, addressing and transfer to the circuit substrate in large quantities to form ultra-fine-pitch LEDs, and further shrink the length of millimeter-level LEDs to micron-level. To achieve ultra-high pixel and ultra-high resolution, it can theoretically adapt to the technology of screens of various sizes.
  • LED growth backplanes include sapphire, GaN layer on Si wafer, SiC, etc. Compared with organic light-emitting display and liquid crystal display, it has the advantages of higher light efficiency, better display effect and lower power, so it has become a research hotspot in the display industry.
  • the present disclosure provides a light emitting device, a light emitting substrate and a manufacturing method of the light emitting device.
  • the light-emitting device includes: a base substrate, and at least one light-emitting structure located on one side of the base substrate; wherein, the light-emitting structure includes:
  • the light-emitting layer is located on the side of the first semiconductor layer away from the base substrate;
  • the second semiconductor layer is located on the side of the light-emitting layer away from the first semiconductor layer, and the doping ions of the second semiconductor layer and the first semiconductor layer are electrically opposite;
  • a barrier structure is located on the side of the second semiconductor layer away from the light-emitting layer, has an opening exposing the second semiconductor layer, and the orthographic projection of the opening on the base substrate is located on the light-emitting layer the layer is within the orthographic projection of the base substrate, and the area of the opening is smaller than the area of the light-emitting layer;
  • a bonding electrode, the bonding electrode is located on a side of the barrier structure away from the second semiconductor layer, and the bonding electrode is in contact with the second semiconductor layer through the opening.
  • the orthographic projection of the second semiconductor layer on the base substrate and the orthographic projection of the light-emitting layer on the base substrate approximately coincide with each other;
  • the barrier structure includes a third semiconductor layer, and a passivation layer located on a side of the third semiconductor layer away from the second semiconductor layer, and the third semiconductor layer is electrically connected to the doped ions of the second semiconductor layer. opposite; the third semiconductor layer has a first sub-opening exposing part of the second semiconductor layer, and the passivation layer has a second sub-opening exposing the third semiconductor layer and the first sub-opening;
  • the bonding electrode is in contact with the second semiconductor layer through the first sub-opening of the third semiconductor layer.
  • the orthographic projection of the second semiconductor layer on the base substrate and the orthographic projection of the light-emitting layer on the base substrate approximately coincide with each other;
  • the barrier structure includes a passivation layer; the passivation layer has a third sub-opening exposing part of the second semiconductor layer;
  • the bonding electrode is in contact with the second semiconductor layer through the third sub-opening of the passivation layer.
  • the thickness of the second semiconductor layer is 20/10000 to 40/1000 of the thickness of the first semiconductor layer.
  • the orthographic projection of the second semiconductor layer on the base substrate is located within the orthographic projection of the light emitting layer on the base substrate, and the second semiconductor layer is located in the The orthographic area of the base substrate is smaller than the orthographic area of the light-emitting layer on the base substrate;
  • the barrier structure includes a passivation layer; the passivation layer has a fourth sub-opening exposing at least part of the second semiconductor layer;
  • the bonding electrode is in contact with the second semiconductor layer through the fourth sub-opening of the passivation layer.
  • an orthographic projection of the fourth sub-opening on the base substrate and an orthographic projection of the second semiconductor layer on the base substrate approximately coincide with each other.
  • the area of the second semiconductor layer is one-fifth to four-fifths of the area of the light-emitting layer.
  • the light emitting device includes at least two light emitting structures connected in series;
  • the light emitting device further includes an encapsulation layer located on a side of the bonding electrode away from the barrier structure, and the at least two light emitting structures connected in series are integrally encapsulated by the encapsulation layer.
  • the light emitting device includes a first light emitting structure and the second light emitting structure connected in series;
  • the light emitting device further includes a bridge electrode located between the blocking structure and the bonding electrode; the first semiconductor layer of the first light emitting structure and the bonding electrode of the second light emitting structure pass through The bridge electrodes are electrically connected.
  • the barrier structure includes at least a passivation layer
  • One end of the bridge electrode is electrically connected to the first semiconductor layer of the first light emitting structure through a via hole penetrating the passivation layer, and the other end is in direct contact with the bonding electrode of the second light emitting structure electrical connection.
  • the light emitting device further includes a connection pad layer located on the side of the encapsulation layer away from the second semiconductor layer, and the connection pad layer includes: a first connecting electrode pad electrically connected to the overlapping electrodes, and a second connecting electrode pad electrically connected to the first semiconductor layer of the second light emitting structure.
  • the bonding electrode of the first light emitting structure includes a first contact portion in contact with the second semiconductor layer, a first bonding portion, and a connecting electrode connected to the first contact portion. and the first connecting portion of the first overlapping portion; the orthographic projection of the first overlapping portion on the base substrate does not overlap with the orthographic projection of the light-emitting layer on the base substrate; the The first connecting electrode pad is electrically connected to the first overlapping portion through a via hole;
  • the first semiconductor layer of the second light emitting structure has an overlapping portion overlapping the light emitting layer, and an extension extending from the overlapping portion, and the second connection electrode pad is connected to the extending portion through a via hole. internal electrical connections.
  • the light emitting device further includes a heat dissipation layer located between the encapsulation layer and the bonding electrode; the orthographic projection of the heat dissipation layer on the base substrate at least covers the first An orthographic projection of the opening of a light emitting structure on the base substrate, and an orthographic projection of the opening of the second light emitting structure on the base substrate.
  • connection pad layer further includes a heat dissipation pad connected to the heat dissipation layer, and the orthographic projection of the heat dissipation pad on the base substrate covers at least all parts of the first light emitting structure.
  • the encapsulation layer has a first encapsulation opening exposing and a second encapsulation opening; the orthographic projection of the first encapsulation opening on the base substrate covers all parts of the first light emitting structure.
  • the orthographic projection of the opening on the base substrate, the orthographic projection of the second package opening on the base substrate covers the orthographic projection of the opening of the second light emitting structure on the base substrate;
  • the heat dissipation pad is in contact with the heat dissipation layer through the first package opening and the second package opening.
  • the heat dissipation pad includes a first heat dissipation pad covering the opening of the first light emitting structure, and a second heat dissipation pad covering the opening of the second light emitting structure, and the first heat dissipation pad covers the opening of the second light emitting structure.
  • a cooling pad and the second cooling pad are integrally connected;
  • the center of the first connection electrode pad, the center of the second connection electrode pad, the center of the first heat dissipation pad, and the center of the second heat dissipation pad form a rectangle; the center of the first connection electrode pad
  • the center and the center of the second connecting electrode pad are respectively located at two vertices on the diagonal of the rectangle, and the center of the first heat dissipation pad and the center of the second heat dissipation pad are respectively located on the other side of the rectangle. Two vertices on the diagonal.
  • An embodiment of the present disclosure further provides a light-emitting substrate, which includes a driving backplane and the light-emitting device provided by the embodiment of the present disclosure disposed on one side of the driving backplane.
  • the driving backplane includes a driving structure one-to-one corresponding to the light emitting devices, and the driving structure includes a first electrode, a second electrode, and a heat dissipation electrode; wherein, the first An electrode is bound and connected to the first connection electrode, the second electrode is bound and connected to the second connection electrode, and the heat dissipation electrode is bound and connected to the heat dissipation pad.
  • the driving backplane further includes a heat dissipation connection electrode, and the heat dissipation electrodes of different driving structures are electrically connected to each other through the heat dissipation connection electrode.
  • An embodiment of the present disclosure also provides a method for manufacturing a light emitting device, including:
  • a barrier structure with an opening exposing the second semiconductor layer is formed on the side of the second semiconductor layer away from the light-emitting layer, and the orthographic projection of the opening on the base substrate is located on the side of the light-emitting layer on the In the orthographic projection of the base substrate, and the area of the opening is smaller than the area of the light-emitting layer;
  • a bonding electrode is formed on a side of the barrier structure away from the second semiconductor layer, so that the bonding electrode contacts the second semiconductor layer through the opening.
  • forming a barrier structure with an opening exposing the second semiconductor layer on the side of the second semiconductor layer away from the light-emitting layer includes:
  • a passivation layer having a second sub-opening is formed on a side of the third semiconductor layer away from the second semiconductor layer, wherein the second sub-opening exposes the third semiconductor layer and the first sub-opening .
  • forming a barrier structure with an opening exposing the second semiconductor layer on the side of the second semiconductor layer away from the light-emitting layer includes:
  • the passivation layer is patterned to form a third sub-opening exposing part of the second semiconductor layer, so that the bonding electrode contacts the second semiconductor layer through the third sub-opening.
  • the forming the second semiconductor layer on a side of the light-emitting layer away from the first semiconductor layer includes: forming a second semiconductor layer on a side of the light-emitting layer away from the first semiconductor layer
  • the second semiconductor layer formed on the orthographic projection of the base substrate is located in the orthographic projection of the light-emitting layer on the base substrate, and the orthographic projection area of the second semiconductor layer on the base substrate is smaller than The orthographic projection area of the luminescent layer on the base substrate;
  • the formation of a barrier structure with an opening exposing the second semiconductor layer on the side of the second semiconductor layer away from the light-emitting layer includes:
  • FIG. 1 is one of the cross-sectional schematic diagrams of a light emitting device provided by an embodiment of the present disclosure
  • Fig. 2 is the second schematic cross-sectional view of a light emitting device provided by an embodiment of the present disclosure
  • Fig. 3 is a third schematic cross-sectional view of a light emitting device provided by an embodiment of the present disclosure
  • connection pad layer provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a light-emitting substrate provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic top view of a driving backplane provided by an embodiment of the present disclosure.
  • Fig. 7 is a schematic diagram of the manufacturing process of the light emitting device provided by the embodiment of the present disclosure.
  • FIG. 8A is a schematic cross-sectional view after forming the second semiconductor layer 22;
  • FIG. 8B is a top view of a single film layer of the light-emitting layer 3;
  • FIG. 8C is a top view of a single film layer of the second semiconductor layer 22;
  • FIG. 9A is a schematic cross-sectional view after forming the third semiconductor layer 41:
  • FIG. 9B is a top view of a single film layer of the third semiconductor layer 41.
  • FIG. 10A is a schematic cross-sectional view after forming the bonding electrode 6;
  • FIG. 10B is a top view of a single film layer of the passivation layer 42;
  • FIG. 10C is a top view of a single film layer of the bridge electrode 5;
  • FIG. 10D is a top view of a single film layer of the bonding electrode 6;
  • FIG. 11A is a schematic cross-sectional view after the encapsulation layer 73 is formed
  • FIG. 11B is a top view of a single film layer of the reflective layer 71;
  • FIG. 11C is a top view of a single film layer of the heat dissipation layer 72;
  • FIG. 11D is a top view of a single film layer of the encapsulation layer 73;
  • FIG. 12A is a schematic cross-sectional view of FIG. 12C along the dotted line E1F1;
  • FIG. 12B is a top view of a single film layer connecting the pad layer 8;
  • Figure 12C is one of the top views of the overall light emitting device
  • FIG. 13A is a schematic cross-sectional view of FIG. 13B along the dotted line E2F2;
  • Figure 13B is the second top view of the overall light emitting device
  • FIG. 14A is a schematic cross-sectional view of FIG. 14B along the dotted line E3F3;
  • Figure 14B is the third top view of the overall light emitting device
  • FIG. 15A is a schematic cross-sectional view of FIG. 15B along the dotted line E4F4;
  • Fig. 15B is the fourth top view of the overall light emitting device.
  • an embodiment of the present disclosure provides a light-emitting device, including: a base substrate 1, and at least one light-emitting structure P located on one side of the base substrate 1; wherein, The light emitting structure P includes:
  • Light-emitting layer 3 the light-emitting layer 3 is positioned at the side of the first semiconductor layer 21 away from the base substrate 1; specifically, the light-emitting layer can be a multiple quantum well layer (MQW, Multiple Quantum Well); the base substrate 1 is used for growing semiconductor layers and Light-emitting layer, for example, the base substrate 1 can be a sapphire substrate;
  • MQW Multiple Quantum Well
  • the base substrate 1 is used for growing semiconductor layers and Light-emitting layer, for example, the base substrate 1 can be a sapphire substrate;
  • the second semiconductor layer 22, the second semiconductor layer 22 is located on the side of the light-emitting layer 3 away from the first semiconductor layer 21, and the doping ions of the second semiconductor layer 22 and the first semiconductor layer 21 are electrically opposite; specifically, for example, the second semiconductor layer A semiconductor layer 21 can be an n-doped semiconductor layer, and the second semiconductor layer 22 can be a p-doped semiconductor layer; specifically, the material of the first semiconductor layer 21 can be n-doped GaN, and the material of the second semiconductor layer 22 can be is p-doped GaN;
  • the barrier structure 4 is located on the side of the second semiconductor layer 22 facing away from the light-emitting layer 3, and has an opening K exposing the second semiconductor layer 22, the orthographic projection of the opening K on the base substrate 1 is located on the base substrate of the light-emitting layer 3 1, and the area of the opening K is smaller than the area of the light emitting layer 3;
  • the bonding electrode 6 is located on the side of the barrier structure 4 facing away from the second semiconductor layer 22 , and the bonding electrode 6 is in contact with the second semiconductor layer 22 through the opening K.
  • the side of the second semiconductor layer 22 facing away from the light-emitting layer 3 has a barrier structure 4, the barrier structure 4 has an opening K exposing the second semiconductor layer 22, and the orthographic projection of the opening K on the base substrate 1 is located in the light-emitting layer.
  • the bonding electrode 6 is in contact with the second semiconductor layer 22 through the opening K, and the barrier structure 4 exposes the opening K of the second semiconductor layer 22 , forming an effective light-emitting area, the area of which is smaller than the area of the original light-emitting layer 3, so as to reduce the light-emitting area of the light-emitting device, and under the same gray-scale voltage applied, the light-emitting efficiency of the light-emitting device can be improved. Reduce the power consumption of light-emitting devices on the basis of maintaining excellent display quality.
  • the barrier structure 4 can be formed in different ways, and the following specific examples are given respectively:
  • the barrier structure 4 includes The third semiconductor layer 41, and the passivation layer 42 located on the side of the third semiconductor layer 1 away from the second semiconductor layer 22, the doping ions of the third semiconductor layer 41 and the second semiconductor layer 22 are electrically opposite; specifically, for example , when the second semiconductor layer 22 is an n-doped semiconductor layer, the third semiconductor layer 41 can specifically be a p-doped semiconductor layer, further, when the material of the second semiconductor layer 22 can be n-doped GaN, the third semiconductor layer The material of 41 may specifically be p-doped GaN; the third semiconductor layer 41 has a first sub-opening K1 exposing part of the second semiconductor layer 22, and the passivation layer 42 has a first sub-opening K1 exposing the third semiconductor layer 22 and the first sub-opening K1.
  • the bonding electrode 6 is in contact with the second semiconductor layer 22 through the first sub-opening K1 of the third semiconductor layer 41 .
  • the third semiconductor layer 41 and the second semiconductor layer 22 form a reverse PN junction, thereby The flow of carriers (for example, electrons) is blocked, so that the region where the first sub-opening K1 is located forms an effective light-emitting region, thereby reducing the light-emitting region of the light-emitting device.
  • the third semiconductor layer 41 may be an electron blocking layer.
  • the orthographic projection of the second semiconductor layer 22 on the base substrate 1 and the orthographic projection of the light emitting layer 3 on the base substrate 1 roughly coincide with each other; the barrier structure 4
  • the passivation layer 42 is included; the passivation layer 42 has a third sub-opening K3 exposing part of the second semiconductor layer 22 ; the bonding electrode 6 is in contact with the second semiconductor layer 22 through the third sub-opening K2 of the passivation layer 42 .
  • the control of the effective light-emitting area is realized, and the method of reducing the light-emitting area is relatively simple and easy to implement.
  • the thickness of the second semiconductor layer 22 is 20 to 40/1000 of the thickness of the first semiconductor layer.
  • the thickness of the second semiconductor layer 22 is one thousandth of the thickness of the first semiconductor layer. 20 to 40/1000, can avoid excessive lateral diffusion of current in the second semiconductor layer 22, and enter the light-emitting layer 3 as soon as possible, so as to have higher luminous efficiency.
  • the orthographic projection of the second semiconductor layer 22 on the base substrate 1 is located within the orthographic projection of the light emitting layer 3 on the base substrate 1, and the second semiconductor layer 22 is located on the base substrate 1
  • the orthographic area of the light-emitting layer 3 is smaller than the orthographic area of the base substrate 1;
  • the barrier structure 4 includes a passivation layer 42;
  • the passivation layer 42 has a fourth sub-opening K4 that exposes at least part of the second semiconductor layer 22;
  • the bonding electrode 6 is in contact with the second semiconductor layer 22 through the fourth sub-opening K2 of the passivation layer 42.
  • the effective light-emitting area can be reduced only by reducing the area of the second semiconductor layer 22.
  • Orthographic projections of the semiconductor layers 22 on the base substrate 1 roughly coincide with each other.
  • the orthographic projection of the semiconductor layer 22 on the base substrate 1 can further reduce the effective light emitting area.
  • the area of the second semiconductor layer 22 is one-fifth to four-fifths of the area of the light-emitting layer 3 .
  • the area of the second semiconductor layer 22 is one-fifth to four-fifths of the area of the light-emitting layer 3, and the effective light-emitting area can be reduced while reducing the area of the second semiconductor layer 22. , to avoid too small effective light-emitting area and too small light output, which will affect the normal use of light-emitting devices.
  • the light-emitting device includes at least two light-emitting structures P connected in series;
  • the encapsulation layer 73 , at least two light emitting structures P connected in series are integrally encapsulated by the encapsulation layer 73 .
  • the light-emitting device includes at least two light-emitting structures P connected in series. This light-emitting device is equivalent to two light-emitting structures connected in series in the current path of VDD ⁇ VSS in the active light-emitting diode drive circuit.
  • the light-emitting device has a higher cross-voltage, which reduces the voltage of the transistor in the driving circuit and forms a high-voltage light-emitting device, which can greatly reduce the cost of the light-emitting device, reduce the current of the line, and reduce power consumption.
  • the light-emitting device includes a first light-emitting structure P1 and a second light-emitting structure P2 connected in series;
  • the bridge electrode 5 between the electrodes 6; the first semiconductor layer 21 of the first light emitting structure P1 and the overlapping electrode 6 of the second light emitting structure P2 are electrically connected through the bridge electrode 6, thereby realizing the connection of different light emitting structures P in series.
  • the barrier structure 4 includes at least a passivation layer 42; one end of the bridge electrode 5 passes through the via hole penetrating the passivation layer 42 and the first semiconductor layer of the first light emitting structure P1. 21, and the other end is in direct contact with and electrically connected to the bonding electrode 6 of the second light emitting structure P2.
  • the light-emitting device further includes a connection pad layer 8 located on the side of the encapsulation layer 73 away from the second semiconductor layer 22.
  • the connection pad layer 8 includes: The first connection electrode pad 81 electrically connected to the bonding electrode 6 of the first light emitting structure P1, and the second connection electrode pad 82 electrically connected to the first semiconductor layer 21 of the second light emitting structure P2. Different electrode terminals of the two light emitting structures P are drawn out.
  • the bonding electrode 6 of the first light emitting structure P1 includes a first contact portion 61 in contact with the second semiconductor layer 22 , and the first bonding electrode 6 portion 62, and the first connecting portion 63 connecting the first contact portion 61 and the first overlapping portion 62; the orthographic projection of the first overlapping portion 62 on the base substrate 1 and the orthographic projection of the light emitting layer 3 on the base substrate 1 Do not overlap; the first connecting electrode pad 81 is electrically connected to the first overlapping part 62 through a via hole, so that the lead-out position of the overlapping electrode 6 in the first light emitting structure P1 is moved out of the effective light emitting area, thereby improving the light extraction efficiency;
  • the first semiconductor layer 21 of the second light emitting structure P2 has an overlapping portion 211 overlapping with the light emitting layer 3, and an extending portion 212 extending from the overlapping portion 211, the second connecting electrode pad 82 is electrically connected to
  • the proportion of via holes will increase.
  • the light extraction efficiency of the light-emitting structure P will decrease instead.
  • the light-emitting efficiency of the light-emitting structure P can be improved after reducing the effective light-emitting area of the light-emitting member P. The problem that efficiency may be reduced.
  • the light emitting device further includes a heat dissipation layer 72 located between the encapsulation layer 73 and the bonding electrode 6; the orthographic projection of the heat dissipation layer 72 on the base substrate 1 covers at least the opening K of the first light emitting structure P1.
  • the light emitting device further includes a heat dissipation layer 72 located between the encapsulation layer 73 and the bonding electrode 6 , which can effectively dissipate heat generated by the light emitting structure P.
  • connection pad layer 8 further includes a heat dissipation pad 83 connected to the heat dissipation layer 72, and the orthographic projection of the heat dissipation pad 83 on the base substrate 1 at least covers the opening K1 of the first light emitting structure P1 on the substrate.
  • the orthographic projection of the base substrate 1 and the orthographic projection of the opening covering the second light emitting structure P2 on the base substrate 1 After reducing the effective light-emitting area of the light-emitting structure P, although the light efficiency of the light-emitting structure P is improved, the hot spots are also more concentrated, and the heat is easier to gather in the light-emitting area.
  • the conductive heat dissipation pad 83 can quickly and effectively dissipate the heat generated by the light-emitting structure P after the effective light-emitting area is reduced, reduce the junction temperature of the light-emitting structure P, and avoid the reduction of light efficiency or the burning of the light-emitting structure P.
  • the encapsulation layer 73 has the first encapsulation opening F1 exposed and the second encapsulation opening F2; the orthographic projection of the first encapsulation opening F1 on the base substrate 1 covers the opening K of the first light emitting structure P1 in The orthographic projection of the base substrate 1, the orthographic projection of the second package opening F2 on the base substrate 1 covers the orthographic projection of the opening K of the second light emitting structure P2 on the base substrate 1; the heat dissipation pad 83 passes through the first package opening F1, the second The second packaging opening F2 is in contact with the heat dissipation layer 72 .
  • the heat dissipation pad 83 is connected to the heat dissipation layer 72 at the position of the effective light emitting area, and the length of the heat dissipation channel can be shortened. , so that the heat generated by the light-emitting structure P can be dissipated quickly and effectively.
  • the heat dissipation pad 83 includes a first heat dissipation pad 831 covering the opening K of the first light emitting structure P1, and a second heat dissipation pad 832 covering the opening K of the second light emitting structure P2,
  • the first heat dissipation pad 831 and the second heat dissipation pad 832 are integrally connected;
  • the center O1 of the first connection electrode pad 81, the center O2 of the second connection electrode pad 82, the center O3 of the first heat dissipation pad 831, and the center of the second heat dissipation pad 832 O4 encloses a rectangle;
  • the center O1 of the first connection electrode pad 81 and the center O2 of the second connection electrode pad 82 are respectively located at the two vertices on the diagonal k1 of the rectangle, the center O3 of the first heat dissipation pad 831, the center O2 of the second The center O4 of the heat dissipation pad
  • a reflective layer 71 between the heat dissipation layer 8 and the bonding electrode 6 .
  • a reflective layer 71 is required, which can be a Bragg reflector (DBR-distributed Bragg reflection).
  • the base substrate 1 improves the light output of the light-emitting structure 1.
  • the reflective layer 71 can use superimposed SiO2 and TiO2 to form a 1/4 wavelength reflector for the required light.
  • an embodiment of the present disclosure further provides a light-emitting substrate, which includes a driving backplane 200 and a light-emitting device provided on one side of the driving backplane 200 as provided in the embodiment of the present disclosure.
  • the driving backplane 200 includes a driving structure 23 that corresponds to the light emitting device one-to-one.
  • the driving structure 23 includes a first electrode 231, a second electrode 232, and a heat sink. Electrodes 233; wherein, the first electrode 231 is bound and connected to the first connecting electrode pad 81, the second electrode 232 is bound and connected to the second connecting electrode pad 82, and the heat dissipation electrode 233 is bound and connected to the heat dissipation pad 83.
  • the driving backplane 200 further includes a heat dissipation connection electrode 234 , and the heat dissipation electrodes 233 of different driving structures 23 are electrically connected to each other through the heat dissipation connection electrode 234 .
  • the driving backplane 200 may further include a driving substrate 21, the driving structure 23 is located on one side of the driving substrate 21, and a
  • the driving layer 22, specifically, the driving layer 22 may be a composite layer including a plurality of film layers.
  • the driving layer 22 may include: a first power line 221 , a second power line 222 , and a driving circuit 223 .
  • the first power line 221 may specifically be a VDD power line
  • the second power line 222 may specifically be a VSS power line.
  • the driving power 223 may specifically include thin film transistors and capacitors.
  • an embodiment of the present disclosure further provides a method for manufacturing a light emitting device, which includes:
  • Step S100 forming a first semiconductor layer on one side of the base substrate
  • Step S200 forming a light-emitting layer on the side of the first semiconductor layer away from the base substrate;
  • Step S300 forming a second semiconductor layer on the side of the light-emitting layer away from the first semiconductor layer;
  • Step S400 forming a barrier structure with an opening exposing the second semiconductor layer on the side of the second semiconductor layer away from the light-emitting layer, the orthographic projection of the opening on the base substrate is located within the orthographic projection of the light-emitting layer on the base substrate, and the orthographic projection of the opening is The area is smaller than the area of the light-emitting layer;
  • Step S500 forming a bonding electrode on a side of the barrier structure away from the second semiconductor layer, so that the bonding electrode contacts the second semiconductor layer through the opening.
  • the effective light-emitting area can be reduced by forming the third semiconductor layer 42, specifically, regarding step S400, that is, forming a second A barrier structure for an opening in a semiconductor layer, comprising:
  • Step S411 forming a third semiconductor layer on the side of the second semiconductor layer facing away from the light-emitting layer, where the doping ions of the third semiconductor layer are electrically opposite to those of the second semiconductor layer;
  • Step S412 patterning the third semiconductor layer to form a first sub-opening exposing part of the second semiconductor layer
  • Step S413 forming a passivation layer with a second sub-opening on the side of the third semiconductor layer facing away from the second semiconductor layer, wherein the second sub-opening exposes the third semiconductor layer and the first sub-opening.
  • the effective light-emitting area can be reduced by adjusting the opening size of the passivation layer.
  • a The barrier structure of the opening of the second semiconductor layer including:
  • Step S421 forming a passivation layer on the side of the second semiconductor layer away from the light-emitting layer;
  • Step S422 patterning the passivation layer to form a third sub-opening exposing part of the second semiconductor layer, so that the bonding electrode contacts the second semiconductor layer through the third sub-opening.
  • the effective light-emitting area can be reduced by adjusting the area of the second semiconductor layer.
  • step S300 that is, forming the second semiconductor layer on the side of the light-emitting layer away from the first semiconductor layer layer, comprising: a second semiconductor layer formed on the side of the light-emitting layer away from the first semiconductor layer in the orthographic projection of the base substrate and located in the orthographic projection of the light-emitting layer on the base substrate, and the second semiconductor layer is formed on the base substrate
  • the area of the orthographic projection of the light-emitting layer is smaller than the area of the orthographic projection of the light-emitting layer on the base substrate;
  • step S400 forming a barrier structure with an opening exposing the second semiconductor layer on the side of the second semiconductor layer away from the light-emitting layer includes:
  • Step S431 forming a passivation layer on the side of the second semiconductor layer away from the light-emitting layer;
  • Step S432 pattern the passivation layer to form a fourth sub-opening exposing the second semiconductor layer, so that the bonding electrode contacts the second semiconductor layer through the fourth sub-opening, wherein the fourth sub-opening is in the substrate.
  • Step 1 Prepare the base film layer of the light-emitting structure P on the base substrate 1 (for example, a sapphire substrate).
  • the preparation method can specifically be a conventional LED chip manufacturing process, which will not be repeated here, including the preparation of n-GaN (as the first semiconductor layer 21), quantum well (MQW, as the light-emitting layer 3), and p-GaN (as the second semiconductor layer 22), as shown in Fig. 8A, Fig. 8B, and Fig. 8C, wherein Fig. 8A is the A schematic cross-sectional view of the layer 22, FIG. 8B is a top view of a single film layer of the light-emitting layer 3, and FIG. 8C is a top view of a single film layer of the second semiconductor layer 22;
  • Step 2 make the third semiconductor layer 41 (electron blocking layer), and form the opening K defining the light-emitting region.
  • the electron blocking layer is n-doped GaN or other materials.
  • the electron blocking layer and p-GaN A reverse PN junction is formed to block the flow of electrons, and the opening K of the electron blocking layer emits light normally, thereby defining the size of the light-emitting area, as shown in Figure 9A and Figure 9B, and the opening K in Figure 9B is the effective LED.
  • FIG. 9A is a schematic cross-sectional view after forming the third semiconductor layer 41
  • FIG. 9B is a top view of a single film layer of the third semiconductor layer 41;
  • Step 3 Make a passivation layer 42, make bridge electrodes 5 and lap electrodes 6, and connect the light-emitting structures P on both sides.
  • This step is to make two sub-LEDs (light-emitting structures P) connected in series inside the same LED (light-emitting device), After all connections are completed, the n-electrode of the left sub-LED will be connected to the p-electrode of the right sub-LED to form a high-voltage LED (this kind of LED is equivalent to connecting two LEDs in series in the current path of VDD ⁇ VSS in the AMLED drive circuit.
  • the cross-voltage obtained is higher, so it becomes a high-voltage LED); the lapping electrode 6 (the specific material can be indium tin oxide), the lapping electrode 6 is lapped through the bridge electrode 5 to form a potential connection, and the left side
  • the bonding electrode 6 connecting the LED to the p-electrode is extended beyond the light-emitting area, so that the via hole 711 of the p-electrode on the reflective layer 71 is kept away from the light-emitting area to avoid affecting the light output of the LED, as shown in Figures 10A, 10B, 10C, and 10D.
  • 10A is a schematic cross-sectional view after forming the bonding electrode 6, FIG.
  • FIG. 10B is a top view of a single film layer of the passivation layer 42
  • FIG. 10C is a top view of a single film layer of the bridge electrode 5
  • FIG. 10D is a top view of the bonding electrode 6. The top view of the single film layer;
  • Step 4 make reflective layer 71, when LED works, the light that goes out of quantum well (light-emitting layer 3) has about 50% light away from substrate substrate 1 (sapphire) surface, therefore need reflective layer 71 (specifically can be Bragg reflector DBR-distributed Bragg reflection, a distributed Bragg reflector, reflects the away light back to the sapphire surface, and improves the light output of the LED.
  • reflective layer 71 specifically can be Bragg reflector DBR-distributed Bragg reflection, a distributed Bragg reflector, reflects the away light back to the sapphire surface, and improves the light output of the LED.
  • the 1/4 wavelength reflector of the required light can be composed of superimposed SiO2 and TiO2; however, conventional LEDs are connected to the p-electrode In this case, it is necessary to overlap the p-GaN via hole formed by etching the DBR in the light-emitting area, and the metal of the p-electrode will absorb part of the photons, thereby reducing the light extraction rate.
  • the light output of the LED decreases instead.
  • FIG. 11A is a schematic cross-sectional view after forming the encapsulation layer 73, FIG.
  • FIG. 11B is a top view of a single film layer of the reflective layer 71
  • FIG. 11C is a top view of a single film layer of the heat dissipation layer 72
  • FIG. 11D is A top view of a single film layer of the encapsulation layer 73;
  • Step 5 complete the production of the connection pad layer 8, connect the heat dissipation layer 72 facing the opening K through the first packaging via hole F1 and the second packaging via hole F2 of the packaging layer 73 to form a heat dissipation channel, and connect the corresponding electrodes to form n
  • the p-electrode is electrically connected, as shown in Figure 12A, Figure 12B, and Figure 12C, wherein Figure 12A is a schematic cross-sectional view after forming the connection pad layer 8, Figure 12B is a top view of a single film layer of the connection pad layer 8, and Figure 12C is the overall For the top view of the light emitting device, FIG. 12A may be a schematic cross-sectional view of FIG. 12C along the dotted line E1F1.
  • the size of the effective light-emitting region can be controlled by adjusting the size of the third sub-opening of the passivation layer 3.
  • This embodiment can reduce the thickness of p-GaN and avoid current flow in p-GaN Excessive lateral diffusion, enter the quantum well as soon as possible; the via area of the third sub-opening K3 of the passivation layer 41 is the overlapping area of the overlapping electrode 6 and p-GaN, that is, the effective light-emitting area.
  • the schematic cross-sectional view behind the pad layer 8, the top view of the overall light-emitting device in Figure 13B, and Figure 13A can be a schematic cross-sectional view along the dotted line E2F2 in Figure 13B; No longer.
  • the area of the second semiconductor layer 22 is reduced by etching to limit the effective light-emitting area; in specific implementation, it can avoid the formation and p-GaN caused by etching the quantum well layer.
  • the structure of GaN is aligned to avoid that if the edges are aligned, leakage channels will be formed through the destroyed lattice structure of p-GaN, quantum wells, and n-GaN edges, thereby reducing the light extraction efficiency of the LED.
  • Figure 14A is the connection A schematic cross-sectional view behind the pad layer 8, a top view of the overall light-emitting device in Figure 14B, and Figure 14A can be a schematic cross-sectional view along the dotted line E3F3 in Figure 14B; No longer.
  • the 8th page of the connecting electrode pad layer may not form a heat dissipation pad 83, so as to increase the third semiconductor layer (electron blocking layer, current blocker, CB) to reduce the effective light-emitting area, and to make a driving backplane
  • Figure 15A is a schematic cross-sectional view after forming the connection pad layer 8
  • Figure 15B is a top view of the overall light-emitting device
  • Figure 15A 15A may be a schematic cross-sectional view along the dotted line E4F4 in FIG. 15B
  • the manufacturing process of the specific film layer may be similar to that of the above-mentioned embodiments, and details will not be repeated here in the embodiments of the present disclosure.
  • the side of the second semiconductor layer 22 facing away from the light-emitting layer 3 has a barrier structure 4, and the barrier structure 4 has an opening K exposing the second semiconductor layer 22, and the opening K is on the substrate.
  • the orthographic projection of the substrate 1 is located within the orthographic projection of the light emitting layer 3 on the base substrate 1, and the area of the opening K is smaller than the area of the light emitting layer 3, the bonding electrode 6 is in contact with the second semiconductor layer 22 through the opening K, and the barrier structure 4 is exposed
  • the opening K of the second semiconductor layer 22 forms an effective light-emitting area.
  • the area of the effective light-emitting area is smaller than the area of the original light-emitting layer 3, so as to reduce the light-emitting area of the light-emitting device. Under the same gray-scale voltage applied, it can Improve the light extraction efficiency of the light-emitting device, and reduce the power consumption of the light-emitting device on the basis of maintaining excellent display quality.

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Abstract

一种发光器件、发光基板和发光器件的制作方法。该发光器件包括至少一个发光结构，发光结构包括：第一半导体层（21）；发光层（3）；第二半导体层（22）；第二半导体层（22）与第一半导体层（21）的掺杂离子电性相反；阻隔结构（4），具有暴露第二半导体层（22）的开口，该开口在衬底基板（1）的正投影位于发光层（3）在衬底基板（1）的正投影内，且开口的面积小于发光层（3）的面积；搭接电极（6），其位于阻隔结构（4）背离第二半导体层（22）的一侧，搭接电极（6）通过开口与第二半导体层（22）接触。

Description

发光器件、发光基板和发光器件的制作方法
相关申请的交叉引用
本申请要求在2021年05月31日提交中国专利局、申请号为202110603573.3、申请名称为“发光器件、发光基板和发光器件的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种发光器件、发光基板和发光器件的制作方法。
背景技术
发光二极管(Light-Emitting Diode，LED)显示是指将传统LED阵列化、微缩化后定址巨量转移到电路基板上，形成超小间距LED，将毫米级别的LED长度进一步微缩到微米级，以达到超高像素、超高解析率，理论上能够适应各种尺寸屏幕的技术，一般LED生长背板有蓝宝石、Si片上的GaN层，SiC等。相对有机发光显示和液晶显示，其具有光效更高、显示效果更好、功率更低的优点，因此成为显示行业的研究热点。
发明内容
本公开提供一种发光器件、发光基板和发光器件的制作方法。所述发光器件，包括：衬底基板，以及位于所述衬底基板一侧的至少一个发光结构；其中，所述发光结构包括：
第一半导体层；
发光层，所述发光层位于所述第一半导体层背离所述衬底基板的一侧；
第二半导体层,所述第二半导体层位于所述发光层背离所述第一半导体层的一侧，所述第二半导体层与所述第一半导体层的掺杂离子电性相反；
阻隔结构，所述阻隔结构位于所述第二半导体层背离所述发光层的一侧，具有暴露所述第二半导体层的开口，所述开口在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述开口的面积小于所述发光层的面积；
搭接电极，所述搭接电极位于所述阻隔结构背离所述第二半导体层的一侧，所述搭接电极通过所述开口与所述第二半导体层接触。
在一种可能的实施方式中，所述第二半导体层在所述衬底基板的正投影与所述发光层在所述衬底基板的正投影大致互相重合；
所述阻隔结构包括第三半导体层，以及位于所述第三半导体层背离所述第二半导体层一侧的钝化层，所述第三半导体层与所述第二半导体层的掺杂离子电性相反；所述第三半导体层具有暴露部分所述第二半导体层的第一子开口，所述钝化层具有暴露所述第三半导体层以及所述第一子开口的第二子开口；
所述搭接电极通过所述第三半导体层的所述第一子开口与所述第二半导体层接触。
在一种可能的实施方式中，所述第二半导体层在所述衬底基板的正投影与所述发光层在所述衬底基板的正投影大致互相重合；
所述阻隔结构包括钝化层；所述钝化层具有暴露部分所述第二半导体层的第三子开口；
所述搭接电极通过所述钝化层的所述第三子开口与所述第二半导体层接触。
在一种可能的实施方式中，所述第二半导体层的厚度为所述第一半导体层厚度的千分之二十至千分之四十。
在一种可能的实施方式中，所述第二半导体层在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述第二半导体层在所述衬底基板的正投影面积小于所述发光层在所述衬底基板的正投影面积；
所述阻隔结构包括钝化层；所述钝化层具有暴露至少部分所述第二半导 体层的第四子开口；
所述搭接电极通过所述钝化层的所述第四子开口与所述第二半导体层接触。
在一种可能的实施方式中，所述第四子开口在所述衬底基板的正投影与所述第二半导体层在所述衬底基板的正投影大致互相重合。
在一种可能的实施方式中，所述第二半导体层的面积为所述发光层面积的五分之一至五分之四。
在一种可能的实施方式中，所述发光器件包括至少两个相互串联的所述发光结构；
所述发光器件还包括位于所述搭接电极背离所述阻隔结构一侧的封装层，所述至少两个相互串联的所述发光结构通过所述封装层一体封装。
在一种可能的实施方式中，所述发光器件包括相互串联的第一发光结构和所述第二发光结构；
所述发光器件还包括位于所述阻隔结构与所述搭接电极之间的桥电极；所述第一发光结构的所述第一半导体层和所述第二发光结构的所述搭接电极通过所述桥电极电连接。
在一种可能的实施方式中，所述阻隔结构至少包括钝化层；
所述桥电极的一端通过贯穿所述钝化层的过孔与所述第一发光结构的所述第一半导体层电连接，另一端与所述第二发光结构的所述搭接电极直接接触电连接。
在一种可能的实施方式中，所述发光器件还包括位于所述封装层背离所述第二半导体层一侧的连接垫层，所述连接垫层包括：与所述第一发光结构的所述搭接电极电连接的第一连接电极垫，以及与所述第二发光结构的所述第一半导体层电连接的第二连接电极垫。
在一种可能的实施方式中，所述第一发光结构的所述搭接电极包括与所述第二半导体层接触的第一接触部，第一搭接部，以及连接所述第一接触部和所述第一搭接部的第一连接部；所述第一搭接部在所述衬底基板的正投影 与所述发光层在所述衬底基板的正投影不交叠；所述第一连接电极垫通过过孔与所述第一搭接部电连接；
所述第二发光结构的所述第一半导体层具有与所述发光层重叠的重叠部，以及由所述重叠部延伸出的延伸部，所述第二连接电极垫通过过孔与所述延伸部电连接。
在一种可能的实施方式中，所述发光器件还包括位于所述封装层与所述搭接电极之间的散热层；所述散热层在所述衬底基板的正投影至少覆盖所述第一发光结构的所述开口在所述衬底基板的正投影，以及所述第二发光结构的所述开口在所述衬底基板的正投影。
在一种可能的实施方式中，所述连接垫层还包括与所述散热层导通的散热垫，所述散热垫在所述衬底基板的正投影至少覆盖所述第一发光结构的所述接开口在所述衬底基板的正投影，以及覆盖所述第二发光结构的所述开口在所述衬底基板的正投影。
在一种可能的实施方式中，所述封装层具有暴露第一封装开口，以及第二封装开口；所述第一封装开口在所述衬底基板的正投影覆盖所述第一发光结构的所述开口在所述衬底基板的正投影，所述第二封装开口在所述衬底基板的正投影覆盖所述第二发光结构的所述开口在所述衬底基板的正投影；
所述散热垫通过所述第一封装开口、所述第二封装开口与所述散热层接触。
在一种可能的实施方式中，所述散热垫包括覆盖所述第一发光结构所述开口的第一散热垫，以及覆盖所述第二发光结构所述开口的第二散热垫，所述第一散热垫、所述第二散热垫一体连接；
所述第一连接电极垫的中心、所述第二连接电极垫的中心、所述第一散热垫的中心、所述第二散热垫的中心围成一矩形；所述第一连接电极垫的中心、所述第二连接电极垫的中心分别位于所述矩形一对角线上的两个顶点，所述第一散热垫的中心、所述第二散热垫的中心分别位于所述矩形另一对角线上两个顶点。
在一种可能的实施方式中，所述散热层与所述搭接电极之间还具有反射层。
本公开实施例还提供一种发光基板，其中，包括驱动背板以及设置于所述驱动背板一侧的如本公开实施例提供的所述发光器件。
在一种可能的实施方式中，所述驱动背板包括与所述发光器件一一对应的驱动结构，所述驱动结构包括第一电极，第二电极，以及散热电极；其中，所述第一电极与所述第一连接电极绑定连接，所述第二电极与所述第二连接电极绑定连接，所述散热电极与所述散热垫绑定连接。
在一种可能的实施方式中，所述驱动背板还包括散热连接电极，不同所述驱动结构的所述散热电极通过所述散热连接电极相互电连接。
本公开实施例还提供一种发光器件的制作方法，其中，包括：
在衬底基板的一侧形成第一半导体层；
在所述第一半导体层背离所述衬底基板的一侧形成发光层；
在所述发光层的背离所述第一半导体层的一侧形成第二半导体层；
在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，所述开口在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述开口的面积小于所述发光层的面积；
在所述阻隔结构背离所述第二半导体层的一侧形成搭接电极，以使所述搭接电极通过所述开口与所述第二半导体层接触。
在一种可能的实施方式中，所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
在所述第二半导体层背离所述发光层的一侧形成第三半导体层，所述第三半导体层与所述第二半导体层的掺杂离子电性相反；
对所述第三半导体层进行图案化，以形成暴露部分所述第二半导体层的第一子开口；
在所述第三半导体层背离所述第二半导体层的一侧形成具有第二子开口的钝化层，其中，所述第二子开口暴露所述第三半导体层以及所述第一子开 口。
在一种可能的实施方式中，所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
在所述第二半导体层背离所述发光层的一侧形成钝化层；
对所述钝化层进行图案化，以形成暴露部分所述第二半导体层的第三子开口，以使所述搭接电极通过所述第三子开口与所述第二半导体层接触。
在一种可能的实施方式中，所述在所述发光层的背离所述第一半导体层的一侧形成第二半导体层，包括：在所述发光层的背离所述第一半导体层的一侧形成在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内的第二半导体层，且所述第二半导体层在所述衬底基板的正投影面积小于所述发光层在所述衬底基板的正投影面积；
所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
在所述第二半导体层背离所述发光层的一侧形成钝化层；
对所述钝化层进行图案化，以形成暴露所述第二半导体层的第四子开口，以使所述搭接电极通过所述第四子开口与所述第二半导体层接触，其中，所述第四子开口在所述衬底基板的正投影与所述第二半导体层在所述衬底基板的正投影大致互相重合。
附图说明
图1为本公开实施例提供的发光器件的剖视示意图之一；
图2为本公开实施例提供的发光器件的剖视示意图之二；
图3为本公开实施例提供的发光器件的剖视示意图之三；
图4为本公开实施例提供的连接垫层的俯视示意图；
图5为本公开实施例提供的发光基板的剖视示意图；
图6为本公开实施例提供的驱动背板的俯视示意图；
图7为本公开实施例提供的发光器件的制作流程示意图；
图8A为形成第二半导体层22后的剖视示意图；
图8B为发光层3的单膜层俯视图；
图8C为第二半导体层22的单膜层俯视图；
图9A为形成第三半导体层41后的剖视示意图：
图9B为第三半导体层41的单膜层俯视图；
图10A为形成搭接电极6后的剖视示意图；
图10B为钝化层42的单膜层俯视图；
图10C为桥电极5的单膜层俯视图；
图10D为搭接电极6的单膜层俯视图；
图11A为形成封装层73后的剖视示意图；
图11B为反射层71的单膜层俯视图；
图11C为散热层72的单膜层俯视图；
图11D为封装层73的单膜层俯视图；
图12A为图12C沿虚线E1F1的截面示意图；
图12B为连接垫层8的单膜层俯视图；
图12C为整体发光器件的俯视图之一；
图13A为图13B沿虚线E2F2的截面示意图；
图13B整体发光器件的俯视图之二；
图14A为图14B沿虚线E3F3的截面示意图；
图14B整体发光器件的俯视图之三；
图15A为图15B沿虚线E4F4的截面示意图；
图15B整体发光器件的俯视图之四。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基 于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
对LED的光电特性测试发现，LED的光效和通过LED发光区域电流的密度存在如图一所示关系。LED光效随电流密度提高而升高，达到一定程度后呈光效饱和趋势。进一步的，对比现阶段主流显示画面所需灰阶发现，目前LED显示面板对LED的光效应用远远没有达到LED的高效发光区域。如图一所示，如果将L255的发光区域降低为25％，LED的光效提升约20％，相应的，可以在保持优秀显示画质的基础上降低LED背板的功耗。据此，通过一定方式降低LED的发光面积，提升电流密度以提升光效成为降低LED显示面板功耗的新思路。
有鉴于此，参见图1、图2、图3所示，本公开实施例提供一种发光器件，包括：衬底基板1，以及位于衬底基板1一侧的至少一个发光结构P；其中，发光结构P包括：
第一半导体层21；
发光层3，发光层3位于第一半导体层21背离衬底基板1的一侧；具体的，发光层可以为多量子阱层(MQW，MultipleQuantum Well)；衬底基板1用 于生长半导体层和发光层，例如，衬底基板1可以为蓝宝石衬底；
第二半导体层22，第二半导体层22位于发光层3背离第一半导体层21的一侧，第二半导体层22与第一半导体层21的掺杂离子电性相反；具体的，例如，第一半导体层21可以为n掺杂半导体层，第二半导体层22可以为p掺杂半导体层；具体的，第一半导体层21的材料可以为n掺杂GaN，第二半导体层22的材料可以为p掺杂GaN；
阻隔结构4，阻隔结构4位于第二半导体层22背离发光层3的一侧，具有暴露第二半导体层22的开口K，开口K在衬底基板1的正投影位于发光层3在衬底基板1的正投影内，且开口K的面积小于发光层3的面积；
搭接电极6，搭接电极6位于阻隔结构4背离第二半导体层22的一侧，搭接电极6通过开口K与第二半导体层22接触。
本公开实施例中，第二半导体层22背离发光层3的一侧具有阻隔结构4，阻隔结构4具有暴露第二半导体层22的开口K，开口K在衬底基板1的正投影位于发光层3在衬底基板1的正投影内，且开口K的面积小于发光层3的面积，搭接电极6通过开口K与第二半导体层22接触，阻隔结构4暴露第二半导体层22的开口K，形成有效发光区域，该有效发光区域的面积小于原发光层3的面积，实现减小发光器件的发光区域，在加载的灰阶电压相同的情形下，可以提升发光器件的出光效率，在保持优秀显示画质的基础上降低发光器件的功耗。
在具体实施时，可以通过不同的方式形成阻隔结构4，以下分别进行具体举例说明：
例如，在一种可能的实施方式中，结合图1所示，第二半导体层22在衬底基板1的正投影与发光层3在衬底基板1的正投影大致互相重合；阻隔结构4包括第三半导体层41，以及位于第三半导体层1背离第二半导体层22一侧的钝化层42，第三半导体层41与第二半导体层22的掺杂离子电性相反；具体的，例如，第二半导体层22为n掺杂半导体层时，第三半导体层41具体可以为p掺杂半导体层，进一步的，第二半导体层22的材料可以为n掺杂 GaN时，第三半导体层41的材料具体可以为p掺杂GaN；第三半导体层41具有暴露部分第二半导体层22的第一子开口K1，钝化层42具有暴露第三半导体层22以及第一子开口K1的第二子开口K2；搭接电极6通过第三半导体层41的第一子开口K1与第二半导体层22接触。本公开实施例中，通过形成与第二半导体层22掺杂离子相反的第三半导体层41，在发光构件P工作时，第三半导体层41和第二半导体层22形成反向PN结，从而阻挡载流子(例如，电子)的流动，使第一子开口K1所在的区域形成有效发光区域，实现降低发光器件的发光区域。
具体的，第三半导体层41可以为电子阻挡层。
又例如，在一种可能的实施方式中，结合图2所示，第二半导体层22在衬底基板1的正投影与发光层3在衬底基板1的正投影大致互相重合；阻隔结构4包括钝化层42；钝化层42具有暴露部分第二半导体层22的第三子开口K3；搭接电极6通过钝化层42的第三子开口K2与第二半导体层22接触。本公开实施例中，通过减小钝化层42的第三子开口K2的尺寸，进而实现对有效发光区域的控制，减小发光区域的方式较为简单，易于实现。
具体的，第二半导体层22的厚度为第一半导体层厚度的千分之二十至千分之四十。本公开实施例中，在通过减小钝化层42的第三子开口K2的尺寸，以实现减小有效发光区域的时，使第二半导体层22的厚度为第一半导体层厚度的千分之二十至千分之四十，可以避免电流在第二半导体层22中过度横向扩散，尽快进入发光层3中，以具有较高的发光效率。
又例如，在一种可能的实施方式中，第二半导体层22在衬底基板1的正投影位于发光层3在衬底基板1的正投影内，且第二半导体层22在衬底基板1的正投影面积小于发光层3在衬底基板1的正投影面积；阻隔结构4包括钝化层42；钝化层42具有暴露至少部分第二半导体层22的第四子开口K4；搭接电极6通过钝化层42的第四子开口K2与第二半导体层22接触。本公开实施例中，通过减小第二半导体层22的面积，进而实现对有效发光区域的控制，减小发光区域的方式较为简单，易于实现。
具体的，可以仅是通过减小第二半导体层22的面积，来实现有效发光区域的减小，例如，结合图3所示，第四子开口K4在衬底基板1的正投影与第二半导体层22在衬底基板1的正投影大致互相重合。具体的，还可以在减小第二半导体层22面积时，同时减小钝化层42的第四子开口K4尺寸，例如，使第四子开口K4在衬底基板1的正投影小于第二半导体层22在衬底基板1的正投影，可以进一步减少有效发光区域。
具体的，结合图3所示，第二半导体层22的面积为发光层3面积的五分之一至五分之四。本公开实施例中，第二半导体层22的面积为发光层3面积的五分之一至五分之四，可以在通过减小第二半导体层22的面积来实现减小有效发光区域的同时，避免有效发光区域过小，出光量过小，影响发光器件的正常使用。
在一种可能的实施方式中，结合图1、图2、图3所示，发光器件包括至少两个相互串联的发光结构P；发光器件还包括位于搭接电极6背离阻隔结构4一侧的封装层73，至少两个相互串联的发光结构P通过封装层73一体封装。本公开实施例中，发光器件包括至少两个相互串联的发光结构P，此种发光器件在有源发光二极管驱动电路中，在VDD→VSS的电流通路中，相当于串联了两颗发光结构，发光器件分得的跨压更高，减小了驱动电路中晶体管的电压，形成高压发光器件，可以大幅度降低发光器件成本，减少线路的电流，降低功耗。
在一种可能的实施方式中，结合图1、图2、图3所示，发光器件包括相互串联的第一发光结构P1和第二发光结构P2；发光器件还包括位于阻隔结构4与搭接电极6之间的桥电极5；第一发光结构P1的第一半导体层21和第二发光结构P2的搭接电极6通过桥电极6电连接，进而实现不同发光结构P的串联。
具体的，结合图1、图2、图3所示，阻隔结构4至少包括钝化层42；桥电极5的一端通过贯穿钝化层42的过孔与第一发光结构P1的第一半导体层21电连接，另一端与第二发光结构P2的搭接电极6直接接触电连接。
在一种可能的实施方式中，结合图1、图2、图3所示，发光器件还包括位于封装层73背离第二半导体层22一侧的连接垫层8，连接垫层8包括：与第一发光结构P1的搭接电极6电连接的第一连接电极垫81，以及与第二发光结构P2的第一半导体层21电连接的第二连接电极垫82，如此，实现将相互串联的两个发光结构P的不同电极端引出。
在一种可能的实施方式中，结合图1、图2、图3所示，第一发光结构P1的搭接电极6包括与第二半导体层22接触的第一接触部61，第一搭接部62，以及连接第一接触部61和第一搭接部62的第一连接部63；第一搭接部62在衬底基板1的正投影与发光层3在衬底基板1的正投影不交叠；第一连接电极垫81通过过孔与第一搭接部62电连接，如此，实现将第一发光结构P1中搭接电极6的引出位置移出有效发光区域，进而提升出光效率；第二发光结构P2的第一半导体层21具有与发光层3重叠的重叠部211，以及由重叠部211延伸出的延伸部212，第二连接电极垫82通过过孔与延伸部212电连接，如此，实现将第二发光结构P2中第一半导体层21的引出位置移出有效发光区域，进而提升出光效率。相比于若第一发光结构P1中搭接电极6的引出位置、第二发光结构P2中第一半导体层21的引出位置，仍在有效发光区域时，会使过孔所占比例增高，在缩小发光构件P的有效发光区域时，发光结构P的出光效率反而会降低，而本公开实施例中，通过将引出位置移出有效发光区域以外，可以改善缩小发光构件P的有效发光区域后，出光效率可能会降低的问题。
在一种可能的实施方式中，发光器件还包括位于封装层73与搭接电极6之间的散热层72；散热层72在衬底基板1的正投影至少覆盖第一发光结构P1的开K口在衬底基板1的正投影，以及第二发光结构P2的开口K在衬底基板1的正投影。本公开实施例中，发光器件还包括位于封装层73与搭接电极6之间的散热层72，可以实现对发光结构P的发热进行有效散热。
在一种可能的实施方式中，连接垫层8还包括与散热层72导通的散热垫83，散热垫83在衬底基板1的正投影至少覆盖第一发光结构P1的接开口K1 在衬底基板1的正投影，以及覆盖第二发光结构P2的开口在衬底基板1的正投影。减小发光结构P的有效发光区域后，虽然发光结构P光效提升，但同样产热点更集中，热量更容易聚集到发光区域，本公开实施例中，连接垫层8还包括与散热层72导通的散热垫83，可以将有效发光区域减小后的发光结构P产生的热量，快速有效的散除，降低发光结构P的结温，避免光效降低或发光结构P的烧毁。
在一种可能的实施方式中，封装层73具有暴露第一封装开口F1，以及第二封装开口F2；第一封装开口F1在衬底基板1的正投影覆盖第一发光结构P1的开口K在衬底基板1的正投影，第二封装开口F2在衬底基板1的正投影覆盖第二发光结构P2的开口K在衬底基板1的正投影；散热垫83通过第一封装开口F1、第二封装开口F2与散热层72接触。本公开实施例中，通过在开孔K位置处设置第一封装开孔F1和第二封装开口F2，实现在有效发光区域位置处将散热垫83与散热层72导通，可以缩短散热通道长度，使发光结构P产生的热量快速有效的散发。
在一种可能的实施方式中，参见图4所示，散热垫83包括覆盖第一发光结构P1开口K的第一散热垫831，以及覆盖第二发光结构P2开口K的第二散热垫832，第一散热垫831、第二散热垫832一体连接；第一连接电极垫81的中心O1、第二连接电极垫82的中心O2、第一散热垫831的中心O3、第二散热垫832的中心O4围成一矩形；第一连接电极垫81的中心O1、第二连接电极垫82的中心O2分别位于矩形一对角线k1上的两个顶点，第一散热垫831的中心O3、第二散热垫832的中心O4分别位于矩形另一对角线k2上两个顶点。
在一种可能的实施方式中，结合图1、图2、图3所示，散热层8与搭接电极6之间还具有反射层71。发光层3的出光有约50％的光背离衬底基板1一侧，因此需要反射层71，具体可以为布拉格反射镜(DBR-distributed Bragg reflection，分布式布拉格反射镜，将背离光反射回衬底基板1，提升发光结构1的出光。具体的，反射层71可以采用叠加的SiO2和TiO2组成所需光的1/4 波长反射镜。
基于同一发明构思，参见图5所示，本公开实施例还提供一种发光基板，其中，包括驱动背板200以及设置于驱动背板200一侧的如本公开实施例提供的发光器件。
在一种可能的实施方式中，参见图5和图6所示，驱动背板200包括与发光器件一一对应的驱动结构23，驱动结构23包括第一电极231，第二电极232，以及散热电极233；其中，第一电极231与第一连接电极垫81绑定连接，第二电极232与第二连接电极垫82绑定连接，散热电极233与散热垫83绑定连接。
在一种可能的实施方式中，结合图6所示，驱动背板200还包括散热连接电极234，不同驱动结构23的散热电极233通过散热连接电极234相互电连接。
在一种可能的实施方式中，驱动背板200还可以包括驱动衬底基板21，驱动结构23位于驱动衬底基板21的一侧，驱动衬底基板21与驱动结构23之间还可以设置有驱动层22，驱动层22具体可以是包括多个膜层的复合层。驱动层22可以包括：第一电源线221，第二电源线222，以及驱动电路223。第一电源线221具体可以为VDD电源线，第二电源线222具体可以是VSS电源线。驱动电力223具体可以包括薄膜晶体管以及电容。
基于同一发明构思，参见图7所示，本公开实施例还提供一种发光器件的制作方法，其中，包括：
步骤S100、在衬底基板的一侧形成第一半导体层；
步骤S200、在第一半导体层背离衬底基板的一侧形成发光层；
步骤S300、在发光层的背离第一半导体层的一侧形成第二半导体层；
步骤S400、在第二半导体层的背离发光层的一侧形成具有暴露第二半导体层开口的阻隔结构，开口在衬底基板的正投影位于发光层在衬底基板的正投影内，且开口的面积小于发光层的面积；
步骤S500、在阻隔结构背离第二半导体层的一侧形成搭接电极，以使搭 接电极通过开口与第二半导体层接触。
在一种可能的实施方式中，可以通过形成第三半导体层42来减小有效发光区域，具体的，关于步骤S400，即，在第二半导体层的背离发光层的一侧形成具有暴露第二半导体层开口的阻隔结构，包括：
步骤S411、在第二半导体层背离发光层的一侧形成第三半导体层，第三半导体层与第二半导体层的掺杂离子电性相反；
步骤S412、对第三半导体层进行图案化，以形成暴露部分第二半导体层的第一子开口；
步骤S413、在第三半导体层背离第二半导体层的一侧形成具有第二子开口的钝化层，其中，第二子开口暴露第三半导体层以及第一子开口。
在一种可能的实施方式中，可以通过调整钝化层的开口尺寸来减小有效发光区域，具体的，关于步骤S400，即，在第二半导体层的背离发光层的一侧形成具有暴露第二半导体层开口的阻隔结构，包括：
步骤S421、在第二半导体层背离发光层的一侧形成钝化层；
步骤S422、对钝化层进行图案化，以形成暴露部分第二半导体层的第三子开口，以使搭接电极通过第三子开口与第二半导体层接触。
在一种可能的实施方式中，可以通过调整第二半导体层的面积来减小有效发光区域，具体的，关于步骤S300，即，在发光层的背离第一半导体层的一侧形成第二半导体层，包括：在发光层的背离第一半导体层的一侧形成在衬底基板的正投影位于发光层在衬底基板的正投影内的第二半导体层，且第二半导体层在衬底基板的正投影面积小于发光层在衬底基板的正投影面积；
相应的，关于步骤S400、在第二半导体层的背离发光层的一侧形成具有暴露第二半导体层开口的阻隔结构，包括：
步骤S431、在第二半导体层背离发光层的一侧形成钝化层；
步骤S432、对钝化层进行图案化，以形成暴露第二半导体层的第四子开口，以使搭接电极通过第四子开口与第二半导体层接触，其中，第四子开口在衬底基板的正投影与第二半导体层在衬底基板的正投影大致互相重合。
为了更清楚地理解本公开实施例提供的发光器件的制作方法，以下通过具体实施例进行进一步说明如下：
在一种可能的实施方式中，以增加第三半导体层(电子阻挡层，current blocker，CB)降低有效发光面积，并制作驱动背板相应散热通道为例，进行详细说明：
步骤一：在衬底基板1(例如，蓝宝石基体)上制备发光结构P的基础膜层，制备方法具体可以为LED芯片常规制程，在此不再赘述，包括制备n-GaN(作为第一半导体层21)、量子阱(MQW，作为发光层3)、p-GaN(作为第二半导体层22)三层，参见图8A、图8B、图8C所示，其中，图8A为形成第二半导体层22后的剖视示意图，图8B为发光层3的单膜层俯视图，图8C为第二半导体层22的单膜层俯视图；
步骤二、制作第三半导体层41(电子阻挡层)，并形成定义发光区域的开口K，该电子阻挡层为n掺杂的GaN或其他材料，在LED工作时，电子阻挡层和p-GaN形成反向PN结，从而阻挡电子的流动，电子阻挡层开口K则正常发光，以此定义发光区域的大小，如图9A和图9B所示，图9B中开口K所示即为LED的有效发光区域，其中，图9A为形成第三半导体层41后的剖视示意图，图9B为第三半导体层41的单膜层俯视图；
步骤三、制作钝化层42，并制作桥电极5、搭接电极6，连接两侧发光结构P，该步骤为同一个LED(发光器件)内部制作串联的两个子LED(发光结构P)，在完成全部连接后，左侧子LED的n电极将连接右侧子LED的p电极，形成高压LED(此种LED在AMLED驱动电路中，在VDD→VSS的电流通路中，相当于串联了两颗LED，分得的跨压更高，因此成为高压LED)；搭接电极6(具体材料可以为氧化铟锡)，将搭接电极6通过桥电极5搭接，形成电位连接，左侧子LED连接p电极的搭接电极6延长至发光区域以外，以便后续使p电极关于反射层71的过孔711远离发光区域，避免影响LED出光，如图10A、图10B、图10C、图10D所示，其中，图10A为形成搭接电极6后的剖视示意图，图10B为钝化层42的单膜层俯视图，图10C为桥电 极5的单膜层俯视图，图10D为搭接电极6的单膜层俯视图；
步骤四、制作反射层71，当LED工作时，量子阱(发光层3)的出光有约50％的光背离衬底基板1(蓝宝石)面，因此需要反射层71(具体可以为布拉格反射镜DBR-distributed Bragg reflection，分布式布拉格反射镜，将背离光反射回蓝宝石面，提升LED出光，可以采用叠加的SiO2和TiO2组成所需光的1/4波长反射镜；然而常规LED在连接p电极时，需要在发光区域通过刻蚀DBR形成的过孔搭接p-GaN，p电极的金属会吸收部分光子，从而降低出光率，本公开实施例中，缩小LED有效发光区域后，过孔所占比例增高，LED出光反而降低，因此需要一定方法将p电极过孔移出发光区域，制作相对完整的DBR以提高出光；在DBR外层制作整面的散热层72(Heat sink)，包覆整个LED并留出后续Pad(连接垫层8)连接电极的过孔；通过封装层73封装LED并刻蚀出Pad金属过孔，用以后续散热通道和电极的连接，如图11A、图11B、图11C、图11D所示，其中，图11A为形成封装层73后的剖视示意图，图11B为反射层71的单膜层俯视图，图11C为散热层72的单膜层俯视图，图11D为封装层73的单膜层俯视图；
步骤五、完成连接垫层8制作，通过封装层73的第一封装过孔F 1、第二封装过孔F2连接开口K正对的散热层72形成散热通道，连接对应电极形成LED的n、p极电学连接，如图12A、图12B、图12C所示，其中，图12A为形成连接垫层8后的剖视示意图，图12B为连接垫层8的单膜层俯视图，图12C为整体发光器件的俯视图，图12A可以是图12C沿虚线E1F1的截面示意图。
在另一种可能的实施方式中，可以通过调整钝化层3的第三子开口大小来控制有效发光区域的大小，此实施例可以减小p-GaN的厚度，避免电流在p-GaN中过度横向扩散，尽快进入量子阱中；钝化层41的第三子开口K3的过孔面积为搭接电极6与p-GaN的搭接面积，即有效发光区域，其中，图13A为形成连接垫层8后的剖视示意图，图13B整体发光器件的俯视图，图13A 可以是图13B沿虚线E2F2的截面示意图；具体膜层的制作流程可以与上述实施例的相似，本公开实施例在此不再赘述。
在另一种可能的实施方式中，通过刻蚀减小第二半导体层22(p-GaN)的面积，限制有效发光区域；在具体实施时，可以避免刻蚀量子阱层导致形成和p-GaN齐边的结构，避免如果齐边时，则会通过p-GaN、量子阱、n-GaN边缘被破坏的晶格结构形成漏电通道，从而降低LED的出光效率，其中，图14A为形成连接垫层8后的剖视示意图，图14B整体发光器件的俯视图，图14A可以是图14B沿虚线E3F3的截面示意图；具体膜层的制作流程可以与上述实施例的相似，本公开实施例在此不再赘述。
在另一种可能的实施方式中，连接电极垫层8页也可以不形成散热垫83，以增加第三半导体层(电子阻挡层，current blocker，CB)降低有效发光面积，并制作驱动背板相应散热通道为例，制作完成后的发光器件的结构示意图具体如图15A、图15B所示，其中，图15A为形成连接垫层8后的剖视示意图，图15B整体发光器件的俯视图，图15A可以是图15B沿虚线E4F4的截面示意图；具体膜层的制作流程可以与上述实施例的相似，本公开实施例在此不再赘述。
本公开实施例有益效果如下：本公开实施例中，第二半导体层22背离发光层3的一侧具有阻隔结构4，阻隔结构4具有暴露第二半导体层22的开口K，开口K在衬底基板1的正投影位于发光层3在衬底基板1的正投影内，且开口K的面积小于发光层3的面积，搭接电极6通过开口K与第二半导体层22接触，阻隔结构4暴露第二半导体层22的开口K，形成有效发光区域，该有效发光区域的面积小于原发光层3的面积，实现减小发光器件的发光区域，在加载的灰阶电压相同的情形下，可以提升发光器件的出光效率，在保持优秀显示画质的基础上降低发光器件的功耗。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (24)

  1. 一种发光器件，包括：衬底基板，以及位于所述衬底基板一侧的至少一个发光结构；其中，所述发光结构包括：
    第一半导体层；
    发光层，所述发光层位于所述第一半导体层背离所述衬底基板的一侧；
    第二半导体层,所述第二半导体层位于所述发光层背离所述第一半导体层的一侧，所述第二半导体层与所述第一半导体层的掺杂离子电性相反；
    阻隔结构，所述阻隔结构位于所述第二半导体层背离所述发光层的一侧，具有暴露所述第二半导体层的开口，所述开口在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述开口的面积小于所述发光层的面积；
    搭接电极，所述搭接电极位于所述阻隔结构背离所述第二半导体层的一侧，所述搭接电极通过所述开口与所述第二半导体层接触。
  2. 如权利要求1所述的发光器件，其中，所述第二半导体层在所述衬底基板的正投影与所述发光层在所述衬底基板的正投影大致互相重合；
    所述阻隔结构包括第三半导体层，以及位于所述第三半导体层背离所述第二半导体层一侧的钝化层，所述第三半导体层与所述第二半导体层的掺杂离子电性相反；所述第三半导体层具有暴露部分所述第二半导体层的第一子开口，所述钝化层具有暴露所述第三半导体层以及所述第一子开口的第二子开口；
    所述搭接电极通过所述第三半导体层的所述第一子开口与所述第二半导体层接触。
  3. 如权利要求1所述的发光器件，其中，所述第二半导体层在所述衬底基板的正投影与所述发光层在所述衬底基板的正投影大致互相重合；
    所述阻隔结构包括钝化层；所述钝化层具有暴露部分所述第二半导体层的第三子开口；
    所述搭接电极通过所述钝化层的所述第三子开口与所述第二半导体层接触。
  4. 如权利要求3所述的发光器件，其中，所述第二半导体层的厚度为所述第一半导体层厚度的千分之二十至千分之四十。
  5. 如权利要求1所述的发光器件，其中，所述第二半导体层在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述第二半导体层在所述衬底基板的正投影面积小于所述发光层在所述衬底基板的正投影面积；
    所述阻隔结构包括钝化层；所述钝化层具有暴露至少部分所述第二半导体层的第四子开口；
    所述搭接电极通过所述钝化层的所述第四子开口与所述第二半导体层接触。
  6. 如权利要求5所述的发光器件，其中，所述第四子开口在所述衬底基板的正投影与所述第二半导体层在所述衬底基板的正投影大致互相重合。
  7. 如权利要求6所述的发光器件，其中，所述第二半导体层的面积为所述发光层面积的五分之一至五分之四。
  8. 如权利要求1-7任一项所述的发光器件，其中，所述发光器件包括至少两个相互串联的所述发光结构；
    所述发光器件还包括位于所述搭接电极背离所述阻隔结构一侧的封装层，所述至少两个相互串联的所述发光结构通过所述封装层一体封装。
  9. 如权利要求8所述的发光器件，其中，所述发光器件包括相互串联的第一发光结构和所述第二发光结构；
    所述发光器件还包括位于所述阻隔结构与所述搭接电极之间的桥电极；所述第一发光结构的所述第一半导体层和所述第二发光结构的所述搭接电极通过所述桥电极电连接。
  10. 如权利要求9所述的发光器件，其中，所述阻隔结构至少包括钝化层；
    所述桥电极的一端通过贯穿所述钝化层的过孔与所述第一发光结构的所述第一半导体层电连接，另一端与所述第二发光结构的所述搭接电极直接接触电连接。
  11. 如权利要求10所述的发光器件，其中，所述发光器件还包括位于所述封装层背离所述第二半导体层一侧的连接垫层，所述连接垫层包括：与所述第一发光结构的所述搭接电极电连接的第一连接电极垫，以及与所述第二发光结构的所述第一半导体层电连接的第二连接电极垫。
  12. 如权利要求11所述的发光器件，其中，所述第一发光结构的所述搭接电极包括与所述第二半导体层接触的第一接触部，第一搭接部，以及连接所述第一接触部和所述第一搭接部的第一连接部；所述第一搭接部在所述衬底基板的正投影与所述发光层在所述衬底基板的正投影不交叠；所述第一连接电极垫通过过孔与所述第一搭接部电连接；
    所述第二发光结构的所述第一半导体层具有与所述发光层重叠的重叠部，以及由所述重叠部延伸出的延伸部，所述第二连接电极垫通过过孔与所述延伸部电连接。
  13. 如权利要求11所述的发光器件，其中，所述发光器件还包括位于所述封装层与所述搭接电极之间的散热层；所述散热层在所述衬底基板的正投影至少覆盖所述第一发光结构的所述开口在所述衬底基板的正投影，以及所述第二发光结构的所述开口在所述衬底基板的正投影。
  14. 如权利要求13所述的发光器件，其中，所述连接垫层还包括与所述散热层导通的散热垫，所述散热垫在所述衬底基板的正投影至少覆盖所述第一发光结构的所述接开口在所述衬底基板的正投影，以及覆盖所述第二发光结构的所述开口在所述衬底基板的正投影。
  15. 如权利要求14所述的发光器件，其中，所述封装层具有暴露第一封装开口，以及第二封装开口；所述第一封装开口在所述衬底基板的正投影覆盖所述第一发光结构的所述开口在所述衬底基板的正投影，所述第二封装开口在所述衬底基板的正投影覆盖所述第二发光结构的所述开口在所述衬底基 板的正投影；
    所述散热垫通过所述第一封装开口、所述第二封装开口与所述散热层接触。
  16. 如权利要求14所述的发光器件，其中，所述散热垫包括覆盖所述第一发光结构所述开口的第一散热垫，以及覆盖所述第二发光结构所述开口的第二散热垫，所述第一散热垫、所述第二散热垫一体连接；
    所述第一连接电极垫的中心、所述第二连接电极垫的中心、所述第一散热垫的中心、所述第二散热垫的中心围成一矩形；所述第一连接电极垫的中心、所述第二连接电极垫的中心分别位于所述矩形一对角线上的两个顶点，所述第一散热垫的中心、所述第二散热垫的中心分别位于所述矩形另一对角线上两个顶点。
  17. 如权利要求13所述的发光器件，其中，所述散热层与所述搭接电极之间还具有反射层。
  18. 一种发光基板，其中，包括驱动背板以及设置于所述驱动背板一侧的如权利要求1-17任一项所述的发光器件。
  19. 如权利要求18所述的发光基板，其中，所述驱动背板包括与所述发光器件一一对应的驱动结构，所述驱动结构包括第一电极，第二电极，以及散热电极；其中，所述第一电极与所述第一连接电极绑定连接，所述第二电极与所述第二连接电极绑定连接，所述散热电极与所述散热垫绑定连接。
  20. 如权利要求19所述的发光基板，其中，所述驱动背板还包括散热连接电极，不同所述驱动结构的所述散热电极通过所述散热连接电极相互电连接。
  21. 一种发光器件的制作方法，其中，包括：
    在衬底基板的一侧形成第一半导体层；
    在所述第一半导体层背离所述衬底基板的一侧形成发光层；
    在所述发光层的背离所述第一半导体层的一侧形成第二半导体层；
    在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半 导体层开口的阻隔结构，所述开口在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内，且所述开口的面积小于所述发光层的面积；
    在所述阻隔结构背离所述第二半导体层的一侧形成搭接电极，以使所述搭接电极通过所述开口与所述第二半导体层接触。
  22. 如权利要求21所述的制作方法，其中，所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
    在所述第二半导体层背离所述发光层的一侧形成第三半导体层，所述第三半导体层与所述第二半导体层的掺杂离子电性相反；
    对所述第三半导体层进行图案化，以形成暴露部分所述第二半导体层的第一子开口；
    在所述第三半导体层背离所述第二半导体层的一侧形成具有第二子开口的钝化层，其中，所述第二子开口暴露所述第三半导体层以及所述第一子开口。
  23. 如权利要求21所述的制作方法，其中，所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
    在所述第二半导体层背离所述发光层的一侧形成钝化层；
    对所述钝化层进行图案化，以形成暴露部分所述第二半导体层的第三子开口，以使所述搭接电极通过所述第三子开口与所述第二半导体层接触。
  24. 如权利要求21所述的制作方法，其中，所述在所述发光层的背离所述第一半导体层的一侧形成第二半导体层，包括：在所述发光层的背离所述第一半导体层的一侧形成在所述衬底基板的正投影位于所述发光层在所述衬底基板的正投影内的第二半导体层，且所述第二半导体层在所述衬底基板的正投影面积小于所述发光层在所述衬底基板的正投影面积；
    所述在所述第二半导体层的背离所述发光层的一侧形成具有暴露所述第二半导体层开口的阻隔结构，包括：
    在所述第二半导体层背离所述发光层的一侧形成钝化层；
    对所述钝化层进行图案化，以形成暴露所述第二半导体层的第四子开口，以使所述搭接电极通过所述第四子开口与所述第二半导体层接触，其中，所述第四子开口在所述衬底基板的正投影与所述第二半导体层在所述衬底基板的正投影大致互相重合。
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CN110212069A (zh) * 2019-04-18 2019-09-06 华灿光电（浙江）有限公司 发光二极管芯片及其制作方法
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