WO2020077842A1 - Oled面板及其制作方法 - Google Patents

Oled面板及其制作方法 Download PDF

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Publication number
WO2020077842A1
WO2020077842A1 PCT/CN2018/123653 CN2018123653W WO2020077842A1 WO 2020077842 A1 WO2020077842 A1 WO 2020077842A1 CN 2018123653 W CN2018123653 W CN 2018123653W WO 2020077842 A1 WO2020077842 A1 WO 2020077842A1
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Prior art keywords
layer
groove
capacitor electrode
flat
passivation
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PCT/CN2018/123653
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English (en)
French (fr)
Inventor
唐甲
任章淳
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020077842A1 publication Critical patent/WO2020077842A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the invention relates to the field of display technology, in particular to an OLED panel and a manufacturing method thereof.
  • the anode uses reflective electrodes, mainly ITO / Ag / ITO, OLED cathode It is a transparent cathode with a larger transmittance.
  • the aperture ratio of the device is greatly improved after the device is completed.
  • the top emission is still in the perfect stage.
  • the small size has been mass-produced, but the large size has obvious IR drop, in addition, OLED cathode transmittance and impedance and other issues make the top-emitting large-size OLED backplane has not yet reached the level of mass production.
  • the large-scale AMOLED backplanes in mass production are still bottom-emitting.
  • the main way to increase the aperture ratio of the bottom-emitting design is to reduce the area of the TFT in the non-light emitting area.
  • the size design is getting smaller and smaller.
  • the size of the TFT shrinks it means that the cost of the lithography technology increases, resulting in an increase in the manufacturing cost of the AMOLED backplane.
  • the object of the present invention is to provide an OLED panel and a method for manufacturing the same.
  • the parallel structure is used to improve the capacitor structure.
  • the flat layer (PLN layer) is assisted by half-tone technology to make the passivation layer (PV layer) of the storage capacitor area thinner.
  • the present invention provides a method for manufacturing an OLED panel, which includes:
  • a TFT light-shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer are sequentially formed on the glass substrate, wherein the TFT A light shielding layer is formed on the glass substrate; the buffer layer is formed on the glass substrate and the TFT light shielding layer; the semiconductor layer is formed on the buffer layer, and the semiconductor layer is formed by patterning A TFT active region and a first capacitor electrode; the gate insulating layer is formed on the TFT active region; the first metal layer is formed on the gate insulating layer through a patterning process, wherein the The TFT active region and the first capacitor electrode outside the area covered by the first metal layer are subjected to a conductive process; the interlayer insulating layer is formed on the first metal layer and the semiconductor layer; the first Two metal layers are formed on the interlayer insulating layer, the second metal is patterned to form a second capacitor electrode, and the second capacitor electrode is located above the first capacitor electrode;
  • At least one flat layer via and a flat layer groove are formed in the flat layer by a halftone technique, the at least one flat layer via exposes a portion of the passivation layer, and the flat layer groove is located in the first layer Two above the capacitor electrode;
  • a transparent conductive layer is formed.
  • the transparent conductive layer is located on the flat layer, in the passivation layer via hole, and in the passivation layer groove.
  • the step of forming the interlayer insulating layer further includes:
  • the second capacitor electrode is formed in the groove of the interlayer insulating layer.
  • the forming the at least one flat layer via and the flat layer groove in the flat layer by a halftone technique includes:
  • the half-tone mask has a light-transmitting area, a half-light transmitting area, and an opaque area;
  • the flat layer after exposure is developed.
  • the invention also provides an OLED panel, including:
  • a TFT light-shielding layer which is arranged on the glass substrate;
  • a gate insulating layer disposed on the TFT active area
  • a first metal layer which is disposed on the gate insulating layer through a patterning process, wherein the TFT active region and the first capacitor electrode outside the area covered by the first metal layer are subjected to a conductive process;
  • An interlayer insulating layer provided on the first metal layer and the semiconductor layer;
  • a passivation layer disposed on the second metal layer, the passivation layer has a passivation layer groove, the passivation layer groove is located above the second capacitor electrode;
  • a color filter is provided on the passivation layer
  • a pixel defining layer is disposed on the flat layer and the transparent conductive layer.
  • a first storage capacitor region is formed between the first capacitor electrode and the second capacitor electrode, and a first capacitor region is formed between the second capacitor electrode and the third capacitor electrode 2. Storage capacitor area.
  • the interlayer insulating layer further includes an interlayer insulating layer groove, the interlayer insulating layer groove is located above the first capacitor electrode, and part of the second capacitor electrode is disposed on In the groove of the interlayer insulating layer.
  • the second capacitor electrode has a second capacitor electrode upper surface
  • the passivation layer has a passivation layer upper surface
  • the second capacitor electrode upper surface is on the passivation layer There is a distance between the surfaces, and the distance is greater than a thickness of the second storage capacitor region.
  • the OLED panel further includes a plurality of metal conductive holes provided in the interlayer insulating layer to electrically connect the semiconductor layer and the second metal layer.
  • the OLED panel further includes a plurality of transparent conductive holes disposed in the passivation layer and passing through the flat layer for electrically connecting the transparent conductive layer and the second Metal layer.
  • the invention also provides a method for manufacturing an OLED panel, including:
  • a TFT light-shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, a second metal layer, and a passivation layer are sequentially formed on the glass substrate , A color filter and a flat layer, wherein the semiconductor layer is patterned to form a TFT active area and a first capacitor electrode; the second metal layer is patterned to form a second capacitor electrode, The second capacitor electrode is located above the first capacitor electrode;
  • a transparent conductive layer is formed.
  • the transparent conductive layer is located on the flat layer, in the passivation layer via hole, and in the passivation layer groove.
  • the forming of at least one flat layer via and a flat layer groove in the flat layer is through a halftone technique, and the halftone technique includes:
  • the half-tone mask has a light-transmitting area, a half-light transmitting area, and an opaque area;
  • the flat layer after exposure is developed.
  • the at least one passivation layer via is formed on the passivation layer exposed by the at least one flat layer via via an etching technique.
  • the passivation layer groove is formed by an etching technique by the passivation layer
  • An upper surface of a passivation layer is etched toward the second metal layer to have the groove of the passivation layer having a first etching depth.
  • the step of forming the interlayer insulating layer further includes:
  • the second capacitor electrode is formed in the groove of the interlayer insulating layer.
  • the beneficial effects of the present invention are: under the same capacitor demand, the OLED panel and its manufacturing method proposed by the present invention improve the capacitor structure and reduce the occupied area, and the corresponding light-emitting area design can be improved to a certain extent, which in turn improves Opening rate.
  • FIG. 1 is a schematic structural diagram of an OLED panel of the present invention.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an OLED panel of the present invention.
  • FIG. 3 is a schematic diagram of step S300 of the method for manufacturing an OLED panel of the present invention.
  • step S400 is a schematic diagram of step S400 of the method for manufacturing an OLED panel of the present invention.
  • FIG. 5 is a schematic diagram of step S500 of the method for manufacturing an OLED panel of the present invention.
  • step S600 is a schematic diagram of step S600 of the method for manufacturing an OLED panel of the present invention.
  • step S700 is a schematic diagram of step S700 of the method for manufacturing an OLED panel of the present invention.
  • the term includes (comprise, comprising, include, including, contain, Containing, have, having) and its changes can be interpreted as the meaning of inclusion (non-exclusive), making the process, method, device, apparatus or system described in this article ( system) is not limited to the description of these functions, parts, elements or steps, but may contain other elements, functions, parts or steps not explicitly listed or the existence of such a process (process), method (method), article (article) or Equipment (apparatus).
  • the term "a” and “an” as used herein is understood to mean one or more.
  • the terms first, second, third, etc. are only used as labels, and do not impose numerical requirements or establish order.
  • FIG. 1 is a schematic structural diagram of an OLED panel of the present invention.
  • the present invention provides an OLED panel 10, including: a glass substrate 110, a TFT light-shielding layer 120, a buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, a first metal layer 160, an interlayer insulation The layer 170, a second metal layer 180, a passivation layer 190, a color filter 200, a flat layer 210, a transparent conductive layer 220 and a pixel defining layer 230.
  • the TFT light-shielding layer 120 is disposed on the glass substrate 110.
  • the TFT light-shielding layer 120 may be made of a metal material, and the material of the TFT light-shielding layer 120 may include Mo, Al, Cu, Ti, or an alloy thereof.
  • the TFT light-shielding layer 120 may be patterned through a photolithography process and etching.
  • the buffer layer 130 is disposed on the glass substrate 110 and the TFT light-shielding layer 120.
  • the buffer layer 130 can form a thin film on the glass substrate 110 and the TFT light-shielding layer 120 by a deposition technique.
  • the buffer layer 130 may be a SiOx, SiNx single-layer film or a layered structure film.
  • the semiconductor layer 140 is disposed on the buffer layer 130.
  • the semiconductor layer 140 undergoes a patterning process to form a TFT active region 141 and a first capacitor electrode 142.
  • the semiconductor layer 140 may be formed on the buffer layer 130 by a deposition technique.
  • the semiconductor layer 140 may be an amorphous oxide semiconductor, such as indium gallium zinc oxide (indium gallium zinc oxide (IGZO), indium zinc tin (indium zinc tin) oxide, IZTO) or indium gallium zinc ti oxide (IGZTO) or other materials with similar characteristics.
  • IGZO indium gallium zinc oxide
  • IZTO indium zinc tin oxide
  • IGZTO indium gallium zinc ti oxide
  • the gate insulating layer 150 is disposed on the TFT active region 141. For example, by depositing an insulating layer, the insulating layer is then patterned to form the gate insulating layer 150.
  • the gate insulating layer 150 may be a SiOx, SiNx film or a stacked structure film.
  • the first metal layer 160 is disposed on the gate insulating layer 150 through a patterning process, wherein the first metal layer 160 covers the TFT active region 141 and the first capacitor electrode 142 outside the area Go through a conductive process, for example to increase the doping concentration. In this way, the TFT active region 141 can form a source and a drain, and the first capacitor electrode 142 can be converted into a conductor characteristic.
  • the first metal layer 160 may also be referred to as a gate metal layer, and the material of the first metal layer 160 may include Mo, Al, Cu, Cu, or an alloy thereof.
  • the interlayer insulating layer 170 is disposed on the first metal layer 160 and the semiconductor layer 140.
  • the interlayer insulating layer 170 may be formed by a deposition technique.
  • the interlayer insulating layer 170 may be a SiOx, SiNx film or a stacked structure film.
  • the second metal layer 180 is disposed on the interlayer insulating layer 170.
  • the second metal layer 180 undergoes a patterning process to form a second capacitor electrode 181.
  • the second capacitor electrode 181 is located on the first Above the capacitor electrode 142.
  • a first storage capacitor region Cs1 is formed between the first capacitor electrode 142 and the second capacitor electrode 181.
  • the passivation layer 190 is disposed on the second metal layer 180.
  • the passivation layer 190 has a passivation layer groove 191.
  • the passivation layer groove 191 is located above the second capacitor electrode 181. .
  • the passivation layer 190 may be formed on the second metal layer 180 by a deposition technique.
  • the groove 191 of the passivation layer can be defined through a photolithography process, and is formed on the passivation layer 190 by an etching technique.
  • the passivation layer 190 may be a SiOx film or a film with a high dielectric constant, such as Al2O3.
  • the color filter 200 is disposed on the passivation layer 190.
  • the flat layer 210 is disposed on the passivation layer 190 and the color filter 200.
  • the flat layer 210 has a flat layer perforation 211 corresponding to the passivation layer groove 191 and is in contact with the passivation layer
  • the groove 191 is in communication.
  • the transparent conductive layer 220 is disposed on the flat layer 210, the flat layer perforation 211 and the passivation layer groove 191, wherein the transparent conductive layer located in the passivation layer groove 191 220 forms a third capacitor electrode 221.
  • a second storage capacitor region Cs2 is formed between the second capacitor electrode 181 and the third capacitor electrode 221.
  • the second capacitor electrode 181 has a second capacitor electrode upper surface S1
  • the passivation layer 190 has a passivation layer upper surface S2
  • the second capacitor electrode upper surface There is a distance D1 between S1 and the upper surface S2 of the passivation layer, and the distance D1 is greater than a thickness T1 of the second storage capacitor region Cs2.
  • the transparent conductive layer 220 is formed on the flat layer 210 by a deposition technique, the flat layer through-hole 211 and the passivation layer groove 191, and the first Three capacitor electrodes 221.
  • the material of the transparent conductive layer 220 may be indium tin oxide (ITO) or other transparent conductive materials with similar characteristics.
  • the pixel defining layer 230 is disposed on the flat layer 210 and the transparent conductive layer 230.
  • the pixel-defining layer 230 may define a light-emitting area through photolithography technology to complete the fabrication of the OLED panel.
  • the OLED panel 10 further includes a plurality of metal conductive holes 171, 172, 173.
  • the plurality of metal conductive holes 171, 172, 173 are provided in the interlayer insulating layer 170 for electrically connecting the semiconductor layer 140 And the second metal layer 180.
  • the interlayer insulating layer 170 has a plurality of metal conductive holes 171, 172 and 173.
  • the conductive holes 171 and 172 are electrically connected to the source and the drain on the TFT active region 141, respectively, and the conductive holes 173 are electrically connected to the first capacitor electrode 142.
  • the second metal layer 180 further has a plurality of metal pads 182, 183, and 184, wherein the metal pad 182 is electrically connected to the metal conductive hole 173, and the metal pads 183 and 184 are electrically connected to the metal, respectively Conductive holes 171, 172.
  • the OLED panel 10 further includes a plurality of transparent conductive holes 222, 223, which are provided in the passivation layer 190 and pass through the flat layer 210 for electrical connection The transparent conductive layer 220 and the second metal layer 180. As shown in FIG. 1, the transparent conductive hole 222 is electrically connected to the metal pad 184, and the transparent conductive hole 223 is electrically connected to the metal pad 182. In this way, the first storage capacitor region Cs1 and the second storage capacitor region Cs2 may be electrically connected, for example, in parallel.
  • the interlayer insulating layer 170 may further include an interlayer insulating layer groove (not shown), the interlayer insulating layer groove is located at Above the first capacitor electrode 142, and part of the second capacitor electrode 181 is disposed in the groove of the interlayer insulating layer.
  • the thickness of the first storage capacitor region Cs1 can be further reduced, so that the capacitance value of the first storage capacitor region Cs1 can be further increased, so that the area occupied by the capacitor structure in the OLED panel 10 can be further reduced, The aperture ratio is further improved.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an OLED panel of the present invention.
  • the invention also provides a manufacturing method of the OLED panel 10, including:
  • Step S100 providing a glass substrate 110.
  • Step S200 a TFT light-shielding layer 120, a buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, a first metal layer 160, an interlayer insulating layer 170 are sequentially formed on the glass substrate 110
  • the second metal layer 180 is patterned to form a second capacitor electrode 181, and the second capacitor electrode 181 is located above the first capacitor electrode 142;
  • step S200 also includes the following detailed steps (step 210 to step 290), the detailed steps are not shown one by one, the results of the detailed steps are shown in FIG. 3, step S210, the TFT shading layer 120 is formed On the glass substrate, for example, it is formed by patterning through a photolithography process and etching.
  • Step S220 the buffer layer 130 is formed on the glass substrate 110 and the TFT light-shielding layer 120, for example, a thin film is formed on the glass substrate 110 and the TFT light-shielding layer 120 by a deposition technique.
  • the buffer layer 130 may be a SiOx, SiNx single-layer film or a layered structure film.
  • Step S230 the semiconductor layer 140 is formed on the buffer layer 130, and the semiconductor layer 140 is patterned to form a TFT active region 141 and a first capacitor electrode 142; the gate insulating layer 150 is formed on On the TFT active area 141.
  • the semiconductor layer 140 may be formed on the buffer layer 130 by a deposition technique.
  • the semiconductor layer 140 may be an amorphous oxide semiconductor, such as indium gallium zinc oxide (indium gallium zinc oxide (IGZO), indium zinc tin (indium zinc tin) oxide, IZTO) or indium gallium zinc ti oxide (IGZTO) or other materials with similar characteristics.
  • the gate insulating layer 150 may be a SiOx, SiNx film or a stacked structure film formed by a deposition technique.
  • Step S240 the first metal layer 160 is formed on the gate insulating layer 150 through a patterning process, wherein the first metal layer 160 covers the TFT active region 141 and the first capacitor outside the area
  • the electrode 142 undergoes a conductive process, for example, to increase the doping concentration.
  • the TFT active region 141 can form a source and a drain, and the first capacitor electrode 142 can be converted into a conductor characteristic.
  • the first metal layer 160 may also be referred to as a gate metal layer, and the material of the first metal layer 160 may include Mo, Al, Cu, Cu, or an alloy thereof.
  • the interlayer insulating layer 170 is formed on the first metal layer 160 and the semiconductor layer 140.
  • the interlayer insulating layer 170 may be a SiOx, SiNx film or a stacked structure film formed by a deposition technique.
  • the interlayer insulating layer 170 has a plurality of metal conductive holes 171, 172, 173.
  • the conductive holes 171 and 172 are electrically connected to the source and the drain on the TFT active region 141, respectively, and the conductive holes 173 are electrically connected to the first capacitor electrode 142.
  • the second metal layer 180 further has a plurality of metal pads 182, 183, 184, wherein the metal pad 182 is electrically connected to the metal conductive hole 173, and the metal pads 183, 184 are electrically connected to the metal Conductive holes 171, 172.
  • Step S260 the second metal layer 180 is formed on the interlayer insulating layer 170, the second metal 180 is patterned to form a second capacitor electrode 181, and the second capacitor electrode 181 is located on the Above the first capacitor electrode 142, a first storage capacitor region Cs1 is formed between the first capacitor electrode 142 and the second capacitor electrode 181.
  • Step S270 forming a passivation layer 190 on the second metal layer 180.
  • the passivation layer 190 may be a SiOx film or a film with a high dielectric constant, such as Al2O3.
  • Step S280 forming a color filter 200 on the passivation layer 190.
  • Step S290 forming a flat layer 210 on the color filter 200 and the passivation layer 190.
  • the flat layer 210 may be an organic photoresist material.
  • Step S300 forming at least one flat layer via 211, 212 and a flat layer groove 213 in the flat layer 210.
  • the flat layer vias 211 and 212 respectively correspond to the metal pads 182 and 184, and the flat layer groove 213 corresponds to and is located on the second capacitor electrode 181.
  • the formation of at least one of the flat layer vias 211, 212 and the flat layer groove 213 in the flat layer 210 may be through a halftone technique, and the halftone technique includes:
  • Step S310 a half-tone mask 500 is provided, wherein the half-tone mask 500 has a light-transmitting region 501, a half-transmitting region 502 and an opaque region 503.
  • Step S320 Expose the flat layer 210 using the halftone mask 500.
  • Step S330 Develop the exposed flat layer 210.
  • step 300 when the flat layer 210 is a positive organic photoresist material, after exposure and development, the flat layer 210 corresponds to the light-transmitting region 501
  • the position of receiving the complete exposure energy is completely exposed, so the flat layer vias 211, 212 are formed after development.
  • the exposure energy received on the flat layer 210 corresponding to the position of the semi-transmissive region 502 is not strong enough, so only the flat layer groove 213 can be formed.
  • the flat layer 210 is a negative organic photoresist material
  • the light-transmitting region 501 and the opaque region 503 on the halftone mask 500 need to be adjusted accordingly, for example FIG. 3 is an example.
  • the light-transmitting area 501 needs to be adjusted to an opaque area
  • the light-opaque area 503 needs to be adjusted to a light-transmitting area.
  • step S400 at least one passivation layer via 192, 193 is formed on the passivation layer 190 exposed by the at least one flat layer via 211, 212.
  • the passivation layer vias 192 and 193 respectively expose the corresponding metal pads 182 and 184 to form the at least one passivation layer via 192 and 193 by an etching technique or other similar techniques.
  • step S500 the material of the planarization layer in the recess 213 of the planarization layer is removed to expose part of the passivation layer 190.
  • the planarization layer material may be removed through an ashing process, or other similar techniques may be used.
  • step S600 a passivation layer groove 191 is formed on the passivation layer 190 exposed by the flat layer groove 213.
  • the details of step S600 may include: forming the passivation layer groove 191 on the passivation layer 190 exposed by the flat layer groove 213 is formed by the passivation layer 190 by an etching technique
  • a passivation layer upper surface S2 etches the passivation layer groove 191 with a first etching depth H1 toward the second capacitor electrode 181 of the second metal layer 180.
  • the first etching depth H1 can be adjusted according to capacitance requirements.
  • step S700 forming a transparent conductive layer 220, the transparent conductive layer 220 is located on the flat layer 210, in the passivation layer vias 192, 193 and the passivation layer groove 191 in.
  • the transparent conductive layer 220 located in the groove 191 of the passivation layer forms a third capacitor electrode 221.
  • a second storage capacitor region Cs2 is formed between the second capacitor electrode 181 and the third capacitor electrode 221.
  • the transparent conductive layer 220 located in the passivation layer vias 192 and 193 forms the transparent conductive holes 222 and 223.
  • the transparent conductive holes 222 and 223 are used to electrically connect the transparent conductive layer 220 and the second metal layer 180.
  • step S250 may further include:
  • Step S251 an interlayer insulating layer groove is formed in the interlayer insulating layer 170 by a halftone technique, and the interlayer insulating layer groove is located above the first capacitor electrode 142; and the subsequent step 26 is also contain:
  • Step S261 Form the second capacitor electrode 181 in the groove of the interlayer insulating layer.
  • the subsequent steps are similar to the steps of the manufacturing method in the above embodiment, and will not be repeated here. In this way, the thickness of the first storage capacitor region Cs1 can be further reduced, and the capacitance of the first storage capacitor region Cs1 can be further increased, so that the area occupied by the capacitor structure in the OLED panel can be further reduced. The aperture ratio is further improved.
  • the beneficial effects of the present invention are: under the same capacitor demand, the OLED panel and its manufacturing method proposed by the present invention improve the capacitor structure and reduce the occupied area, and the corresponding light-emitting area design can be improved to a certain extent, which in turn Opening rate. It means that the halftone technique is used to reduce the thickness between the first capacitor electrode and the second metal layer (such as IGZO-M2) and between the second metal layer and the transparent electrode layer (such as M2-ITO), so the capacitor structure can be reduced Occupied area and maintain the same capacitance value

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Abstract

本发明公开了一种OLED面板及其制作方法。所述OLED面板的制作方法包含：提供一玻璃基板；在所述玻璃基板上依序形成一TFT遮光层、一缓冲层、一半导体层、一栅极绝缘层、一第一金属层、一层间绝缘层、一第二金属层、一钝化层、一彩色滤光片及一平坦层，所述半导体层具有一TFT有源区及一第一电容电极；所述第二金属层具有一第二电容电极，位于所述第一电容电极上方；在所述钝化层中形成至少一钝化层过孔及一钝化层凹槽；以及形成一透明导电层，所述透明导电层位于所述平坦层上、所述钝化层过孔中及所述钝化层凹槽中。

Description

OLED面板及其制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种OLED面板及其制作方法。
 背景技术
随着主动式有机发光显示器(Active Matrix Organic Light Emitting Display, AMOLED)的解析度要求不断提高，相应的增大开口率的最佳办法是顶发光背板，与底发光不同的是其阳极采用的是反射性电极，主要是ITO/Ag/ITO，OLED阴极则为较大透过率的透明阴极，器件完成后开口率大大提高，但目前顶发光还处于完善阶段，小尺寸的已经实现量产，但大尺寸存在明显的IR drop，另外OLED阴极透过率和阻抗等问题使得顶发光大尺寸OLED背板还没能达到量产水平。
 技术问题
目前量产的大尺寸AMOLED背板仍是底发光方式，而底发光设计增加开口率的主要方式是减小非发光区TFT面积， TFT制程如光刻技术也越来越精细化，因此TFT的尺寸设计也越来越小。但时随着TFT的尺寸缩小意味着光刻技术成本的提高，导致AMOLED背板的制作成本提高。
故，有必要提供一种OLED面板及其制作方法，以解决现有技术所存在的问题。
 技术解决方案
本发明的目的在于提供一种OLED面板及其制作方法，对导体化后半导体层与第二金属层之间(例如IGZO-M2)及第二金属层与透明电极之间(例如M2-ITO)并联结构用作电容结构改善，平坦层(PLN层)利用半色调技术(half-tone)辅助，使储存电容区的钝化层(PV层)减薄，根据C=εS/4πkd，当C保持定值，减小d(两极板间距离)，则相应两极正对面积降低，这样整个TFT的尺寸就会相应减少，OLED面板的发光区域的面积可以相应增加，解决了现有技术所存在的问题。
为达成本发明的前述目的，本发明提供一种OLED面板的制作方法，其包含：
提供一玻璃基板；
在所述玻璃基板上依序形成一TFT遮光层、一缓冲层、一半导体层、一栅极绝缘层、一第一金属层、一层间绝缘层及一第二金属层，其中所述TFT遮光层形成在所述玻璃基板上；所述缓冲层形成在所述玻璃基板及所述TFT遮光层上；所述半导体层形成在所述缓冲层上，所述半导体层通过图形化处理形成一TFT有源区及一第一电容电极；所述栅极绝缘层形成在所述TFT有源区上；所述第一金属层经图形化处理形成在所述栅极绝缘层上，其中所述第一金属层覆盖区域以外的所述TFT有源区及所述第一电容电极经历导体化处理；所述层间绝缘层形成在所述第一金属层及所述半导体层上；所述第二金属层形成在所述层间绝缘层上，所述第二金属通过历图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
在所述第二金属层上形成一钝化层；
在所述钝化层上形成一彩色滤光片；
在所述彩色滤光片及所述钝化层形成一平坦层；
通过半色调技术在所述平坦层形成至少一平坦层过孔及一平坦层凹槽，所述至少一平坦层过孔暴露部分所述钝化层，并且所述平坦层凹槽位于所述第二电容电极上方；
通过蚀刻技术在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成至少一钝化层过孔，并且所述钝化层过孔暴露部分所述第二金属层；
移除所述平坦层凹槽内的所述平坦化层材料，用以暴露部分所述部分所述钝化层；
通过蚀刻技术在由所述平坦层凹槽所暴露出的所述钝化层上，形成一钝化层凹槽；以及
形成一透明导电层，所述透明导电层位于所述平坦层上、所述钝化层过孔中及所述钝化层凹槽中。
根据本发明一实施例，形成所述层间绝缘层的步骤更包括：
通过半色调技术在所述层间绝缘层形成一层间绝缘层凹槽，并且所述层间绝缘层凹槽位于所述第一电容电极上方；及
所述层间绝缘层凹槽中形成所述第二电容电极。
根据本发明一实施例，所述通过半色调技术在所述平坦层形成所述至少一平坦层过孔及所述平坦层凹槽包括：
提供一半色调掩模板，其中所述半色调掩模板具有一透光区、一半透光区及一不透光区；
使用所述半色调掩模板对所述平坦层进行曝光；及
对曝光后的所述平坦层进行显影。
本发明还提供一种OLED面板，包括：
一玻璃基板；
一TFT遮光层，设置于所述玻璃基板上；
一缓冲层，设置于所述玻璃基板及所述TFT遮光层上；
一半导体层，设置于所述缓冲层上，所述半导体层经历图形化处理形成一TFT有源区及一第一电容电极；
一栅极绝缘层，设置于所述TFT有源区上；
一第一金属层，经图形化处理设置于所述栅极绝缘层上，其中所述第一金属层覆盖区域以外的所述TFT有源区及所述第一电容电极经历导体化处理；
一层间绝缘层，设置于所述第一金属层及所述半导体层上；
一第二金属层，设置于所述层间绝缘层上，所述第二金属层经历图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
一钝化层，设置于所述第二金属层上，所述钝化层具有一钝化层凹槽，所述钝化层凹槽位于所述第二电容电极上方；
一彩色滤光片设置于所述钝化层上；
一平坦层，设置于所述钝化层及所彩色滤光片上，所述平坦层具有一平坦层穿孔对应所述钝化层凹槽并且与所述钝化层凹槽连通；
一透明导电层，设置于所述平坦层上、所述平坦层穿孔及所述钝化层凹槽中，其中位于所述钝化层凹槽中的所述透明导电层形成一第三电容电极；及
一像素限定层，设置于所述平坦层及所述透明导电层上。
根据本发明一实施例，在所述第一电容电极与所述第二电容电极之间形成一第一储存电容区域，在所述第二电容电极与所述第三电容电极之间形成一第二储存电容区域。
根据本发明一实施例，所述层间绝缘层更包括一层间绝缘层凹槽，所述层间绝缘层凹槽位于所述第一电容电极上方，并且部分所述第二电容电极设于所述层间绝缘层凹槽中。
根据本发明一实施例，所述一第二电容电极具有一第二电容电极上表面，所述钝化层具有一钝化层上表面，所第二电容电极上表面到所述钝化层上表面之间具有一距离，并且所述距离大于所述第二储存电容区域的一厚度。
根据本发明一实施例，所述OLED面板更包括多个金属导电孔，设于所述层间绝缘层中用以电性连接所述半导体层及所述第二金属层。
根据本发明一实施例，所述OLED面板更包括多个透明导电孔，设于所述钝化层中并且穿过所述平坦层，用以电性连接所述透明导电层及所述第二金属层。
本发明还提供一种OLED面板的制作方法，包括：
提供一玻璃基板；
在所述玻璃基板上依序形成一TFT遮光层、一缓冲层、一半导体层、一栅极绝缘层、一第一金属层、一层间绝缘层、一第二金属层、一钝化层、一彩色滤光片及一平坦层，其中所述半导体层通过图形化处理形成一TFT有源区及一第一电容电极；所述第二金属层通过图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
在所述平坦层形成至少一平坦层过孔及一平坦层凹槽；
在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成至少一钝化层过孔；
移除所述平坦层凹槽内的所述平坦化层材料，用以暴露部分所述钝化层；
在由所述平坦层凹槽所暴露出的所述钝化层上，形成一钝化层凹槽；以及
形成一透明导电层，所述透明导电层位于所述平坦层上、所述钝化层过孔中及所述钝化层凹槽中。
根据本发明一实施例，其中所述在所述平坦层形成至少一平坦层过孔及一平坦层凹槽是通过一半色调技术，所述半色调技术包括：
提供一半色调掩模板，其中所述半色调掩模板具有一透光区、一半透光区及一不透光区；
使用所述半色调掩模板对所述平坦层进行曝光；及
对曝光后的所述平坦层进行显影。
根据本发明一实施例，其中所述在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成所述至少一钝化层过孔是通过一蚀刻技术。
根据本发明一实施例，其中所述在由所述平坦层凹槽所暴露出的所述钝化层上，形成所述钝化层凹槽是通过一蚀刻技术，由所述钝化层的一钝化层上表面朝向所述所述第二金属层蚀刻出具有一第一蚀刻深度的所述钝化层凹槽。
根据本发明一实施例，形成所述层间绝缘层的步骤更包括：
通过半色调技术在所述层间绝缘层形成一层间绝缘层凹槽，并且所述层间绝缘层凹槽位于所述第一电容电极上方；及
所述层间绝缘层凹槽中形成所述第二电容电极。
 有益效果
本发明的有益效果为：在相同电容需求下，本发明所提的OLED面板及其制作方法改善了电容结构而减小所占面积，相应的发光区设计可以在一定程度上提高，进而提高了开口率。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1是本发明的一种OLED面板的结构示意图。
图2是本发明的一种OLED面板的制作方法流程示意图。
图3是本发明的一种OLED面板的制作方法的步骤S300的示意图。
图4是本发明的一种OLED面板的制作方法的步骤S400的示意图。
图5是本发明的一种OLED面板的制作方法的步骤S500的示意图。
图6是本发明的一种OLED面板的制作方法的步骤S600的示意图。
图7是本发明的一种OLED面板的制作方法的步骤S700的示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在本文中，用语包含(comprise, comprising, include, including, contain, containing, have, having)及其变化，都可以解释为包含的意义(非独有的)，使得本文中描述的步骤(process)、方法(method)、装置(device)、设备(apparatus)或***(system)不限定于这些功能、部分、元件或步骤的叙述，但可能包含其他元件、功能、部分或步骤未明确列出或存在这样的步骤(process)、方法(method)、物品(article)或设备(apparatus)。此外，除非另有明确规定，用语一(a、an)在本文所用的目的是被理解为是指一个或多个。另外，用语第一、第二、第三等仅仅作为标示使用，并没有强加数字要求或建立顺序。
请参阅图1，图1是本发明的一种OLED面板的结构示意图。本发明提供一种OLED面板10，包括：一玻璃基板110、一TFT遮光层120、一缓冲层130、一半导体层140、一栅极绝缘层150、一第一金属层160、一层间绝缘层170、一第二金属层180、一钝化层190、一彩色滤光片200、一平坦层210、一透明导电层220及一像素限定层230。
所述TFT遮光层120，设置于所述玻璃基板110上。所述TFT遮光层120可以由金属材料所制成，所述TFT遮光层120的材料可以包含Mo、Al、Cu、Ti或其合金。所述TFT遮光层120可以透过光刻制程及蚀刻图形化形成。
所述缓冲层130，设置于所述玻璃基板110及所述TFT遮光层120上。所述缓冲层130可以通过沈积技术形成一薄膜于所述玻璃基板110及所述TFT遮光层120上。所述缓冲层130可以是SiOx、SiNx单层薄膜或叠层结构薄膜。
所述半导体层140，设置于所述缓冲层130上，所述半导体层140经历图形化处理形成一TFT有源区141及一第一电容电极142。所述半导体层140可以通过沈积技术形成于所述缓冲层130上。所述半导体层140可以是非晶氧化物半导体，例如铟镓锌氧化物(indium gallium zinc oxide, IGZO)、铟锌锡氧化物(indium zinc tin oxide, IZTO)或铟镓锌钛氧化物(indium gallium zinc ti oxide, IGZTO)或其他具有相似特性的材料。
所述栅极绝缘层150，设置于所述TFT有源区141上。例如通过沈积一绝缘层，随后所述绝缘层经图形化形成所述栅极绝缘层150。所述栅极绝缘层150可以是SiOx、SiNx薄膜或叠层结构薄膜。
所述第一金属层160，经图形化处理设置于所述栅极绝缘层150上，其中所述第一金属层160覆盖区域以外的所述TFT有源区141及所述第一电容电极142经历导体化处理，例如提高掺杂浓度。如此一来，所述TFT有源区141可以形成源级及漏极，而所述第一电容电极142可以转换为导体特性。所述第一金属层160也可以称为栅极金属层，所述第一金属层160的材料可以包含Mo、A1、Cu、Cu，或者其合金。
所述层间绝缘层170，设置于所述第一金属层160及所述半导体层140上。所述层间绝缘层170可以通过沈积技术形成。所述层间绝缘层170可以是SiOx、SiNx薄膜或叠层结构薄膜。
所述第二金属层180，设置于所述层间绝缘层170上，所述第二金属层180经历图形化处理形成一第二电容电极181，所述第二电容电极181位于所述第一电容电极142上方。而在所述第一电容电极142与所述第二电容电极181之间形成一第一储存电容区域Cs1。
所述钝化层190，设置于所述第二金属层180上，所述钝化层190具有一钝化层凹槽191，所述钝化层凹槽191位于所述第二电容电极181上方。所述钝化层190可通过沈积技术形成在所述第二金属层180上。所述钝化层凹槽191可以透过光刻制程定义，并且通过蚀刻技术形成在所述钝化层190上。所述钝化层190可以是SiOx薄膜或是具有高介电常数的薄膜，例如Al2O3。
所述彩色滤光片200设置于所述钝化层190上。
所述平坦层210，设置于所述钝化层190及所彩色滤光片200上，所述平坦层210具有一平坦层穿孔211对应所述钝化层凹槽191并且与所述钝化层凹槽191连通。
所述透明导电层220，设置于所述平坦层210上、所述平坦层穿孔211及所述钝化层凹槽191中，其中位于所述钝化层凹槽191中的所述透明导电层220形成一第三电容电极221。并且在所述第二电容电极181与所述第三电容电极221之间形成一第二储存电容区域Cs2。此外，请参阅图1及图6，所述一第二电容电极181具有一第二电容电极上表面S1，所述钝化层190具有一钝化层上表面S2，所第二电容电极上表面S1到所述钝化层上表面S2之间具有一距离D1，并且所述距离D1大于所述第二储存电容区域Cs2的一厚度T1。所述透明导电层220通过沈积技术形成于所述平坦层210上、所述平坦层穿孔211及所述钝化层凹槽191中，并且透过光刻技术及蚀刻技术定义形成所述第三电容电极221。所述透明导电层220的材料可以是氧化铟锡(ITO)或是其他具有类似特性的透明导电材料。
所述像素限定层230，设置于所述平坦层210及所述透明导电层230上。所述像素限定层230可以通过光刻技术定义发光区，完成OLED面板的制作。
所述OLED面板10更包含多个金属导电孔171、172、173，所述多个金属导电孔171、172、173设于所述层间绝缘层170中用以电性连接所述半导体层140及所述第二金属层180。如图1所示，所述层间绝缘层170具有多个金属导电孔171、172、173。所述导电孔171、172分别电性连接所述TFT有源区141上的源级及漏极，所述导电孔173电性连接所述所述第一电容电极142。所述第二金属层180还具有多个金属接垫182、183、184，其中金属接垫182电性连接所述金属导电孔173，所述金属接垫183、184分别电性连接所述金属导电孔171、172。
所述OLED面板10更包含多个透明导电孔222、223，所述多个透明导电孔222、223设于所述钝化层190中并且穿过所述平坦层210，用以电性连接所述透明导电层220及所述第二金属层180。如图1所示，所述透明导电孔222电性连接所述所述金属接垫184，所述透明导电孔223电性连接所述所述金属接垫182。如此一来，可以将所述第一储存电容区域Cs1与所述第二储存电容区域Cs2电性连接，例如并联。
如上述实施例的延伸变化，在本发明的另一实施例中，所述层间绝缘层170可以更包括一层间绝缘层凹槽(未绘示)，所述层间绝缘层凹槽位于所述第一电容电极142上方，并且部分所述第二电容电极181设于所述层间绝缘层凹槽中。如此一来，所述第一储存电容区域Cs1的厚度可以进一步的减低，使得所述第一储存电容区域Cs1的电容值可以进一步提高，使得OLED面板10中的电容结构所占面积可以进一步缩小，进一步的提高了开口率。
图2是本发明的一种OLED面板的制作方法流程示意图。本发明还提供一种OLED面板10的制作方法，包括：
步骤S100、提供一玻璃基板110。
步骤S200、在所述玻璃基板110上依序形成一TFT遮光层120、一缓冲层130、一半导体层140、一栅极绝缘层150、一第一金属层160、一层间绝缘层170、一第二金属层180、一钝化层190、一彩色滤光片200及一平坦层210，其中所述半导体层140通过图形化处理形成一TFT有源区141及一第一电容电极142；所述第二金属层180通过图形化处理形成一第二电容电极181，所述第二电容电极181位于所述第一电容电极142上方；
其中，步骤S200也包含了以下详细步骤(步骤210至步骤290)，所述详细步骤未逐一绘示，所述详细步骤的成果如图3所示，步骤S210、所述TFT遮光层120形成所述玻璃基板上，例如透过光刻制程及蚀刻图形化形成。
步骤S220、所述缓冲层130形成在所述玻璃基板110及所述TFT遮光层120上，例如通过沈积技术形成一薄膜于所述玻璃基板110及所述TFT遮光层120上。所述缓冲层130可以是SiOx、SiNx单层薄膜或叠层结构薄膜。
步骤S230、所述半导体层140形成在所述缓冲层130上，所述半导体层140通过图形化处理形成一TFT有源区141及一第一电容电极142；所述栅极绝缘层150形成在所述TFT有源区141上。所述半导体层140可以通过沈积技术形成于所述缓冲层130上。所述半导体层140可以是非晶氧化物半导体，例如铟镓锌氧化物(indium gallium zinc oxide, IGZO)、铟锌锡氧化物(indium zinc tin oxide, IZTO)或铟镓锌钛氧化物(indium gallium zinc ti oxide, IGZTO)或其他具有相似特性的材料。所述栅极绝缘层150可以是通过沈积技术形成的SiOx、SiNx薄膜或叠层结构薄膜。
步骤S240、所述第一金属层160经图形化处理形成在所述栅极绝缘层150上，其中所述第一金属层160覆盖区域以外的所述TFT有源区141及所述第一电容电极142经历导体化处理，例如提高掺杂浓度。如此一来，所述TFT有源区141可以形成源级及漏极，而所述第一电容电极142可以转换为导体特性。所述第一金属层160也可以称为栅极金属层，所述第一金属层160的材料可以包含Mo、A1、Cu、Cu，或者其合金。
步骤S250、所述层间绝缘层170形成在所述第一金属层160及所述半导体层140上。所述层间绝缘层170可以是通过沈积技术形成的SiOx、SiNx薄膜或叠层结构薄膜。所述层间绝缘层170具有多个金属导电孔171、172、173。所述导电孔171、172分别电性连接所述TFT有源区141上的源级及漏极，所述导电孔173电性连接所述所述第一电容电极142。所述第二金属层180还具有多个金属接垫182、183、184，其中金属接垫182电性连接所述金属导电孔173，所述金属接垫183、184分别电性连接所述金属导电孔171、172。
步骤S260、所述第二金属层180形成在所述层间绝缘层170上，所述第二金属180通过历图形化处理形成一第二电容电极181，所述第二电容电极181位于所述第一电容电极142上方，使得所述第一电容电极142与所述第二电容电极181之间形成一第一储存电容区域Cs1。
步骤S270、在所述第二金属层180上形成一钝化层190。所述钝化层190可以是SiOx薄膜或是具有高介电常数的薄膜，例如Al2O3。
步骤S280、在所述钝化层190上形成一彩色滤光片200。
步骤S290、在所述彩色滤光片200及所述钝化层190上形成一平坦层210。其中所述平坦层210可以是有机光阻材料。
步骤S300、在所述平坦层210形成至少一平坦层过孔211、212及一平坦层凹槽213。其中所述平坦层过孔211、212分别对应所述金属接垫182、184，所述平坦层凹槽213对应并且位于所述第二电容电极181上。如图3所示，所述在所述平坦层210形成至少一所述平坦层过孔211、212及所述平坦层凹槽213可以是通过一半色调技术，所述半色调技术包括：
步骤S310、提供一半色调掩模板500，其中所述半色调掩模板500具有一透光区501、一半透光区502及一不透光区503。
步骤S320、使用所述半色调掩模板500对所述平坦层210进行曝光。
步骤S330、对曝光后的所述平坦层210进行显影。
以图3所示的实施例来说明，在步骤300的过程中，当所述平坦层210是正型有机光阻材料时，在曝光显影之后，所述平坦层210上对应所述透光区501的位置接收完整的曝光能量完全地曝光，因此在显影之后形成了所述平坦层过孔211、212。而所述平坦层210上对应所述半透光区502的位置所接收的曝光能量不够强，因此仅能形成了所述平坦层凹槽213。透过这样的半色调技术就可以在同一道掩模板及同一次曝光中形成不同深度的凹陷。同理，若所述平坦层210是负型有机光阻材料时，所述半色调掩模板500上的所述透光区501及所述不透光区503就需要相对应的调整，例如以图3为例，所述透光区501需要调整为不透光区，而所述不透光区503需要调整为透光区。
如图4所示，步骤S400、在由所述至少一平坦层过孔211、212所暴露出的所述钝化层190上，形成至少一钝化层过孔192、193。所述钝化层过孔192、193分别暴露出相对应的所述金属接垫182、184而形成所述至少一钝化层过孔192、193可以是通过一蚀刻技术或其他相似技术。
如图5所示，步骤S500、移除所述平坦层凹槽213内的所述平坦化层材料，用以暴露部分所述钝化层190。步骤S500可以透过灰化(Ash)处理来移除所述平坦化层材料，或是利用其他类似的技术进行。
如图6所示，步骤S600、在由所述平坦层凹槽213所暴露出的所述钝化层190上，形成一钝化层凹槽191。步骤S600细节可以包含：在由所述平坦层凹槽213所暴露出的所述钝化层190上，形成所述钝化层凹槽191是通过一蚀刻技术，由所述钝化层190的一钝化层上表面S2朝向所述所述第二金属层180的所述第二电容电极181蚀刻出具有一第一蚀刻深度H1的所述钝化层凹槽191。所述第一蚀刻深度H1可以根据电容需求调整。
如图7所示，步骤S700、形成一透明导电层220，所述透明导电层220位于所述平坦层210上、所述钝化层过孔192、193中及所述钝化层凹槽191中。其中位于所述钝化层凹槽191中的所述透明导电层220形成一第三电容电极221。在所述第二电容电极181与所述第三电容电极221之间形成一第二储存电容区域Cs2。而位于所述钝化层过孔192、193中的透明导电层220形成所述透明导电孔222、223。所述透明导电孔222、223用以电性连接所述透明导电层220及所述第二金属层180。
在本发明的另一实施例的OLED面板的制作方法，可以视为上述实施例的变化延伸，其中在步骤S250更可以包含：
步骤S251、通过半色调技术在所述层间绝缘层170形成一层间绝缘层凹槽，并且所述层间绝缘层凹槽位于所述第一电容电极142上方；并且随后的步骤26中也包含：
步骤S261、在所述层间绝缘层凹槽中形成所述第二电容电极181。而随后的步骤与上述实施例的制作方法步骤相似，在此不再赘述。如此一来，所述第一储存电容区域Cs1可以进一步的厚度可以进一步的减低，所述第一储存电容区域Cs1的电容值可以进一步提高，使得OLED面板中的电容结构所占面积可以进一步缩小，进一步的提高了开口率。
本发明的有益效果为：在相同电容需求下，本发明所提的OLED面板及其制作方法改善了电容结构而减小所占面积，相应的发光区设计可以在一定程度上提高，进而提高了开口率。意即利用半色调技术降低第一电容电极与第二金属层之间(例如IGZO-M2)及第二金属层与透明电极层之间(例如M2-ITO)的厚度，因此可以电容结构可以减少占用的面积并且维持相同的电容值
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种OLED面板的制作方法，其包含：
    提供一玻璃基板；
    在所述玻璃基板上依序形成一TFT遮光层、一缓冲层、一半导体层、一栅极绝缘层、一第一金属层、一层间绝缘层及一第二金属层，其中所述TFT遮光层形成在所述玻璃基板上；所述缓冲层形成在所述玻璃基板及所述TFT遮光层上；所述半导体层形成在所述缓冲层上，所述半导体层通过图形化处理形成一TFT有源区及一第一电容电极；所述栅极绝缘层形成在所述TFT有源区上；所述第一金属层经图形化处理形成在所述栅极绝缘层上，其中所述第一金属层覆盖区域以外的所述TFT有源区及所述第一电容电极经历导体化处理；所述层间绝缘层形成在所述第一金属层及所述半导体层上；所述第二金属层形成在所述层间绝缘层上，所述第二金属通过历图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
    在所述第二金属层上形成一钝化层；
    在所述钝化层上形成一彩色滤光片；
    在所述彩色滤光片及所述钝化层形成一平坦层；
    通过半色调技术在所述平坦层形成至少一平坦层过孔及一平坦层凹槽，所述至少一平坦层过孔暴露部分所述钝化层，并且所述平坦层凹槽位于所述第二电容电极上方；
    通过蚀刻技术在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成至少一钝化层过孔，并且所述钝化层过孔暴露部分所述第二金属层；
    移除所述平坦层凹槽内的所述平坦化层材料，用以暴露部分所述部分所述钝化层；
    通过蚀刻技术在由所述平坦层凹槽所暴露出的所述钝化层上，形成一钝化层凹槽；以及
    形成一透明导电层，所述透明导电层位于所述平坦层上、所述钝化层过孔中及所述钝化层凹槽中。
  2. 如权利要求1所述的OLED面板的制作方法，其中形成所述层间绝缘层的步骤更包括：
    通过半色调技术在所述层间绝缘层形成一层间绝缘层凹槽，并且所述层间绝缘层凹槽位于所述第一电容电极上方；及
    所述层间绝缘层凹槽中形成所述第二电容电极。
  3. 如权利要求1所述的OLED面板的制作方法，其中所述通过半色调技术在所述平坦层形成所述至少一平坦层过孔及所述平坦层凹槽包括：
    提供一半色调掩模板，其中所述半色调掩模板具有一透光区、一半透光区及一不透光区；
    使用所述半色调掩模板对所述平坦层进行曝光；及
    对曝光后的所述平坦层进行显影。
  4. 一种OLED面板，其包含：
    一玻璃基板；
    一TFT遮光层，设置于所述玻璃基板上；
    一缓冲层，设置于所述玻璃基板及所述TFT遮光层上；
    一半导体层，设置于所述缓冲层上，所述半导体层经历图形化处理形成一TFT有源区及一第一电容电极；
    一栅极绝缘层，设置于所述TFT有源区上；
    一第一金属层，经图形化处理设置于所述栅极绝缘层上，其中所述第一金属层覆盖区域以外的所述TFT有源区及所述第一电容电极经历导体化处理；
    一层间绝缘层，设置于所述第一金属层及所述半导体层上；
    一第二金属层，设置于所述层间绝缘层上，所述第二金属层经历图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
    一钝化层，设置于所述第二金属层上，所述钝化层具有一钝化层凹槽，所述钝化层凹槽位于所述第二电容电极上方；
    一彩色滤光片设置于所述钝化层上；
    一平坦层，设置于所述钝化层及所彩色滤光片上，所述平坦层具有一平坦层穿孔对应所述钝化层凹槽并且与所述钝化层凹槽连通；
    一透明导电层，设置于所述平坦层上、所述平坦层穿孔及所述钝化层凹槽中，其中位于所述钝化层凹槽中的所述透明导电层形成一第三电容电极；及
    一像素限定层，设置于所述平坦层及所述透明导电层上。
  5. 如权利要求4所述的OLED面板，其中在所述第一电容电极与所述第二电容电极之间形成一第一储存电容区域，在所述第二电容电极与所述第三电容电极之间形成一第二储存电容区域。
  6. 如权利要求5所述的OLED面板，其中所述层间绝缘层更包括一层间绝缘层凹槽，所述层间绝缘层凹槽位于所述第一电容电极上方，并且部分所述第二电容电极设于所述层间绝缘层凹槽中。
  7. 如权利要求5所述的OLED面板，其中所述一第二电容电极具有一第二电容电极上表面，所述钝化层具有一钝化层上表面，所第二电容电极上表面到所述钝化层上表面之间具有一距离，并且所述距离大于所述第二储存电容区域的一厚度。
  8. 如权利要求4所述的OLED面板，其中所述OLED面板更包括多个金属导电孔，设于所述层间绝缘层中用以电性连接所述半导体层及所述第二金属层。
  9. 如权利要求8所述的OLED面板，其中所述OLED面板更包括多个透明导电孔，设于所述钝化层中并且穿过所述平坦层，用以电性连接所述透明导电层及所述第二金属层。
  10.    一种OLED面板的制作方法，其包含：
    提供一玻璃基板；
    在所述玻璃基板上依序形成一TFT遮光层、一缓冲层、一半导体层、一栅极绝缘层、一第一金属层、一层间绝缘层、一第二金属层、一钝化层、一彩色滤光片及一平坦层，其中所述半导体层通过图形化处理形成一TFT有源区及一第一电容电极；所述第二金属层通过图形化处理形成一第二电容电极，所述第二电容电极位于所述第一电容电极上方；
    在所述平坦层形成至少一平坦层过孔及一平坦层凹槽；
    在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成至少一钝化层过孔；
    移除所述平坦层凹槽内的所述平坦化层材料，用以暴露部分所述钝化层；
    在由所述平坦层凹槽所暴露出的所述钝化层上，形成一钝化层凹槽；以及
    形成一透明导电层，所述透明导电层位于所述平坦层上、所述钝化层过孔中及所述钝化层凹槽中。
  11.    如权利要求10所述的OLED面板的制作方法，其中所述在所述平坦层形成至少一平坦层过孔及一平坦层凹槽是通过一半色调技术，所述半色调技术包括：
    提供一半色调掩模板，其中所述半色调掩模板具有一透光区、一半透光区及一不透光区；
    使用所述半色调掩模板对所述平坦层进行曝光；及
    对曝光后的所述平坦层进行显影。
  12.    如权利要求10所述的OLED面板的制作方法，其中所述在由所述至少一平坦层过孔所暴露出的所述钝化层上，形成所述至少一钝化层过孔是通过一蚀刻技术。
  13.    如权利要求10所述的OLED面板的制作方法，其中所述在由所述平坦层凹槽所暴露出的所述钝化层上，形成所述钝化层凹槽是通过一蚀刻技术，由所述钝化层的一钝化层上表面朝向所述所述第二金属层蚀刻出具有一第一蚀刻深度的所述钝化层凹槽。
  14.    如权利要求10所述的OLED面板的制作方法，其中形成所述层间绝缘层的步骤更包括：
    通过半色调技术在所述层间绝缘层形成一层间绝缘层凹槽，并且所述层间绝缘层凹槽位于所述第一电容电极上方；及
    在所述层间绝缘层凹槽中形成所述第二电容电极。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111969015A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种阵列基板膜层结构及其制备方法
CN113793856A (zh) * 2021-09-13 2021-12-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110071148A (zh) * 2019-04-10 2019-07-30 深圳市华星光电半导体显示技术有限公司 有机发光二极管显示装置及其制造方法
CN110071069B (zh) * 2019-04-19 2021-11-23 深圳市华星光电半导体显示技术有限公司 显示背板及其制作方法
CN110112193B (zh) * 2019-04-29 2021-10-15 上海天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN110164870A (zh) * 2019-05-14 2019-08-23 深圳市华星光电半导体显示技术有限公司 含电容背板构造
CN110120466A (zh) * 2019-05-30 2019-08-13 京东方科技集团股份有限公司 显示基板及其制造方法、显示面板
CN110473897B (zh) * 2019-06-28 2024-02-27 福建华佳彩有限公司 一种内嵌式oled显示面板及其制作方法
CN110416263A (zh) * 2019-07-22 2019-11-05 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN110867474B (zh) * 2019-11-26 2022-01-25 深圳市华星光电半导体显示技术有限公司 Oled显示面板
US11900874B2 (en) 2020-11-27 2024-02-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel circuit and driving method thereof, display substrate and display apparatus
CN116868702A (zh) * 2021-01-27 2023-10-10 华为技术有限公司 半导体器件及其制造方法以及显示设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101286515A (zh) * 2007-04-13 2008-10-15 群康科技(深圳)有限公司 薄膜晶体管基板及其制造方法
US20180012947A1 (en) * 2016-07-06 2018-01-11 Lg Display Co., Ltd. Organic Light Emitting Display Device Comprising Multi-Type Thin Film Transistor and Method of Manufacturing the Same
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108417582B (zh) * 2012-06-15 2022-06-07 索尼公司 显示装置
CN104064688B (zh) * 2014-07-11 2016-09-21 深圳市华星光电技术有限公司 具有存储电容的tft基板的制作方法及该tft基板
KR102408898B1 (ko) * 2015-06-19 2022-06-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
CN107403804B (zh) * 2016-05-17 2020-10-30 群创光电股份有限公司 显示设备
CN107039465A (zh) * 2017-04-28 2017-08-11 京东方科技集团股份有限公司 一种阵列基板及制备方法、显示面板和显示装置
CN107359188A (zh) * 2017-08-28 2017-11-17 惠科股份有限公司 显示面板及其制造方法
CN108550582B (zh) * 2018-05-09 2022-11-08 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101286515A (zh) * 2007-04-13 2008-10-15 群康科技(深圳)有限公司 薄膜晶体管基板及其制造方法
US20180012947A1 (en) * 2016-07-06 2018-01-11 Lg Display Co., Ltd. Organic Light Emitting Display Device Comprising Multi-Type Thin Film Transistor and Method of Manufacturing the Same
CN107680993A (zh) * 2017-10-23 2018-02-09 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111969015A (zh) * 2020-08-19 2020-11-20 福建华佳彩有限公司 一种阵列基板膜层结构及其制备方法
CN113793856A (zh) * 2021-09-13 2021-12-14 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113793856B (zh) * 2021-09-13 2024-05-07 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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