WO2020015630A1 - 发光二极管的半导体芯片及其制造方法 - Google Patents

发光二极管的半导体芯片及其制造方法 Download PDF

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Publication number
WO2020015630A1
WO2020015630A1 PCT/CN2019/096141 CN2019096141W WO2020015630A1 WO 2020015630 A1 WO2020015630 A1 WO 2020015630A1 CN 2019096141 W CN2019096141 W CN 2019096141W WO 2020015630 A1 WO2020015630 A1 WO 2020015630A1
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type electrode
semiconductor chip
layer
type
semiconductor
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PCT/CN2019/096141
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English (en)
French (fr)
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邬新根
李俊贤
刘英策
魏振东
周弘毅
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厦门乾照光电股份有限公司
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Priority claimed from CN201810783043.XA external-priority patent/CN108831976B/zh
Priority claimed from CN201810784329.XA external-priority patent/CN109192830B/zh
Application filed by 厦门乾照光电股份有限公司 filed Critical 厦门乾照光电股份有限公司
Priority to US16/961,259 priority Critical patent/US11469349B2/en
Publication of WO2020015630A1 publication Critical patent/WO2020015630A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials

Definitions

  • the invention relates to an LED chip, in particular to a semiconductor chip of a light emitting diode and a manufacturing method thereof.
  • front-mounted LED chips There are two types of front-mounted LED chips in the prior art.
  • the industry usually uses photolithography steps to name the two types of front-mounted LED chips, that is, a three-channel front-mounted LED chip and a five-channel front-mounted LED chip. That is to say, three-structured front-mounted LED chips use three lithographic steps during the fabrication process, and five-structured front-mounted LED chips use five lithographic steps during the fabrication process.
  • five-structured The lithography steps of the LED chip can also be simplified from five lithography steps to four lithography steps.
  • the process includes the Mesa process (step, which refers to the process of making the N-type layer exposed area on the surface of the epitaxial wafer by dry etching), and ITO process (refers to the transparent conductive film).
  • Layer pattern process) and PV & Pad process referring to the process that the passivation layer and the electrode use the same process of photolithographic pattern production
  • the process includes the Mesa process, the CB process (current blocking Layer manufacturing process), ITO process, and PV & Pad process. From a structural point of view, there is no significant difference between three-structured form-fitted LED chips and five-structured form-fitted LED chips.
  • five-structured form-mounted LED chips have more current blocking layer (CB) than five-structured form-mounted LED chips.
  • the structure is a current blocking layer of the P-type electrode. The purpose is to prevent the current crowding effect caused by the current injected by the LED chip from the P-type electrode being concentrated under the P-type electrode.
  • the increase in the current blocking layer structure is to increase the cost of the process of mounting the LED chip.
  • the low-power chips and display chips commonly used in the industry are three-channel structure-mounted LED chips, while the high-power chips and lighting chips are five-channel structure-mounted. LED chip.
  • the P-type electrode current flows through the metal electrode to be expanded by the metal electrode and is injected into the transparent conductive layer, and then the transparent conductive layer is injected into the P-type gallium nitride layer. Finally, it enters the active layer; the N-type electrode resistance is composed of electrons passing through the metal electrode to be expanded by the metal electrode, and then injected into the N-type gallium nitride layer, and finally enters the active region to compound light emission in the active region. From the perspective of the entire current process, the conductivity of the metal electrode is higher than the conductivity of the semiconductor layer.
  • the current on the surface of the P-type electrode tends to gather at the end of the P-interdigital electrode. From the curve of the light-emitting characteristics of the five-channel structure-mounted LED chip, as the current density increases, the brightness tends to rise and then decrease, and there is a saturation current density, which will affect the light-emitting efficiency of the five-channel structure-mounted LED chip.
  • the ideal high-brightness light-emitting chip structure can maintain the current density of the mounted LED chip in a region with high luminous efficiency.
  • the current five-channel structured mounted LED chip cannot be achieved.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein the brightness of the semiconductor chip can be effectively improved.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method for manufacturing the same, in which a current injected into a P-type semiconductor layer of the semiconductor chip can be uniformly distributed, thereby facilitating the brightness of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein the semiconductor chip provides a P-type electrode, and the current injected into the semiconductor chip through the P-type electrode can be forcibly distributed. Manner, so that the current injected into the P-type semiconductor layer can be evenly distributed, which is beneficial to improving the brightness of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method for manufacturing the same, wherein the semiconductor chip provides a current blocking layer laminated on the P-type semiconductor layer and a layer stacked on the P-type semiconductor layer and covering the semiconductor device.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method for manufacturing the same, wherein a P-type interdigit of the P-type electrode is inserted into the transparent conductive layer, so that a current injected into the P-type electrode can be further self-controlled.
  • the transparent conductive layer is injected into the surface and the inside of the transparent conductive layer. In this way, the current can be uniformly distributed to the P-type semiconductor layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein the transparent conductive layer provides at least one perforation to correspond to the current blocking layer, and wherein the P-type fork of the P-type electrode is Refers to the perforations formed and held in the transparent conductive layer, so that the current injected into the P-type electrode can be further injected into the transparent conductive layer from the surface and the inside of the transparent conductive layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method of manufacturing the same, wherein in the process of forming the P-type electrode, the P-type interdigital of the P-type electrode is formed on and held by the P-type electrode.
  • This combination of the P-type electrode and the transparent conductive layer can effectively ensure the stability and reliability of the chip. Sex.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein the semiconductor chip provides the transparent conductive layer laminated on the P-type semiconductor layer and the P layer laminated on the transparent conductive layer.
  • Type electrodes in which the current injected through the P-type electrode can be uniformly injected into the P-type semiconductor layer after being diffused by the transparent conductive layer, thereby helping to improve the overall brightness of the semiconductor chip.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method for manufacturing the same, wherein the P-type electrode provides at least one row of P-type interdigital fingers, and one row of the P-type interdigital fingers is arranged along a length direction of the semiconductor chip. And inserted into the transparent conductive layer. In this way, a current can be injected into the transparent conductive layer from the surface and the inside of the transparent conductive layer through the P-type electrode, which is beneficial for uniform injection. A current flows to the P-type semiconductor layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein the P-type electrode provides a P-type electrode pad and at least one P-type electrode extension strip, wherein the P-type electrode pad is formed on A first end portion of the semiconductor chip, the P-type electrode extension strip extending from the P-type electrode pad toward a second end portion of the semiconductor chip, and each P in a row of the P-type interdigital fingers Type interdigital fingers are formed at intervals on the P-type electrode extension strips, and at least one of the P-type interdigital fingers in a row and the adjacent P-type interdigital fingers have different shapes or sizes, In this way, it is advantageous that the current injected through the P-type electrode can be uniformly injected into the P-type semiconductor layer after being diffused by the transparent conductive layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein a shape of each of the P-shaped interdigital fingers in a row of the P-shaped interdigital fingers is gradually changed along the P-shaped electrode extension bar, In this way, it is beneficial that the current injected through the P-type electrode can be uniformly injected into the P-type semiconductor layer after being diffused by the transparent conductive layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a manufacturing method thereof, wherein a size of each of the P-shaped interdigital fingers in a row of the P-shaped interdigital fingers is gradually changed along the P-shaped electrode extension bar, In this way, it is beneficial that the current injected through the P-type electrode can be uniformly injected into the P-type semiconductor layer after being diffused by the transparent conductive layer.
  • An object of the present invention is to provide a semiconductor chip of a light emitting diode and a method for manufacturing the same, wherein a distance between two adjacent P-type interdigital fingers in a row of the P-type interdigital fingers is extended along the P-type electrode In this way, the bar is gradually changed, which facilitates that the current injected through the P-type electrode can be uniformly injected into the P-type semiconductor layer after being diffused by the transparent conductive layer.
  • the present invention provides a semiconductor chip of a light emitting diode, which includes:
  • An epitaxial unit wherein the epitaxial unit includes a substrate and an N-type semiconductor layer, an active region, and a P-type semiconductor layer sequentially grown from the substrate, wherein the epitaxial unit has at least one semiconductor exposed portion The exposed portion of the semiconductor extends from the P-type semiconductor layer through the active region to the N-type semiconductor layer;
  • At least one current blocking layer wherein the current blocking layer is stacked on the P-type semiconductor layer of the epitaxial unit;
  • a transparent conductive layer wherein the transparent conductive layer has at least one perforation, wherein the transparent conductive layer is laminated on the P-type semiconductor layer so as to cover the current blocking layer, and the transparent conductive layer is The perforation corresponds to the current blocking layer;
  • An electrode group wherein the electrode group includes at least one N-type electrode and at least one P-type electrode, wherein the N-type electrode is stacked on the N-type semiconductor layer in a manner to be formed on the semiconductor bare portion, wherein the The P-type electrode has at least one P-type interdigital.
  • the P-type electrode is laminated on the transparent conductive layer, the P-type interdigital of the P-type electrode is formed on and held by the transparent conductive layer. The perforation.
  • the N-type electrode includes an N-type electrode pad formed at a second end portion of the semiconductor chip and a first end from the N-type electrode pad to the semiconductor chip. At least one N-type electrode extension strip extending in the direction of the substrate, wherein the P-type electrode includes a P-type electrode pad formed at a first end portion of the semiconductor chip, and the P-type electrode pad extends from the P-type electrode pad to the semiconductor. At least two P-type electrode extension strips extending in the direction of the second end of the chip, at least one of the N-type electrode extension strips is held between two adjacent P-type electrode extension strips.
  • the number of the N-type electrode extension strips of the N-type electrode is one, and the N-type electrode extension strips are along the length direction of the semiconductor chip in the middle of the semiconductor chip. Extending, wherein the number of the P-type electrode extension strips of the P-type electrode is two, and the two P-type electrode extension strips are symmetrical with each other along the edge of the semiconductor chip along the semiconductor chip Length direction.
  • the number of the N-type electrode extension strips of the N-type electrode is two, and the N-type electrode extension strips are along the length of the semiconductor chip in the middle of the semiconductor chip.
  • Direction extension wherein the number of the P-type electrode extension strips of the P-type electrode is three, which are a first P-type electrode extension strip, a second P-type electrode extension strip, and a third P-type electrode extension Strip, the first P-type electrode extension strip and the third P-type electrode extension strip extend along the length direction of the semiconductor chip at the edges of the semiconductor chip in a mutually symmetrical manner, and the second P-type electrode extension strip
  • An electrode extension strip extends in the middle of the semiconductor chip along the length direction of the semiconductor chip, and one of the N-type electrode extension strips is held between the first P-type electrode extension strip and the second P-type electrode. Between the extension bars, another N-type electrode extension bar is held between the second P-type electrode extension bar and the third P-type electrode extension bar.
  • the N-type electrode includes an N-type electrode pad formed at a second end portion of the semiconductor chip and a first end from the N-type electrode pad to the semiconductor chip. At least two N-type electrode extension strips extending in the direction of the substrate, wherein the P-type electrode includes a P-type electrode pad formed at a first end portion of the semiconductor chip, and the P-type electrode pad extends from the P-type electrode pad to the semiconductor At least one P-type electrode extension strip extending in the direction of the second end portion of the chip, wherein at least one of the P-type electrode extension strips is held between two adjacent N-type electrode extension strips.
  • the number of the N-type electrode extension strips of the N-type electrode is two, and the two N-type electrode extension strips are symmetrical along the edges of the semiconductor chip in a mutually symmetrical manner. Extending along the length of the semiconductor chip, wherein the number of the P-type electrode extension strips of the P-type electrode is one, and the P-type electrode extension strips run along the semiconductor chip in the middle of the semiconductor chip Length direction.
  • the number of the N-type electrode extension strips of the N-type electrode is three, which are a first N-type electrode extension strip, a second N-type electrode extension strip, and a third An N-type electrode extension strip, the first N-type electrode extension strip and the third N-type electrode extension strip extending along the length direction of the semiconductor chip at edges of the semiconductor chip in a mutually symmetrical manner, the The second N-type electrode extension strip extends in the middle of the semiconductor chip along the length direction of the semiconductor chip, wherein the number of the P-type electrode extension strips of the P-type electrode is two, of which two are P-type electrode extension strips extend in the middle of the semiconductor chip along the length of the semiconductor chip, and one of the P-type electrode extension strips is held between the first N-type extension strips and the second N Between the P-type electrode expansion strips, another P-type electrode expansion strip is held between the second N-type electrode expansion strip and the third N-type electrode expansion strip.
  • the N-type electrode includes an N-type electrode pad formed at a second end portion of the semiconductor chip, and the P-type electrode includes a first end formed at the semiconductor chip. And a P-type electrode pad extending from the P-type electrode pad toward a second end portion of the semiconductor chip.
  • At least one of the current blocking layers is laminated on a surface of the N-type semiconductor layer of the epitaxial unit that is exposed on the semiconductor bare portion, wherein the N-type electrode is overlaid on The current blocking layer of the N-type semiconductor layer.
  • the current blocking layer laminated on the N-type semiconductor layer is in a strip shape, and extends along a length direction of the semiconductor chip.
  • the number of the current blocking layers stacked on the N-type semiconductor layer is plural, and the current blocking layers extend in a stripe arrangement along the length direction of the semiconductor chip. And there is a gap between two adjacent current blocking layers.
  • the semiconductor chip further includes a passivation layer, wherein the passivation layer has a first through hole and a second through hole, and wherein the passivation layer covers the N
  • the P-type electrode and the P-type electrode are stacked on the P-type semiconductor layer and the transparent conductive layer, and the first through hole of the passivation layer corresponds to the N-type electrode, the passivation The second through hole of the layer corresponds to the P-type electrode.
  • the present invention further provides a method for manufacturing a semiconductor chip, wherein the manufacturing method includes the following steps:
  • the manufacturing method further includes steps:
  • the method further includes the following steps:
  • the step (a) before the step (a.2), further includes a step: a positive photolithography current blocking layer structure, so that in the step (a.2), Wet etching the insulating layer according to a current blocking layer structure to form the current blocking layer laminated on the P-type semiconductor layer through the insulating layer, and after the step (a.2), the Step (a) further includes the step of removing the photoresist.
  • a material of the insulating layer is a SiO2 material.
  • the reaction gases SiH4, N2O, and N2 are used to deposit the insulating layer on the P-type semiconductor layer.
  • the thickness of the insulating layer ranges from 500 Angstroms to 10,000 Angstroms.
  • the thickness dimension of the photoresist ranges from 0.5 ⁇ m to 5 ⁇ m.
  • an etching solution used for wet etching the insulating layer is a mixed solution of hydrofluoric acid and ammonium fluoride.
  • the method further includes the following steps:
  • the step (b) before the step (b.2), further includes a step of: photoresist transparent conductive layer structure, so that in the step (b.2), Etching the indium tin oxide layer according to the structure of the transparent conductive layer to form the transparent conductive layer and the perforations of the transparent conductive layer by the indium tin oxide layer, and in the step (b.2 ), The step (b) further includes a step of removing the photoresist.
  • the step (b) before the step of photoresist-transparent conductive layer, the step (b) further includes a step of alloying the indium tin oxide layer.
  • an etching solution used for wet etching the indium tin oxide layer is a mixed solution of hydrochloric acid and ferric chloride.
  • the current blocking layer is further laminated on a surface of the N-type semiconductor layer that is exposed on the semiconductor exposed portion, so that in the step (c ), The N-type electrode covers the current blocking layer laminated on the N-type semiconductor layer.
  • the present invention further provides a semiconductor chip of a light emitting diode, which includes:
  • An epitaxial unit wherein the epitaxial unit includes a substrate, an N-type semiconductor layer, an active region, and a P-type semiconductor layer, which are sequentially stacked, and has an extension from the P-type semiconductor layer through the active region to At least one semiconductor exposed portion of the N-type semiconductor layer;
  • At least one current blocking layer wherein the current blocking layer is stacked on the P-type semiconductor layer;
  • a transparent conductive layer wherein the transparent conductive layer has at least one row of perforations, wherein the transparent conductive layer is laminated on the P-type semiconductor layer so as to cover the current blocking layer, and the perforations of the transparent conductive layer Corresponding to the current blocking layer, and at least one of the perforations in a row of the perforations is different from an adjacent perforation;
  • the electrode group includes an N-type electrode laminated on the N-type semiconductor layer and a P-type electrode laminated on the transparent conductive layer
  • the N-type electrode includes a semiconductor chip formed on the semiconductor chip
  • the P-type electrode includes a P-type electrode pad formed at a first end portion of the semiconductor chip and extending from the P-type electrode pad to the At least one P-type electrode extension strip extending in the direction of the second end portion of the semiconductor chip, wherein the P-type electrode extension strip has a row of P-type interdigital fingers, wherein the P-type interdigital fingers are formed on and held by the transparent conductive The perforation of the layer.
  • the N-type electrode further includes at least one N-type electrode extension strip, wherein the N-type electrode extension strip is directed from the N-type electrode pad to a second end portion of the semiconductor chip. extend.
  • a size of each of the through holes in a row of the through holes gradually increases from a first end portion to the second end portion of the semiconductor chip, so that a row of the P-shaped forks
  • the size of each of the P-shaped interdigital fingers gradually increases in the opposite direction from the first end portion to the second end portion of the semiconductor chip.
  • the size of each of the through holes in a row of the through holes gradually decreases from the first end portion to the second end portion of the semiconductor chip, so that a row of the P-shaped forks
  • the size of each of the P-shaped interdigital fingers gradually decreases in the opposite direction from the first end portion to the second end portion of the semiconductor chip.
  • a distance between two adjacent through-holes in one row of the through-holes gradually increases from a first end portion of the semiconductor chip to the second end portion, so that one row of A pitch between two adjacent P-type interdigital fingers of the P-type interdigital finger gradually increases from a first end portion of the semiconductor chip toward the second end portion.
  • a pitch between two adjacent through-holes in one row of the through-holes gradually decreases from a first end portion of the semiconductor chip to the second end portion, so that one row of A distance between two adjacent P-type interdigital fingers among the P-type interdigital fingers gradually decreases from a first end portion of the semiconductor chip toward the second end portion.
  • the N-type electrode includes one of the N-type electrode extension strips, and the N-type electrode extension strips extend along a length direction of the semiconductor chip in a middle portion of the semiconductor chip, wherein
  • the P-type electrode includes two of the P-type electrode extension strips, and the two P-type electrode extension strips extend along a length direction of the semiconductor chip at an edge of the semiconductor chip in a mutually symmetrical manner, wherein An N-type electrode extension bar is held between the two P-type electrode extension bars.
  • the N-type electrode includes two of the N-type electrode extension strips, and the exposed portions of the two N-type electrode extension strips are along the length of the semiconductor chip in the middle of the semiconductor chip.
  • the P-type electrode includes three of the P-type electrode extension strips, which are a first P-type electrode extension strip, a second P-type electrode extension strip, and a third P-type electrode extension strip, respectively
  • the first P-type electrode extension strip and the third P-type electrode extension strip extend along the length direction of the semiconductor chip at edges of the semiconductor chip in a mutually symmetrical manner
  • the second P-type electrode extension strip A middle portion of the semiconductor chip extends along a length direction of the semiconductor chip, and one of the N-type electrode extension strips is held between the first P-type electrode extension strips and the second P-type electrode extension strips. Meanwhile, another N-type electrode extension bar is held between the second P-type electrode extension bar and the third P-type electrode extension bar.
  • the N-type electrode includes two of the N-type electrode extension strips, and the two N-type electrode extension strips are symmetrical to each other along an edge of the semiconductor chip along the semiconductor.
  • the chip extends in the length direction, wherein the P-type electrode includes one of the P-type electrode extension strips, and the P-type electrode extension strips extend in the middle of the semiconductor chip along the length direction of the P-type electrodes, where The P-type electrode extension bar is held between two of the N-type electrode extension bars.
  • the N-type electrode includes three of the N-type electrode extension strips, which are a first N-type electrode extension strip, a second N-type electrode extension strip, and a third N-type electrode.
  • An extension strip, the first N-type electrode extension strip and the third N-type electrode extension strip extend symmetrically to each other at the edge of the semiconductor chip along the length direction of the semiconductor chip, and the second N
  • the P-type electrode extension strip extends in the middle of the semiconductor chip along the length direction of the semiconductor chip, wherein the P-type electrode includes two of the P-type electrode extension strips, and the two P-type electrode extension strips are connected to each other.
  • a symmetrical manner extends in the middle of the semiconductor chip along the length of the semiconductor chip.
  • One of the P-type electrode extension strips is held between the first N-type electrode extension strip and the second N-type electrode. Between the extension bars, another P-type electrode extension bar is held between the second N-type electrode extension bar and the third N-type electrode extension bar.
  • At least one of the current blocking layers is laminated on a surface of the N-type semiconductor layer of the epitaxial unit that is exposed on the semiconductor bare portion, wherein the N-type electrode is overlaid on The current blocking layer of the N-type semiconductor layer.
  • the current blocking layer laminated on the N-type semiconductor layer is in a strip shape, and extends along a length direction of the semiconductor chip.
  • the number of the current blocking layers stacked on the N-type semiconductor layer is plural, and the current blocking layers extend in a stripe arrangement along the length direction of the semiconductor chip. And there is a gap between two adjacent current blocking layers.
  • the semiconductor chip further includes a passivation layer, wherein the passivation layer has a first through hole and a second through hole, and wherein the passivation layer covers the N
  • the P-type electrode and the P-type electrode are stacked on the P-type semiconductor layer and the transparent conductive layer, and the first through hole of the passivation layer corresponds to the N-type electrode, the passivation The second through hole of the layer corresponds to the P-type electrode.
  • FIG. 1A is a schematic cross-sectional view of one of the manufacturing steps of a semiconductor chip according to the first preferred embodiment of the present invention.
  • FIG. 1B is a schematic top view of one of the manufacturing steps of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional view of the second manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 2B is a schematic plan view of the second manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 3A is a schematic sectional view of the third manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 3B is a schematic top view of the third manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 4A is a schematic sectional view of the fourth manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 4B is a schematic top view of the fourth manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • 5A is a schematic cross-sectional view of the fifth manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention, which illustrates a cross-sectional state of the semiconductor chip.
  • FIG. 5B is a schematic top view of the fifth manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention, which illustrates a top view state of the semiconductor chip.
  • FIG. 6 is a schematic diagram of manufacturing steps of a modified embodiment of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of manufacturing steps of another modified embodiment of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 8 is a schematic diagram of manufacturing steps according to still another modified embodiment of the semiconductor chip according to the foregoing preferred embodiment of the present invention.
  • FIG. 9 is a schematic diagram of manufacturing steps of still another modified embodiment of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 10A is a schematic top view of a manufacturing step of a semiconductor chip according to a second preferred embodiment of the present invention.
  • FIG. 10B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • 11A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a third preferred embodiment of the present invention.
  • FIG. 11B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 12A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a fourth preferred embodiment of the present invention.
  • FIG. 12B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 13A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a fifth preferred embodiment of the present invention.
  • FIG. 13B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • 14A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a sixth preferred embodiment of the present invention.
  • FIG. 14B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • 15A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a seventh preferred embodiment of the present invention.
  • FIG. 15B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above-mentioned preferred embodiment of the present invention.
  • FIG. 16A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to an eighth preferred embodiment of the present invention.
  • FIG. 16B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 17A is a schematic cross-sectional view of a manufacturing step of a semiconductor chip according to a ninth preferred embodiment of the present invention.
  • FIG. 17B is a schematic cross-sectional view of a manufacturing step of the semiconductor chip according to the above preferred embodiment of the present invention.
  • FIG. 18 is a schematic diagram of the manufacturing steps of the semiconductor chip according to the tenth preferred embodiment of the present invention.
  • FIG. 19 is a schematic diagram of manufacturing steps of the semiconductor chip according to the eleventh preferred embodiment of the present invention.
  • FIG. 20 is a schematic diagram of manufacturing steps of the semiconductor chip according to a twelfth preferred embodiment of the present invention.
  • FIG. 21 is a schematic diagram of manufacturing steps of the semiconductor chip according to a thirteenth preferred embodiment of the present invention.
  • a semiconductor chip of a light emitting diode according to a preferred embodiment of the present invention is disclosed and explained in the following description, wherein the semiconductor chip includes a The epitaxial unit 10, at least one current blocking layer 20, a transparent conductive layer 30, and an electrode group 40.
  • the epitaxial unit 10 includes a substrate 11, an N-type semiconductor layer 12, an active region 13, and a P-type semiconductor layer 14, wherein the N-type semiconductor layer 12 is grown from the substrate 11.
  • the substrate 11 To stack the N-type semiconductor layer 12 on the substrate 11, wherein the active region 13 is grown from the N-type semiconductor layer 12, so that the active region 13 is stacked on the N-type semiconductor A layer 12, wherein the P-type semiconductor layer 14 is grown from the active region 13 so that the P-type semiconductor layer 14 is stacked on the active region 13.
  • the type of the substrate 11 of the epitaxial unit 10 is not limited in the semiconductor chip of the present invention.
  • the substrate 11 may be, but is not limited to, a sapphire substrate and a silicon substrate. Wait.
  • the types of the N-type semiconductor layer 12 and the P-type semiconductor layer 14 may not be limited in the semiconductor chip of the present invention.
  • the N-type semiconductor layer 12 may be an N-type gallium nitride layer.
  • the P-type semiconductor layer 14 may be a P-type gallium nitride layer.
  • the epitaxial unit 10 has at least one semiconductor exposed portion 15, wherein the semiconductor exposed portion 15 extends from the P-type semiconductor layer 14 through the active region 13 to the N-type semiconductor.
  • a metal-organic chemical vapor deposition device can be used to sequentially grow the N-type semiconductor layer 12 from the substrate 11 and the The source region 13 and the P-type semiconductor layer 14 obtain the substrate 11, the N-type semiconductor layer 12, the active region 13, and the P-type semiconductor layer 14 sequentially stacked.
  • a Mesa pattern is made using a photoresist.
  • ICP inductively coupled plasma
  • the region 13 extends to the semiconductor exposed portion 15 of the N-type semiconductor layer 12 and exposes the N-type semiconductor layer 12 to the semiconductor exposed portion 15.
  • the N-type semiconductor layer 12 may be further etched by using an inductive coupling plasma to form the P-type semiconductor layer 14 through the active region. 13 extends to the semiconductor exposed portion 15 of the N-type semiconductor layer 12 and exposes the N-type semiconductor layer 12 to the semiconductor exposed portion 15. That is, in this preferred example of the semiconductor chip of the present invention, the thickness dimension of the N-type semiconductor layer 12 corresponding to the semiconductor exposed portion 15 is smaller than that of other portions of the N-type semiconductor layer 12. Thickness dimensions.
  • a depth dimension of the semiconductor exposed portion 15 of the epitaxial unit 10 ranges from 0.7 ⁇ m to 3 ⁇ m (including 0.7 ⁇ m and 3 ⁇ m).
  • the gases used when dry-etching the P-type semiconductor layer 14, the active region 13, and the N-type semiconductor layer 12 using inductively coupled plasma are Cl2 (chlorine gas), BCl3 (boron trichloride) And Ar (argon). Removing the photoresist after dry-etching the P-type semiconductor layer 14, the active region 13, and the N-type semiconductor layer 12 using an inductively coupled plasma to form the semiconductor exposed portion 15, To obtain the epitaxial unit 10.
  • the manner of removing the photoresist is not limited in the semiconductor chip of the present invention.
  • the photoresist may be removed by, but not limited to, a de-gluing solution.
  • the semiconductor chip has a first end portion 101 and a second end portion 102 corresponding to the first end portion 101.
  • the semiconductor exposed portion 15 has an N-type electrode pad exposed portion 151 and two N-type electrode extension strip exposed portions 152.
  • the N-type electrode of the semiconductor exposed portion 15 is soldered.
  • a disk exposed portion 151 is formed at the second end portion 102 of the semiconductor chip, and the two N-type electrode extension strip exposed portions 152 of the semiconductor exposed portion 15 are symmetrical to each other in the middle of the semiconductor chip. Extending from the N-type electrode pad exposed portion 151 to the first end portion 101 of the semiconductor chip along the length direction of the semiconductor chip.
  • the two N-type electrode extension strip exposed portions 152 of the semiconductor exposed portion 15 communicate with the N-type electrode pad exposed portions 151, respectively.
  • the N-type electrode pad exposed portion 151 and the two N-type electrode extension strip exposed portions 152 of the semiconductor exposed portion 15 are formed by the same etching process, and the semiconductor exposed portion 15 Both the N-type electrode pad exposed portion 151 and the two N-type electrode extension strip exposed portions 152 extend from the P-type semiconductor layer 14 through the active region 13 to the N-type semiconductor layer 12, A part of the surface of the N-type semiconductor layer 12 is exposed on the N-type electrode pad exposed portion 151 and the two N-type electrode extension strip exposed portions 152 on the semiconductor exposed portion 15.
  • the number of the current blocking layers 20 is three, and all three of the current blocking layers 20 are in a strip shape, wherein the three current blocking layers 20 are defined as a first current blocking layer in sequence. 20a, a second current blocking layer 20b, and a third current blocking layer 20c, wherein the first current blocking layer 20a, the second current blocking layer 20b, and the third current blocking layer 20c are respectively along the The length direction of the semiconductor chip extends from the first end portion 101 to the second end portion 102 of the semiconductor chip.
  • One of the N-type electrode extension strip exposed portions 152 of the semiconductor exposed portion 15 is held between the first current blocking layer 20a and the second current blocking layer 20b, and the other of the semiconductor exposed portions 15
  • the N-type electrode extension strip exposed portion 152 is held between the second current blocking layer 20b and the third current blocking layer 20c.
  • the first current blocking layer 20a and the third current blocking layer 20c are symmetrical to each other at the edge of the semiconductor chip along the length direction of the semiconductor chip from the first portion of the semiconductor chip.
  • One end portion 101 extends in the direction of the second end portion 102, and the second current blocking layer 20b is held between the first current blocking layer 20a and the third current blocking layer 20c.
  • a middle portion of the semiconductor chip extends along the length direction of the semiconductor chip from the first end portion 101 to the second end portion 102 of the semiconductor chip.
  • the manner in which the current blocking layer 20 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10 is not limited in the semiconductor chip of the present invention.
  • a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD) is used to deposit a layer of SiO2 (silicon dioxide) on the epitaxial unit.
  • the P-type semiconductor layer 14 of 10 has a thickness of SiO2 in the range of 500 Angstroms to 10,000 Angstroms (including 500 Angstroms and 10,000 Angstroms).
  • the reaction gases used are SiH4 (silane), N2O (nitrogen monoxide), and N2 (nitrogen). ).
  • the structure of the current blocking layer 20 is photolithographically using a positive resist, wherein the thickness of the photoresist ranges from 0.5 ⁇ m to 5 ⁇ m (including 0.5 ⁇ m and 5 ⁇ m).
  • SiO2 is etched using a wet etching method to form a pattern of the current blocking layer 20, wherein the etching solution is a mixed solution in hydrofluoric acid and ammonium fluoride.
  • the photoresist is removed after the etching is completed to form the current blocking layer 20 of the P-type semiconductor layer 14 laminated on the epitaxial unit 10.
  • the current blocking layer 20 may be stacked on the N-type semiconductor layer 12 of the epitaxial unit 10.
  • the current blocking layer 20 may be formed on the N-type electrode extension strip exposed portion 152 of the semiconductor exposed portion 15 so that the current blocking layer 20 is stacked on the epitaxial unit 10.
  • the number of the current blocking layers 20 stacked on the N-type semiconductor layer 12 of the epitaxial unit 10 is As an example, there are gaps between a plurality of and adjacent current blocking layers 20 to expose and explain the content and characteristics of the semiconductor chip of the present invention, but those skilled in the art should understand that the FIG.
  • the semiconductor chip is only an example, and it should not be considered as a limitation on the content and scope of the semiconductor chip of the present invention, that is, in other possible examples of the semiconductor chip, stacked on the N-type semiconductor layer
  • the number of the current blocking layer 20 may be one, and the current blocking layer 20 is in a strip shape, so that the extending direction and length of the current blocking layer 20 are the same as those of the semiconductor bare portion 15.
  • the extension direction and the extension length of the N-type electrode extension strip exposed portion 152 are the same.
  • an indium tin oxide layer (ITO) is deposited on the P-type semiconductor layer 14 of the epitaxial unit 10, wherein the indium tin oxide layer is electrically connected to Mentioned P-type semiconductor layer 14.
  • the indium tin oxide layer is alloyed.
  • the manner of alloying the indium tin oxide layer is not limited in the semiconductor chip of the present invention.
  • a rapid annealing furnace or an alloy furnace tube may be used for alloying the indium tin oxide.
  • the wet etching method is used to etch the indium tin oxide layer after the photoresist is completed, so as to obtain the obtained after the etching is completed and the photoresist is removed.
  • the etching solution used when the indium tin oxide layer is etched by a wet etching method is a mixed solution of hydrochloric acid and ferric chloride.
  • the transparent conductive layer 30 has three rows of the perforations 31, wherein one row of the perforations 31 of the transparent conductive layer 30 respectively corresponds to different positions of the first current blocking layer 20a, and the transparent conductive layer 30
  • the perforations 31 in another column of 30 correspond to different positions of the second current blocking layer 20b
  • the perforations 31 in another column of the transparent conductive layer 30 correspond to different positions of the third current blocking layer 20c.
  • a pattern of an N-type electrode 41 and a pattern of a P-type electrode 42 of the electrode group 40 are etched on the surface of the transparent conductive layer 30 by using a negative photoresist.
  • a metal electrode layer is deposited by evaporation or sputtering.
  • the excess metal layer and the residual photoresist are removed by a peeling method to form the N-type electrode 41 and the P-type electrode 42 of the electrode group 40.
  • the N-type electrode 41 includes an N-type electrode pad 411 and two N-type electrode extension strips 412 electrically connected to the N-type electrode pad 411, wherein the N of the N-type electrode 41 A type electrode pad 411 is formed on the N-type electrode pad exposed portion 151 of the semiconductor exposed portion 15 of the epitaxial unit 10 so that the N-type electrode pad 411 is stacked on and electrically connected to the N-type electrode pad 411.
  • the N-type electrode extension strip 412 of the N-type electrode 41 is formed on the N-type electrode extension strip of the semiconductor exposed portion 15 of the epitaxial unit 10.
  • the exposed portion 152 is such that the N-type electrode extension strip 412 is stacked on and electrically connected to the N-type semiconductor layer 12 of the epitaxial unit 10. It can be understood that the N-type electrode extension strip 412 fills a gap between the adjacent current blocking layers 20 stacked on the N-type semiconductor layer 12.
  • the two N-type electrode extension strips 412 are symmetrical to each other in the middle of the semiconductor chip along the length direction of the semiconductor chip from the N-type electrode pad 411 to the semiconductor chip.
  • the first end portion 101 extends in the direction.
  • the P-type electrode 42 includes a P-type electrode pad 421 and three P-type electrode extension bars 422 electrically connected to the P-type electrode pad 421, and one of the P-type electrode extension bars 422 is defined Is a first P-type electrode extension strip 422a, another P-type electrode extension strip 422 is defined as a second P-type electrode extension strip 422b, and another P-type electrode extension strip 423 is defined as a third P-type electrode extension bar 422c.
  • the P-type electrode pads 421 and each of the P-type electrode extension strips 422 of the P-type electrode 42 are laminated on the transparent conductive layer 30, wherein the P-type electrode of the P-type electrode 42 is welded.
  • a disc 421 is formed at the first end portion 101 of the semiconductor chip, and each of the P-type electrode extension strips 422 of the P-type electrode 42 extends along the length direction of the semiconductor chip from the P-type electrode, respectively.
  • the pad 421 extends in the direction of the second end portion 102.
  • the first P-type electrode extension strip 422a of the P-type electrode 42 and the first current blocking layer 20a overlap each other, so that the first P-type electrode extension strip 422a A P-shaped interdigital finger 4220 is formed and held in each of the perforations 31 of the transparent conductive layer 30; the second P-type electrode extension strip 422b of the P-type electrode 42 and the second current block The layers 20b are overlapped with each other, so that the P-shaped interdigits 4220 of the second P-type electrode extension strip 422b are formed and held in each of the perforations 31 of the transparent conductive layer 30; the P-type The third P-type electrode extension strip 422c of the electrode 42 and the third current blocking layer 20c overlap each other, so that the P-type interdigital fingers 4220 of the first P-type electrode extension strip 422a are formed and held.
  • the first P-type electrode extension strips 422a and the third P-type electrode extension strips 422c of the P-type electrodes 42 are respectively symmetrical along the semiconductor chip at the edges of the semiconductor chip in a mutually symmetrical manner.
  • the length direction of the chip extends from the P-type electrode pad 421 to the second end portion 102 of the semiconductor chip, and the second P-type electrode extension strip 422b of the P-type electrode 42 is in the semiconductor.
  • the middle portion of the chip extends from the P-type electrode pad 421 to the second end portion 102 of the semiconductor chip along the length direction of the semiconductor chip.
  • One of the N-type electrode extension strips 412 of the N-type electrode 41 is held between the first P-type electrode extension strip 422a and the second P-type electrode extension strip 422b of the P-type electrode 42, The other N-type electrode extension strip 412 is held between the second P-type electrode extension strip 422b and the third P-type electrode extension strip 422c.
  • the semiconductor chip further includes a passivation layer 50, wherein the passivation layer 50 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent layer
  • the first through-holes 41 and correspondingly, the second through-holes 52 of the passivation layer 50 correspond to the P-type electrode pads 421 of the P-type electrodes 42 of the electrode group 40 to The P-type electrode pad 421 is exposed in the second through hole 42.
  • a layer of SiO 2 (silicon dioxide) is deposited on the epitaxial unit 10 by using a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of SiO2 ranges from 500 Angstroms to 10,000 Angstroms (including 500 Angstroms and 10,000 Angstroms).
  • the reaction gases used are SiH4 (silane), N2O (nitrogen monoxide), and N2 (nitrogen).
  • the structure of the passivation layer 30 is etched using positive resist.
  • SiO2 is etched by using a wet etching method to form a pattern of the passivation layer 30.
  • the etching solution is a mixed solution of hydrofluoric acid and ammonium fluoride.
  • the photoresist is removed after the etching is completed to form the passivation layer 50 laminated on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent
  • the conductive layer 30 and the N-type electrode 41 and the P-type electrode 42 of the electrode group 40, and the first through hole 51 of the passivation layer 50 corresponds to the N of the electrode group 40
  • the N-type electrode pad 411 of the type electrode 41 and the second through hole 52 correspond to the P-type electrode pad 421 of the P-type electrode 42 of the electrode group 40.
  • External power can be supplied to the N-type electrode 41 and the P-type electrode 42 of the electrode group 40 through the first through-hole 51 and the second through-hole 52 of the passivation layer 50, respectively.
  • a current can be injected into the N-type semiconductor layer 12 of the epitaxial unit 10 through the N-type electrode pad 411 and the N-type electrode extension strip 412 of the N-type electrode 41, where the N-type electrode expands
  • the current blocking layer 20 is held between the strip 412 and the N-type semiconductor layer 12, wherein the current blocking layer 20 can prevent current from being concentrated on the lower portion of the N-type electrode extension strip 412, so that the current can be directed to The periphery is uniformly implanted into the N-type semiconductor layer 12.
  • a current can be injected into the transparent conductive layer 30 through the P-type electrode pads 421 of the P-type electrode 42 and each of the P-type electrode extension bars 422, because each of the P-type electrode extension bars 422 is stacked on the transparent conductive layer 30 and the P-shaped interdigital fingers 4220 of each of the P-type electrode extension strips 422 are respectively held in the perforations 31 of the transparent conductive layer 30, so that current can flow freely.
  • the surface and the inside of the transparent conductive layer 30 are uniformly injected into the transparent conductive layer 30 through the P-type electrode extension strips 422, and because a certain distance is maintained between the transparent conductive layer 30 and the P-type semiconductor layer 14
  • the current blocking layer 20 can prevent current from being concentrated on the lower portion of the P-type electrode extension strip 422, so that the current can be uniformly injected into the P-type semiconductor layer 14 around the periphery.
  • the current that is uniformly injected into the N-type semiconductor layer 12 and the current that is uniformly injected into the P-type semiconductor layer 14 can recombine in the active region 13 to generate light, and in this way, the semiconductor chip's Brightness can be effectively increased.
  • FIG. 6 shows a modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIGS. 1A to 5B is this preferred example of the semiconductor chip shown in FIG. 6.
  • the N-type electrode pad exposed portion 151 and the N-type electrode extension bar exposed portion 152 are formed, wherein the N-type electrode pad exposed portion 151 is formed on the semiconductor chip.
  • the second end portion 102, the N-type electrode extension strip exposed portion 152 in the middle of the semiconductor chip along the length direction of the semiconductor chip from the N-type electrode pad exposed portion 151 to the semiconductor
  • the first end portion 101 of the chip extends in a direction.
  • the N-type electrode 41 includes an N-type layer that is stacked on the N-type semiconductor layer 12 and held by the N-type electrode pad exposed portion 151.
  • the number of the current blocking layers 20 is two, and two of the current blocking layers 20 are symmetrical to each other at the edges of the semiconductor chip along the length direction of the semiconductor chip.
  • the first end portion 101 of the semiconductor chip extends in the direction of the second end portion 102.
  • the transparent conductive layer 30 is laminated on the P-type semiconductor layer 14 so as to cover the current blocking layer 20, and the through holes 31 of the transparent conductive layer 30 respectively correspond to the current blocking layer. 20.
  • the transparent conductive layer 30 has two rows of the perforations 31, wherein each row of the perforations 31 corresponds to a different position of each of the current blocking layers 20.
  • the P-type electrode 42 includes one P-type electrode pad 421 and two P-type electrode extension strips 422 laminated on the transparent conductive layer 30.
  • the P-type electrode pads 421 are formed at the first end portion 101 of the semiconductor chip, and each of the P-type electrode extension strips 422 is formed along the edges of the semiconductor chip in a symmetrical manner with each other.
  • the length direction of the semiconductor chip extends from the P-type electrode pad 421 to the second end portion 102 of the semiconductor chip, and the P-type fork of each of the P-type electrode extension strips 422
  • a finger 4220 is formed and held in each of the through holes 31 of the transparent conductive layer 30, respectively. Referring to FIG. 6, the N-type electrode extension strip 412 of the N-type electrode 41 is held between two P-type electrode extension strips 422 of the P-type electrode 42.
  • the passivation layer 50 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent conductive layer 30 and the electrode group 40.
  • the first through-hole 51 of the passivation layer 50 and the second through-hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • the second through hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • FIG. 7 shows another modified embodiment of the semiconductor chip.
  • the semiconductor exposed portion 15 has one of the N-type electrode pad exposed portions 151 and three of the N-type electrode extension strip exposed portions 152, wherein the N-type electrode pad exposed portions 151 are formed in the In the second end portion 102 of the semiconductor chip, three of the N-type electrode extension bar exposed portions 152 are defined as a first extension bar exposed portion 152a, a second extension bar exposed portion 152b, and a third extension, respectively.
  • Strip exposed portion 152c wherein the first extension strip exposed portion 152a and the third extension strip exposed portion 152c are symmetrical to each other on the edge of the semiconductor chip along the length direction of the semiconductor chip from the N Type electrode pad exposed portion 151 extends in the direction of the first end portion 101 of the semiconductor chip, and the second extension strip exposed portion 152b is located in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • N-type electrode welding Exposed portion 151 extending direction of the semiconductor chip 101 of the first end portion.
  • the N-type electrode 41 includes one N-type electrode pad 411 and three N-type electrode extension strips 412, wherein the N-type electrode pad 411 is stacked on the N-type semiconductor layer 12 and held on the N-type electrode pad exposed portion 151, wherein three of the N-type electrode extension strips 412 are defined as a first N-type electrode extension strip 412a, a A second N-type electrode extension strip 412b and a third N-type electrode extension strip 412c, wherein the first N-type electrode extension strip 412a, the second N-type electrode extension strip 412b, and the third N-type electrode extension A strip 412c is stacked on the N-type semiconductor layer 12 and held on the first extension strip exposed portion 152a, the second extension strip exposed portion 152b, and the third extension strip exposed portion 152c, respectively, so that all the The first N-type electrode extension strip 412a and the third N-type electrode extension strip 412c are symmetrical to each other at the edge
  • the number of the current blocking layers 20 is two, and two of the current blocking layers 20 are symmetrical to each other in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the first end portion 101 of the semiconductor chip extends in the direction of the second end portion 102.
  • the transparent conductive layer 30 is laminated on the P-type semiconductor layer 14 so as to cover the current blocking layer 20, and the through holes 31 of the transparent conductive layer 30 respectively correspond to the current blocking layer. 20.
  • the transparent conductive layer 30 has two rows of the perforations 31, wherein each row of the perforations 31 corresponds to each of the current blocking layers 20.
  • the P-type electrode 42 includes one P-type electrode pad 421 and two P-type electrode extension strips 422 laminated on the transparent conductive layer 30.
  • each of the P-type electrode extension strips 422 is respectively symmetrical with each other in the middle of the semiconductor chip along the length direction of the semiconductor chip from the P-type electrode pad 421 to the semiconductor chip.
  • the second end portion 102 extends in a direction, and the P-shaped interdigital fingers 4220 of each of the P-type electrode extension strips 422 are formed and held in each of the through holes 31 of the transparent conductive layer 30, respectively.
  • one of the P-type electrode extension bars 422 of the P-type electrode 42 is held between the first N-type electrode extension bar 412 a and the second N-type electrode extension bar 412 b, and the other The P-type electrode extension strip 422 is held between the second N-type electrode extension strip 412b and the third N-type electrode extension strip 412c.
  • the passivation layer 50 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent conductive layer 30 and the electrode group 40.
  • the first through-hole 51 of the passivation layer 50 and the second through-hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • the second through hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • FIG. 8 shows another modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIG. 7 is that in this preferred example of the semiconductor chip shown in FIG. 8,
  • the semiconductor exposed portion 15 includes one N-type electrode pad exposed portion 151 and two N-type electrode extension strip exposed portions 152, wherein the N-type electrode pad exposed portion 151 is formed on the semiconductor chip.
  • the second end portion 102 and the two N-type electrode extension strip exposed portions 152 are exposed from the N-type electrode pads along the length of the semiconductor chip along the length of the semiconductor chip in an symmetrical manner to each other.
  • the portion 151 extends in the direction of the first end portion 101 of the semiconductor chip.
  • the N-type electrode 41 includes one N-type electrode pad 411 and two N-type electrode extension strips 412, wherein the N-type electrode pad 411 is stacked on the N-type semiconductor layer 12 and held on the N-type electrode pad exposed portion 151, wherein each of the N-type electrode extension strips 412 is stacked on the N-type semiconductor layer 12 and held on the Each of the N-type electrode extension strips 152 is exposed, so that each of the N-type electrode extension strips 412 is symmetrical to each other at the edge of the semiconductor chip along the length direction of the semiconductor chip from the N
  • the type electrode pad 411 extends in the direction of the first end portion 101 of the semiconductor chip.
  • the number of the current blocking layers 20 is one, wherein the current blocking layer 20 is located in the middle of the semiconductor chip from the first end of the semiconductor chip along the length direction of the semiconductor chip.
  • the portion 101 extends in the direction of the second end portion 102.
  • the transparent conductive layer 30 is laminated on the P-type semiconductor layer 14 in a manner covering the current blocking layer 20, and the perforations 31 of the transparent conductive layer 30 correspond to the current blocking layer 20. .
  • the P-type electrode 42 includes the P-type electrode pad 421 and the P-type electrode extension strip 422 laminated on the transparent conductive layer 30, wherein, the P-type electrode pad 421 is formed at the first end portion 101 of the semiconductor chip, and the P-type electrode extension strip 421 is located in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the P-type electrode pad 421 extends toward the second end portion 102 of the semiconductor chip, and the P-type interdigital 4220 of the P-type electrode extension strip 422 is formed and held in the transparent conductive The perforations 31 of the layer 30. Referring to FIG. 8, the P-type electrode extension strip 422 of the P-type electrode 42 is held between two N-type electrode extension strips 412 of the N-type electrode 41.
  • the passivation layer 50 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent conductive layer 30 and the electrode group 40.
  • the first through-hole 51 of the passivation layer 50 and the second through-hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • the second through hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • FIG. 9 shows another modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIG. 8 is that, in this preferred example of the semiconductor chip shown in FIG. 9,
  • the semiconductor exposed portion 15 has only one of the N-type electrode pad exposed portions 151 formed at the second end portion 102 of the semiconductor chip.
  • the N-type electrode 41 includes only one N-type electrode pad 411, wherein the N-type electrode pad 411 is stacked on the N-type semiconductor layer 12 And held in the N-type electrode pad exposed portion 151.
  • the number of the current blocking layers 20 is one, wherein the current blocking layer 20 is located in the middle of the semiconductor chip along the length direction of the semiconductor chip from the first end of the semiconductor chip.
  • the portion 101 extends in the direction of the second end portion 102.
  • the transparent conductive layer 30 is laminated on the P-type semiconductor layer 14 in a manner to cover the current blocking layer 20, and the transparent conductive layer 30
  • the perforation 31 corresponds to the current blocking layer 20.
  • the P-type electrode 42 includes the P-type electrode pad 421 and the P-type electrode extension strip 422 laminated on the transparent conductive layer 30, wherein, the P-type electrode pad 421 is formed at the first end portion 101 of the semiconductor chip, and the P-type electrode extension strip 421 is located in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the P-type electrode pad 421 extends toward the second end portion 102 of the semiconductor chip, and the P-type interdigital 4220 of the P-type electrode extension strip 422 is formed and held in the transparent conductive The perforations 31 of the layer 30.
  • the passivation layer 50 is stacked on the P-type semiconductor layer 14 of the epitaxial unit 10, and the passivation layer 50 covers the transparent conductive layer 30 and the electrode group 40.
  • the first through-hole 51 of the passivation layer 50 and the second through-hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • the second through hole 52 of the passivation layer 50 correspond to the P-type electrode 42 so that the P-type electrode 42 is exposed to the P-type electrode 42.
  • the present invention further provides a method for manufacturing the semiconductor chip, wherein the method includes the following steps:
  • the manufacturing method includes steps:
  • the substrate 11, the N-type semiconductor layer 12, the active region 13, the second semiconductor layer 14, The thicknesses of the current blocking layer 20, the transparent conductive layer 30, the N-type electrode 41, and the P-type electrode 42 are merely examples, and do not represent the substrate 11, the N-type semiconductor layer 12, The true thicknesses of the active region 13, the second semiconductor layer 14, the current blocking layer 20, the transparent conductive layer 30, the N-type electrode 41 and the P-type electrode 42.
  • the true ratio between 41 and the P-type electrode 42 is also not as shown in the drawings.
  • the ratios of the sizes of the N-type electrode 41 and the P-type electrode 42 of the electrode group 40 to the sizes of other layers of the semiconductor chip are not limited to those shown in the drawings.
  • a semiconductor chip of a light emitting diode according to another preferred embodiment of the present invention is disclosed and explained in the following description, wherein the semiconductor chip includes An epitaxial unit 10 ', at least one current blocking layer 20', a transparent conductive layer 30 ', and an electrode group 40'.
  • the epitaxial unit 10 ′ includes a substrate 11 ′, an N-type semiconductor layer 12 ′, an active region 13 ′, and a P-type semiconductor layer 14 ′, wherein the N-type semiconductor layer 12 ′ is The substrate 11 'is grown so that the N-type semiconductor layer 12' is stacked on the substrate 11 ', wherein the active region 13' is grown from the N-type semiconductor layer 12 'so that the An active region 13 'is stacked on the N-type semiconductor layer 12', wherein the P-type semiconductor layer 14 'is grown from the active region 13' so that the P-type semiconductor layer 14 'is stacked on the organic layer Source area 13 '.
  • the type of the substrate 11 ′ of the epitaxial unit 10 ′ is not limited in the semiconductor chip of the present invention.
  • the substrate 11 ′ may be, but is not limited to, a sapphire substrate, Silicon substrate, etc.
  • the types of the N-type semiconductor layer 12 ′ and the P-type semiconductor layer 14 ′ may not be limited in the semiconductor chip of the present invention.
  • the N-type semiconductor layer 12 ′ may be N-type nitrogen.
  • a gallium layer, correspondingly, the P-type semiconductor layer 14 ′ may be a P-type gallium nitride layer.
  • the epitaxial unit 10 has at least one semiconductor exposed portion 15', wherein the semiconductor exposed portion 15 'extends from the P-type semiconductor layer 14' through the active region 13 'to
  • the N-type semiconductor layer 12 ' is exposed to expose the N-type semiconductor layer 12'. That is, a part of the surface of the N-type semiconductor layer 12 'is exposed to the semiconductor exposed portion 15'.
  • a metal-organic chemical vapor deposition device can be used to sequentially grow the N-type semiconductor layer 12 ′ from the substrate 11 ′,
  • the active region 13 'and the P-type semiconductor layer 14' are obtained by sequentially stacking the substrate 11 ', the N-type semiconductor layer 12', the active region 13 ', and the P-type semiconductor layer. 14 '.
  • a Mesa pattern is made using a photoresist.
  • ICP inductively coupled plasma
  • the active region 13 ' extends to the semiconductor exposed portion 15' of the N-type semiconductor layer 12 ', and the N-type semiconductor layer 12' is exposed to the semiconductor exposed portion 15 '.
  • the N-type semiconductor layer 12 ' can be further etched using an inductive coupling plasma to form a P-type semiconductor layer 14'
  • a source region 13 ' extends to the semiconductor exposed portion 15' of the N-type semiconductor layer 12 ', and exposes the N-type semiconductor layer 12' to the semiconductor exposed portion 15 '. That is, in this preferred example of the semiconductor chip of the present invention, the thickness dimension of the N-type semiconductor layer 12 'corresponding to the semiconductor exposed portion 15' is smaller than that of the N-type semiconductor layer 12 '. The thickness of other parts.
  • the semiconductor exposed portion 15 'of the epitaxial unit 10' has a depth dimension ranging from 0.7 m to 3 m (including 0.7 m and 3 m).
  • the gases used when dry-etching the P-type semiconductor layer 14 ', the active region 13', and the N-type semiconductor layer 12 'using inductively coupled plasma are Cl2 (chlorine gas), BCl3 (trichloride Boron) and Ar (argon).
  • Cl2 chlorine gas
  • BCl3 trichloride Boron
  • Ar argon
  • the semiconductor chip has a first end portion 101 'and a second end portion 102' corresponding to the first end portion 101 '.
  • the semiconductor exposed portion 15 ′ has an N-type electrode pad exposed portion 151 ′ and two N-type electrode extension strip exposed portions 152 ′, wherein the semiconductor exposed portion 15 ′ An N-type electrode pad exposed portion 151 'is formed at the second end portion 102' of the semiconductor chip, and the two N-type electrode extension strip exposed portions 152 'of the semiconductor exposed portion 15' are symmetrical to each other.
  • the method extends from the N-type electrode pad exposed portion 151 ′ to the first end portion 101 ′ of the semiconductor chip in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the two N-type electrode extension strip exposed portions 152 'of the semiconductor exposed portion 15' communicate with the N-type electrode pad exposed portions 151 ', respectively.
  • the N-type electrode pad exposed portion 151 'and the two N-type electrode extension strip exposed portions 152' of the semiconductor exposed portion 15 ' are formed by the same etching process, and the semiconductor Both the N-type electrode pad exposed portion 151 'and the two N-type electrode extension strip exposed portions 152' of the exposed portion 15 'extend from the P-type semiconductor layer 14' through the active region 13 'to
  • the N-type semiconductor layer 12 'to expose a part of the surface of the N-type semiconductor layer 12' to the N-type electrode pad exposed portion 151 'of the semiconductor exposed portion 15' and the two N-type electrodes Expansion strip exposed 152 '.
  • the current blocking layers 20 ' is stacked on the P-type semiconductor layer 14' of the epitaxial unit 10 '.
  • the number of the current blocking layers 20 ′ is three, and all three of the current blocking layers 20 ′ are in a strip shape, wherein the three current blocking layers 20 ′ are sequentially defined as a first A current blocking layer 20a ', a second current blocking layer 20b', and a third current blocking layer 20c ', wherein the first current blocking layer 20a', the second current blocking layer 20b ', and the third current
  • the barrier layers 20 c ′ extend from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip along the length direction of the semiconductor chip, respectively.
  • One of the N-type electrode extension strip exposed portions 152 'of the semiconductor exposed portion 15' is held between the first current blocking layer 20a 'and the second current blocking layer 20b', and the semiconductor exposed portion 15 'of the other N-type electrode extension strip exposed portion 152' is held between the second current blocking layer 20b 'and the third current blocking layer 20c'.
  • the first current blocking layer 20a 'and the third current blocking layer 20c' are symmetrical to each other at the edge of the semiconductor chip along the length direction of the semiconductor chip from the location of the semiconductor chip.
  • the first end portion 101 ′ extends toward the second end portion 102 ′, and the second current blocking layer 20 b ′ is held between the first current blocking layer 20 a ′ and the third current blocking layer 20 c.
  • the method of “between” extends from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′ in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the manner in which the current blocking layer 20 'is stacked on the P-type semiconductor layer 14' of the epitaxial cell 10 ' is not limited in the semiconductor chip of the present invention.
  • a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD) is used to deposit a layer of SiO2 (silicon dioxide) on the epitaxial unit. 10 'of the P-type semiconductor layer 14', the thickness of SiO2 ranges from 500 Angstroms to 10,000 Angstroms (including 500 Angstroms and 10,000 Angstroms), and the reaction gases used are SiH4 (silane), N2O (nitrogen monoxide), and N2 (Nitrogen).
  • the structure of the current blocking layer 20 ' is photolithographically using positive resist, wherein the thickness of the photoresist ranges from 0.5 m to 5 m (including 0.5 m and 5 m).
  • SiO2 is etched by wet etching to make a pattern of the current blocking layer 20 ', wherein the etching solution is a mixed solution of hydrofluoric acid and ammonium fluoride.
  • the photoresist is removed after the etching is completed to form the current blocking layer 20 'of the P-type semiconductor layer 14' laminated on the epitaxial unit 10 '.
  • the current blocking layer 20 ' may be stacked on the N-type semiconductor layer 12' of the epitaxial unit 10 '.
  • the current blocking layer 20 ′ may be formed on the N-type electrode extension strip exposed portion 152 ′ of the semiconductor bare portion 15 ′, so that the current blocking layer 20 ′ is stacked on the semiconductor blocking portion 15 ′.
  • the current blocking by the N-type semiconductor layer 12 ′ laminated on the epitaxial unit 10 ′ The number of the layers 20 ′ is multiple and there is a gap between the adjacent current blocking layers 20 ′, but those skilled in the art should understand that the semiconductor chip shown in FIGS. 10A and 10B is only an example. That is, in other possible examples of the semiconductor chip, the number of the current blocking layers 20 ′ laminated on the N-type semiconductor layer 12 ′ may be one, and the current blocking layers 20 ′ are striped. Shape so that the extension direction and extension length of the current blocking layer 20 'are consistent with the extension direction and extension length of the N-type electrode extension strip bare portion 152' of the semiconductor bare portion 15 '.
  • an indium tin oxide layer (ITO) is deposited on the P-type semiconductor layer 14 'of the epitaxial unit 10', wherein the indium tin oxide layer is electrically connected On the P-type semiconductor layer 14 '.
  • the indium tin oxide layer is alloyed.
  • the manner of alloying the indium tin oxide layer is not limited in the semiconductor chip of the present invention.
  • a rapid annealing furnace or an alloy furnace tube may be used for alloying the indium tin oxide.
  • the wet etching method is used to etch the indium tin oxide layer after the photoresist is completed, so as to obtain the obtained after the etching is completed and the photoresist is removed.
  • the transparent conductive layer 30 ′ wherein the transparent conductive layer 30 ′ has at least one row of perforations 31 ′, wherein each of the perforations 31 ′ in each column of the perforations 31 ′ corresponds to the current blocking layer 20, respectively. Different positions of the current blocking layer 20 'to expose the through holes 31' of the transparent conductive layer 30 '.
  • the etching solution used when the indium tin oxide layer is etched by a wet etching method is a mixed solution of hydrochloric acid and ferric chloride.
  • the transparent conductive layer 30 ′ has three rows of the perforations 31 ′, wherein each of the perforations 31 ′ of one row of the perforations 31 ′ of the transparent conductive layer 30 ′ corresponds to each other.
  • each of the perforations 31' in another row of the perforations 31 'of the transparent conductive layer 30' corresponds to the second current blocking layer 20b ', respectively.
  • each of the perforations 31' in the another row of the perforations 31 ' corresponds to different positions of the third current blocking layer 20c'.
  • At least one of the through-holes 31 ′ in at least one column of the through-holes 31 ′ is different from the adjacent through-holes 31 ′, for example, in In this preferred example of the semiconductor chip of the present invention, at least one of the through-holes 31 ′ in at least one row of the through-holes 31 ′ and the adjacent through-holes 31 ′ have different sizes.
  • at least one of the through-holes 31 'and at least one of the through-holes 31' and adjacent to the through-holes 31 ' The shape can be different, or the shape and size can be different.
  • the size of each of the through holes 31 'in at least one column of the through holes 31' is from the size of the semiconductor chip.
  • the first end portion 101 ′ is sequentially increased in the direction of the second end portion 102 ′. That is, the size of the through hole 31 'near the second end portion 102' of the semiconductor chip is larger than the size of the through hole 31 'near the first end portion 101' of the semiconductor chip.
  • a pattern of an N-type electrode 41 ′ and a pattern of a P-type electrode 42 ′ of the electrode group 40 ′ are etched on the surface of the transparent conductive layer 30 ′ with a negative photoresist.
  • a metal electrode layer is deposited by evaporation or sputtering.
  • the excess metal layer and the remaining photoresist are removed by peeling to form the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 '.
  • the N-type electrode 41 ′ includes an N-type electrode pad 411 ′ and two N-type electrode extension strips 412 ′ electrically connected to the N-type electrode pad 411 ′, wherein the N-type electrode 41 'The N-type electrode pad 411' is formed in the N-type electrode pad exposed portion 151 'of the semiconductor exposed portion 15' of the epitaxial unit 10 ', so that the N-type electrode pad 411 'is laminated on and electrically connected to the N-type semiconductor layer 12' of the epitaxial unit 10 ', wherein the N-type electrode extension strip 412' of the N-type electrode 41 'is formed on the epitaxial unit 10' The N-type electrode extension strip exposed portion 152 'of the semiconductor exposed portion 15', so that the N-type electrode extension strip 412 'is laminated on and electrically connected to the N-type semiconductor of the epitaxial unit 10' Layer 12 '.
  • the N-type electrode extension strip 412 ' fills a gap between the adjacent current blocking layers 20' stacked on the N-type semiconductor layer 12 '.
  • the two N-type electrode extension strips 412 ' are symmetrical to each other in the middle of the semiconductor chip along the length direction of the semiconductor chip from the N-type electrode pad 411' to the semiconductor chip.
  • the first end portion 101 ' extends in a direction.
  • the P-type electrode 42 ' includes a P-type electrode pad 421' and three P-type electrode extension bars 422 'electrically connected to the P-type electrode pad 421', and one of the P-type electrodes is expanded.
  • the strip 422 ' is defined as a first P-shaped electrode extension strip 422a'
  • the other P-shaped electrode expansion strip 422 ' is defined as a second P-shaped electrode expansion strip 422b'
  • the other P-shaped electrode is extended
  • the strip 422 ' is defined as a third P-type electrode extension strip 422c'.
  • the length direction extends from the P-type electrode pad 421 ′ from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′.
  • the P-shaped interdigital finger 4220 'of the strip 422a' is formed and held in each of the perforations 31 'of the transparent conductive layer 30'; the second P-shaped electrode extension strip 422b of the P-shaped electrode 42 ' 'Coincident with the second current blocking layer 20b', so that the P-shaped interdigits 4220 'of the second P-type electrode extension strip 422b' are formed and held on the transparent conductive layer 30 '
  • Each of the perforations 31 '; the third P-type electrode extension strip 422c' of the P-type electrode 42 'and the third current blocking layer 20c' overlap with each other, so that the first P-type electrode
  • the P-shaped interdigital finger 4220 'of the extension strip 422a' is formed and held in each of the through holes
  • the first P-type electrode extension strip 422a 'and the third P-type electrode extension strip 422c' of the P-type electrode 42 ' are respectively symmetric along the edges of the semiconductor chip along the edges of the semiconductor chip.
  • the length direction of the semiconductor chip extends from the P-type electrode pad 421 ′ to the second end portion 102 ′ of the semiconductor chip, and the second P-type electrode of the P-type electrode 42 ′ is expanded.
  • the strip 422 b ′ extends from the P-type electrode pad 421 ′ to the second end portion 102 ′ of the semiconductor chip in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • One of the N-type electrode extension strips 412 ′ of the N-type electrode 41 ′ is held by the first P-type electrode extension strip 422 a ′ and the second P-type electrode extension strip of the P-type electrode 42 ′. Between 422b ', another N-type electrode extension bar 412' is held between the second P-type electrode extension bar 422b 'and the third P-type electrode extension bar 422c'.
  • Each of the P-type electrode extension strips 422 'of the P-type electrode 42' has a row of the P-type interdigital fingers 4220 ', that is, the first P-type electrode extension strip 422a' has a row of the P-type electrodes
  • a row of the P-type interdigital fingers 4220 'of the first P-type electrode extension strip 422a' of the P-type electrode 42 ' Each of the P-shaped interdigital fingers 4220 'is simultaneously formed in and held in each row of the through-holes 31' of the transparent conductive layer 30 ', because the transparent conductive layer 30'
  • the size of each of the through-holes 31 ′ in a row of the through-holes 31 ′ is sequentially increased from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′, so that the first P A row of the P-shaped interdigital finger 4220 'of each of the P-shaped interdigital fingers 4220' of the type electrode extension bar 422a 'has a size from the first end portion 101' to the second end portion of the semiconductor chip
  • the 102 'direction increases in sequence.
  • the size of the P-type interdigital finger 4220 'near the P-type electrode pad 411' of the P-type interdigital finger 4220 ' is smaller than the P of the P-type electrode finger 411' far from the P-type electrode pad 411 '.
  • the size of the interdigital finger 4220 ' is beneficial to the uniform distribution of current to the P-type semiconductor layer 14'.
  • a row of the P-type interdigital fingers 4220 'of the second P-type electrode extension strip 422b' of the P-type electrode 42 ' is simultaneously formed in and held in each row of the through-holes 31' of the transparent conductive layer 30 ', because the transparent conductive layer 30'
  • the size of each of the through-holes 31 ′ of a row of the through-holes 31 ′ is sequentially increased from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′, so that the second P A row of the P-shaped interdigital finger 4220 'of each of the P-shaped interdigital fingers 4220' of the type electrode extension bar 422b 'has a size from the first end portion 101' to the second end portion of the semiconductor chip.
  • the 102 'direction increases in sequence. That is, the size of the P-type interdigital finger 4220 'near the P-type electrode pad 411' of the P-type interdigital finger 4220 'is smaller than the P of the P-type electrode finger 411' far from the P-type electrode pad 411 '.
  • the size of the interdigital finger 4220 ' is beneficial to the uniform distribution of current to the P-type semiconductor layer 14'.
  • a row of the P-type interdigital fingers 4220 'of the third P-type electrode extension strip 422c' of the P-type electrode 42 ' is simultaneously formed in and held in a row of the perforations 31' of the transparent conductive layer 30 ', each of the P-shaped interdigital fingers 4220' because the transparent conductive
  • the size of each of the through-holes 31 ′ of a row of the through-holes 31 ′ of the layer 30 ′ is sequentially increased from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′, so that the A row of the third P-shaped electrode extension strip 422c 'has a size of each of the P-shaped interdigitals 4220' from the first end portion 101 'of the semiconductor chip to the first
  • the size of the P-type interdigital finger 4220 'near the P-type electrode pad 411' of the P-type interdigital finger 4220 ' is smaller than the P of the P-type electrode finger 411' far from the P-type electrode pad 411 '.
  • the size of the interdigital finger 4220 ' is beneficial to the uniform distribution of current to the P-type semiconductor layer 14'.
  • the semiconductor chip further includes a passivation layer 50 ′, wherein the passivation layer 50 ′ is stacked on the P-type semiconductor layer 14 ′ of the epitaxial unit 10 ′, And the passivation layer 50 'covers the transparent conductive layer 30' and the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 ', wherein the passivation layer 50' has At least one first through hole 51 'and at least one second through hole 52', wherein the first through hole 51 'of the passivation layer 50' corresponds to the N-type electrode 41 of the electrode group 40 ' 'The N-type electrode pad 411', so that the N-type electrode pad 411 'is exposed in the first through hole 51', and accordingly, the second passivation layer 50 '
  • the through hole 52 ' corresponds to the P-type electrode pad 421' of the P-type electrode 42 'of the electrode group 40', so that the P-
  • a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition (PECVD)) is used to deposit a layer of SiO2 (silicon dioxide) on the epitaxial unit 10 '.
  • the P-type semiconductor layer 14 ' has a thickness ranging from 500 Angstroms to 10,000 Angstroms (including 500 Angstroms and 10,000 Angstroms), and the reaction gases used are SiH4 (silane), N2O (nitrogen monoxide), and N2 (nitrogen).
  • the structure of the passivation layer 30 is etched using positive resist.
  • SiO2 is etched by wet etching to make a pattern of the passivation layer 50 ', wherein the etching solution is a mixed solution of hydrofluoric acid and ammonium fluoride.
  • the photoresist is removed after the etching is completed to form the passivation layer 50 'of the P-type semiconductor layer 14' laminated on the epitaxial unit 10 ', and the passivation layer 50' covers The N-type electrode 41 'and the P-type electrode 42' covering the transparent conductive layer 30 'and the electrode group 40', and the first through hole 51 'of the passivation layer 50' corresponds to The N-type electrode pad 411 'of the N-type electrode 41' of the electrode group 40 ', and the second through hole 52' correspond to the P-type electrode 42 of the electrode group 40 ' 'The P-type electrode pad 421'.
  • External power can be supplied to the N-type electrode 41 'and the P of the electrode group 40' via the first through hole 51 'and the second through hole 52' of the passivation layer 50 ', respectively.
  • a current can be injected into the N-type semiconductor layer 12 'of the epitaxial unit 10' through the N-type electrode pad 411 'and the N-type electrode extension strip 412' of the N-type electrode 41 '.
  • the current blocking layer 20 ' is held between the N-type electrode extension strip 412' and the N-type semiconductor layer 12 ', wherein the current blocking layer 20' can prevent current from being concentrated in the N-type electrode extension strip A lower portion of 412 ', so that a current can be uniformly injected into the N-type semiconductor layer 12' around.
  • a current can be injected into the transparent conductive layer 30 'through the P-type electrode pad 421' of the P-type electrode 42 'and each of the P-type electrode extension strips 422', because each of the P A type electrode extension strip 422 'is laminated on the transparent conductive layer 30' and the P-type interdigital 4220 'of each of the P type electrode extension strips 422' is held in these places of the transparent conductive layer 30 ', respectively.
  • the perforation 31 ', and the size of the P-shaped interdigit 4220' of each of the P-shaped electrode extension strips 422 ' is from the P-shaped electrode pad 421' to the second end portion of the semiconductor chip
  • the direction of 102 ' is sequentially increased, so that current can be uniformly injected into the transparent conductive layer 30' from the surface and the inside of the transparent conductive layer 30 'via the P-type electrode extension strip 422'.
  • the current blocking layer 20 ' is held between the layer 30' and the P-type semiconductor layer 14 ', so that the current blocking layer 20' can prevent current from being concentrated on the lower portion of the P-type electrode extension strip 422 ', so as to This allows current to be uniformly injected into the P-type semiconductor layer 14 ′ around the periphery.
  • the current that is uniformly injected into the N-type semiconductor layer 12 'and the current that is uniformly injected into the P-type semiconductor layer 14' can recombine in the active region 13 'to generate light, and in such a way that the The brightness of the semiconductor chip can be effectively improved.
  • FIGS. 11A and 11B illustrate a modified embodiment of the semiconductor chip, and at least one row of the through holes 31 'in the transparent conductive layer 30' in the semiconductor chip shown in FIGS. 10A and 10B.
  • the size of each of the through holes 31 ′ is sequentially increased from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip.
  • the dimensions shown in FIGS. 11A and 11B are as follows.
  • a size of each of the through holes 31 'in at least one row of the through holes 31' of the transparent conductive layer 30 ' is from the first end portion 101' of the semiconductor chip. Decreases in order toward the second end portion 102 '. That is, the size of the through hole 31 'near the second end portion 102' of the semiconductor chip is smaller than the size of the through hole 31 'near the first end portion 101' of the semiconductor chip.
  • each of the P-shaped interdigital fingers 4220 ′ decreases in order from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′. That is, the size of the P-shaped prongs 4220 'near the second end portion 102' of the semiconductor chip is smaller than the P-shaped prongs near the first end portion 101 'of the semiconductor chip. It refers to the size of 4220 ', which is beneficial for the current to be evenly distributed to the P-type semiconductor layer 14'.
  • FIGS. 12A and 12B illustrate a modified embodiment of the semiconductor chip, and in at least one column of the perforations 31 ′ of the transparent conductive layer 30 ′ in the semiconductor chip shown in FIGS. 10A and 10B.
  • the size of each of the through holes 31 ′ is sequentially increased from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip.
  • the difference is that the dimensions shown in FIGS. 12A and 12B are as follows.
  • each of the through-holes 31 'of at least one row of the transparent conductive layer 30' has the same size, and at least one of the rows of the transparent conductive layer 30 'has the same size.
  • a distance between two adjacent through-holes 31 ′ of the through-hole 31 ′ gradually decreases from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′. Therefore, after the P-type electrode 42 'is laminated on the transparent conductive layer 30', a row of the P-type interdigital finger 4220 'in the P-type electrode extension strip 422' of the P-type electrode 42 ' The size of each of the P-shaped interdigital fingers 4220 'is unchanged, and a row of the P-shaped interdigital fingers 4220' of the P-shaped electrode extension strip 422 'of the P-shaped electrode 42' is adjacent to each other. The distance between the P-shaped interdigital fingers 4220 'gradually decreases from the first end portion 101' to the second end portion 102 'of the semiconductor chip.
  • the P-type semiconductor layer 14 ' is described.
  • FIGS. 13A and 13B illustrate a modified embodiment of the semiconductor chip, and in at least one column of the perforations 31 ′ of the transparent conductive layer 30 ′ in the semiconductor chip shown in FIGS. 10A and 10B.
  • the size of each of the through holes 31 ′ is sequentially increased from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip.
  • the difference is that the dimensions shown in FIGS. 13A and 13B are as follows.
  • a size of each of the through holes 31 'in at least one row of the through holes 31' of the transparent conductive layer 30 ' is from the first end portion 101' of the semiconductor chip.
  • a row of the P-type interdigital fingers 4220 'of the P-type electrode extension strip 422' of the P-type electrode 42 ' It gradually decreases from the first end portion 101 ′ of the semiconductor chip toward the second end portion 102 ′, and two adjacent P-shaped interdigitals 4220 of the column of P-shaped interdigitals 4220 ′ The interval between the distances gradually decreases from the first end portion 101 ′ of the semiconductor chip toward the second end portion 102 ′. This manner is beneficial to the current being evenly distributed to the P-type semiconductor layer 14. '.
  • FIGS. 14A and 14B illustrate a modified embodiment of the semiconductor chip, and in at least one column of the perforations 31 ′ of the transparent conductive layer 30 ′ in the semiconductor chip shown in FIGS. 10A and 10B.
  • the size of each of the through holes 31 ′ is sequentially increased from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip.
  • the difference is that the dimensions shown in FIGS. 14A and 14B are as follows.
  • a size of each of the through holes 31 'in at least one row of the through holes 31' of the transparent conductive layer 30 ' is from the first end portion 101' of the semiconductor chip.
  • a row of the P-type interdigital fingers 4220 'of the P-type electrode extension strip 422' of the P-type electrode 42 ' It gradually decreases from the first end portion 101 ′ of the semiconductor chip toward the second end portion 102 ′, and two adjacent P-shaped interdigitals 4220 of the column of P-shaped interdigitals 4220 ′
  • FIGS. 15A and 15B illustrate a modified embodiment of the semiconductor chip, and in at least one column of the perforations 31 'of the transparent conductive layer 30' in the semiconductor chip shown in FIGS. 10A and 10B.
  • the size of each of the through holes 31 ′ is sequentially increased from the first end portion 101 ′ to the second end portion 102 ′ of the semiconductor chip.
  • the difference is that the dimensions shown in FIGS. 15A and 15B are as follows.
  • each of the through-holes 31 'of at least one row of the transparent conductive layer 30' has the same size, and at least one of the rows of the transparent conductive layer 30 'has the same size.
  • a distance between two adjacent through holes 31 ′ of the through hole 31 ′ gradually increases from the first end portion 101 ′ of the semiconductor chip to the second end portion 102 ′. Therefore, after the P-type electrode 42 'is laminated on the transparent conductive layer 30', a row of the P-type interdigital finger 4220 'in the P-type electrode extension strip 422' of the P-type electrode 42 ' The size of each of the P-shaped interdigital fingers 4220 'is unchanged, and a row of the P-shaped interdigital fingers 4220' of the P-shaped electrode extension strip 422 'of the P-shaped electrode 42' is adjacent to each other. The distance between the P-shaped interdigital fingers 4220 'gradually increases from the first end portion 101' to the second end portion 102 'of the semiconductor chip. This way is beneficial to the current being evenly distributed to the P-type semiconductor layer 14 '.
  • FIGS. 16A and 16B show a modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIGS. 10A and 10B is that the semiconductor shown in FIGS. 16A and 16B
  • the size of each of the through holes 31 'in at least one row of the through holes 31' of the transparent conductive layer 30 ' is from the first end portion 101' of the semiconductor chip toward the The direction of the second end portion 102 ′ is gradually increased, and a distance between two adjacent through holes 31 ′ of the row of the through holes 31 ′ is from the first end portion 101 ′ of the semiconductor chip to the The direction of the second end portion 102 'gradually decreases.
  • FIGS. 17A and 17B show a modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIGS. 10A and 10B is that the semiconductor shown in FIGS. 17A and 17B
  • the size of each of the through holes 31 'in at least one row of the through holes 31' of the transparent conductive layer 30 ' is from the first end portion 101' of the semiconductor chip toward the The direction of the second end portion 102 ′ is gradually increased, and a distance between two adjacent through holes 31 ′ of the row of the through holes 31 ′ is from the first end portion 101 ′ of the semiconductor chip to the The direction of the second end portion 102 'gradually increases.
  • FIG. 18 shows a modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIGS. 10A and 10B is this preferred example of the semiconductor chip shown in FIG. 18.
  • the semiconductor exposed portion 15 ' there is one N-type electrode pad exposed portion 151' and one N-type electrode extension strip exposed portion 152 ', wherein the N-type electrode pad exposed portion 151' is formed on The second end portion 102 ′ of the semiconductor chip, and the N-type electrode extension strip exposed portion 152 ′ are exposed from the N-type electrode pad in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the portion 151 ' extends in the direction of the first end portion 101' of the semiconductor chip.
  • the N-type electrode 41' includes an N-type electrode layer 41 'laminated on the N-type semiconductor layer 12' and held in the N-type electrode pad exposed portion 151 '.
  • the N-type electrode extension strip 412 ′ extends from the N-type electrode pad 411 ′ to the first end portion 101 ′ of the semiconductor chip in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the number of the current blocking layers 20 ′ is two, and two of the current blocking layers 20 ′ are symmetrical to each other at the edges of the semiconductor chip along the length direction of the semiconductor chip.
  • the first end portion 101 ′ of the semiconductor chip extends in the direction of the second end portion 102 ′.
  • the transparent conductive layer 30 ′ is stacked on the P-type semiconductor layer 14 ′ so as to cover the current blocking layer 20 ′, and the perforations 31 ′ of each column of the transparent conductive layer 30 ′ are respectively Corresponds to the current blocking layer 20 '.
  • the transparent conductive layer 30 ' has two rows of the perforations 31', wherein each of the perforations 31 'in each of the columns of the perforations 31' corresponds to a difference in each of the current blocking layers 20 ', respectively. position.
  • the P-type electrode 42' includes one P-type electrode pad 421 'and two P-type electrodes laminated on the transparent conductive layer 30'.
  • An electrode extension strip 422 ' wherein the P-type electrode pad 421' is formed at the first end portion 101 'of the semiconductor chip, wherein each of the P-type electrode extension strips 422' is symmetrical to each other At the edge of the semiconductor chip extending from the P-type electrode pad 421 'to the second end portion 102' of the semiconductor chip along the length direction of the semiconductor chip, and each of the P-type
  • the P-shaped interdigital finger 4220 'of the electrode extension strip 422' is formed and held in each of the through holes 31 'of the transparent conductive layer 30', respectively. Referring to FIG. 18, the N-type electrode extension strip 412 'of the N-type electrode 41' is held between two P-type electrode extension strips 422 'of the P-type electrode 42'.
  • the passivation layer 50 ′ is stacked on the P-type semiconductor layer 14 ′ of the epitaxial unit 10 ′, and the passivation layer 50 ′ covers the transparent conductive layer 30 ′ and the transparent conductive layer 30 ′.
  • the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 ' wherein the first through hole 51' of the passivation layer 50 'corresponds to the N-type electrode 41', and The N-type electrode 41 ′ is exposed to the first through-hole 51 ′ of the passivation layer 50 ′, and the second through-hole 52 ′ of the passivation layer 50 ′ corresponds to the P-type The electrode 42 ', so that the P-type electrode 42' is exposed to the second through hole 52 'of the passivation layer 50'.
  • FIG. 19 shows another modified embodiment of the semiconductor chip.
  • the semiconductor exposed portion 15 ' has one of the N-type electrode pad exposed portions 151' and three of the N-type electrode extension strip exposed portions 152 ', wherein the N-type electrode pad exposed portions 151' Formed on the second end portion 102 ′ of the semiconductor chip, three of the N-type electrode extension bar exposed portions 152 ′ are defined as a first extension bar exposed portion 152 a ′ and a second extension bar exposed, respectively.
  • a portion 152b 'and a third extension bar exposed portion 152c' wherein the first extension bar exposed portion 152a 'and the third extension bar exposed portion 152c' are along the edges of the semiconductor chip in a symmetrical manner with each other.
  • the length direction of the semiconductor chip extends from the N-type electrode pad exposed portion 151 ′ to the first end portion 101 ′ of the semiconductor chip, and the second extension strip exposed portion 152 b ′ is in the semiconductor.
  • the N-type electrode 41' includes one N-type electrode pad 411 'and three N-type electrode extension strips 412', wherein the N A type electrode pad 411 'is stacked on the N-type semiconductor layer 12' and held at the N-type electrode pad exposed portion 151 ', wherein three of the N-type electrode extension strips 412' are defined as a first N-type electrode extension strip 412a ', a second N-type electrode extension strip 412b', and a third N-type electrode extension strip 412c ', wherein the first N-type electrode extension strip 412a' and the second N-type electrode
  • the extension strip 412 b ′ and the third N-type electrode extension strip 412 c ′ are stacked on the N-type semiconductor layer 12 ′, and are respectively held by the first extension strip exposed portion 152 a ′ and the second extension strip are exposed.
  • Portion 152b 'and the third extension bar exposed portion 152c' so that the first N-type electrode extension bar 412a 'and the third N-type electrode extension bar 412c' are symmetrical to each other on the semiconductor chip Along the length of the semiconductor chip from the N-type electrode pad 411 'to the half
  • the body chip extends in the direction of the first end portion 101 ′, and the second N-type electrode extension strip 412 b ′ extends from the N-type electrode pad 411 in the middle of the semiconductor chip along the length direction of the semiconductor chip. Extending in the direction of the first end portion 101 of the semiconductor chip.
  • the number of the current blocking layers 20 ′ is two, and two of the current blocking layers 20 ′ are symmetrical to each other in the middle of the semiconductor chip along the length direction of the semiconductor chip.
  • the first end portion 101 ′ of the semiconductor chip extends in the direction of the second end portion 102 ′.
  • the transparent conductive layer 30 ' is laminated on the P-type semiconductor layer 14' in a manner of covering the current blocking layer 20 ', and the perforations 31' of the transparent conductive layer 30 'respectively correspond to The current blocking layer 20 '.
  • the transparent conductive layer 30 ' has two rows of the perforations 31', wherein each row of the perforations 31 'corresponds to each of the current blocking layers 20'.
  • the P-type electrode 42' includes one P-type electrode pad 421 'and two P-type electrodes laminated on the transparent conductive layer 30'.
  • An electrode extension strip 422 ' wherein each of the P-type electrode extension strips 422' is symmetrical to each other in the middle of the semiconductor chip along the length direction of the semiconductor chip from the P-type electrode pad 421 ' Extending toward the second end portion 102 ′ of the semiconductor chip, and the P-shaped interdigits 4220 ′ of each of the P-type electrode extension strips 422 ′ are formed and held on the transparent conductive layer, respectively 30 'of each of said perforations 31'. Referring to FIG.
  • one of the P-type electrode extension bars 422 'of the P-type electrode 42' is held between the first N-type electrode extension bar 412a 'and the second N-type electrode extension bar 412b'. Meanwhile, another P-type electrode extension strip 422 'is held between the second N-type electrode extension strip 412b' and the third N-type electrode extension strip 412c '.
  • the passivation layer 50 ′ is stacked on the P-type semiconductor layer 14 ′ of the epitaxial unit 10 ′, and the passivation layer 50 ′ covers the transparent conductive layer 30 ′ and the transparent conductive layer 30 ′.
  • the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 ' wherein the first through hole 51' of the passivation layer 50 'corresponds to the N-type electrode 41', and The N-type electrode 41 ′ is exposed to the first through-hole 51 ′ of the passivation layer 50 ′, and the second through-hole 52 ′ of the passivation layer 50 ′ corresponds to the P-type The electrode 42 ', so that the P-type electrode 42' is exposed to the second through hole 52 'of the passivation layer 50'.
  • FIG. 20 shows another modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIG. 19 is that in this preferred example of the semiconductor chip shown in FIG. 20,
  • the semiconductor exposed portion 15 ' has one N-type electrode pad exposed portion 151' and two N-type electrode extension strip exposed portions 152 ', wherein the N-type electrode pad exposed portion 151' is formed at The second end portion 102 ′ of the semiconductor chip, and the two exposed portions 152 ′ of the N-type electrode extension strips are symmetrical to each other at the edges of the semiconductor chip along the length direction of the semiconductor chip.
  • the N-type electrode pad exposed portion 151 ' extends toward the first end portion 101' of the semiconductor chip.
  • the N-type electrode 41' includes one of the N-type electrode pad 411 'and two of the N-type electrode extension strip 412', wherein the N A type electrode pad 411 'is laminated on the N-type semiconductor layer 12' and held on the N-type electrode pad exposed portion 151 ', wherein each of the N-type electrode extension bars 412' is laminated on the N Type semiconductor layer 12 'and each exposed part 152' of the N-type electrode extension strip, so that each of the N-type electrode extension strip 412 'runs along the edge of the semiconductor chip in a mutually symmetrical manner.
  • the length direction of the semiconductor chip extends from the N-type electrode pad 411 ′ toward the first end portion 101 ′ of the semiconductor chip.
  • the number of the current blocking layers 20 ′ is one, and the current blocking layers 20 ′ are located in the middle of the semiconductor chip along the length direction of the semiconductor chip from the first portion of the semiconductor chip.
  • One end portion 101 ' extends in the direction of the second end portion 102'.
  • the transparent conductive layer 30 ' is laminated on the P-type semiconductor layer 14' in a manner covering the current blocking layer 20 ', and the perforations 31' of the transparent conductive layer 30 'correspond to The current blocking layer 20 'is described.
  • the P-type electrode 42' includes a P-type electrode pad 421 'and a P-type electrode laminated on the transparent conductive layer 30'.
  • An extension strip 422 ' wherein the P-type electrode pad 421' is formed at the first end portion 101 'of the semiconductor chip, and the P-type electrode extension strip 422' is formed along a middle portion of the semiconductor chip.
  • the length direction of the semiconductor chip extends from the P-type electrode pad 421 ′ to the second end portion 102 ′ of the semiconductor chip, and the P-type interdigit of the P-type electrode extension strip 422 ′.
  • 4220 ' is formed in and held in the through hole 31' of the transparent conductive layer 30 '. Referring to FIG. 20, the P-type electrode extension strip 422 'of the P-type electrode 42' is held between two N-type electrode extension strips 412 'of the N-type electrode 41'.
  • the passivation layer 50 ′ is stacked on the P-type semiconductor layer 14 ′ of the epitaxial unit 10 ′, and the passivation layer 50 ′ covers the transparent conductive layer 30 ′ and the transparent conductive layer 30 ′.
  • the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 ' wherein the first through hole 51' of the passivation layer 50 'corresponds to the N-type electrode 41', and The N-type electrode 41 ′ is exposed to the first through-hole 51 ′ of the passivation layer 50 ′, and the second through-hole 52 ′ of the passivation layer 50 ′ corresponds to the P-type The electrode 42 ', so that the P-type electrode 42' is exposed to the second through hole 52 'of the passivation layer 50'.
  • FIG. 21 shows another modified embodiment of the semiconductor chip.
  • the difference from the semiconductor chip shown in FIG. 20 is that in this preferred example of the semiconductor chip shown in FIG. 21,
  • the semiconductor exposed portion 15 ' has only one of the N-type electrode pad exposed portions 151', which is formed on the second end portion 102 'of the semiconductor chip.
  • the N-type electrode 41 ′ includes only one N-type electrode pad 411 ′, wherein the N-type electrode pad 411 ′ is stacked on the N Type semiconductor layer 12 'and the exposed portion 151' held in the N-type electrode pad.
  • the number of the current blocking layer 20 ′ is one, and the current blocking layer 20 ′ is located in the middle of the semiconductor chip from the first direction of the semiconductor chip along the length direction of the semiconductor chip.
  • One end portion 101 ′ extends in the direction of the second end portion 102 ′, and subsequently, the transparent conductive layer 30 ′ is laminated on the P-type semiconductor layer 14 ′ so as to cover the current blocking layer 20 ′.
  • the through hole 31 'of the transparent conductive layer 30' corresponds to the current blocking layer 20 '.
  • the P-type electrode 42' includes a P-type electrode pad 421 'and a P-type electrode laminated on the transparent conductive layer 30'.
  • An extension strip 422 ' wherein the P-type electrode pad 421' is formed at the first end portion 101 'of the semiconductor chip, and the P-type electrode extension strip 421 runs along the middle of the semiconductor chip The length direction of the semiconductor chip extends from the P-type electrode pad 421 ′ to the second end portion 102 ′ of the semiconductor chip, and the P-type interdigital 4220 of the P-type electrode extension strip 422 ′.
  • the perforations 31' formed and held in the transparent conductive layer 30 '.
  • the passivation layer 50 ′ is stacked on the P-type semiconductor layer 14 ′ of the epitaxial unit 10 ′, and the passivation layer 50 ′ covers the transparent conductive layer 30 ′ and the transparent conductive layer 30 ′.
  • the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 ' wherein the first through hole 51' of the passivation layer 50 'corresponds to the N-type electrode 41', and The N-type electrode 41 ′ is exposed to the first through-hole 51 ′ of the passivation layer 50 ′, and the second through-hole 52 ′ of the passivation layer 50 ′ corresponds to the P-type The electrode 42 ', so that the P-type electrode 42' is exposed to the second through hole 52 'of the passivation layer 50'.
  • the substrate 11 ', the N-type semiconductor layer 12', the active region 13 ', and the P-type semiconductor layer of the semiconductor chip shown in the drawings of the present invention 14 ', the thickness of the current blocking layer 20', the transparent conductive layer 30 ', the N-type electrode 41', and the P-type electrode 42 ' are merely examples, and they do not represent the substrate 11' , The N-type semiconductor layer 12 ', the active region 13', the P-type semiconductor layer 14 ', the current blocking layer 20', the transparent conductive layer 30 ', and the N-type electrode 41' And the true thickness of the P-type electrode 42 '.
  • the substrate 11 ', the N-type semiconductor layer 12', the active region 13 ', the P-type semiconductor layer 14', the current blocking layer 20 ', and the transparent conductive layer 30' The true ratio between the N-type electrode 41 'and the P-type electrode 42' is not as shown in the drawings. In addition, the ratio of the size of the N-type electrode 41 'and the P-type electrode 42' of the electrode group 40 'to the size of other layers of the semiconductor chip is not limited to that shown in the drawings.
  • the size of the perforations 31 ′ of the transparent conductive layer 30 ′ of the semiconductor chip shown in the drawings of the present invention are all examples for exposing and explaining the content and features of the semiconductor chip of the present invention, and should not be considered as limiting the content and scope of the semiconductor chip of the present invention.
  • the size of the P-shaped interdigital finger 4220 'of the P-shaped electrode 42' of the semiconductor chip shown in the drawings of the present invention, and the size ratio of the adjacent P-shaped interdigital finger 4220 ' And the distance between the adjacent P-shaped interdigital fingers 4220 ' is an example for exposing and explaining the content and characteristics of the semiconductor chip of the present invention, and should not be regarded as the content of the semiconductor chip of the present invention. And limits of scope.

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Abstract

本发明公开了一发光二极管的半导体芯片及其制造方法，其中所述芯片包括依次层叠的一衬底、一N型半导体层、一有源区和一P型半导体层以及具有自所述P型半导体层延伸至所述N型半导体层的至少一半导体裸露部，所述芯片还包括一电流阻挡层、一透明导电层、一N型电极和一P型电极，其中所述电流阻挡层层叠于所述P型半导体层，所述透明导电层以包覆所述电流阻挡层的方式层叠于所述P型半导体层，且所述透明导电层的穿孔对应于所述电流阻挡层，所述N型电极层叠于所述N型半导体层，所述P型电极层叠于所述透明导电层，且所述P型电极的P型叉指被保持在所述透明导电层的所述穿孔。

Description

发光二极管的半导体芯片及其制造方法 技术领域
本发明涉及一LED芯片，特别涉及一发光二极管的半导体芯片及其制造方法。
背景技术
现有技术的正装LED芯片由两种结构，业界通常使用光刻步骤来对这两种结构的正装LED芯片进行命名，即，三道结构正装LED芯片和五道结构正装LED芯片。也就是说，三道结构正装LED芯片在被制作的过程中使用三道光刻步骤，五道结构正装LED芯片在被制作的过程中使用五道光刻步骤，通常情况下，五道结构正装LED芯片的光刻步骤也可以由五道光刻步骤简化为四道光刻步骤。对于三道结构正装LED芯片来说，其工序包括Mesa工序(台阶，指的是利用干法蚀刻的方式在外延片表面制作N型层裸露区域的工序)、ITO工序(指的是透明导电膜层图形工序)以及PV&Pad工序(指的是钝化层和电极使用相同的一道工序光刻图形制作的工序)；对于五道结构正装LED芯片来说，其工序包括Mesa工序、CB工序(电流阻挡层的制作工序)、ITO工序以及PV&Pad工序。从结构上来看说，三道结构正装LED芯片和五道结构正装LED芯片无明显差异，从流程上来说，五道结构正装LED芯片比五道结构正装LED芯片多了电流阻挡层(CB)的结构，其为P型电极的电流阻挡层，目的是为了防止正装LED芯片从P型电极注入的电流集中在P型电极的正下方而造成的电流拥挤效应。当然，电流阻挡层结构的增加为增加正装LED芯片制程成本，基于此，业内常用的小功率芯片、显示用芯片为三道结构正装LED芯片，而大功率芯片、照明用芯片为五道结构正装LED芯片。
从五道结构正装LED芯片的PN二极管正负极电阻组成来看，P型电极电流流经金属电极以被金属电极扩展后注入透明导电层，然后经过透明导电层之后注入P型氮化镓层，最后进入有源层；而N型电极电阻组成为电子经过金属电极以被金属电极扩展后注入N型氮化镓层，最后进入有源区，以在有源区复合发光。从整个电流过程来看，相对于半导体层的电导率，金属电极的电导率较高，因此，P型电极表面的电流有聚集在P叉指电极末端的趋势。从五道结构正装LED芯片的发光特性的曲线来看，随着电流密度的上升，亮度有上升然后下降的趋势，存在饱和电流密度，这会影响五道结构正装LED芯片的发光效率。理想的高亮度发光芯片结构能够使得正装LED芯片的电流密度维持在发光效率较高的区域，然而，目前的五道结构正装LED芯片无法实现。
发明内容
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述半导体芯片的亮度能够被有效地提升。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中注入所述半导体芯片的一P型半导体层的电流能够被均匀地分布，从而有利于提升所述半导体芯片的亮 度。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述半导体芯片提供一P型电极，通过所述P型电极注入所述半导体芯片的电流能够被强制分布，通过这样的方式，使得注入所述P型半导体层的电流能够被均匀地分布，从而有利于提升所述半导体芯片的亮度。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述半导体芯片提供层叠于所述P型半导体层的一电流阻挡层和层叠于所述P型半导体层且包覆所述电流阻挡层的一透明导电层，其中所述P型电极层叠于所述透明导电层，以使得自所述P型电极注入的电流能够进一步注入所述透明导电层后被所述电流阻挡层阻拦，从而避免电流聚集在所述P型电极的不良现象出现，以在后续能够使电流均匀地分布至所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述P型电极的P型叉指***所述透明导电层，以使被注入所述P型电极的电流能够进一步自所述透明导电层的表面和内部注入所述透明导电层，通过这样的方式，电流能够均匀地分布至所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述透明导电层提供至少一穿孔，以对应于所述电流阻挡层，其中所述P型电极的所述P型叉指形成于和被保持在所述透明导电层的所述穿孔，从而使得被注入所述P型电极的电流能够进一步自所述透明导电层的表面和内部注入所述透明导电层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中在所述P型电极成型的过程中，所述P型电极的所述P型叉指形成于和被保持在所述透明导电层的所述穿孔，从而使得所述P型电极嵌入所述透明导电层，所述P型电极和所述透明导电层的这种结合方式能够有效地保证所述芯片的稳定性和可靠性。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述半导体芯片提供层叠于所述P型半导体层的所述透明导电层和层叠于所述透明导电层的所述P型电极，其中经所述P型电极注入的电流能够经所述透明导电层的扩散后被均匀地注入所述P型半导体层，从而有利于提升所述半导体芯片的整体亮度。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述P型电极提供至少一列P型叉指，其中一列所述P型叉指沿着所述半导体芯片的长度方向排列并***到所述透明导电层的内部，通过这样的方式，电流能够自所述透明导电层的表面和内部经所述P型电极被注入所述透明导电层，这样的方式有利于均匀地注入电流至所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中所述P型电极提供一P型电极焊盘和至少一P型电极扩展条，其中所述P型电极焊盘形成于所述半导体芯片的第一端部，所述P型电极扩展条自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸，一列所述P型叉指中的每个P型叉指分别相互间隔地形成于所述P型电极扩展条，并且一列所述P型叉指中的至少一个所述P型叉指和相邻所述P型叉指的形状或尺寸不同，通过这样的方式，有利于经所述P型电极注入的电流能够经所述透明导电层的扩散 后被均匀地注入所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中一列所述P型叉指中的每个所述P型叉指的形状沿着所述P型电极扩展条渐变，通过这样的方式，有利于经所述P型电极注入的电流能够经所述透明导电层的扩散后被均匀地注入所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中一列所述P型叉指中的每个所述P型叉指的尺寸沿着所述P型电极扩展条渐变，通过这样的方式，有利于经所述P型电极注入的电流能够经所述透明导电层的扩散后被均匀地注入所述P型半导体层。
本发明的一个目的在于提供一发光二极管的半导体芯片及其制造方法，其中一列所述P型叉指中的相邻两个所述P型叉指之间的间距沿着所述P型电极扩展条渐变，通过这样的方式，有利于经所述P型电极注入的电流能够经所述透明导电层的扩散后被均匀地注入所述P型半导体层。
依本发明的一个方面，本发明提供一发光二极管的半导体芯片，其包括：
一外延单元，其中所述外延单元包括一衬底和自所述衬底依次生长的一N型半导体层、一有源区和一P型半导体层，其中所述外延单元具有至少一半导体裸露部，所述半导体裸露部自所述P型半导体层经所述有源区延伸至所述N型半导体层；
至少一电流阻挡层，其中所述电流阻挡层层叠于所述外延单元的所述P型半导体层；
一透明导电层，其中所述透明导电层具有至少一穿孔，其中所述透明导电层以包覆所述电流阻挡层的方式层叠于所述P型半导体层，并且所述透明导电层的所述穿孔对应于所述电流阻挡层；以及
一电极组，其中所述电极组包括至少一N型电极和至少一P型电极，其中所述N型电极以形成于所述半导体裸露部的方式层叠于所述N型半导体层，其中所述P型电极具有至少一P型叉指，在所述P型电极层叠于所述透明导电层时，所述P型电极的所述P型叉指形成于和被保持在所述透明导电层的所述穿孔。
根据本发明的一个实施例，所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘和自所述N型电极焊盘向所述半导体芯片的第一端部方向延伸的至少一N型电极扩展条，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少两P型电极扩展条，其中至少一个所述N型电极扩展条被保持在相邻两个所述P型电极扩展条之间。
根据本发明的一个实施例，所述N型电极的所述N型电极扩展条的数量是一个，并且所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是两个，并且两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸。
根据本发明的一个实施例，所述N型电极的所述N型电极扩展条的数量是两个，并且所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是三个，分别为一第一P型电极扩展条、一第二P型电极扩展条以及一第三P型电极扩展条，所述第一P型电极扩展条和所述第三P型 电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述N型电极扩展条被保持在所述第一P型电极扩展条和所述第二P型电极扩展条之间，另一个所述N型电极扩展条被保持在所述第二P型电极扩展条和所述第三P型电极扩展条之间。
根据本发明的一个实施例，所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘和自所述N型电极焊盘向所述半导体芯片的第一端部方向延伸的至少两N型电极扩展条，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少一P型电极扩展条，其中至少一个所述P型电极扩展条被保持在相邻两个所述N型电极扩展条之间。
根据本发明的一个实施例，所述N型电极的所述N型电极扩展条的数量是两个，并且两个所述N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是一个，并且所述P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸。
根据本发明的一个实施例，所述N型电极的所述N型电极扩展条的数量是三个，分别为一第一N型电极扩展条、一第二N型电极扩展条以及一第三N型电极扩展条，所述第一N型电极扩展条和所述第三N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是两个，其中两个所述P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述P型电极扩展条被保持在所述第一N型极扩展条和所述第二N型电极扩展条之间，另一个所述P型电极扩展条被保持在所述第二N型电极扩展条和所述第三N型电极扩展条之间。
根据本发明的一个实施例，所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的一P型电极扩展条。
根据本发明的一个实施例，所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
根据本发明的一个实施例，层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
根据本发明的一个实施例，层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
根据本发明的一个实施例，所述半导体芯片进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
依本发明的另一个方面，本发明进一步提供一半导体芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠一电流阻挡层于一外延单元的一P型半导体层；
(b)以包覆所述电流阻挡层的方式层叠一透明导电层于所述P型半导体层，其中所述透明导电层具有至少一穿孔，以对应于所述电流阻挡层；以及
(c)以一N型电极被保持在所述外延单元的一半导体裸露部的方式层叠所述N型电极于所述外延单元的一N型半导体层，和以一P型电极的P型叉指形成于所述透明导电层的所述穿孔的方式层叠所述P型电极于所述透明导电层，以制得所述半导体芯片。
根据本发明的一个实施例，所述制造方法进一步包括步骤：
(d)以包覆所述N型电极和所述P型电极的方式层叠一钝化层于所述透明导电层和所述P型半导体层，其中所述钝化层具有对应于所述N型电极的一第一通道和对应于所述P型电极的一第二通道。
根据本发明的一个实施例，在所述步骤(a)中，进一步包括步骤：
(a.1)沉积一层绝缘层于所述P型半导体层；和
(a.2)湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层。
根据本发明的一个实施例，在所述步骤(a.2)之前，所述步骤(a)进一步包括步骤：正胶光刻电流阻挡层结构，从而在所述步骤(a.2)中，根据电流阻挡层结构湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层，并且在所述步骤(a.2)之后，所述步骤(a)进一步包括步骤：去除光刻胶。
根据本发明的一个实施例，所述绝缘层的材料是SiO2材料。
根据本发明的一个实施例，在所述步骤(a.1)中，反应气体SiH4、N2O和N2，以沉积所述绝缘层于所述P型半导体层。
根据本发明的一个实施例，所述绝缘层的厚度尺寸范围为500埃至10000埃。
根据本发明的一个实施例，光刻胶的厚度尺寸范围为0.5μm至5μm。
根据本发明的一个实施例，湿法蚀刻所述绝缘层使用的蚀刻液为氢氟酸和氟化铵的混合溶液。
根据本发明的一个实施例，在所述步骤(b)中，进一步包括步骤：
(b.1)沉积包覆所述电流阻挡层的一层氧化铟锡层于所述P型半导体层；和
(b.2)湿法蚀刻所述氧化铟锡，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔。
根据本发明的一个实施例，在所述步骤(b.2)之前，所述步骤(b)进一步包括步骤：正胶光刻透明导电层结构，从而在所述步骤(b.2)中，根据透明导电层的结构蚀刻所述氧化铟锡层，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔，并且在所述步骤(b.2)之后，所述步骤(b)进一步包括步骤：去除光刻胶。
根据本发明的一个实施例，在所述正胶光刻透明导电层的步骤之前，所述步骤(b)进一步包括步骤：对所述氧化铟锡层进行合金。
根据本发明的一个实施例，湿法蚀刻所述氧化铟锡层使用的蚀刻液为盐酸和氯化铁混合 溶液。
根据本发明的一个实施例，在所述步骤(a)中，进一步层叠所述电流阻挡层于所述N型半导体层的被暴露在所述半导体裸露部的表面，从而在所述步骤(c)中，所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
依本发明的另一个方面，本发明进一步提供一发光二极管的半导体芯片，其包括：
一外延单元，其中所述外延单元包括依次层叠的一衬底、一N型半导体层、一有源区和一P型半导体层以及具有自所述P型半导体层经所述有源区延伸至所述N型半导体层的至少一半导体裸露部；
至少一电流阻挡层，其中所述电流阻挡层层叠于所述P型半导体层；
一透明导电层，其中所述透明导电层具有至少一列穿孔，其中所述透明导电层以包覆所述电流阻挡层的方式层叠于所述P型半导体层，所述透明导电层的所述穿孔对应于所述电流阻挡层，并且一列所述穿孔中的至少一个所述穿孔与相邻所述穿孔不同；以及
一电极组，其中所述电极组包括层叠于所述N型半导体层的一N型电极和层叠于所述透明导电层的一P型电极，其中所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少一P型电极扩展条，其中所述P型电极扩展条具有一列P型叉指，其中所述P型叉指形成于和被保持在所述透明导电层的所述穿孔。
根据本发明的一个实施例，所述N型电极进一步包括至少一N型电极扩展条，其中所述N型电极扩展条自所述N型电极焊盘向所述半导体芯片的第二端部方向延伸。
根据本发明的一个实施例，一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐增大。
根据本发明的一个实施例，一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐减小。
根据本发明的一个实施例，一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
根据本发明的一个实施例，一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
根据本发明的一个实施例，所述N型电极包括一个所述N型电极扩展条，所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括两个所述P型电极扩展条，两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所述N型电极扩展条被保持在两个所述P型电极扩展条之间。
根据本发明的一个实施例，所述N型电极包括两个所述N型电极扩展条，两个所述N 型电极扩展条裸露部在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括三个所述P型电极扩展条，分别为一第一P型电极扩展条、一第二P型电极扩展条以及一第三P型电极扩展条，所述第一P型电极扩展条和所述第三P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述N型电极扩展条被保持在所述第一P型电极扩展条和所述第二P型电极扩展条之间，另一个所述N型电极扩展条被保持在所述第二P型电极扩展条和所述第三P型电极扩展条之间。
根据本发明的一个实施例，所述N型电极包括两个所述N型电极扩展条，两个所述N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括一个所述P型电极扩展条，所述P型电极扩展条在所述半导体芯片的中部沿着所述P型电极的长度方向延伸，其中所述P型电极扩展条被保持在两个所述N型电极扩展条之间。
根据本发明的一个实施例，所述N型电极包括三个所述N型电极扩展条，分别为一第一N型电极扩展条、一第二N型电极扩展条以及一第三N型电极扩展条，所述第一N型电极扩展条和所述第三N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括两个所述P型电极扩展条，两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方形延伸，其中一个所述P型电极扩展条被保持在所述第一N型电极扩展条和所述第二N型电极扩展条之间，另一个所述P型电极扩展条被保持在所述第二N型电极扩展条和所述第三N型电极扩展条之间。
根据本发明的一个实施例，所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
根据本发明的一个实施例，层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
根据本发明的一个实施例，层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
根据本发明的一个实施例，所述半导体芯片进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
附图说明
图1A是依本发明的第一较佳实施例的一半导体芯片的制造步骤之一的剖视示意图。
图1B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之一的俯视示意图。
图2A是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之二的剖视示意图。
图2B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之二的俯视示意图。
图3A是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之三的剖视示意图。
图3B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之三的俯视示意图。
图4A是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之四的剖视示意图。
图4B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之四的俯视示意图。
图5A是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之五的剖视示意图，其示出了所述半导体芯片的剖视状态。
图5B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤之五的俯视示意图，其示出了所述半导体芯片的俯视状态。
图6是依本发明的上述较佳实施例的所述半导体芯片的一个变形实施方式的制造步骤示意图。
图7是依本发明的上述较佳实施例的所述半导体芯片的另一个变形实施方式的制造步骤示意图。
图8是依本发明的上述较佳实施例的所述半导体芯片的再一个变形实施方式的制造步骤示意图。
图9是依本发明的上述较佳实施例的所述半导体芯片的再一个变形实施方式的制造步骤示意图。
图10A是依本发明的第二较佳实施例的一半导体芯片的制造步骤的俯视示意图。
图10B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图11A是依本发明的第三较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图11B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图12A是依本发明的第四较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图12B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图13A是依本发明的第五较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图13B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图14A是依本发明的第六较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图14B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图15A是依本发明的第七较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图15B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图16A是依本发明的第八较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图16B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图17A是依本发明的第九较佳实施例的一半导体芯片的制造步骤的剖视示意图。
图17B是依本发明的上述较佳实施例的所述半导体芯片的制造步骤的剖视示意图。
图18是依本发明的第十较佳实施例的所述半导体芯片的制造步骤示意图。
图19是依本发明的第十一较佳实施例的所述半导体芯片的制造步骤示意图。
图20是依本发明的第十二较佳实施例的所述半导体芯片的制造步骤示意图。
图21是依本发明的第十三较佳实施例的所述半导体芯片的制造步骤示意图。
具体实施方式
以下描述用于揭露本发明以使本领域技术人员能够实现本发明。以下描述中的优选实施例只作为举例，本领域技术人员可以想到其他显而易见的变型。在以下描述中界定的本发明的基本原理可以应用于其他实施方案、变形方案、改进方案、等同方案以及没有背离本发明的精神和范围的其他技术方案。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
参考本发明的说明书附图之附图1A至图5B，依本发明的一较佳实施例的一发光二极管的半导体芯片在接下来的描述中被揭露和被阐述，其中所述半导体芯片包括一外延单元10、至少一电流阻挡层20、一透明导电层30以及一电极组40。
具体地说，所述外延单元10包括一衬底11、一N型半导体层12、一有源区13以及一P型半导体层14，其中所述N型半导体层12自所述衬底11生长，以使所述N型半导体层12层叠于所述衬底11，其中所述有源区13自所述N型半导体层12生长，以使所述有源区13层叠于所述N型半导体层12，其中所述P型半导体层14自所述有源区13生长，以使所述P型半导体层14层叠于所述有源区13。
值得一提的是，所述外延单元10的所述衬底11的类型在本发明的所述半导体芯片中不受限制，例如所述衬底11可以是但不限于蓝宝石衬底、硅衬底等。另外，所述N型半导体层12和所述P型半导体层14的类型在本发明的所述半导体芯片中也可以不受限制，比如所述N型半导体层12可以是N型氮化镓层，相应地，所述P型半导体层14可以是P型氮化镓层。
参考附图1A和图1B，所述外延单元10具有至少一半导体裸露部15，其中所述半导体裸露部15自所述P型半导体层14经所述有源区13延伸至所述N型半导体层12，以暴露所述N型半导体层12。也就是说，所述N型半导体层12的一部分表面被暴露在所述半导体裸露部15。
在本发明的所述半导体芯片中，首先，可以利用金属有机化合物化学气相沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)自所述衬底11依次生长所述N型半导体层12、所述有源区13和所述P型半导体层14，得到依次层叠的所述衬底11、所述N型半导体层12、所述有源区13和所述P型半导体层14。其次，使用光刻胶制作Mesa图形。然后，使用感应耦合等离子体(Inductively Coupled Plasma，ICP)依次对所述P型半导体层14和所述有源区13进行干法蚀刻，以形成自所述P型半导体层14经所述有源区13延伸至所述N型半导体层12的所述半导体裸露部15，并且使得所述N型半导体层12暴露在所述 半导体裸露部15。
在本发明的所述半导体芯片的另一个较佳示例中，可以使用感应耦合等离体子进一步蚀刻所述N型半导体层12，以形成自所述P型半导体层14经所述有源区13延伸至所述N型半导体层12的所述半导体裸露部15，并且使得所述N型半导体层12暴露在所述半导体裸露部15。也就是说，在本发明的所述半导体芯片的这个较佳示例中，所述N型半导体层12的对应于所述半导体裸露部15的厚度尺寸小于所述N型半导体层12的其他部分的厚度尺寸。
优选地，所述外延单元10的所述半导体裸露部15的深度尺寸范围为0.7μm至3μm(包括0.7μm和3μm)。在使用感应耦合等离子体对所述P型半导体层14、所述有源区13和所述N型半导体层12进行干法蚀刻时使用的气体为Cl2(氯气)、BCl3(三氯化硼)和Ar(氩气)。在使用感应耦合等离子体对所述P型半导体层14、所述有源区13和所述N型半导体层12进行干法蚀刻而形成所述半导体裸露部15后，去除所述光刻胶，以得到所述外延单元10。去除所述光刻胶的方式在本发明的所述半导体芯片中不受限制，例如可以通过但不限于去胶液去胶的方式去除所述光刻胶。
进一步地，参考附图1A至图5B，所述半导体芯片具有一第一端部101和对应于所述第一端部101的一第二端部102。继续参考附图1A和图1B，所述半导体裸露部15具有一N型电极焊盘裸露部151和两N型电极扩展条裸露部152，其中所述半导体裸露部15的所述N型电极焊盘裸露部151形成于所述半导体芯片的所述第二端部102，所述半导体裸露部15的两个所述N型电极扩展条裸露部152以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151向所述半导体芯片的所述第一端部101方向延伸。所述半导体裸露部15的两个所述N型电极扩展条裸露部152分别连通所述N型电极焊盘裸露部151。
可以理解的是，所述半导体裸露部15的所述N型电极焊盘裸露部151和两个所述N型电极扩展条裸露部152藉由同一道蚀刻工艺形成，并且所述半导体裸露部15的所述N型电极焊盘裸露部151和两个所述N型电极扩展条裸露部152均自所述P型半导体层14经所述有源区13延伸至所述N型半导体层12，以暴露所述N型半导体层12的一部分表面于所述半导体裸露部15的所述N型电极焊盘裸露部151和两个所述N型电极扩展条裸露部152。
参考附图2A和图2B，在所述外延单元10的所述P型半导体层14层叠至少一个所述电流阻挡层20。优选地，所述电流阻挡层20的数量为三个，并且三个所述电流阻挡层20均呈条带状，其中这三个所述电流阻挡层20依次被定义为一第一电流阻挡层20a、一第二电流阻挡层20b以及一第三电流阻挡层20c，其中所述第一电流阻挡层20a、所述第二电流阻挡层20b和所述第三电流阻挡层20c分别沿着所述半导体芯片的长度方向从所述半导体芯片的所述第一端部101向所述第二端部102方向延伸。
所述半导体裸露部15的一个所述N型电极扩展条裸露部152被保持在所述第一电流阻挡层20a和所述第二电流阻挡层20b之间，所述半导体裸露部15的另一个所述N型电极扩展条裸露部152被保持在所述第二电流阻挡层20b和所述第三电流阻挡层20c之间。优选地，所述第一电流阻挡层20a和所述第三电流阻挡层20c以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端 部102方向延伸，所述第二电流阻挡层20b以被保持在所述第一电流阻挡层20a和所述第三电流阻挡层20c之间的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端部102方向延伸。
层叠所述电流阻挡层20于所述外延单元10的所述P型半导体层14的方式在本发明的所述半导体芯片中不受限制。例如，在本发明的所述半导体芯片的一个具体示例中，首先，利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉淀一层SiO2(二氧化硅)于所述外延单元10的所述P型半导体层14，SiO2的厚度范围为500埃至10000埃(包括500埃和10000埃)，使用的反应气体为SiH4(硅烷)、N2O(一氧化二氮)以及N2(氮气)。其次，使用正胶光刻出所述电流阻挡层20的结构，其中所述光刻胶的厚度范围为0.5μm至5μm(包括0.5μm和5μm)。接着，使用湿法蚀刻的方式蚀刻SiO2以制作所述电流阻挡层20的图形，其中蚀刻液为氢氟酸和氟化铵内的混合溶液。最后，在蚀刻完成后去除所述光刻胶，以形成层叠于所述外延单元10的所述P型半导体层14的所述电流阻挡层20。
优选地，所述电流阻挡层20也可以层叠于所述外延单元10的所述N型半导体层12。例如，参考附图2B，所述电流阻挡层20可以形成于所述半导体裸露部15的所述N型电极扩展条裸露部152，以使得所述电流阻挡层20层叠于所述外延单元10的所述N型半导体层12。更优选地，相邻所述电流阻挡层20相互间隔，并且这些所述电流阻挡层20以相互间隔和呈条带状的方式沿着所述半导体裸露部15的所述N型电极扩展条裸露部152的延伸方向延伸。
值得一提的是，尽管在附图2B示出的所述半导体芯片的这个较佳示例中以层叠于所述外延单元10的所述N型半导体层12的所述电流阻挡层20的数量为多个且相邻所述电流阻挡层20之间具有间隔缝隙为例来揭露和阐述本发明的所述半导体芯片的内容和特征，但本领域技术人员应当理解的是，附图2B示出的所述半导体芯片仅为示例，其不应被视为对本发明的所述半导体芯片的内容和范围的限制，即，在所述半导体芯片的其他可能的示例中，层叠于所述N型半导体层12的所述电流阻挡层20的数量可以是一个，并且所述电流阻挡层20呈条带状，以使所述电流阻挡层20的延伸方向和延伸长度与所述半导体裸露部15的所述N型电极扩展条裸露部152的延伸方向和延伸长度一致。
参考附图3A和图3B，首先，沉积一层氧化铟锡层(Indium Tin Oxides，ITO)于所述外延单元10的所述P型半导体层14，其中所述氧化铟锡层电连接于所述P型半导体层14。其次，对所述氧化铟锡层进行合金处理。优选地，对所述氧化铟锡层进行合金处理的方式在本发明的所述半导体芯片中不受限制，例如可以使用快速退火炉或者合金炉管对所述氧化铟锡进行合金处理。接着，利用正胶对所述氧化铟锡层进行图形光刻，在光刻完成后利用湿法蚀刻的方式蚀刻所述氧化铟锡层，以在蚀刻完成和去除所述光刻胶后得到所述透明导电层30，其中所述透明导电层30具有至少一穿孔31，所述透明导电层30的这些所述穿孔31分别对应层叠于所述P型半导体层14的所述电流阻挡层20的不同位置，以使所述电流阻挡层20被暴露在所述透明导电层30的所述穿孔31。优选地，在利用湿法蚀刻的方式蚀刻所述氧化铟锡层时使用的蚀刻溶液为盐酸和氯化铁的混合溶液。
优选地，所述透明导电层30具有三列所述穿孔31，其中所述透明导电层30的一列所 述穿孔31分别对应于所述第一电流阻挡层20a的不同位置，所述透明导电层30的另一列所述穿孔31分别对应于所述第二电流阻挡层20b的不同位置，所述透明导电层30的再一列所述穿孔31分别对应于所述第三电流阻挡层20c的不同位置。
参考附图4A和图4B，首先，在所述透明导电层30的表面利用负胶光刻出所述电极组40的一N型电极41的图形和一P型电极42的图形。其次，利用蒸镀或溅镀的方式沉积金属电极层。接着，采用剥离的方式去除多余的金属层和去除残余的光刻胶，以形成所述电极组40的所述N型电极41和所述P型电极42。
具体地说，所述N型电极41包括一N型电极焊盘411和电连接于所述N型电极焊盘411的两N型电极扩展条412，其中所述N型电极41的所述N型电极焊盘411形成于所述外延单元10的所述半导体裸露部15的所述N型电极焊盘裸露部151，以使的所述N型电极焊盘411层叠于和电连接于所述外延单元10的所述N型半导体层12，其中所述N型电极41的所述N型电极扩展条412形成于所述外延单元10的所述半导体裸露部15的所述N型电极扩展条裸露部152，以使所述N型电极扩展条412层叠于和电连接于所述外延单元10的所述N型半导体层12。可以理解的是，所述N型电极扩展条412填充在层叠于所述N型半导体层12的相邻所述电流阻挡层20之间的间隔缝隙。优选地，两个所述N型电极扩展条412以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411向所述半导体芯片的所述第一端部101方向延伸。
相应地，所述P型电极42包括一P型电极焊盘421和电连接于所述P型电极焊盘421的三P型电极扩展条422，其中一条所述P型电极扩展条422被定义为一第一P型电极扩展条422a，另一条所述P型电极扩展条422被定义为一第二P型电极扩展条422b，再一条所述P型电极扩展条423被定义为一第三P型电极扩展条422c。所述P型电极42的所述P型电极焊盘421和每条所述P型电极扩展条422均层叠于所述透明导电层30，其中所述P型电极42的所述P型电极焊盘421形成于所述半导体芯片的所述第一端部101，所述P型电极42的每条所述P型电极扩展条422分别沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述第二端部102方向延伸。在所述半导体芯片的高度方向，所述P型电极42的所述第一P型电极扩展条422a与所述第一电流阻挡层20a相互重合，从而使得所述第一P型电极扩展条422a的P型叉指4220形成于和被保持在所述透明导电层30的每个所述穿孔31；所述P型电极42的所述第二P型电极扩展条422b与所述第二电流阻挡层20b相互重合，从而使得所述第二P型电极扩展条422b的所述P型叉指4220指形成于和被保持在所述透明导电层30的每个所述穿孔31；所述P型电极42的所述第三P型电极扩展条422c与所述第三电流阻挡层20c相互重合，从而使得所述第一P型电极扩展条422a的所述P型叉指4220形成于和被保持在所述透明导电层30的每个所述穿孔31。
也就是说，所述P型电极42的所述第一P型电极扩展条422a和所述第三P型电极扩展条422c以相互对称的方式分别在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸，所述P型电极42的所述第二P型电极扩展条422b在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸。所述N型电极41的一个所述N型电极扩展条412被保持在所述P型电极42的所述第一P型电极扩展 条422a和所述第二P型电极扩展条422b之间，另一个所述N型电极扩展条412被保持在所述第二P型电极扩展条422b和所述第三P型电极扩展条422c之间。
优选地，所述半导体芯片进一步包括一钝化层50，其中所述钝化层50层叠于所述外延单元10的所述P型半导体层14，并且所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，其中所述钝化层50具有至少一第一通孔51和至少一第二通孔52，其中所述钝化层50的所述第一通孔51对应于所述电极组40的所述N型电极41的所述N型电极焊盘411，以使所述N型电极焊盘411被暴露在所述第一通孔41，相应地，所述钝化层50的所述第二通孔52对应于所述电极组40的所述P型电极42的所述P型电极焊盘421，以使所述P型电极焊盘421被暴露在所述第二通孔42。
具体地说，参考附图5A和图5B，首先，利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉淀一层SiO2(二氧化硅)于所述外延单元10的所述P型半导体层14，SiO2的厚度范围为500埃至10000埃(包括500埃和10000埃)，使用的反应气体为SiH4(硅烷)、N2O(一氧化二氮)以及N2(氮气)。其次，使用正胶光刻出所述钝化层30的结构。接着，使用湿法蚀刻的方式蚀刻SiO2以制作所述钝化层30的图形，其中蚀刻液为氢氟酸和氟化铵内的混合溶液。最后，在蚀刻完成后去除所述光刻胶，以形成层叠于所述外延单元10的所述P型半导体层14的所述钝化层50，并且所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，并且所述钝化层50的所述第一通孔51对应于所述电极组40的所述N型电极41的所述N型电极焊盘411，和所述第二通孔52对应于所述电极组40的所述P型电极42的所述P型电极焊盘421。
外部电源能够经所述钝化层50的所述第一通孔51和所述第二通孔52分别提供给所述电极组40的所述N型电极41和所述P型电极42。电流能够经所述N型电极41的所述N型电极焊盘411和所述N型电极扩展条412注入所述外延单元10的所述N型半导体层12，其中在所述N型电极扩展条412和所述N型半导体层12之间被保持有所述电流阻挡层20，其中所述电流阻挡层20能够防止电流集中在所述N型电极扩展条412的下部，以使得电流能够向四周均匀地注入至所述N型半导体层12。相应地，电流能够经所述P型电极42的所述P型电极焊盘421和每条所述P型电极扩展条422注入所述透明导电层30，因为每条所述P型电极扩展条422层叠于所述透明导电层30和每条所述P型电极扩展条422的所述P型叉指4220分别被保持在所述透明导电层30的这些所述穿孔31，从而电流能够自所述透明导电层30的表面和内部经所述P型电极扩展条422均匀地注入所述透明导电层30，又因为在所述透明导电层30和所述P型半导体层14之间保持有所述电流阻挡层20，从而所述电流阻挡层20能够防止电流集中在所述P型电极扩展条422的下部，以使得电流能够向四周均匀地注入至所述P型半导体层14。被均匀地注入所述N型半导体层12的电流和被均匀地注入所述P型半导体层14的电流能够在所述有源区13复合而产生光线，并且这样的方式使得所述半导体芯片的亮度能够被有效地提升。
附图6示出了所述半导体芯片的一个变形实施方式，与附图1A至图5B示出的所述半导体芯片不同的是，在附图6示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15具有一个所述N型电极焊盘裸露部151和一个所述N型电极扩展条裸露部152，其中所 述N型电极焊盘裸露部151形成于所述半导体芯片的所述第二端部102，所述N型电极扩展条裸露部152在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151向所述半导体芯片的所述第一端部101方向延伸。
相应地，在后续所述N型电极41成型后，所述N型电极41包括一个层叠于所述N型半导体层12且被保持在所述N型电极焊盘裸露部151的所述N型电极焊盘411和一个层叠于所述N型半导体层12且被保持在所述N型电极扩展条裸露部152的所述N型电极扩展条412，其中所述N型电极扩展条412在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411向所述半导体芯片的所述第一端部101方向延伸。
参考附图6，所述电流阻挡层20的数量是两个，其中两个所述电流阻挡层20以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端部102方向延伸。在后续，以包覆所述电流阻挡层20的方式层叠所述透明导电层30于所述P型半导体层14，并且所述透明导电层30的所述穿孔31分别对应于所述电流阻挡层20。相应地，所述透明导电层30具有两列所述穿孔31，其中每列所述穿孔31分别对应于每个所述电流阻挡层20的不同位置。
相应地，在后续所述P型电极42成型后，所述P型电极42包括一个层叠于所述透明导电层30的所述P型电极焊盘421和两个所述P型电极扩展条422，其中所述P型电极焊盘421形成于所述半导体芯片的所述第一端部101，其中每个所述P型电极扩展条422分别以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸，并且每个所述P型电极扩展条422的所述P型叉指4220分别形成于和被保持在所述透明导电层30的每个所述穿孔31。参考附图6，所述N型电极41的所述N型电极扩展条412被保持在所述P型电极42的两个所述P型电极扩展条422之间。
继续参考附图6，层叠所述钝化层50于所述外延单元10的所述P型半导体层14，并且所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，其中所述钝化层50的所述第一通孔51对应于所述N型电极41，以使所述N型电极41被暴露在所述钝化层50的所述第一通孔51，所述钝化层50的所述第二通孔52对应于所述P型电极42，以使所述P型电极42被暴露在所述钝化层50的所述第二通孔52。
附图7示出了所述半导体芯片的另一个变形实施方式，与附图1A至图5B示出的所述半导体芯片不同的是，在附图7示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15具有一个所述N型电极焊盘裸露部151和三个所述N型电极扩展条裸露部152，其中所述N型电极焊盘裸露部151形成于所述半导体芯片的所述第二端部102，其中三个所述N型电极扩展条裸露部152分别被定义为一第一扩展条裸露部152a、一第二扩展条裸露部152b以及一第三扩展条裸露部152c，其中所述第一扩展条裸露部152a和所述第三扩展条裸露部152c以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151向所述半导体芯片的所述第一端部101方向延伸，所述第二扩展条裸露部152b在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151向所述半导体芯片的所述第一端部101方向延伸。
相应地，在后续所述N型电极41成型后，所述N型电极41包括一个所述N型电极焊 盘411和三个所述N型电极扩展条412，其中所述N型电极焊盘411层叠于所述N型半导体层12和被保持在所述N型电极焊盘裸露部151，其中三个所述N型电极扩展条412被定义为一第一N型电极扩展条412a、一第二N型电极扩展条412b以及一第三N型电极扩展条412c，其中所述第一N型电极扩展条412a、所述第二N型电极扩展条412b和所述第三N型电极扩展条412c分别层叠于所述N型半导体层12和分别被保持在所述第一扩展条裸露部152a、所述第二扩展条裸露部152b和所述第三扩展条裸露部152c，从而使得所述第一N型电极扩展条412a和所述第三N型电极扩展条412c以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘411向所述半导体芯片的所述第一端部101方向延伸，所述第二N型电极扩展条412b在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411向所述半导体芯片的所述第一端部101方向延伸。
参考附图7，所述电流阻挡层20的数量是两个，其中两个所述电流阻挡层20以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端部102方向延伸。在后续，以包覆所述电流阻挡层20的方式层叠所述透明导电层30于所述P型半导体层14，并且所述透明导电层30的所述穿孔31分别对应于所述电流阻挡层20。相应地，所述透明导电层30具有两列所述穿孔31，其中每列所述穿孔31分别对应于每个所述电流阻挡层20。
相应地，在后续所述P型电极42成型后，所述P型电极42包括一个层叠于所述透明导电层30的所述P型电极焊盘421和两个所述P型电极扩展条422，其中每个所述P型电极扩展条422分别以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸，并且每个所述P型电极扩展条422的所述P型叉指4220分别形成于和被保持在所述透明导电层30的每个所述穿孔31。参考附图7，所述P型电极42的一个所述P型电极扩展条422被保持在所述第一N型电极扩展条412a和所述第二N型电极扩展条412b之间，另一个所述P型电极扩展条422被保持在所述第二N型电极扩展条412b和所述第三N型电极扩展条412c之间。
继续参考附图7，层叠所述钝化层50于所述外延单元10的所述P型半导体层14，并且所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，其中所述钝化层50的所述第一通孔51对应于所述N型电极41，以使所述N型电极41被暴露在所述钝化层50的所述第一通孔51，所述钝化层50的所述第二通孔52对应于所述P型电极42，以使所述P型电极42被暴露在所述钝化层50的所述第二通孔52。
附图8示出了所述半导体芯片的另一个变形实施方式，与附图7示出的所述半导体芯片不同的是，在附图8示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15具有一个所述N型电极焊盘裸露部151和两个所述N型电极扩展条裸露部152，其中所述N型电极焊盘裸露部151形成于所述半导体芯片的所述第二端部102，两个所述N型电极扩展条裸露部152以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151向所述半导体芯片的所述第一端部101方向延伸。
相应地，在后续所述N型电极41成型后，所述N型电极41包括一个所述N型电极焊 盘411和两个所述N型电极扩展条412，其中所述N型电极焊盘411层叠于所述N型半导体层12和被保持在所述N型电极焊盘裸露部151，其中每个所述N型电极扩展条412分别层叠于所述N型半导体层12和被保持在每个所述N型电极扩展条裸露部152，从而使得每个所述N型电极扩展条412以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘411向所述半导体芯片的所述第一端部101方向延伸。
参考附图8，所述电流阻挡层20的数量是一个，其中所述电流阻挡层20在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端部102方向延伸。在后续，以包覆所述电流阻挡层20的方式层叠所述透明导电层30于所述P型半导体层14，并且所述透明导电层30的所述穿孔31对应于所述电流阻挡层20。
相应地，在后续所述P型电极42成型后，所述P型电极42包括一个层叠于所述透明导电层30的所述P型电极焊盘421和一个所述P型电极扩展条422，其中所述P型电极焊盘421形成于所述半导体芯片的所述第一端部101，所述P型电极扩展条421在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸，并且所述P型电极扩展条422的所述P型叉指4220形成于和被保持在所述透明导电层30的所述穿孔31。参考附图8，所述P型电极42的所述P型电极扩展条422被保持在所述N型电极41的两个所述N型电极扩展条412之间。
继续参考附图8，层叠所述钝化层50于所述外延单元10的所述P型半导体层14，并且所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，其中所述钝化层50的所述第一通孔51对应于所述N型电极41，以使所述N型电极41被暴露在所述钝化层50的所述第一通孔51，所述钝化层50的所述第二通孔52对应于所述P型电极42，以使所述P型电极42被暴露在所述钝化层50的所述第二通孔52。
附图9示出了所述半导体芯片的另一个变形实施方式，与附图8示出的所述半导体芯片不同的是，在附图9示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15仅具有一个所述N型电极焊盘裸露部151，其形成在所述半导体芯片的所述第二端部102。相应地，在后续所述N型电极41成型后，所述N型电极41仅包括一个所述N型电极焊盘411，其中所述N型电极焊盘411层叠于所述N型半导体层12和被保持在所述N型电极焊盘裸露部151。
参考附图9，所述电流阻挡层20的数量是一个，其中所述电流阻挡层20在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101向所述第二端部102方向延伸，在后续，以包覆所述电流阻挡层20的方式层叠所述透明导电层30于所述P型半导体层14，并且所述透明导电层30的所述穿孔31对应于所述电流阻挡层20。
相应地，在后续所述P型电极42成型后，所述P型电极42包括一个层叠于所述透明导电层30的所述P型电极焊盘421和一个所述P型电极扩展条422，其中所述P型电极焊盘421形成于所述半导体芯片的所述第一端部101，所述P型电极扩展条421在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421向所述半导体芯片的所述第二端部102方向延伸，并且所述P型电极扩展条422的所述P型叉指4220形成于和被保持在所述透明导电层30的所述穿孔31。
继续参考附图9，层叠所述钝化层50于所述外延单元10的所述P型半导体层14，并且 所述钝化层50包覆所述透明导电层30以及所述电极组40的所述N型电极41和所述P型电极42，其中所述钝化层50的所述第一通孔51对应于所述N型电极41，以使所述N型电极41被暴露在所述钝化层50的所述第一通孔51，所述钝化层50的所述第二通孔52对应于所述P型电极42，以使所述P型电极42被暴露在所述钝化层50的所述第二通孔52。
依本发明的另一个方面，本发明进一步提供所述半导体芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠所述电流阻挡层20于所述外延单元10的所述P型半导体层14；
(b)以包覆所述电流阻挡层20的方式层叠所述透明导电层30于所述P型半导体层14，其中所述透明导电层30具有至少一个所述穿孔31，以对应于所述电流阻挡层20；以及
(c)以所述N型电极41被保持在所述外延单元10的所述半导体裸露部15的方式层叠所述N型电极41于所述外延单元10的所述N型半导体层12，和以所述P型电极42的所述P型叉指4220形成于所述透明导电层30的所述穿孔31的方式层叠所述P型电极42于所述透明导电层30，以制得所述半导体芯片。
进一步地，所述制造方法包括步骤：
(d)以包覆所述N型电极41和所述P型电极42的方式层叠所述钝化层50于所述透明导电层30和所述P型半导体层14，其中所述钝化层50具有对应于所述N型电极41的所述第一通道51和对应于所述P型电极52的所述第二通道42。
值得注意的是，在本发明的附图中示出的所述半导体芯片的所述衬底11、所述N型半导体层12、所述有源区13、所述第二半导体层14、所述电流阻挡层20、所述透明导电层30、所述N型电极41和所述P型电极42的厚度仅为示例，其并不表示所述衬底11、所述N型半导体层12、所述有源区13、所述第二半导体层14、所述电流阻挡层20、所述透明导电层30、所述N型电极41和所述P型电极42的真实厚度。并且，所述衬底11、所述N型半导体层12、所述有源区13、所述第二半导体层14、所述电流阻挡层20、所述透明导电层30、所述N型电极41和所述P型电极42之间的真实比例也并不像附图中示出的那样。另外，所述电极组40的所述N型电极41和所述P型电极42的尺寸与所述半导体芯片的其他层的尺寸比例也不受限于附图中示出的那样。
参考本发明的说明书附图之附图10A和图10B，依本发明的另一较佳实施例的一发光二极管的半导体芯片在接下来的描述中被揭露和被阐述，其中所述半导体芯片包括一外延单元10’、至少一电流阻挡层20’、一透明导电层30’以及一电极组40’。
具体地说，所述外延单元10’包括一衬底11’、一N型半导体层12’、一有源区13’以及一P型半导体层14’，其中所述N型半导体层12’自所述衬底11’生长，以使所述N型半导体层12’层叠于所述衬底11’，其中所述有源区13’自所述N型半导体层12’生长，以使所述有源区13’层叠于所述N型半导体层12’，其中所述P型半导体层14’自所述有源区13’生长，以使所述P型半导体层14’层叠于所述有源区13’。
值得一提的是，所述外延单元10’的所述衬底11’的类型在本发明的所述半导体芯片中不受限制，例如所述衬底11’可以是但不限于蓝宝石衬底、硅衬底等。另外，所述N型半导体层12’和所述P型半导体层14’的类型在本发明的所述半导体芯片中也可以不受限制，比如所述N型半导体层12’可以是N型氮化镓层，相应地，所述P型半导体层14’可 以是P型氮化镓层。
参考附图10A和图10B，所述外延单元10’具有至少一半导体裸露部15’，其中所述半导体裸露部15’自所述P型半导体层14’经所述有源区13’延伸至所述N型半导体层12’，以暴露所述N型半导体层12’。也就是说，所述N型半导体层12’的一部分表面被暴露在所述半导体裸露部15’。
在本发明的所述半导体芯片中，首先，可以利用金属有机化合物化学气相沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)自所述衬底11’依次生长所述N型半导体层12’、所述有源区13’和所述P型半导体层14’，得到依次层叠的所述衬底11’、所述N型半导体层12’、所述有源区13’和所述P型半导体层14’。其次，使用光刻胶制作Mesa图形。然后，使用感应耦合等离子体(Inductively Coupled Plasma，ICP)依次对所述P型半导体层14’和所述有源区13’进行干法蚀刻，以形成自所述P型半导体层14’经所述有源区13’延伸至所述N型半导体层12’的所述半导体裸露部15’，并且使得所述N型半导体层12’暴露在所述半导体裸露部15’。
在本发明的所述半导体芯片的另一个较佳示例中，可以使用感应耦合等离体子进一步蚀刻所述N型半导体层12’，以形成自所述P型半导体层14’经所述有源区13’延伸至所述N型半导体层12’的所述半导体裸露部15’，并且使得所述N型半导体层12’暴露在所述半导体裸露部15’。也就是说，在本发明的所述半导体芯片的这个较佳示例中，所述N型半导体层12’的对应于所述半导体裸露部15’的厚度尺寸小于所述N型半导体层12’的其他部分的厚度尺寸。
优选地，所述外延单元10’的所述半导体裸露部15’的深度尺寸范围为0.7μm至3μm(包括0.7μm和3μm)。在使用感应耦合等离子体对所述P型半导体层14’、所述有源区13’和所述N型半导体层12’进行干法蚀刻时使用的气体为Cl2(氯气)、BCl3(三氯化硼)和Ar(氩气)。在使用感应耦合等离子体对所述P型半导体层14’、所述有源区13’和所述N型半导体层12’进行干法蚀刻而形成所述半导体裸露部15’后，去除所述光刻胶，以得到所述外延单元10’。去除所述光刻胶的方式在本发明的所述半导体芯片中不受限制，例如可以通过但不限于去胶液去胶的方式去除所述光刻胶。
进一步地，参考附图10A和图10B，所述半导体芯片具有一第一端部101’和对应于所述第一端部101’的一第二端部102’。继续参考附图10A和图10B，所述半导体裸露部15’具有一N型电极焊盘裸露部151’和两N型电极扩展条裸露部152’，其中所述半导体裸露部15’的所述N型电极焊盘裸露部151’形成于所述半导体芯片的所述第二端部102’，所述半导体裸露部15’的两个所述N型电极扩展条裸露部152’以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151’向所述半导体芯片的所述第一端部101’方向延伸。所述半导体裸露部15’的两个所述N型电极扩展条裸露部152’分别连通所述N型电极焊盘裸露部151’。
可以理解的是，所述半导体裸露部15’的所述N型电极焊盘裸露部151’和两个所述N型电极扩展条裸露部152’藉由同一道蚀刻工艺形成，并且所述半导体裸露部15’的所述N型电极焊盘裸露部151’和两个所述N型电极扩展条裸露部152’均自所述P型半导体层14’经所述有源区13’延伸至所述N型半导体层12’，以暴露所述N型半导体层12’的一部 分表面于所述半导体裸露部15’的所述N型电极焊盘裸露部151’和两个所述N型电极扩展条裸露部152’。
参考附图10A和图10B，在所述外延单元10’的所述P型半导体层14’层叠至少一个所述电流阻挡层20’。优选地，所述电流阻挡层20’的数量为三个，并且三个所述电流阻挡层20’均呈条带状，其中这三个所述电流阻挡层20’依次被定义为一第一电流阻挡层20a’、一第二电流阻挡层20b’以及一第三电流阻挡层20c’，其中所述第一电流阻挡层20a’、所述第二电流阻挡层20b’和所述第三电流阻挡层20c’分别沿着所述半导体芯片的长度方向从所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。
所述半导体裸露部15’的一个所述N型电极扩展条裸露部152’被保持在所述第一电流阻挡层20a’和所述第二电流阻挡层20b’之间，所述半导体裸露部15’的另一个所述N型电极扩展条裸露部152’被保持在所述第二电流阻挡层20b’和所述第三电流阻挡层20c’之间。优选地，所述第一电流阻挡层20a’和所述第三电流阻挡层20c’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸，所述第二电流阻挡层20b’以被保持在所述第一电流阻挡层20a’和所述第三电流阻挡层20c’之间的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。
层叠所述电流阻挡层20’于所述外延单元10’的所述P型半导体层14’的方式在本发明的所述半导体芯片中不受限制。例如，在本发明的所述半导体芯片的一个具体示例中，首先，利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉淀一层SiO2(二氧化硅)于所述外延单元10’的所述P型半导体层14’，SiO2的厚度范围为500埃至10000埃(包括500埃和10000埃)，使用的反应气体为SiH4(硅烷)、N2O(一氧化二氮)以及N2(氮气)。其次，使用正胶光刻出所述电流阻挡层20’的结构，其中所述光刻胶的厚度范围为0.5μm至5μm(包括0.5μm和5μm)。接着，使用湿法蚀刻的方式蚀刻SiO2以制作所述电流阻挡层20’的图形，其中蚀刻液为氢氟酸和氟化铵内的混合溶液。最后，在蚀刻完成后去除所述光刻胶，以形成层叠于所述外延单元10’的所述P型半导体层14’的所述电流阻挡层20’。
优选地，所述电流阻挡层20’也可以层叠于所述外延单元10’的所述N型半导体层12’。例如，参考附图10A，所述电流阻挡层20’可以形成于所述半导体裸露部15’的所述N型电极扩展条裸露部152’，以使得所述电流阻挡层20’层叠于所述外延单元10’的所述N型半导体层12’。更优选地，层叠于所述N型半导体层12’的相邻所述电流阻挡层20’相互间隔，并且这些所述电流阻挡层20’以相互间隔和呈条带状的方式沿着所述半导体裸露部15’的所述N型电极扩展条裸露部152’的延伸方向延伸。
值得一提的是，尽管在附图10A和图10B示出的所述半导体芯片的这个较佳示例中以层叠于所述外延单元10’的所述N型半导体层12’的所述电流阻挡层20’的数量为多个且相邻所述电流阻挡层20’之间具有间隔缝隙，但本领域技术人员应当理解的是，附图10A和图10B示出的所述半导体芯片仅为示例，即，在所述半导体芯片的其他可能的示例中，层叠于所述N型半导体层12’的所述电流阻挡层20’的数量可以是一个，并且所述电流阻 挡层20’呈条带状，以使所述电流阻挡层20’的延伸方向和延伸长度与所述半导体裸露部15’的所述N型电极扩展条裸露部152’的延伸方向和延伸长度一致。
参考附图10A和图10B，首先，沉积一层氧化铟锡层(Indium Tin Oxides，ITO)于所述外延单元10’的所述P型半导体层14’，其中所述氧化铟锡层电连接于所述P型半导体层14’。其次，对所述氧化铟锡层进行合金处理。优选地，对所述氧化铟锡层进行合金处理的方式在本发明的所述半导体芯片中不受限制，例如可以使用快速退火炉或者合金炉管对所述氧化铟锡进行合金处理。接着，利用正胶对所述氧化铟锡层进行图形光刻，在光刻完成后利用湿法蚀刻的方式蚀刻所述氧化铟锡层，以在蚀刻完成和去除所述光刻胶后得到所述透明导电层30’，其中所述透明导电层30’具有至少一列穿孔31’，其中每列所述所述穿孔31’中的每个所述穿孔31’分别对应于所述电流阻挡层20’的不同位置，以使所述电流阻挡层20’被暴露在所述透明导电层30’的这些所述穿孔31’。优选地，在利用湿法蚀刻的方式蚀刻所述氧化铟锡层时使用的蚀刻溶液为盐酸和氯化铁的混合溶液。
优选地，参考附图10A，所述透明导电层30’具有三列所述穿孔31’，其中所述透明导电层30’的一列所述穿孔31’中的每个所述穿孔31’分别对应于所述第一电流阻挡层20a’的不同位置，所述透明导电层30’的另一列所述穿孔31’中的每个所述穿孔31’分别对应于所述第二电流阻挡层20b’的不同位置，所述透明导电层30’的再一列所述穿孔31’中的每个所述穿孔31’分别对应于所述第三电流阻挡层20c’的不同位置。在附图10A和图10B示出的所述半导体芯片的这个较佳示例中，至少一列所述穿孔31’中的至少一个所述穿孔31’和相邻所述穿孔31’不同，例如，在本发明的所述半导体芯片的这个较佳示例中，至少一列所述穿孔31’中的至少一个所述穿孔31’和相邻所述穿孔31’的尺寸不同。当然，本领域技术人员应当理解的是，在本发明的所述半导体芯片的其他较佳示例中，至少一列所述穿孔31’中的至少一个所述穿孔31’和相邻所述穿孔31’的形状可以不同，或者形状和尺寸均可以不同。
优选地，在附图10A和图10B示出的所述半导体芯片的这个较佳示例中，至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增。也就是说，靠近所述半导体芯片的所述第二端部102’的所述穿孔31’的尺寸大于靠近所述半导体芯片的所述第一端部101’的所述穿孔31’的尺寸。
参考附图10A和图10B，首先，在所述透明导电层30’的表面利用负胶光刻出所述电极组40’的一N型电极41’的图形和一P型电极42’的图形。其次，利用蒸镀或溅镀的方式沉积金属电极层。接着，采用剥离的方式去除多余的金属层和去除残余的光刻胶，以形成所述电极组40’的所述N型电极41’和所述P型电极42’。
具体地说，所述N型电极41’包括一N型电极焊盘411’和电连接于所述N型电极焊盘411’的两N型电极扩展条412’，其中所述N型电极41’的所述N型电极焊盘411’形成于所述外延单元10’的所述半导体裸露部15’的所述N型电极焊盘裸露部151’，以使的所述N型电极焊盘411’层叠于和电连接于所述外延单元10’的所述N型半导体层12’，其中所述N型电极41’的所述N型电极扩展条412’形成于所述外延单元10’的所述半导体裸露部15’的所述N型电极扩展条裸露部152’，以使所述N型电极扩展条412’层叠于和电连接于所述外延单元10’的所述N型半导体层12’。可以理解的是，所述N型电极 扩展条412’填充在层叠于所述N型半导体层12’的相邻所述电流阻挡层20’之间的间隔缝隙。优选地，两个所述N型电极扩展条412’以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411’向所述半导体芯片的所述第一端部101’方向延伸。
相应地，所述P型电极42’包括一P型电极焊盘421’和电连接于所述P型电极焊盘421’的三P型电极扩展条422’，其中一条所述P型电极扩展条422’被定义为一第一P型电极扩展条422a’，另一条所述P型电极扩展条422’被定义为一第二P型电极扩展条422b’，再一条所述P型电极扩展条422’被定义为一第三P型电极扩展条422c’。所述P型电极42’的所述P型电极焊盘421’和每条所述P型电极扩展条422’均层叠于所述透明导电层30’，其中所述P型电极42’的所述P型电极焊盘421’形成于所述半导体芯片的所述第一端部101’，所述P型电极42’的每条所述P型电极扩展条422’分别沿着所述半导体芯片的长度方向自所述P型电极焊盘421’从所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。在所述芯片的高度方向，所述P型电极42’的所述第一P型电极扩展条422a’与所述第一电流阻挡层20a’相互重合，从而使得所述第一P型电极扩展条422a’的P型叉指4220’形成于和被保持在所述透明导电层30’的每个所述穿孔31’；所述P型电极42’的所述第二P型电极扩展条422b’与所述第二电流阻挡层20b’相互重合，从而使得所述第二P型电极扩展条422b’的所述P型叉指4220’指形成于和被保持在所述透明导电层30’的每个所述穿孔31’；所述P型电极42’的所述第三P型电极扩展条422c’与所述第三电流阻挡层20c’相互重合，从而使得所述第一P型电极扩展条422a’的所述P型叉指4220’形成于和被保持在所述透明导电层30’的每个所述穿孔31’。
也就是说，所述P型电极42’的所述第一P型电极扩展条422a’和所述第三P型电极扩展条422c’以相互对称的方式分别在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸，所述P型电极42’的所述第二P型电极扩展条422b’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸。所述N型电极41’的一个所述N型电极扩展条412’被保持在所述P型电极42’的所述第一P型电极扩展条422a’和所述第二P型电极扩展条422b’之间，另一个所述N型电极扩展条412’被保持在所述第二P型电极扩展条422b’和所述第三P型电极扩展条422c’之间。
所述P型电极42’的每个所述P型电极扩展条422’分别具有一列所述P型叉指4220’，即，所述第一P型电极扩展条422a’具有一列所述P型叉指4220’，所述第二P型电极扩展条422b’具有一列所述P型叉指4220’，所述第三P型电极扩展条422c’具有一列所述P型叉指4220’。
在所述P型电极42’层叠于所述透明导电层30’的过程中，所述P型电极42’的所述第一P型电极扩展条422a’的一列所述P型叉指4220’中的每个所述P型叉指4220’同时形成于和被保持在所述透明导电层30’的一列所述穿孔31’的每个所述穿孔31’，因为所述透明导电层30’的一列所述穿孔31’的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增，从而所述第一P型电极扩展条422a’ 的一列所述P型叉指4220’的每个所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增。也就是说，一列所述P型叉指4220’中靠近所述P型电极焊盘411’的所述P型叉指4220’的尺寸小于远离所述P型电极焊盘411’的所述P型叉指4220’的尺寸，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
在所述P型电极42’层叠于所述透明导电层30’的过程中，所述P型电极42’的所述第二P型电极扩展条422b’的一列所述P型叉指4220’中的每个所述P型叉指4220’同时形成于和被保持在所述透明导电层30’的一列所述穿孔31’的每个所述穿孔31’，因为所述透明导电层30’的一列所述穿孔31’的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增，从而所述第二P型电极扩展条422b’的一列所述P型叉指4220’的每个所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增。也就是说，一列所述P型叉指4220’中靠近所述P型电极焊盘411’的所述P型叉指4220’的尺寸小于远离所述P型电极焊盘411’的所述P型叉指4220’的尺寸，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
在所述P型电极42’层叠于所述透明导电层30’的过程中，所述P型电极42’的所述第三P型电极扩展条422c’的一列所述P型叉指4220’中的每个所述P型叉指4220’同时形成于和被保持在所述透明导电层30’的一列所述穿孔31’的每个所述P型叉指4220’，因为所述透明导电层30’的一列所述穿孔31’的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增，从而所述第三P型电极扩展条422c’的一列所述P型叉指4220’的每个所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递增。也就是说，一列所述P型叉指4220’中靠近所述P型电极焊盘411’的所述P型叉指4220’的尺寸小于远离所述P型电极焊盘411’的所述P型叉指4220’的尺寸，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
优选地，参考附图10A和图10B，所述半导体芯片进一步包括一钝化层50’，其中所述钝化层50’层叠于所述外延单元10’的所述P型半导体层14’，并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，其中所述钝化层50’具有至少一第一通孔51’和至少一第二通孔52’，其中所述钝化层50’的所述第一通孔51’对应于所述电极组40’的所述N型电极41’的所述N型电极焊盘411’，以使所述N型电极焊盘411’被暴露在所述第一通孔51’，相应地，所述钝化层50’的所述第二通孔52’对应于所述电极组40’的所述P型电极42’的所述P型电极焊盘421’，以使所述P型电极焊盘421’被暴露在所述第二通孔52’。
具体地说，参考附图10A和图10B，首先，利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉淀一层SiO2(二氧化硅)于所述外延单元10’的所述P型半导体层14’，SiO2的厚度范围为500埃至10000埃(包括500埃和10000埃)，使用的反应气体为SiH4(硅烷)、N2O(一氧化二氮)以及N2(氮气)。其次，使用正胶光刻出所述钝化层30的结构。接着，使用湿法蚀刻的方式蚀刻SiO2以制作所述钝化层50’的图形，其中蚀刻液为氢氟酸和氟化铵内的混合溶液。最后，在蚀刻完成后去除所述光刻胶，以形成层叠于所述外延单元10’的所述P型半导体层14’的所述钝化层50’， 并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，并且所述钝化层50’的所述第一通孔51’对应于所述电极组40’的所述N型电极41’的所述N型电极焊盘411’，和所述第二通孔52’对应于所述电极组40’的所述P型电极42’的所述P型电极焊盘421’。
外部电源能够经所述钝化层50’的所述第一通孔51’和所述第二通孔52’分别提供给所述电极组40’的所述N型电极41’和所述P型电极42’。电流能够经所述N型电极41’的所述N型电极焊盘411’和所述N型电极扩展条412’注入所述外延单元10’的所述N型半导体层12’，其中在所述N型电极扩展条412’和所述N型半导体层12’之间被保持有所述电流阻挡层20’，其中所述电流阻挡层20’能够防止电流集中在所述N型电极扩展条412’的下部，以使得电流能够向四周均匀地注入至所述N型半导体层12’。相应地，电流能够经所述P型电极42’的所述P型电极焊盘421’和每条所述P型电极扩展条422’注入所述透明导电层30’，因为每条所述P型电极扩展条422’层叠于所述透明导电层30’和每条所述P型电极扩展条422’的所述P型叉指4220’分别被保持在所述透明导电层30’的这些所述穿孔31’，并且每条所述P型电极扩展条422’的所述P型叉指4220’的尺寸从所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’的方向依次增加，从而电流能够自所述透明导电层30’的表面和内部经所述P型电极扩展条422’均匀地注入所述透明导电层30’，又因为在所述透明导电层30’和所述P型半导体层14’之间保持有所述电流阻挡层20’，从而所述电流阻挡层20’能够防止电流集中在所述P型电极扩展条422’的下部，以使得电流能够向四周均匀地注入至所述P型半导体层14’。被均匀地注入所述N型半导体层12’的电流和被均匀地注入所述P型半导体层14’的电流能够在所述有源区13’复合而产生光线，并且这样的方式使得所述半导体芯片的亮度能够被有效地提升。
附图11A和图11B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片中所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’依次递增不同的是，在附图11A和图11B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递减。也就是说，靠近所述半导体芯片的所述第二端部102’的所述穿孔31’的尺寸小于靠近所述半导体芯片的所述第一端部101’的所述穿孔31’的尺寸。
相应地，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’的每个所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向依次递减。也就是说，靠近所述半导体芯片的所述第二端部102’的所述P型叉指4220’的尺寸小于靠近所述半导体芯片的所述第一端部101’的所述P型叉指4220’的尺寸，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图12A和图12B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片中所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’依次递增不同的 是，在附图12A和图12B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’的每个所述穿孔31’的尺寸均相同，并且所述透明导电层30’的至少一列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’中的每个所述P型叉指4220’的尺寸不变，并且所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’中的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图13A和图13B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片中所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’依次递增不同的是，在附图13A和图13B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递减，并且该列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递减，并且该列所述P型叉指4220’的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图14A和图14B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片中所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’依次递增不同的是，在附图14A和图14B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递减，并且该列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递减，并且该列所述P型叉指4220’的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图15A和图15B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片中所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’依次递增不同的是，在附图15A和图15B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’的每个所述穿孔31’的尺寸均相同，并且所述透明导电层30’的 至少一列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’中的每个所述P型叉指4220’的尺寸不变，并且所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’中的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图16A和图16B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片不同的是，在附图16A和图16B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递增，并且该列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递增，并且该列所述P型叉指4220’的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐减小，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图17A和图17B示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片不同的是，在附图17A和图17B示出的所述半导体芯片的这个较佳示例中，所述透明导电层30’的至少一列所述穿孔31’中的每个所述穿孔31’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递增，并且该列所述穿孔31’的相邻两个所述穿孔31’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加。从而，在所述P型电极42’层叠于所述透明导电层30’之后，所述P型电极42’的所述P型电极扩展条422’的一列所述P型叉指4220’的尺寸从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐递增，并且该列所述P型叉指4220’的相邻两个所述P型叉指4220’之间的间距从所述半导体芯片的所述第一端部101’向所述第二端部102’方向逐渐增加，这样的方式有利于电流均匀地分布至所述P型半导体层14’。
附图18示出了所述半导体芯片的一个变形实施方式，与附图10A和图10B示出的所述半导体芯片不同的是，在附图18示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15’具有一个所述N型电极焊盘裸露部151’和一个所述N型电极扩展条裸露部152’，其中所述N型电极焊盘裸露部151’形成于所述半导体芯片的所述第二端部102’，所述N型电极扩展条裸露部152’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151’向所述半导体芯片的所述第一端部101’方向延伸。
相应地，在后续所述N型电极41’成型后，所述N型电极41’包括一个层叠于所述N型半导体层12’且被保持在所述N型电极焊盘裸露部151’的所述N型电极焊盘411’和一个层叠于所述N型半导体层12’且被保持在所述N型电极扩展条裸露部152’的所述N 型电极扩展条412’，其中所述N型电极扩展条412’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411’向所述半导体芯片的所述第一端部101’方向延伸。
参考附图18，所述电流阻挡层20’的数量是两个，其中两个所述电流阻挡层20’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。在后续，以包覆所述电流阻挡层20’的方式层叠所述透明导电层30’于所述P型半导体层14’，并且所述透明导电层30’的每列所述穿孔31’分别对应于所述电流阻挡层20’。相应地，所述透明导电层30’具有两列所述穿孔31’，其中每列所述穿孔31’中的每个所述穿孔31’分别对应于每个所述电流阻挡层20’的不同位置。
相应地，在后续所述P型电极42’成型后，所述P型电极42’包括一个层叠于所述透明导电层30’的所述P型电极焊盘421’和两个所述P型电极扩展条422’，其中所述P型电极焊盘421’形成于所述半导体芯片的所述第一端部101’，其中每个所述P型电极扩展条422’分别以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸，并且每个所述P型电极扩展条422’的所述P型叉指4220’分别形成于和被保持在所述透明导电层30’的每个所述穿孔31’。参考附图18，所述N型电极41’的所述N型电极扩展条412’被保持在所述P型电极42’的两个所述P型电极扩展条422’之间。
继续参考附图18，层叠所述钝化层50’于所述外延单元10’的所述P型半导体层14’，并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，其中所述钝化层50’的所述第一通孔51’对应于所述N型电极41’，以使所述N型电极41’被暴露在所述钝化层50’的所述第一通孔51’，所述钝化层50’的所述第二通孔52’对应于所述P型电极42’，以使所述P型电极42’被暴露在所述钝化层50’的所述第二通孔52’。
附图19示出了所述半导体芯片的另一个变形实施方式，与附图10A和图10B示出的所述半导体芯片不同的是，在附图19示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15’具有一个所述N型电极焊盘裸露部151’和三个所述N型电极扩展条裸露部152’，其中所述N型电极焊盘裸露部151’形成于所述半导体芯片的所述第二端部102’，其中三个所述N型电极扩展条裸露部152’分别被定义为一第一扩展条裸露部152a’、一第二扩展条裸露部152b’以及一第三扩展条裸露部152c’，其中所述第一扩展条裸露部152a’和所述第三扩展条裸露部152c’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151’向所述半导体芯片的所述第一端部101’方向延伸，所述第二扩展条裸露部152b’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151’向所述半导体芯片的所述第一端部101’方向延伸。
相应地，在后续所述N型电极41’成型后，所述N型电极41’包括一个所述N型电极焊盘411’和三个所述N型电极扩展条412’，其中所述N型电极焊盘411’层叠于所述N型半导体层12’和被保持在所述N型电极焊盘裸露部151’，其中三个所述N型电极扩 展条412’被定义为一第一N型电极扩展条412a’、一第二N型电极扩展条412b’以及一第三N型电极扩展条412c’，其中所述第一N型电极扩展条412a’、所述第二N型电极扩展条412b’和所述第三N型电极扩展条412c’分别层叠于所述N型半导体层12’和分别被保持在所述第一扩展条裸露部152a’、所述第二扩展条裸露部152b’和所述第三扩展条裸露部152c’，从而使得所述第一N型电极扩展条412a’和所述第三N型电极扩展条412c’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘411’向所述半导体芯片的所述第一端部101’方向延伸，所述第二N型电极扩展条412b’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述N型电极焊盘411’向所述半导体芯片的所述第一端部101’方向延伸。
参考附图19，所述电流阻挡层20’的数量是两个，其中两个所述电流阻挡层20’以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。在后续，以包覆所述电流阻挡层20’的方式层叠所述透明导电层30’于所述P型半导体层14’，并且所述透明导电层30’的所述穿孔31’分别对应于所述电流阻挡层20’。相应地，所述透明导电层30’具有两列所述穿孔31’，其中每列所述穿孔31’分别对应于每个所述电流阻挡层20’。
相应地，在后续所述P型电极42’成型后，所述P型电极42’包括一个层叠于所述透明导电层30’的所述P型电极焊盘421’和两个所述P型电极扩展条422’，其中每个所述P型电极扩展条422’分别以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸，并且每个所述P型电极扩展条422’的所述P型叉指4220’分别形成于和被保持在所述透明导电层30’的每个所述穿孔31’。参考附图19，所述P型电极42’的一个所述P型电极扩展条422’被保持在所述第一N型电极扩展条412a’和所述第二N型电极扩展条412b’之间，另一个所述P型电极扩展条422’被保持在所述第二N型电极扩展条412b’和所述第三N型电极扩展条412c’之间。
继续参考附图19，层叠所述钝化层50’于所述外延单元10’的所述P型半导体层14’，并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，其中所述钝化层50’的所述第一通孔51’对应于所述N型电极41’，以使所述N型电极41’被暴露在所述钝化层50’的所述第一通孔51’，所述钝化层50’的所述第二通孔52’对应于所述P型电极42’，以使所述P型电极42’被暴露在所述钝化层50’的所述第二通孔52’。
附图20示出了所述半导体芯片的另一个变形实施方式，与附图19示出的所述半导体芯片不同的是，在附图20示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15’具有一个所述N型电极焊盘裸露部151’和两个所述N型电极扩展条裸露部152’，其中所述N型电极焊盘裸露部151’形成于所述半导体芯片的所述第二端部102’，两个所述N型电极扩展条裸露部152’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘裸露部151’向所述半导体芯片的所述第一端部101’方向延伸。
相应地，在后续所述N型电极41’成型后，所述N型电极41’包括一个所述N型电 极焊盘411’和两个所述N型电极扩展条412’，其中所述N型电极焊盘411’层叠于所述N型半导体层12’和被保持在所述N型电极焊盘裸露部151’，其中每个所述N型电极扩展条412’分别层叠于所述N型半导体层12’和被保持在每个所述N型电极扩展条裸露部152’，从而使得每个所述N型电极扩展条412’以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向自所述N型电极焊盘411’向所述半导体芯片的所述第一端部101’方向延伸。
参考附图20，所述电流阻挡层20’的数量是一个，其中所述电流阻挡层20’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸。在后续，以包覆所述电流阻挡层20’的方式层叠所述透明导电层30’于所述P型半导体层14’，并且所述透明导电层30’的所述穿孔31’对应于所述电流阻挡层20’。
相应地，在后续所述P型电极42’成型后，所述P型电极42’包括一个层叠于所述透明导电层30’的所述P型电极焊盘421’和一个所述P型电极扩展条422’，其中所述P型电极焊盘421’形成于所述半导体芯片的所述第一端部101’，所述P型电极扩展条422’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸，并且所述P型电极扩展条422’的所述P型叉指4220’形成于和被保持在所述透明导电层30’的所述穿孔31’。参考附图20，所述P型电极42’的所述P型电极扩展条422’被保持在所述N型电极41’的两个所述N型电极扩展条412’之间。
继续参考附图20，层叠所述钝化层50’于所述外延单元10’的所述P型半导体层14’，并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，其中所述钝化层50’的所述第一通孔51’对应于所述N型电极41’，以使所述N型电极41’被暴露在所述钝化层50’的所述第一通孔51’，所述钝化层50’的所述第二通孔52’对应于所述P型电极42’，以使所述P型电极42’被暴露在所述钝化层50’的所述第二通孔52’。
附图21示出了所述半导体芯片的另一个变形实施方式，与附图20示出的所述半导体芯片不同的是，在附图21示出的所述半导体芯片的这个较佳示例中，所述半导体裸露部15’仅具有一个所述N型电极焊盘裸露部151’，其形成在所述半导体芯片的所述第二端部102’。相应地，在后续所述N型电极41’成型后，所述N型电极41’仅包括一个所述N型电极焊盘411’，其中所述N型电极焊盘411’层叠于所述N型半导体层12’和被保持在所述N型电极焊盘裸露部151’。
参考附图21，所述电流阻挡层20’的数量是一个，其中所述电流阻挡层20’在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述半导体芯片的所述第一端部101’向所述第二端部102’方向延伸，在后续，以包覆所述电流阻挡层20’的方式层叠所述透明导电层30’于所述P型半导体层14’，并且所述透明导电层30’的所述穿孔31’对应于所述电流阻挡层20’。
相应地，在后续所述P型电极42’成型后，所述P型电极42’包括一个层叠于所述透明导电层30’的所述P型电极焊盘421’和一个所述P型电极扩展条422’，其中所述P型 电极焊盘421’形成于所述半导体芯片的所述第一端部101’，所述P型电极扩展条421在所述半导体芯片的中部沿着所述半导体芯片的长度方向自所述P型电极焊盘421’向所述半导体芯片的所述第二端部102’方向延伸，并且所述P型电极扩展条422’的所述P型叉指4220’形成于和被保持在所述透明导电层30’的所述穿孔31’。
继续参考附图21，层叠所述钝化层50’于所述外延单元10’的所述P型半导体层14’，并且所述钝化层50’包覆所述透明导电层30’以及所述电极组40’的所述N型电极41’和所述P型电极42’，其中所述钝化层50’的所述第一通孔51’对应于所述N型电极41’，以使所述N型电极41’被暴露在所述钝化层50’的所述第一通孔51’，所述钝化层50’的所述第二通孔52’对应于所述P型电极42’，以使所述P型电极42’被暴露在所述钝化层50’的所述第二通孔52’。
值得注意的是，在本发明的附图中示出的所述半导体芯片的所述衬底11’、所述N型半导体层12’、所述有源区13’、所述P型半导体层14’、所述电流阻挡层20’、所述透明导电层30’、所述N型电极41’和所述P型电极42’的厚度仅为示例，其并不表示所述衬底11’、所述N型半导体层12’、所述有源区13’、所述P型半导体层14’、所述电流阻挡层20’、所述透明导电层30’、所述N型电极41’和所述P型电极42’的真实厚度。并且，所述衬底11’、所述N型半导体层12’、所述有源区13’、所述P型半导体层14’、所述电流阻挡层20’、所述透明导电层30’、所述N型电极41’和所述P型电极42’之间的真实比例也并不像附图中示出的那样。另外，所述电极组40’的所述N型电极41’和所述P型电极42’的尺寸与所述半导体芯片的其他层的尺寸比例也不受限于附图中示出的那样。
另外，在本发明的附图中示出的所述半导体芯片的所述透明导电层30’的所述穿孔31’的尺寸、相邻所述穿孔31’的尺寸比例以及相邻所述穿孔31’的间距均为示例，以用于揭露和阐述本发明的所述半导体芯片的内容和特征，并不应被视为对本发明的所述半导体芯片的内容和范围的限制。
相应地，在本发明的附图中示出的所述半导体芯片的所述P型电极42’的所述P型叉指4220’的尺寸、相邻所述P型叉指4220’的尺寸比例以及相邻所述P型叉指4220’的间距均为示例，以用于揭露和阐述本发明的所述半导体芯片的内容和特征，并不应被视为对本发明的所述半导体芯片的内容和范围的限制。
本领域的技术人员可以理解的是，以上实施例仅为举例，其中不同实施例的特征可以相互组合，以得到根据本发明揭露的内容很容易想到但是在附图中没有明确指出的实施方式。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (95)

  1. 一半导体芯片，其特征在于，包括：
    一外延单元，其中所述外延单元包括一衬底和自所述衬底依次生长的一N型半导体层、一有源区和一P型半导体层，其中所述外延单元具有至少一半导体裸露部，所述半导体裸露部自所述P型半导体层经所述有源区延伸至所述N型半导体层；
    至少一电流阻挡层，其中所述电流阻挡层层叠于所述外延单元的所述P型半导体层；
    一透明导电层，其中所述透明导电层具有至少一穿孔，其中所述透明导电层以包覆所述电流阻挡层的方式层叠于所述P型半导体层，并且所述透明导电层的所述穿孔对应于所述电流阻挡层；以及
    一电极组，其中所述电极组包括至少一N型电极和至少一P型电极，其中所述N型电极以形成于所述半导体裸露部的方式层叠于所述N型半导体层，其中所述P型电极具有至少一P型叉指，在所述P型电极层叠于所述透明导电层时，所述P型电极的所述P型叉指形成于和被保持在所述透明导电层的所述穿孔。
  2. 根据权利要求1所述的半导体芯片，其中所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘和自所述N型电极焊盘向所述半导体芯片的第一端部方向延伸的至少一N型电极扩展条，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少两P型电极扩展条，其中至少一个所述N型电极扩展条被保持在相邻两个所述P型电极扩展条之间。
  3. 根据权利要求2所述的半导体芯片，其中所述N型电极的所述N型电极扩展条的数量是一个，并且所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是两个，并且两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸。
  4. 根据权利要求2所述的半导体芯片，其中所述N型电极的所述N型电极扩展条的数量是两个，并且所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是三个，分别为一第一P型电极扩展条、一第二P型电极扩展条以及一第三P型电极扩展条，所述第一P型电极扩展条和所述第三P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述N型电极扩展条被保持在所述第一P型电极扩展条和所述第二P型电极扩展条之间，另一个所述N型电极扩展条被保持在所述第二P型电极扩展条和所述第三P型电极扩展条之间。
  5. 根据权利要求1所述的半导体芯片，其中所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘和自所述N型电极焊盘向所述半导体芯片的第一端部方向延伸的至少两N型电极扩展条，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少一P 型电极扩展条，其中至少一个所述P型电极扩展条被保持在相邻两个所述N型电极扩展条之间。
  6. 根据权利要求5所述的半导体芯片，其中所述N型电极的所述N型电极扩展条的数量是两个，并且两个所述N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是一个，并且所述P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸。
  7. 根据权利要求5所述的半导体芯片，其中所述N型电极的所述N型电极扩展条的数量是三个，分别为一第一N型电极扩展条、一第二N型电极扩展条以及一第三N型电极扩展条，所述第一N型电极扩展条和所述第三N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极的所述P型电极扩展条的数量是两个，其中两个所述P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述P型电极扩展条被保持在所述第一N型极扩展条和所述第二N型电极扩展条之间，另一个所述P型电极扩展条被保持在所述第二N型电极扩展条和所述第三N型电极扩展条之间。
  8. 根据权利要求1所述的半导体芯片，其中所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的一P型电极扩展条。
  9. 根据权利要求1至8中任一所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  10. 根据权利要求9所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  11. 根据权利要求9所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  12. 根据权利要求1至8中任一所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  13. 根据权利要求9所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  14. 一半导体芯片的制造方法，其特征在于，所述制造方法包括如下步骤：
    (a)层叠一电流阻挡层于一外延单元的一P型半导体层；
    (b)以包覆所述电流阻挡层的方式层叠一透明导电层于所述P型半导体层，其中所述 透明导电层具有至少一穿孔，以对应于所述电流阻挡层；以及
    (c)以一N型电极被保持在所述外延单元的一半导体裸露部的方式层叠所述N型电极于所述外延单元的一N型半导体层，和以一P型电极的P型叉指形成于所述透明导电层的所述穿孔的方式层叠所述P型电极于所述透明导电层，以制得所述半导体芯片。
  15. 根据权利要求14所述的制造方法，进一步包括步骤：
    (d)以包覆所述N型电极和所述P型电极的方式层叠一钝化层于所述透明导电层和所述P型半导体层，其中所述钝化层具有对应于所述N型电极的一第一通道和对应于所述P型电极的一第二通道。
  16. 根据权利要求14所述的制造方法，其中在所述步骤(a)中，进一步包括步骤：
    (a.1)沉积一层绝缘层于所述P型半导体层；和
    (a.2)湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层。
  17. 根据权利要求15所述的制造方法，其中在所述步骤(a)中，进一步包括步骤：
    (a.1)沉积一层绝缘层于所述P型半导体层；和
    (a.2)湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层。
  18. 根据权利要求16所述的制造方法，其中在所述步骤(a.2)之前，所述步骤(a)进一步包括步骤：正胶光刻电流阻挡层结构，从而在所述步骤(a.2)中，根据电流阻挡层结构湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层，并且在所述步骤(a.2)之后，所述步骤(a)进一步包括步骤：去除光刻胶。
  19. 根据权利要求17所述的制造方法，其中在所述步骤(a.2)之前，所述步骤(a)进一步包括步骤：正胶光刻电流阻挡层结构，从而在所述步骤(a.2)中，根据电流阻挡层结构湿法蚀刻所述绝缘层，以藉由所述绝缘层形成层叠于所述P型半导体层的所述电流阻挡层，并且在所述步骤(a.2)之后，所述步骤(a)进一步包括步骤：去除光刻胶。
  20. 根据权利要求18所述的制造方法，其中所述绝缘层的材料是SiO2材料。
  21. 根据权利要求19所述的制造方法，其中所述绝缘层的材料是SiO2材料。
  22. 根据权利要求20所述的制造方法，其中在所述步骤(a.1)中，反应气体SiH4、N2O和N2，以沉积所述绝缘层于所述P型半导体层。
  23. 根据权利要求21所述的制造方法，其中在所述步骤(a.1)中，反应气体SiH4、N2O和N2，以沉积所述绝缘层于所述P型半导体层。
  24. 根据权利要求22所述的制造方法，其中所述绝缘层的厚度尺寸范围为500埃至10000埃。
  25. 根据权利要求23所述的制造方法，其中所述绝缘层的厚度尺寸范围为500埃至10000埃。
  26. 根据权利要求18所述的制造方法，其中光刻胶的厚度尺寸范围为0.5μm至5μm。
  27. 根据权利要求19所述的制造方法，其中光刻胶的厚度尺寸范围为0.5μm至5μm。
  28. 根据权利要求16至27中任一所述的制造方法，其中湿法蚀刻所述绝缘层使用的蚀刻液为氢氟酸和氟化铵的混合溶液。
  29. 根据权利要求14所述的制造方法，其中在所述步骤(b)中，进一步包括步骤：
    (b.1)沉积包覆所述电流阻挡层的一层氧化铟锡层于所述P型半导体层；和
    (b.2)湿法蚀刻所述氧化铟锡，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔。
  30. 根据权利要求15所述的制造方法，其中在所述步骤(b)中，进一步包括步骤：
    (b.1)沉积包覆所述电流阻挡层的一层氧化铟锡层于所述P型半导体层；和
    (b.2)湿法蚀刻所述氧化铟锡，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔。
  31. 根据权利要求29所述的制造方法，其中在所述步骤(b.2)之前，所述步骤(b)进一步包括步骤：正胶光刻透明导电层结构，从而在所述步骤(b.2)中，根据透明导电层的结构蚀刻所述氧化铟锡层，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔，并且在所述步骤(b.2)之后，所述步骤(b)进一步包括步骤：去除光刻胶。
  32. 根据权利要求30所述的制造方法，其中在所述步骤(b.2)之前，所述步骤(b)进一步包括步骤：正胶光刻透明导电层结构，从而在所述步骤(b.2)中，根据透明导电层的结构蚀刻所述氧化铟锡层，以藉由所述氧化铟锡层形成所述透明导电层和形成所述透明导电层的所述穿孔，并且在所述步骤(b.2)之后，所述步骤(b)进一步包括步骤：去除光刻胶。
  33. 根据权利要求31所述的制造方法，其中在所述正胶光刻透明导电层的步骤之前，所述步骤(b)进一步包括步骤：对所述氧化铟锡层进行合金。
  34. 根据权利要求32所述的制造方法，其中在所述正胶光刻透明导电层的步骤之前，所述步骤(b)进一步包括步骤：对所述氧化铟锡层进行合金。
  35. 根据权利要求29至34中任一所述的制造方法，其中湿法蚀刻所述氧化铟锡层使用的蚀刻液为盐酸和氯化铁混合溶液。
  36. 根据权利要求14至27、29至34中任一所述的制造方法，其中在所述步骤(a)中，进一步层叠所述电流阻挡层于所述N型半导体层的被暴露在所述半导体裸露部的表面，从而在所述步骤(c)中，所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  37. 根据权利要求28所述的制造方法，其中在所述步骤(a)中，进一步层叠所述电流阻挡层于所述N型半导体层的被暴露在所述半导体裸露部的表面，从而在所述步骤(c)中，所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  38. 根据权利要求36所述的制造方法，其中在所述步骤(a)中，进一步层叠所述电流阻挡层于所述N型半导体层的被暴露在所述半导体裸露部的表面，从而在所述步骤(c)中，所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  39. 一半导体芯片，其特征在于，包括：
    一外延单元，其中所述外延单元包括依次层叠的一衬底、一N型半导体层、一有源区和一P型半导体层以及具有自所述P型半导体层经所述有源区延伸至所述N型半导体层的至少一半导体裸露部；
    至少一电流阻挡层，其中所述电流阻挡层层叠于所述P型半导体层；
    一透明导电层，其中所述透明导电层具有至少一列穿孔，其中所述透明导电层以包覆所述电流阻挡层的方式层叠于所述P型半导体层，所述透明导电层的所述穿孔对应于所述电流阻挡层，并且一列所述穿孔中的至少一个所述穿孔与相邻所述穿孔不同；以及
    一电极组，其中所述电极组包括层叠于所述N型半导体层的一N型电极和层叠于所述透明导电层的一P型电极，其中所述N型电极包括形成于所述半导体芯片的第二端部的一N型电极焊盘，其中所述P型电极包括形成于所述半导体芯片的第一端部的一P型电极焊盘和自所述P型电极焊盘向所述半导体芯片的第二端部方向延伸的至少一P型电极扩展条，其中所述P型电极扩展条具有一列P型叉指，其中所述P型叉指形成于和被保持在所述透明导电层的所述穿孔。
  40. 根据权利要求39所述的半导体芯片，其中所述N型电极进一步包括至少一N型电极扩展条，其中所述N型电极扩展条自所述N型电极焊盘向所述半导体芯片的第二端部方向延伸。
  41. 根据权利要求39所述的半导体芯片，其中一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐增大。
  42. 根据权利要求40所述的半导体芯片，其中一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐增大。
  43. 根据权利要求39所述的半导体芯片，其中一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐减小。
  44. 根据权利要求40所述的半导体芯片，其中一列所述穿孔中的每个所述穿孔的尺寸从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的每个所述P型叉指的尺寸从所述半导体芯片的第一端部向第二端部反向逐渐减小。
  45. 根据权利要求39所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  46. 根据权利要求40所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  47. 根据权利要求41所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  48. 根据权利要求42所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉 指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  49. 根据权利要求43所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  50. 根据权利要求44所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐增大。
  51. 根据权利要求39所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  52. 根据权利要求40所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  53. 根据权利要求41所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  54. 根据权利要求42所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  55. 根据权利要求43所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  56. 根据权利要求44所述的半导体芯片，其中一列所述穿孔中的相邻两个所述穿孔之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小，从而一列所述P型叉指中的相邻两个所述P型叉指之间的间距从所述半导体芯片的第一端部向所述第二端部方向逐渐减小。
  57. 根据权利要求40至56中任一所述的半导体芯片，其中所述N型电极包括一个所述N型电极扩展条，所述N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括两个所述P型电极扩展条，两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所 述N型电极扩展条被保持在两个所述P型电极扩展条之间。
  58. 根据权利要求40至56中任一所述的半导体芯片，其中所述N型电极包括两个所述N型电极扩展条，两个所述N型电极扩展条裸露部在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括三个所述P型电极扩展条，分别为一第一P型电极扩展条、一第二P型电极扩展条以及一第三P型电极扩展条，所述第一P型电极扩展条和所述第三P型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二P型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中一个所述N型电极扩展条被保持在所述第一P型电极扩展条和所述第二P型电极扩展条之间，另一个所述N型电极扩展条被保持在所述第二P型电极扩展条和所述第三P型电极扩展条之间。
  59. 根据权利要求40至56中任一所述的半导体芯片，其中所述N型电极包括两个所述N型电极扩展条，两个所述N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括一个所述P型电极扩展条，所述P型电极扩展条在所述半导体芯片的中部沿着所述P型电极的长度方向延伸，其中所述P型电极扩展条被保持在两个所述N型电极扩展条之间。
  60. 根据权利要求40至56中任一所述的半导体芯片，其中所述N型电极包括三个所述N型电极扩展条，分别为一第一N型电极扩展条、一第二N型电极扩展条以及一第三N型电极扩展条，所述第一N型电极扩展条和所述第三N型电极扩展条以相互对称的方式在所述半导体芯片的边缘沿着所述半导体芯片的长度方向延伸，所述第二N型电极扩展条在所述半导体芯片的中部沿着所述半导体芯片的长度方向延伸，其中所述P型电极包括两个所述P型电极扩展条，两个所述P型电极扩展条以相互对称的方式在所述半导体芯片的中部沿着所述半导体芯片的长度方形延伸，其中一个所述P型电极扩展条被保持在所述第一N型电极扩展条和所述第二N型电极扩展条之间，另一个所述P型电极扩展条被保持在所述第二N型电极扩展条和所述第三N型电极扩展条之间。
  61. 根据权利要求40至56中任一所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  62. 根据权利要求57所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  63. 根据权利要求58所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  64. 根据权利要求59所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆层叠于所述N型半导体层的所述电流阻挡层。
  65. 根据权利要求60所述的半导体芯片，其中所述外延单元的所述N型半导体层的被暴露在所述半导体裸露部的表面层叠有至少一个所述电流阻挡层，其中所述N型电极包覆 层叠于所述N型半导体层的所述电流阻挡层。
  66. 根据权利要求61所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  67. 根据权利要求62所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  68. 根据权利要求63所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  69. 根据权利要求64所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  70. 根据权利要求65所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层呈条带状，其沿着所述半导体芯片的长度方向延伸。
  71. 根据权利要求66所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  72. 根据权利要求67所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  73. 根据权利要求68所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  74. 根据权利要求69所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  75. 根据权利要求70所述的半导体芯片，其中层叠于所述N型半导体层的所述电流阻挡层的数量是多个，这些所述电流阻挡层呈条带状排列地沿着所述半导体芯片的长度方向延伸，并且在相邻两个所述电流阻挡层之间具有间隔缝隙。
  76. 根据权利要求39至56中任一所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  77. 根据权利要求57所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  78. 根据权利要求58所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  79. 根据权利要求59所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  80. 根据权利要求60所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  81. 根据权利要求61所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  82. 根据权利要求62所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  83. 根据权利要求63所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  84. 根据权利要求64所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  85. 根据权利要求65所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  86. 根据权利要求66所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  87. 根据权利要求67所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  88. 根据权利要求68所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层 叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  89. 根据权利要求69所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  90. 根据权利要求70所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  91. 根据权利要求71所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  92. 根据权利要求72所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  93. 根据权利要求73所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  94. 根据权利要求74所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
  95. 根据权利要求75所述的半导体芯片，进一步包括一钝化层，其中所述钝化层具有一第一通孔和一第二通孔，其中所述钝化层以包覆所述N型电极和所述P型电极的方式层叠于所述P型半导体层和所述透明导电层，并且所述钝化层的所述第一通孔对应于所述N型电极，所述钝化层的所述第二通孔对应于所述P型电极。
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