WO2019223230A1 - 解决vr掉电时序测试powergood信号不单调的方法及*** - Google Patents

解决vr掉电时序测试powergood信号不单调的方法及*** Download PDF

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WO2019223230A1
WO2019223230A1 PCT/CN2018/112004 CN2018112004W WO2019223230A1 WO 2019223230 A1 WO2019223230 A1 WO 2019223230A1 CN 2018112004 W CN2018112004 W CN 2018112004W WO 2019223230 A1 WO2019223230 A1 WO 2019223230A1
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power
powergood signal
chip
powergood
load
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PCT/CN2018/112004
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French (fr)
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隋鑫
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郑州云海信息技术有限公司
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere

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  • the invention relates to the technical field of power supply testing, in particular to a method and a system for solving the problem that the power-good signal of the VR power-down timing test is not monotonous.
  • the server motherboard and other boards need to measure VR (Voltage, Regulation, Chinese name: power supply module) power-down sequence during the development phase, and analyze whether there is any abnormality in the power-down sequence.
  • the measured VR power-down timing waveform should be smooth and monotonous before and after the drop. There should be no abnormal overshoot, drop and other abrupt changes. Non-monotonic conditions are not allowed during the waveform drop.
  • the VCC, ENABLE, POWERGOOD, and VOUT signals of the VR chip are usually led out by soldering flying leads, and then these 4 groups of signals are connected by 4 single-ended probes.
  • the power-off waveform of the captured POWERGOOD signal will not be monotonic.
  • the purpose of the present invention is to provide a method and system for solving the non-monotonic POWERGOOD signal of the VR power-down timing test.
  • the present invention adopts the following technical solutions:
  • the first invention of the present invention provides a method for solving the problem that the POWERGOOD signal of the VR power-down timing test is not monotonous, as follows:
  • the method before the step of loading a small amount of current at the power source of the POWERGOOD signal line of the VR chip, the method further includes:
  • VCC, ENABLE, POWERGOOD, and VOUT signals of the VR chip are led out by soldering flying leads and connected to the oscilloscope through a single-ended probe.
  • the step of loading a small amount of current at the power source of the POWERGOOD signal line of the VR chip specifically includes:
  • the positive and negative electrodes of the electronic load meter are each connected to a load line.
  • the positive load line is welded to the power supply of the POWERGOOD signal.
  • the negative load line shares the ground with the board under test where the VR chip is located.
  • the method further includes:
  • the oscilloscope captures the power-off waveform of the POWERGOOD signal of the VR chip and saves it.
  • the second aspect of the present invention provides a non-monotonic system for solving a power-down timing test of VR power failure, which is characterized by including a VR chip, a pull-up resistor and a pull-up power supply connected in order to the POWERGOOD signal line of the VR chip, and a VR chip.
  • An oscilloscope connected to the measurement point of the POWERGOOD signal, and a current load unit connected to the pull-up power supply.
  • the current load unit includes an electronic load meter, the positive and negative electrodes of the electronic load meter are each connected to a load line, and the positive load line is welded to the POWERGOOD signal pull-up power supply , The negative load line shares the ground with the board under test where the VR chip is located.
  • the beneficial effect of the present invention is that the present invention solves the problem that the POWERGOOD signal is not monotonic in the VR power-down timing test by loading a small amount of current at the pull-up power supply. It can accurately and quickly solve the problem that the POWERGOOD signal is not monotonous in the VR power-down timing test, which reflects the real working condition of VR, which improves the test efficiency and is simple and efficient.
  • FIG. 1 is a schematic diagram of a system circuit of the present invention
  • FIG. 2 is a waveform diagram of a VR power-down test where a non-monotonic problem occurs before the improvement of the present invention
  • FIG. 3 is a waveform diagram of a VR power-down test after the improvement of the present invention.
  • FIG. 4 is a flowchart of a method for solving the power failure timing test of the VR power failure signal to be monotonous.
  • the POWERGOOD signal of the VR control chip pin is connected to the pull-up power supply through a 4.7K ⁇ pull-up resistor, and the pull-up power supply voltage is 3.3V.
  • the POWERGOOD signal will be synchronously powered down with the VR chip VCC, and the voltage will gradually decrease until the VR chip loses control of the POWERGOOD signal, and the POWERGOOD signal is at a low level.
  • VCC, ENABLE, POWERGOOD, and VOUT signals of the VR chip are led out by soldering flying leads and connected to the oscilloscope through a single-ended probe;
  • the positive and negative electrodes of the electronic load meter are each connected to a load line.
  • the positive load line is welded to the power supply of the POWERGOOD signal.
  • the negative load line shares the ground with the board under test where the VR chip is located.
  • the oscilloscope captures the power-off waveform of the POWERGOOD signal of the VR chip and saves it.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

本发明公开了解决VR掉电时序测试POWERGOOD信号不单调的方法,具体如下:在VR芯片的POWERGOOD信号线上拉电源处加载小额电流。还公开了一种解决VR掉电时序测试POWERGOOD信号不单调的***,能够准确快速解决VR掉电时序测试中POWERGOOD信号不单调的问题,反映出VR真实工作情况,提高了测试效率,简洁高效。

Description

解决VR掉电时序测试POWERGOOD信号不单调的方法及***
本申请要求于2018年5月22日提交中国专利局、申请号为201810492541.9、申请名称为“解决VR掉电时序测试POWERGOOD信号不单调的方法及***”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电源测试技术领域,尤其是解决VR掉电时序测试POWERGOOD信号不单调的方法及***。
背景技术
服务器主板和其他板卡在开发阶段需要量测VR(Voltage Regulation,中文名称:电源模块)掉电时序,分析掉电时序有无异常。量测的VR掉电时序波形下降前后应该是平滑单调的,不应存在异常上冲,跌落等突变,波形下降过程中也不允许出现不单调的情况。
但是,在实际量测中,会发现一些经上拉电阻连接到上拉电源的POWERGOOD信号掉电时会出现不单调的情况,影响对VR真实工作情况的判断,降低了测试效率。
目前针对VR掉电时序的测试,通常会将VR芯片的VCC、ENABLE、POWERGOOD、VOUT 4个信号通过焊接飞线引出来,然后采用4根单端探棒连接这4组信号。
将示波器设置为信号下降沿触发,关机抓取4路信号波形(关机分两种方式:1、直接断AC 2、正常关机),观察波形下降过程中是否有不单调或异常突变的情况,以此来判断VR的掉电时序是否正常。
在VR芯片的POWERGOOD信号经上拉电阻连接到上拉电源时,抓取的POWERGOOD信号掉电波形会出现不单调的问题。
发明内容
本发明的目的是提供解决VR掉电时序测试POWERGOOD信号不单调的方法及***。
为实现上述目的,本发明采用下述技术方案:
本发明第一发明提供了一种解决VR掉电时序测试POWERGOOD信号不单调的方法,具体如下:
在VR芯片的POWERGOOD信号线上拉电源处加载小额电流。
结合第一方面,在第一方面第一种可能的实现方式中,所述VR芯片的POWERGOOD信号线上拉电源处加载小额电流步骤之前,还包括:
将VR芯片的VCC、ENABLE、POWERGOOD、VOUT 4个信号通过焊接飞线引出并通过单端探棒与示波器连接。
结合第一方面,在第一方面第二种可能的实现方式中,所述在VR芯片的POWERGOOD信号线上拉电源处加载小额电流,具体包括:
S1、电子负载仪正负极各接一根负载线,正极负载线焊接于POWERGOOD信号上拉电源处,负极负载线与VR芯片所在待测板卡共地;
S2、将待测板卡上电,使用电子负载仪加载0.5A左右电流。
结合第一方面,在第一方面第三种可能的实现方式中所述将待测板卡上电,使用电子负载仪加载0.5A左右电流步骤之后,还包括:
切断待测板卡与电源VCC连接,示波器抓取VR芯片的POWERGOOD信号掉电波形并保存。
本发明第二方面提供了一种解决VR掉电时序测试POWERGOOD信号不单调***,其特征是,包括VR芯片,与VR芯片的POWERGOOD信号线依次连接的上拉电阻和上拉电源,与VR芯片的POWERGOOD信号测量点连接的示波器,与上拉电源连接的电流负载单元。
结合第二方面,在第二方面第一种可能的实现方式中所述电流负载单元包括电子负载仪,电子负载仪正负极各接一根负载线,正极负载线焊接于POWERGOOD信号上拉电源处,负极负载线与VR芯片所在待测板卡共地。
本发明的有益效果是:本发明通过在上拉电源处加载小额电流的方式解决VR掉电时序测试中POWERGOOD信号不单调的问题。能够准确快速解决VR掉电时序测试中POWERGOOD信号不单调的问题,反映出VR真实工作情况,提高了测试效率,简洁高效。
附图说明
图1是本发明***电路原理图;
图2是本发明改进前出现不单调问题的VR掉电测试波形图;
图3是本发明改进后VR掉电测试波形图;
图4是解决VR掉电时序测试POWERGOOD信号不单调的方法流程图。
具体实施方式
为能清楚说明本方案的技术特点,下面通过具体实施方式,并结合其附图,对本发明进行详细阐述。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
如图1所示,VR控制芯片引脚POWERGOOD信号通过4.7KΩ的上拉电阻连接到上拉电源,上拉电源电压值为3.3V。
进行掉电操作时,POWERGOOD信号会随着VR芯片VCC同步掉电,电压逐渐降低,直至VR芯片失去对POWERGOOD信号的控制,POWERGOOD信号处于低电平状态。
但是,由于VCC掉电速度较快,当VR芯片失去对POWERGOOD信号的控制时,上拉电源仍然处于掉电过程中,电压并未降到低电平。此时由于上拉电阻的作用,POWERGOOD信号的电压值与上拉电源的电压值相同,因此POWERGOOD信号的掉电波形会有短暂上升,即波形不是单调下降的,之后再随着上拉电源同步掉电直至掉电完毕。现在方案中出现POWERGOOD信号不单调问题的VR掉电测试波形如图2所示。在圆圈内部可明显看到波形不单调。
为了解决VR掉电时序测试中POWERGOOD信号不单调的问题,采取在上拉电源处加载小额电流的方法,使上拉电源掉电速度加快,使用电子负载仪在3.3V上拉电源处加0.5A负载,其他测试流程无变化,可以发现VR掉电时POWERGOOD信号波形不再出现不单调的情况,POWERGOOD信号掉电时不再出现短暂上升情况,波形单调下降。测试波形如图3所示。
如图4所示,解决VR掉电时序测试中POWERGOOD信号不单调的问题时方法步骤如下:
S1、将VR芯片的VCC、ENABLE、POWERGOOD、VOUT 4个信号通过焊接飞线引出并通过单端探棒与示波器连接;
S2、电子负载仪正负极各接一根负载线,正极负载线焊接于POWERGOOD信号上拉电源处,负极负载线与VR芯片所在待测板卡共地;
S3、将待测板卡上电,使用电子负载仪加载0.5A左右电流;
S4、切断待测板卡与电源VCC连接,示波器抓取VR芯片的POWERGOOD信号掉电波形并保存。
上述虽然结合附图对本发明的具体实施方式进行了描述,但并非对本发明保护范围的限制,所属领域技术人员应该明白,在本发明的技术方案的基础上,本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本发明的保护范围以内。

Claims (6)

  1. 解决VR掉电时序测试POWERGOOD信号不单调的方法,其特征是,具体如下:
    在VR芯片的POWERGOOD信号线上拉电源处加载小额电流。
  2. 如权利要求1所述的解决VR掉电时序测试POWERGOOD信号不单调的方法,其特征是,所述VR芯片的POWERGOOD信号线上拉电源处加载小额电流步骤之前,还包括:
    将VR芯片的VCC、ENABLE、POWERGOOD、VOUT 4个信号通过焊接飞线引出并通过单端探棒与示波器连接。
  3. 如权利要求2所述的解决VR掉电时序测试POWERGOOD信号不单调的方法,其特征是,所述在VR芯片的POWERGOOD信号线上拉电源处加载小额电流,具体包括:
    S1、电子负载仪正负极各接一根负载线,正极负载线焊接于POWERGOOD信号上拉电源处,负极负载线与VR芯片所在待测板卡共地;
    S2、将待测板卡上电,使用电子负载仪加载0.5A左右电流。
  4. 如权利要求3所述的解决VR掉电时序测试POWERGOOD信号不单调的方法,其特征是,所述将待测板卡上电,使用电子负载仪加载0.5A左右电流步骤之后,还包括:
    切断待测板卡与电源VCC连接,示波器抓取VR芯片的POWERGOOD信号掉电波形并保存。
  5. 解决VR掉电时序测试POWERGOOD信号不单调***,其特征是,包括VR芯片,与VR芯片的POWERGOOD信号线依次连接的上拉电阻和上拉电源,与VR芯片的POWERGOOD信号测量点连接的示波器,与上拉电源连接的电流负载单元。
  6. 如权利要求5所述的解决VR掉电时序测试POWERGOOD信号不单调***,其特征是,所述电流负载单元包括电子负载仪,电子负载仪正负极各接一根负载线,正极负载线焊接于POWERGOOD信号上拉电源处,负极负载线与VR芯片所在待测板卡共地。
PCT/CN2018/112004 2018-05-22 2018-10-26 解决vr掉电时序测试powergood信号不单调的方法及*** WO2019223230A1 (zh)

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CN109188242B (zh) * 2018-08-29 2021-08-31 郑州云海信息技术有限公司 一种时序测试方法、装置及vr芯片
CN109726056B (zh) * 2018-10-10 2021-11-02 郑州云海信息技术有限公司 一种改善vr时序信号不单调的方法与***
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