WO2019170045A1 - 一种共射共基异质结双极型晶体管 - Google Patents

一种共射共基异质结双极型晶体管 Download PDF

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WO2019170045A1
WO2019170045A1 PCT/CN2019/076793 CN2019076793W WO2019170045A1 WO 2019170045 A1 WO2019170045 A1 WO 2019170045A1 CN 2019076793 W CN2019076793 W CN 2019076793W WO 2019170045 A1 WO2019170045 A1 WO 2019170045A1
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bipolar transistor
heterojunction bipolar
cascode
copper pillar
heat sink
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PCT/CN2019/076793
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English (en)
French (fr)
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刘洪刚
袁志鹏
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苏州闻颂智能科技有限公司
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Priority to US16/627,385 priority Critical patent/US11195939B2/en
Publication of WO2019170045A1 publication Critical patent/WO2019170045A1/zh

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Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a cascode heterojunction bipolar transistor.
  • Heterojunction Bipolar Transistor has the advantages of high frequency, high efficiency, high linearity, high power density, and single-supply operation. It is widely used in wireless communications, satellite, radar, electronic warfare and other fields.
  • the power transistor In order to improve the RF output power of the heterojunction bipolar transistor, the power transistor generally adopts a multi-cell parallel structure, and there is a strong thermoelectric coupling effect between the cells of the bipolar transistor, thereby causing the junction temperature of the intermediate cell to be far. Above the edge cells, if the thermoelectric coupling effect between the cells is not effectively suppressed, it will eventually cause the heterojunction bipolar transistor to burn out.
  • thermoelectric coupling effect of a heterojunction bipolar transistor in two ways: one is to use an emitter or a base ballast resistor to increase the temperature stability of the current gain, but at the expense of the RF power efficiency of the transistor;
  • the thermal resistance of the transistor is reduced by thinning the substrate and the back via, and the complicated backside process poses a great challenge to the manufacturing yield of the conventional gallium arsenide and indium phosphide heterojunction bipolar transistor.
  • a cascode heterojunction bipolar transistor is disposed on a package substrate, wherein the package substrate is provided with a heat sink, and the cascode heterojunction bipolar transistor comprises at least one cascode a heterojunction bipolar transistor unit, the cascode heterojunction bipolar transistor unit comprising a common base heterojunction bipolar transistor and a common emitter heterojunction bipolar transistor;
  • the common base heterojunction bipolar transistor includes a first base, a first emitter, and a first collector;
  • the common emitter heterojunction bipolar transistor includes a second base, a second emitter, and a second collector;
  • the cascode heterojunction bipolar transistor unit further includes:
  • thermal shunt bridge for connecting the first emitter and the second collector
  • the fourth copper pillar is disposed above the second emitter
  • the cascode heterojunction bipolar transistor unit is flipped over the package substrate, and the fourth copper pillar is soldered to the heat sink.
  • the thermal shunt bridge is made of one or more of high thermal conductivity materials copper, gold, aluminum.
  • the thermal shunt bridge has a thickness of from 0.5 to 20 microns.
  • the cascode heterojunction bipolar transistor unit further includes a first copper pillar, the second copper pillar, the third copper pillar, and the fourth copper pillar respectively disposed on top of the first copper pillar Copper gold tin alloy solder.
  • the first copper pillar, the second copper pillar, the third copper pillar, the fourth copper pillar are equally distributed, and the heat sink comprises a first heat separated from each other by two a first layer of copper, a second heat sink layer, a third heat sink layer, and a fourth heat sink layer, wherein the eutectic eutectic heterojunction bipolar transistor unit is flipped on the package substrate, the first copper a first one of the column, the second copper pillar, the third copper pillar, and the fourth copper pillar are welded to the first heat sink layer, the second heat sink layer, and the third heat sink a layer, the fourth heat sink layer.
  • the cascode heterojunction bipolar transistor comprises two or more of the cascode heterojunction bipolar transistor units
  • two or more of the The cascode heterojunction bipolar transistor units are connected in parallel with each other.
  • the material system comprises InGaP/GaAs, InGaP/GaAsSb, InGaP/InGaAsSb, InP/InGaAs, InP/GaAsSb, InP/InGaAsSb.
  • the present invention has the following advantages over the prior art: a cascode heterojunction bipolar transistor of the present invention, which adopts a high power gain, high linearity cascode circuit
  • a cascode heterojunction bipolar transistor of the present invention which adopts a high power gain, high linearity cascode circuit
  • the combination of topology and low thermal resistance copper column flip-chip structure overcomes the limitations of traditional heterojunction bipolar transistors in terms of high efficiency and thermal stability, achieving high gain, high linearity and high temperature stability.
  • the performance of heterojunction bipolar transistors has broad application prospects in the field of RF power amplifier technology.
  • FIG. 1 is a schematic plan view showing a planar structure of a cascode heterojunction bipolar transistor according to the present invention
  • FIG. 2 is a schematic cross-sectional view showing a cascode heterojunction bipolar transistor according to the present invention
  • FIG. 3 is a schematic diagram showing a flip-chip structure of a cascode heterojunction bipolar transistor according to the present invention.
  • FIG. 4 is a schematic view showing the structure and heat dissipation of a conventional heterojunction bipolar transistor
  • VCE collector-emitter voltage
  • FIG. 6 is a diagram showing the RF output power (POUT) and power added efficiency (PAE) of a cascode heterojunction bipolar transistor and a conventional structure heterojunction bipolar transistor according to the present invention with a radio frequency input power (PIN). Change relationship.
  • FIG. 1 is a schematic diagram showing the planar structure of a cascode heterojunction bipolar transistor according to an embodiment of the present invention.
  • the common emitter multi-cell heterojunction bipolar transistor is located in the lower half of the figure.
  • the common base heterojunction bipolar transistor is located in the upper half of the figure.
  • the common emitter heterojunction bipolar transistor is located in the figure. the second half.
  • the second collector 103 and the first emitter 109 are connected by a thermal shunt bridge 107 to form a cascode heterojunction bipolar transistor.
  • the common emitter heterojunction bipolar transistor of FIG. 1 includes eight sets of common emitter heterojunction bipolar transistor cells, and each set of common emitter heterojunction bipolar transistor cells includes two second emitters 101.
  • the upper portions of the eight sets of second emitters 101 are connected to the fourth copper pillars 105.
  • the second base 102 surrounding the second emitter 101 is connected in parallel to the third pad 113 through the second base lead 104, and the third copper pillar 106 is disposed on the third pad 113.
  • the area and layout of the first emitter 109 in FIG. 1 is the same as the area and layout of the second emitter 101.
  • the first emitter 109 is connected to the second collector 103 via a thermal shunt bridge 107.
  • the thermal shunt bridge 107 is constructed of a high thermal conductivity metal to provide a more uniform temperature distribution of the common base heterojunction bipolar transistor.
  • the high thermal conductivity metal includes, but is not limited to, copper, gold, aluminum.
  • the thickness of the high thermal conductivity metal is typically greater than the skin depth of the radio frequency transmission line. In this embodiment, the thickness of the high thermal conductivity metal is 0.5-20 microns.
  • the first base 114 is connected to the first pads 110 on both sides through the first base lead 115 , and the first copper pillars 108 are disposed on the first pads 110 .
  • the first collector 116 is connected in parallel to the upper second pad 117 through the first collector lead 111, and the second copper pillar 112 is located on the second pad 117.
  • the InGaP/GaAs HBT includes a first emitter metal 217, a second emitter metal 223, a GaAs emitter region 219, an InGaP emitter region 220, a heavily doped P-type GaAs base region 215, and a first base metal 216.
  • the GaAs is semi-insulating in the substrate 201.
  • the primary wiring metal 204 is positioned over the first collector metal 203 and the second collector metal 225 at a level that is flush with the first emitter metal 217 and the second emitter metal 223.
  • a polyimide (Polyimide) dielectric layer or a benzocyclobutene (BCB) dielectric layer 205 is formed over the metal electrode by a spin coating process, and a gap between the metal electrodes is filled to planarize the chip surface.
  • a secondary wiring metal is formed by an electroplating gold process to a thickness of 5-10 microns, and a second emitter lead electrode 206, a first collector lead electrode 212, and a heat shunt bridge 222 are formed, respectively.
  • a polyimide (secondary planarization dielectric layer 207) and a passivation layer SiN are formed on the secondary wiring metal, and a fourth copper pillar 208 is formed on the second emitter lead electrode 206, and the second copper pillar 211 is formed. Formed on the first collector lead electrode 212.
  • a fourth copper-gold-tin alloy solder 209 is disposed on the top of the fourth copper pillar 208, and a second copper-gold-tin alloy solder 210 is disposed on the top of the second copper pillar 211.
  • the fourth copper pillar 208 is equal to the second copper pillar 211, and the copper pillar structure is favorable for improving the yield of the flip chip process.
  • FIG. 3 is a schematic diagram of a flip-chip structure of a cascode heterojunction bipolar transistor according to an embodiment of the present invention.
  • the emitter heat-dissipating copper post 301 has a height of about 50 microns and is connected to the emitter metal 302 of the common-emitter heterojunction bipolar transistor, and the cascode heterojunction bipolar type is flip-chip mounted.
  • the heat generated inside the transistor is directly introduced into the heat sink 304 of the package substrate 303 through the emitter heat-dissipating copper post 301.
  • FIG. 4 is a schematic diagram of the package structure and heat dissipation of a conventional heterojunction bipolar transistor.
  • the heat generated by the heterojunction bipolar transistor passes through a high thermal resistance GaAs substrate 401 (the thickness is usually 100 micrometers, and the thermal resistivity is 10 for metallic copper). Diffusion to the heat sink 402 on the back side, and reducing the thickness of the GaAs substrate to 50 ⁇ m or less can improve the heat dissipation effect of the heterojunction bipolar transistor, but causes a large increase in the chipping rate of the back surface process.
  • the cascode heterojunction bipolar transistor structure with heat-dissipating copper pillar provided by the invention can greatly improve the heat dissipation effect of the transistor and effectively suppress the cascode caused by the temperature rise.
  • the thermoelectric coupling effect of the heterojunction bipolar transistor prevents the cascode heterojunction bipolar transistor from burning during high power operation.
  • V CE collector-emitter voltage
  • the measured junction temperature of the conventional structure common-emitter type InGaP/GaAs HBT is increased from 31 ° C to 85 ° C, and the present invention provides a heat-dissipating copper pillar structure.
  • the measured junction temperature of the cascode-type InGaP/GaAs HBT is only increased from 35 ° C to 53 ° C, showing excellent heat dissipation.
  • FIG. 6 is a diagram showing an RF output power (P OUT ) and a power added efficiency (PAE) of a cascode heterojunction bipolar transistor and a conventional structure heterojunction bipolar transistor according to an embodiment of the present invention.
  • the cascode-type InGaP/GaAs HBT with heat-dissipating copper pillar structure provided by the invention has a saturated output power of 33 dBm, a peak power accessory efficiency (PAE) of more than 66%, and a saturation output characteristic superior to that of the conventional structure InGaP/GaAs HBT.
  • the power attachment efficiency (PAE) of the cascode InGaP/GaAs HBT with the heat dissipation copper pillar structure is still greater than 60%.
  • the power accessory efficiency (PAE) of the conventional structure InGaP/GaAs HBT has been less than 30%, which indicates that the Miller capacitance feedback effect of the cascode type InGaP/GaAs HBT with the heat dissipation copper pillar structure provided by the present invention is very low. .
  • the cascode heterojunction bipolar transistor provided by the present invention has excellent power gain and power added efficiency over a very wide range of RF input power, which is characterized by an envelope tracking (ET) architecture.
  • ETD envelope tracking

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

本发明公开了一种共射共基异质结双极型晶体管，设于封装基板上，封装基板上设有热沉，共射共基异质结双极型晶体管包括具有第一基极、第一发射极、第一集电极的共基极异质结双极型晶体管和具有第二基极、第二发射极、第二集电极的共发射极异质结双极型晶体管，以及用于连接第一发射极和第二集电极的热分流桥、用于连接第一基极的第一焊盘和第一铜柱、用于连接第一集电极的第二焊盘和第二铜柱、用于连接第二基极的第三焊盘和第三铜柱、设于第二发射极上方的第四铜柱，共射共基异质结双极型晶体管倒装于封装基板上，第四铜柱焊接于热沉上。本发明一种共射共基异质结双极型晶体管，具有高增益、高线性度、高温度稳定性。

Description

一种共射共基异质结双极型晶体管 技术领域
本发明涉及半导体器件技术领域，特别涉及一种共射共基异质结双极型晶体管。
背景技术
异质结双极型晶体管(Heterojunction Bipolar Transistor，HBT)具有高频率、高效率、高线性度、高功率密度、单电源工作等优点，广泛应用于无线通信、卫星、雷达、电子战等领域。为了提高异质结双极型晶体管的射频输出功率，功率型晶体管通常采用多元胞并联结构，双极型晶体管各元胞之间存在较强的热电耦合效应，从而造成中间元胞的结温远高于边缘元胞，如果元胞间的热电耦合效应不能有效抑制，最终将造成异质结双极型晶体管的烧毁。现有技术抑制异质结双极型晶体管的热电耦合效应通常采用两种方式：一是采用发射极或者基极镇流电阻提高电流增益的温度稳定性，但是会牺牲晶体管的射频功率效率；二是采用减薄衬底与背面通孔等方式降低晶体管的热阻，复杂的背面工艺对传统砷化镓与磷化铟异质结双极型晶体管的制造良率形成巨大挑战。
发明内容
本发明的目的是提供一种共射共基异质结双极型晶体管，具有较高的温度稳定性和优异的散热效果。
为达到上述目的，本发明采用的技术方案是：
一种共射共基异质结双极型晶体管，设于封装基板上，所述封装基板上设有热沉，所述共射共基异质结双极型晶体管包括至少一个共射共基异质结双极型晶体管单元，所述共射共基异质结双极型晶体管单元包括共基极异质结双极型晶体管、共发射极异质结双极型晶体管；
所述共基极异质结双极型晶体管包括第一基极、第一发射极、第一集电极；
所述共发射极异质结双极型晶体管包括第二基极、第二发射极、第二集电极；
所述共射共基异质结双极型晶体管单元还包括：
用于连接所述第一发射极和所述第二集电极的热分流桥；
用于连接所述第一基极的第一焊盘，设于所述第一焊盘上方的第一铜柱；
用于连接所述第一集电极的第二焊盘，设于所述第二焊盘上方的第二铜柱；
用于连接所述第二基极的第三焊盘，设于所述第三焊盘上方的第三铜柱；
第四铜柱，所述第四铜柱设于所述第二发射极上方；
所述共射共基异质结双极型晶体管单元倒装于所述封装基板上，所述第四铜柱焊接于所述热沉上。
优选地，所述热分流桥由高导热材料铜、金、铝中的一种或一种以上制成。
优选地，所述热分流桥的厚度为0.5-20微米。
优选地，所述共射共基异质结双极型晶体管单元还包括分别设于所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱顶部的铜金锡合金焊料。
优选地，所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱等高分布，所述热沉包括两两之间相互隔开的第一热沉层、第二热沉层、第三热沉层、第四热沉层，所述共射共基异质结双极型晶体管单元倒装于所述封装基板上时，所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱一一对应的焊接于所述第一热沉层、所述第二热沉层、所述第三热沉层、所述第四热沉层上。
优选地，当所述共射共基异质结双极型晶体管包括两个或两个以 上的所述共射共基异质结双极型晶体管单元时，两个或两个以上的所述共射共基异质结双极型晶体管单元相互并联。
优选地，在所述共射共基异质结双极型晶体管单元中，材料体系包括InGaP/GaAs、InGaP/GaAsSb、InGaP/InGaAsSb、InP/InGaAs、InP/GaAsSb、InP/InGaAsSb。
由于上述技术方案的运用，本发明与现有技术相比具有下列优点：本发明一种共射共基异质结双极型晶体管，通过将高功率增益、高线性度的共射共基电路拓扑结构与低热阻铜柱倒装结构相结合，克服了传统异质结双极型晶体管在高效率、热稳定性等方面的局限性，实现了具有高增益、高线性度、高温度稳定性性能的异质结双极型晶体管，在射频功率放大器技术领域具有广阔的应用前景。
附图说明
附图1为本发明所提供的共射共基异质结双极型晶体管的平面结构示意图；
附图2为本发明所提供的共射共基异质结双极型晶体管的剖面结构示意图；
附图3为本发明所提供的共射共基异质结双极型晶体管的倒装结构示意图；
附图4为传统异质结双极型晶体管的正装结构与散热示意图；
附图5为本发明所提供的共射共基异质结双极型晶体管与传统结构异质结双极型晶体管的发射区实测结温(BE Junction Temperature)随集电极-发射极电压(VCE)的变化关系；
附图6为本发明所提供的共射共基异质结双极型晶体管与传统结构异质结双极型晶体管的射频输出功率(POUT)与功率附加效率(PAE)随射频输入功率(PIN)的变化关系。
具体实施方式
下面结合附图来对本发明的技术方案作进一步的阐述。
图1为本发明所提供的一种实施例共射共基异质结双极型晶体管的平面结构示意图。共发射极多元胞结构异质结双极型晶体管位于 图中下半部分，共基极异质结双极型晶体管位于图中上半部分，共发射极异质结双极型晶体管位于图中下半部分。第二集电极103与第一发射极109通过热分流桥107相连构成共射共基异质结双极型晶体管。
图1中共发射极异质结双极型晶体管包括八组共发射极异质结双极型晶体管单元，每组共发射极异质结双极型晶体管单元中包含两个第二发射极101。八组第二发射极101的上方与第四铜柱105相连。围绕第二发射极101的第二基极102通过第二基极引线104并联至第三焊盘113，第三铜柱106设于第三焊盘113之上。
图1中第一发射极109的面积与布局与第二发射极101的面积与布局相同。第一发射极109通过热分流桥107与第二集电极103相连。热分流桥107由高热导金属构成，可以使共基极异质结双极型晶体管的温度分布更加均匀。在本实施例中，高热导金属包括但不限于铜、金、铝。高热导金属的厚度通常大于射频传输线的趋肤深度，在本实施例中，高热导金属的厚度为0.5-20微米。
图1中第一基极114通过第一基极引线115并联至两侧的第一焊盘110上，第一铜柱108设于第一焊盘110上。第一集电极116通过第一集电极引线111并联至上方的第二焊盘117上，第二铜柱112位于第二焊盘117上。
图2为本发明所提供的一种实施例共射共基异质结双极型晶体管的剖面结构示意图。本实施以InGaP/GaAs HBT为例进行具体说明。本实施例中，InGaP/GaAs HBT包括第一发射极金属217、第二发射极金属223、GaAs发射区219、InGaP发射区220、重掺杂P型GaAs基区215、第一基极金属216、第二基极金属224、轻掺杂N型GaAs集电区214、重掺杂N型GaAs集电区213、第一集电极金属203、第二集电极金属225，B注入隔离区202以及GaAs半绝缘衬底201中。一次布线金属204位于第一集电极金属203和第二集电极金属225之上，其高度与第一发射极金属217和第二发射极金属223平齐。采用旋涂工艺在金属电极上方形成聚酰亚胺(Polyimide)介质层或者苯并环丁烯(BCB)介质层205，并填充金属电极间的空隙使芯片表片 平坦化。采用电镀金工艺形成二次布线金属，厚度为5-10微米，分别形成第二发射极引线电极206、第一集电极引线电极212、热分流桥222。聚酰亚胺(Polyimide)二次平坦化介质层207与钝化层SiN形成于二次布线金属之上，第四铜柱208形成于第二发射极引线电极206之上，第二铜柱211形成于第一集电极引线电极212之上。第四铜柱208顶部设有第四铜金锡合金焊料209，第二铜柱211顶部设有第二铜金锡合金焊料210。第四铜柱208与第二铜柱211等高，该铜柱结构有利于提升芯片倒装工艺的良率。
图3为本发明所提供的一种实施例共射共基异质结双极型晶体管的倒装结构示意图。图中发射极散热铜柱301的高度为50微米左右并且与共发射极异质结双极型晶体管的发射极金属302相连接，并通过芯片倒装方式将共射共基异质结双极型晶体管内部产生的热量通过发射极散热铜柱301直接导入封装基板303的热沉304。
图4为传统异质结双极型晶体管的正装结构与散热示意图，异质结双极型晶体管产生的热量通过高热阻GaAs衬底401(厚度通常为100微米，热阻率是金属铜的10倍左右)扩散至背面的热沉402，将GaAs衬底厚度减薄至50微米以下可以提高异质结双极型晶体管的散热效果，但是会导致背面工艺破片率的大幅度提高。与常规结构InGaP/GaAs HBT相比较，本发明提供的具有散热铜柱的共射共基异质结双极型晶体管结构能极大地提高晶体管的散热效果，有效抑制温升导致的共射共基异质结双极型晶体管的热电耦合效应，防止共射共基异质结双极型晶体管在高功率工作时烧毁。
图5为本发明所提供的一种实施例共射共基异质结双极型晶体管与传统结构异质结双极型晶体管的发射区实测结温(BE Junction Temperature)随集电极-发射极电压(V CE)的变化关系。当集电极-发射极电压(V CE)从1V增加至5V，传统结构共射型InGaP/GaAs HBT的实测结温从31℃升高至85℃，而本发明提供的具有散热铜柱结构的共射共基型InGaP/GaAs HBT的实测结温仅从35℃升高至53℃，表现出优异的散热效果。
图6为本发明所提供的一种实施例共射共基异质结双极型晶体管与传统结构异质结双极型晶体管的射频输出功率(P OUT)与功率附加效率(PAE)随射频输入功率(P IN)的变化关系。本发明提供的具有散热铜柱结构的共射共基型InGaP/GaAs HBT的饱和输出功率达到33dBm，峰值功率附件效率(PAE)超过66％，饱和输出特性优于传统结构InGaP/GaAs HBT。更为重要的是，当射频输入功率(P IN)回退到0dBm时，本发明提供的具有散热铜柱结构的共射共基型InGaP/GaAs HBT的功率附件效率(PAE)依然大于60％，而传统结构InGaP/GaAs HBT的功率附件效率(PAE)已经低于30％，这说明本发明提供的具有散热铜柱结构的共射共基型InGaP/GaAs HBT的密勒电容反馈效应非常低。因此，本发明提供的共射共基异质结双极型晶体管在非常宽的射频输入功率范围内都具有优异的功率增益与功率附加效率，这一特性在采用包络追踪(ET)构架的4G LTE以及未来的5G通信终端的多模多频射频功率放大器应用中具有非常重要的应用前景。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并加以实施，并不能以此限制本发明的保护范围，凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围内。

Claims (7)

  1. 一种共射共基异质结双极型晶体管，设于封装基板上，所述封装基板上设有热沉，其特征在于：所述共射共基异质结双极型晶体管包括至少一个共射共基异质结双极型晶体管单元，所述共射共基异质结双极型晶体管单元包括共基极异质结双极型晶体管、共发射极异质结双极型晶体管；
    所述共基极异质结双极型晶体管包括第一基极、第一发射极、第一集电极；
    所述共发射极异质结双极型晶体管包括第二基极、第二发射极、第二集电极；
    所述共射共基异质结双极型晶体管单元还包括：
    用于连接所述第一发射极和所述第二集电极的热分流桥；
    用于连接所述第一基极的第一焊盘，设于所述第一焊盘上方的第一铜柱；
    用于连接所述第一集电极的第二焊盘，设于所述第二焊盘上方的第二铜柱；
    用于连接所述第二基极的第三焊盘，设于所述第三焊盘上方的第三铜柱；
    第四铜柱，所述第四铜柱设于所述第二发射极上方；
    所述共射共基异质结双极型晶体管单元倒装于所述封装基板上，所述第四铜柱焊接于所述热沉上。
  2. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：所述热分流桥由高导热材料铜、金、铝中的一种或一种以上制成。
  3. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：所述热分流桥的厚度为0.5-20微米。
  4. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：所述共射共基异质结双极型晶体管单元还包括分别设于所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱顶部的铜金锡合金焊料。
  5. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱等高分布，所述热沉包括两两之间相互隔开的第一热沉层、第二热沉层、第三热沉层、第四热沉层，所述共射共基异质结双极型晶体管单元倒装于所述封装基板上时，所述第一铜柱、所述第二铜柱、所述第三铜柱、所述第四铜柱一一对应的焊接于所述第一热沉层、所述第二热沉层、所述第三热沉层、所述第四热沉层上。
  6. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：当所述共射共基异质结双极型晶体管包括两个或两个以上的所述共射共基异质结双极型晶体管单元时，两个或两个以上的所述共射共基异质结双极型晶体管单元相互并联。
  7. 根据权利要求1所述的一种共射共基异质结双极型晶体管，其特征在于：在所述共射共基异质结双极型晶体管单元中，材料体系包括InGaP/GaAs、InGaP/GaAsSb、InGaP/InGaAsSb、InP/InGaAs、InP/GaAsSb、InP/InGaAsSb。
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