WO2019168027A1 - Production method for nonvolatile storage device - Google Patents

Production method for nonvolatile storage device Download PDF

Info

Publication number
WO2019168027A1
WO2019168027A1 PCT/JP2019/007555 JP2019007555W WO2019168027A1 WO 2019168027 A1 WO2019168027 A1 WO 2019168027A1 JP 2019007555 W JP2019007555 W JP 2019007555W WO 2019168027 A1 WO2019168027 A1 WO 2019168027A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
sacrificial layer
sacrificial
etching
conductive layer
Prior art date
Application number
PCT/JP2019/007555
Other languages
French (fr)
Japanese (ja)
Inventor
和雄 吉備
大久保　和哉
俊武 津田
李　彰原
寿 加藤
Original Assignee
東京エレクトロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Publication of WO2019168027A1 publication Critical patent/WO2019168027A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • the present disclosure relates to a method for manufacturing a nonvolatile memory device.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • This disclosure provides a technique capable of improving the durability of a conductive layer used as an etch stop layer.
  • the end portions of the multilayer film in which the first insulating layers and the first sacrificial layers are alternately stacked and the end portions are formed stepwise are provided.
  • Laminating a second sacrificial layer on the exposed portion of each of the first sacrificial layers exposed in step and laminating a second insulating layer on the multilayer film so as to cover the second sacrificial layer.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 6 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment.
  • a NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged.
  • the NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating layer 16, and a plurality of contact plugs 18.
  • the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
  • the substrate 12 is a substrate formed of a semiconductor such as silicon.
  • the multilayer film 14 has a structure in which the insulating layers 22 and the conductive layers 24 are alternately stacked and the end portions are formed in a stepped shape.
  • a plurality of pairs of the insulating layer 22 and the conductive layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction.
  • Each pair of the insulating layer 22 and the conductive layer 24 at the end portion of the multilayer film 14 is not covered with another pair arranged in the upper layer.
  • Each conductive layer 24 functions as a word line of each memory cell, for example.
  • Each conductive layer 24 is made of a metal such as W (tungsten).
  • Each conductive layer 24 except the conductive layer 24 disposed at the uppermost layer is not covered with the insulating layer 22 disposed at the upper layer at the end of the multilayer film 14 and is thicker than the other portions.
  • a portion (hereinafter referred to as “thick film portion”) 24 a is included.
  • each insulating layer 22 functions as an interlayer insulating film that insulates between the conductive layers 24 adjacent in the Z direction.
  • Each insulating layer 22 is, for example, a silicon oxide film.
  • the insulating layer 16 is formed on the multilayer film 14 so as to cover the multilayer film 14.
  • the insulating layer 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating layer 16.
  • the insulating layer 16 is, for example, a silicon oxide film.
  • the insulating layer 16 has a plurality of contact holes CH penetrating the insulating layer 16 in the Z direction.
  • the plurality of contact holes CH are collectively formed by etching using each conductive layer 24 as an etch stop layer.
  • each contact hole CH reaches the thick film portion 24 a of each conductive layer 24. Since the thick film portions 24a of the respective conductive layers 24 are thicker than the other portions, even when the corresponding contact holes CH reach the thick film portions 24a of the respective conductive layers 24 by etching, an etch stop margin is obtained. Is difficult to damage the wiring.
  • Each contact plug 18 is disposed in each contact hole CH.
  • Each contact plug 18 is made of a metal such as W, for example.
  • Each contact plug 18 is in contact with the thick film portion 24 a of each conductive layer 24.
  • each conductive layer 24 has the thick film portion 24a, and the corresponding contact hole CH is formed by etching so as to reach the thick film portion 24a.
  • the etch stop margin is large and wiring damage is less likely to occur. That is, the durability of the conductive layer 24 used as an etch stop layer can be improved.
  • the contact hole CH reaching the conductive layer 24 in each layer is normally formed.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment.
  • 3 to 8 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
  • the multilayer film 44 in which the insulating layers 52 and the sacrificial layers 54 are alternately stacked and the end portions are formed stepwise is formed on the substrate 42.
  • the insulating layer 52 is made of a material for forming the insulating layer 22, such as SiO 2 (silicon oxide film).
  • the sacrificial layer 54 is made of, for example, SiN (silicon nitride film). As shown in FIG. 3, the sacrificial layer 54 disposed on the uppermost layer is exposed as a whole.
  • Each sacrificial layer 54 except the sacrificial layer 54 disposed on the uppermost layer is partially exposed at the end of the multilayer film 44 as shown in FIG.
  • a portion of each sacrificial layer 54 exposed at the end of the multilayer film 44 is referred to as an “exposed portion”.
  • the insulating layer 52 is an example of a first insulating layer
  • the sacrificial layer 54 is an example of a first sacrificial layer.
  • the stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction within the plane of each layer, and the direction parallel to the paper surface of FIG. It is defined as the Y direction.
  • a sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. That is, the sacrificial layer 56 is formed on the upper surface of the exposed portion of each sacrificial layer 54 and is not formed on the side surface of each sacrificial layer 54.
  • the thickness of the sacrificial layer 56 is smaller than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54.
  • the sacrificial layer 56 is made of, for example, SiN (silicon nitride film).
  • the sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).
  • the sacrificial layer 56 is laminated not only on the exposed portion of each sacrificial layer 54 but also on the sacrificial layer 54 disposed on the uppermost layer.
  • the sacrificial layer 56 is an example of a second sacrificial layer.
  • the sacrificial layer 56 can be formed by ALD, for example.
  • ALD includes, for example, a first adsorption process, a treatment process, a second adsorption process, and a nitridation process. Specific conditions for ALD are as follows. ⁇ First adsorption step> Etching gas: mixed gas of Cl 2 and Ar Etching temperature: 200 to 500 ° C. ⁇ Etching time: 10 to 180 sec ⁇ Treatment process> Etching gas: NH 3 and Ar mixed gas Etching temperature: 200-500 ° C ⁇ Etching time: 10 to 180 sec ⁇ Second adsorption process> Etching gas: SiH 2 Cl 2 and N 2 mixed gas Etching temperature: 200 to 500 ° C.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54.
  • an insulating layer 46 is laminated on the multilayer film 44.
  • the insulating layer 46 is laminated on the multilayer film 44 so that the sacrificial layer 56 is covered.
  • the insulating layer 46 is stacked on the multilayer film 44 by, for example, CVD or ALD.
  • the insulating layer 46 is an example of a second insulating layer.
  • the insulating layer 46 is, for example, SiO 2 (silicon oxide film).
  • Specific film forming conditions for the insulating layer 46 are as follows. Raw materials: TEOS (tetraethyl orthosilicate), O 2 -Formation temperature: 400-900 ° C ⁇ Formation time: 5-12hours
  • step S ⁇ b> 104 of FIG. 2 and FIG. 6 the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74. That is, in the replacement in step S104, the sacrificial layer 54 and the sacrificial layer 56 are first removed by isotropic etching such as wet etching, for example. Thereafter, the conductive layer 74 is disposed by filling the space in which the sacrificial layer 54 and the sacrificial layer 56 are disposed with a metal material.
  • the sacrificial layer 54 is located in the space where the exposed portion and the sacrificial layer 56 were disposed and is thicker than the other portions.
  • a thick portion (hereinafter referred to as a “thick film portion”) 74 a is formed in the conductive layer 74.
  • the wet etching of the sacrificial layer 54 and the sacrificial layer 56 is performed, for example, under the following conditions.
  • the metal material is tungsten
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the insulating layer 46 is etched using the conductive layer 74 as an etch stop layer, and a contact hole CH ′ penetrating the insulating layer 46 in the Z direction is formed in the insulating layer 46.
  • a plurality of are formed.
  • the plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching), for example.
  • RIE Reactive Ion Etching
  • the etching stop margin is large. The damage is less likely to occur.
  • the etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as the etching apparatus. Specific conditions for etching at this time are as follows.
  • Etching gas CF 4 , Ar and O 2 mixed gas
  • Gas flow rate: CF 4 / Ar / O 2 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm ⁇
  • a metal material 48 is filled in each contact hole CH ′.
  • the metal material 48 and the thick film portion 74a of the conductive layer 74 are in contact with each other.
  • the metal material 48 is a metal material for forming the contact plug 18 such as W (tungsten), and a well-known technique such as CVD or ALD using a raw material such as WF 6 or W (CO) 6 can be used. It is. In this way, the NAND flash memory 10 according to this embodiment is manufactured.
  • the substrate 42 functions as the substrate 12
  • the insulating layer 52 functions as the insulating layer 22
  • the conductive layer 74 functions as the conductive layer 24
  • the insulating layer 46 functions as the insulating layer 16.
  • the metal material 48 functions as the contact plug 18 and the contact hole CH ′ functions as the contact hole CH.
  • the sacrificial layer 56 is stacked on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44, and the insulating layer 46 is stacked.
  • Each of the sacrificial layer 54 and the sacrificial layer 56 is replaced with a conductive layer 74.
  • the conductive layer 74 is located in the space where the exposed portion of the sacrificial layer 54 and the sacrificial layer 56 are disposed, and toward the portion thicker than the other portions (that is, the thick film portion 74a).
  • the insulating layer 46 is etched.
  • the thick film portion 74a of the conductive layer 74 is thicker than the other portions, even when the corresponding contact hole CH ′ reaches the thick film portion 74a of the conductive layer 74 by etching, an etch stop margin is obtained. Is difficult to damage the wiring. That is, according to this embodiment, the durability of the conductive layer 74 used as the etch stop layer can be improved. As a result, in the NAND flash memory 10 having the stacked structure, the contact hole CH ′ reaching the conductive layer 74 in each layer is normally formed.
  • the thickness of the sacrificial layer 56 is thinner than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54. Therefore, when the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74, the conductive layers 74 adjacent in the stacking direction of the multilayer film 44 are electrically insulated from each other by the respective insulating layers 52. . As a result, in the NAND flash memory 10 having the stacked structure, a short circuit between the conductive layers 74 in each layer is avoided.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. Thereby, the sacrificial layer 56 can be laminated with high efficiency.
  • Multilayer film 46 Insulating layer (second insulating layer) 48 Metal material 52 Insulating layer (first insulating layer) 54 Sacrificial layer (first sacrificial layer) 56 Sacrificial layer (second sacrificial layer) 74 Conductive layer

Abstract

A production method for a nonvolatile storage device (10). The production method includes: a step for laminating second sacrificial layers (56) at exposed portions of first sacrificial layers that are exposed at stair-shaped end parts of a multilayer film (44) that is formed by alternatingly laminating first insulation layers (52) and the first sacrificial layers (54); a step for laminating a second insulation layer (46) on the multilayer film so as to cover the second sacrificial layers; a step for replacing the first sacrificial layers and the second sacrificial layers with conductive layers (74); and a step for etching the second insulation layer toward thick portions (74a) of the conductive layers, the thick portions being positioned in the spaces at which the second sacrificial layers and the exposed portions of the first sacrificial layers were disposed and being thicker than other portions.

Description

不揮発性記憶装置の製造方法Method for manufacturing nonvolatile memory device
　本開示は、不揮発性記憶装置の製造方法に関するものである。 The present disclosure relates to a method for manufacturing a nonvolatile memory device.
　小型で大容量な不揮発性記憶装置として、ＮＡＮＤ型フラッシュメモリが知られている。また、メモリセルの高集積化を図るために、複数のメモリセルを３次元的に配置した積層構造のＮＡＮＤ型フラッシュメモリが知られている。 A NAND flash memory is known as a small and large capacity non-volatile storage device. In addition, in order to achieve high integration of memory cells, a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
　積層構造のＮＡＮＤ型フラッシュメモリでは、各メモリセルのワード線として機能する導電層に対してコンタクトを形成することが求められる。コンタクトの形成では、例えば、各層における導電層をエッチストップ層として用いるエッチングを行うことによって、各層における導電層へ到達するコンタクトホールを形成する。その後、コンタクトホール内に導電性を有する材料を充填して、当該材料と、各層における導電層とを接触させる。これにより、各層における導電層に対するコンタクトが形成される。 In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell. In forming the contact, for example, etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
米国特許出願公開第２０１７／０１１０３６５号明細書US Patent Application Publication No. 2017/0110365
　本開示は、エッチストップ層として用いられる導電層の耐久性を向上することができる技術を提供する。 This disclosure provides a technique capable of improving the durability of a conductive layer used as an etch stop layer.
　開示する不揮発性記憶装置の製造方法は、１つの実施態様において、第１の絶縁層と第１の犠牲層とが交互に積層され、端部が階段状に形成された多層膜の前記端部において露出するそれぞれの前記第１の犠牲層の露出部分に第２の犠牲層を積層する工程と、前記第２の犠牲層が覆われるように前記多層膜上に第２の絶縁層を積層する工程と、それぞれの前記第１の犠牲層及び前記第２の犠牲層を導電層に置換する工程と、前記導電層のうち、それぞれの前記第１の犠牲層の露出部分及び前記第２の犠牲層が配置されていた空間に位置し且つ他の部分よりも厚さが厚い部分に向かって、前記第２の絶縁層をエッチングする工程と、を含む。 In one embodiment of the disclosed method for manufacturing a nonvolatile memory device, the end portions of the multilayer film in which the first insulating layers and the first sacrificial layers are alternately stacked and the end portions are formed stepwise are provided. Laminating a second sacrificial layer on the exposed portion of each of the first sacrificial layers exposed in step, and laminating a second insulating layer on the multilayer film so as to cover the second sacrificial layer. A step of replacing the first sacrificial layer and the second sacrificial layer with a conductive layer, and an exposed portion of the first sacrificial layer and the second sacrificial layer of the conductive layer. Etching the second insulating layer toward a portion that is located in the space where the layer was disposed and is thicker than the other portions.
　開示する不揮発性記憶装置の製造方法の１つの態様によれば、エッチストップ層として用いられる導電層の耐久性を向上することができるという効果を奏する。 According to one aspect of the disclosed method for manufacturing a nonvolatile memory device, there is an effect that the durability of the conductive layer used as the etch stop layer can be improved.
図１は、本実施形態に係るＮＡＮＤ型フラッシュメモリの構造の一例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment. 図２は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を示すフローチャートである。FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment. 図３は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment. 図４は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment. 図５は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment. 図６は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 6 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment. 図７は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment. 図８は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
　以下に、開示する不揮発性記憶装置の製造方法の実施形態について、図面に基づいて詳細に説明する。なお、本実施形態により開示する不揮発性記憶装置の製造方法が限定されるものではない。 Hereinafter, embodiments of a method for manufacturing a disclosed nonvolatile memory device will be described in detail with reference to the drawings. Note that the manufacturing method of the nonvolatile memory device disclosed by the present embodiment is not limited.
　小型で大容量な不揮発性記憶装置として、ＮＡＮＤ型フラッシュメモリが知られている。また、メモリセルの高集積化を図るために、複数のメモリセルを３次元的に配置した積層構造のＮＡＮＤ型フラッシュメモリが知られている。 A NAND flash memory is known as a small and large capacity non-volatile storage device. In addition, in order to achieve high integration of memory cells, a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
　積層構造のＮＡＮＤ型フラッシュメモリでは、各メモリセルのワード線として機能する導電層に対してコンタクトを形成することが求められる。コンタクトの形成では、例えば、各層における導電層をエッチストップ層として用いるエッチングを行うことによって、各層における導電層へ到達するコンタクトホールを形成する。その後、コンタクトホール内に導電性を有する材料を充填して、当該材料と、各層における導電層とを接触させる。これにより、各層における導電層に対するコンタクトが形成される。 In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell. In forming the contact, for example, etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
　ところで、積層構造のＮＡＮＤ型フラッシュメモリでは、さらなる高集積化を図るため、メモリセルの積層数がさらに増加することが想定される。メモリセルの積層数が増加するほど、最上層に配置された導電層と最下層に配置された導電層との間の距離が増大する。そのため、各層における導電層をエッチストップ層として用いるエッチングが行われる場合、最下層に配置された導電層にコンタクトホールが到達するまでに、最上層に配置された導電層のエッチストップマージンが少なく、配線にダメージが発生する虞がある。その結果、各層における導電層へ到達するコンタクトホールが正常に形成されず、各層における導電層に対するコンタクトを適切に形成することが困難となる。 By the way, in a NAND flash memory having a stacked structure, it is assumed that the number of stacked memory cells is further increased in order to achieve higher integration. As the number of stacked memory cells increases, the distance between the uppermost conductive layer and the lowermost conductive layer increases. Therefore, when etching using the conductive layer in each layer as an etch stop layer is performed, the etching stop margin of the conductive layer disposed in the uppermost layer is small until the contact hole reaches the conductive layer disposed in the lowermost layer, There is a risk of damage to the wiring. As a result, contact holes reaching the conductive layer in each layer are not normally formed, and it is difficult to appropriately form a contact to the conductive layer in each layer.
　そこで、エッチストップ層として用いられる導電層の耐久性を向上することが期待されている。 Therefore, it is expected to improve the durability of the conductive layer used as the etch stop layer.
［ＮＡＮＤ型フラッシュメモリ１０の構造］
　図１は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の構造の一例を示す縦断面図である。図１に示すＮＡＮＤ型フラッシュメモリ１０は、図示しない複数のメモリセルを３次元的に配置した積層構造のＮＡＮＤ型フラッシュメモリである。ＮＡＮＤ型フラッシュメモリ１０は、基板１２と、多層膜１４と、絶縁層１６と、複数のコンタクトプラグ１８とを有する。なお、以下では、図１に示した多層膜１４の積層方向をＺ方向と定義し、各層の面内において、図１の紙面に垂直な方向をＸ方向と定義し、図１の紙面に平行な方向をＹ方向と定義する。 [Structure of NAND Flash Memory 10]
FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment. A NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged. The NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating layer 16, and a plurality of contact plugs 18. In the following, the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
　基板１２は、例えばシリコン等の半導体により形成される基板である。 The substrate 12 is a substrate formed of a semiconductor such as silicon.
　多層膜１４は、絶縁層２２と導電層２４とが交互に積層され、端部が階段状に形成された構造を有する。絶縁層２２と導電層２４との複数の対は、Ｚ方向に３次元的に配置された複数のメモリセルにそれぞれ対応する。多層膜１４の端部において絶縁層２２と導電層２４のそれぞれの対は、上層に配置された他の対によって覆われていない。それぞれの導電層２４は、例えば、各メモリセルのワード線として機能する。それぞれの導電層２４は、例えば、Ｗ（タングステン）等の金属で構成される。最上層に配置された導電層２４を除くそれぞれの導電層２４は、多層膜１４の端部において、上層に配置された絶縁層２２によって覆われておらず且つ他の部分よりも厚さが厚い部分（以下「厚膜部分」と呼ぶ）２４ａを有する。また、それぞれの絶縁層２２は、Ｚ方向に隣り合う導電層２４間を絶縁する層間絶縁膜として機能する。それぞれの絶縁層２２は、例えば、シリコン酸化膜等である。 The multilayer film 14 has a structure in which the insulating layers 22 and the conductive layers 24 are alternately stacked and the end portions are formed in a stepped shape. A plurality of pairs of the insulating layer 22 and the conductive layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction. Each pair of the insulating layer 22 and the conductive layer 24 at the end portion of the multilayer film 14 is not covered with another pair arranged in the upper layer. Each conductive layer 24 functions as a word line of each memory cell, for example. Each conductive layer 24 is made of a metal such as W (tungsten). Each conductive layer 24 except the conductive layer 24 disposed at the uppermost layer is not covered with the insulating layer 22 disposed at the upper layer at the end of the multilayer film 14 and is thicker than the other portions. A portion (hereinafter referred to as “thick film portion”) 24 a is included. In addition, each insulating layer 22 functions as an interlayer insulating film that insulates between the conductive layers 24 adjacent in the Z direction. Each insulating layer 22 is, for example, a silicon oxide film.
　絶縁層１６は、多層膜１４を覆うように多層膜１４上に形成される。絶縁層１６は、多層膜１４と、絶縁層１６上に配置される配線層との間を絶縁する層間絶縁膜として機能する。絶縁層１６は、例えば、シリコン酸化膜等である。 The insulating layer 16 is formed on the multilayer film 14 so as to cover the multilayer film 14. The insulating layer 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating layer 16. The insulating layer 16 is, for example, a silicon oxide film.
　本実施形態において、絶縁層１６には、Ｚ方向に絶縁層１６を貫通するコンタクトホールＣＨが複数形成されている。複数のコンタクトホールＣＨは、例えば、それぞれの導電層２４をエッチストップ層として、エッチングにより一括で形成される。複数のコンタクトホールＣＨがエッチングにより形成される場合、それぞれのコンタクトホールＣＨは、それぞれの導電層２４の厚膜部分２４ａへ到達する。それぞれの導電層２４の厚膜部分２４ａは、他の部分よりも厚さが厚いので、対応するコンタクトホールＣＨがエッチングによりそれぞれの導電層２４の厚膜部分２４ａに到達した場合でも、エッチストップマージンが大きく配線のダメージが発生し難くなる。 In this embodiment, the insulating layer 16 has a plurality of contact holes CH penetrating the insulating layer 16 in the Z direction. For example, the plurality of contact holes CH are collectively formed by etching using each conductive layer 24 as an etch stop layer. When a plurality of contact holes CH are formed by etching, each contact hole CH reaches the thick film portion 24 a of each conductive layer 24. Since the thick film portions 24a of the respective conductive layers 24 are thicker than the other portions, even when the corresponding contact holes CH reach the thick film portions 24a of the respective conductive layers 24 by etching, an etch stop margin is obtained. Is difficult to damage the wiring.
　それぞれのコンタクトプラグ１８は、それぞれのコンタクトホールＣＨ内に配置される。それぞれのコンタクトプラグ１８は、例えば、Ｗ等の金属で構成される。それぞれのコンタクトプラグ１８は、それぞれの導電層２４の厚膜部分２４ａに接触している。 Each contact plug 18 is disposed in each contact hole CH. Each contact plug 18 is made of a metal such as W, for example. Each contact plug 18 is in contact with the thick film portion 24 a of each conductive layer 24.
　このように、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０では、それぞれの導電層２４が厚膜部分２４ａを有し、厚膜部分２４ａへ到達するように、対応するコンタクトホールＣＨがエッチングにより形成される。これにより、対応するコンタクトホールＣＨがエッチングによりそれぞれの導電層２４の厚膜部分２４ａに到達した場合でも、エッチストップマージンが大きく配線のダメージが発生し難くなる。つまり、エッチストップ層として用いられる導電層２４の耐久性を向上することができる。その結果、積層構造のＮＡＮＤ型フラッシュメモリ１０において、各層における導電層２４へ到達するコンタクトホールＣＨが正常に形成される。 Thus, in the NAND flash memory 10 according to the present embodiment, each conductive layer 24 has the thick film portion 24a, and the corresponding contact hole CH is formed by etching so as to reach the thick film portion 24a. The As a result, even when the corresponding contact hole CH reaches the thick film portion 24a of each conductive layer 24 by etching, the etch stop margin is large and wiring damage is less likely to occur. That is, the durability of the conductive layer 24 used as an etch stop layer can be improved. As a result, in the NAND flash memory 10 having the stacked structure, the contact hole CH reaching the conductive layer 24 in each layer is normally formed.
［ＮＡＮＤ型フラッシュメモリ１０の製造方法］
　次に、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法について説明する。図２は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法の一例を示すフローチャートである。図３～図８は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法の一例を説明するための図である。 [Method of Manufacturing NAND Flash Memory 10]
Next, a method for manufacturing the NAND flash memory 10 according to this embodiment will be described. FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment. 3 to 8 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
　図２のステップＳ１０１及び図３に示すように、絶縁層５２と犠牲層５４とが交互に積層され、端部が階段状に形成された多層膜４４が基板４２上に作成される。図３に示した多層膜４４において、絶縁層５２は、例えば、ＳｉＯ２（シリコン酸化膜）等、絶縁層２２を形成するための材料によって構成される。また、犠牲層５４は、例えば、ＳｉＮ（シリコン窒化膜）等で構成される。最上層に配置された犠牲層５４は、図３に示すように、全体的に露出している。最上層に配置された犠牲層５４を除くそれぞれの犠牲層５４は、図３に示すように、多層膜４４の端部において、部分的に露出している。以下では、それぞれの犠牲層５４のうち、多層膜４４の端部において露出する部分を「露出部分」と呼ぶ。絶縁層５２は、第１の絶縁層の一例であり、犠牲層５４は、第１の犠牲層の一例である。なお、図３に示した多層膜４４の積層方向をＺ方向と定義し、各層の面内において、図３の紙面に垂直な方向をＸ方向と定義し、図３の紙面に平行な方向をＹ方向と定義する。 As shown in step S101 of FIG. 2 and FIG. 3, the multilayer film 44 in which the insulating layers 52 and the sacrificial layers 54 are alternately stacked and the end portions are formed stepwise is formed on the substrate 42. In the multilayer film 44 shown in FIG. 3, the insulating layer 52 is made of a material for forming the insulating layer 22, such as SiO 2 (silicon oxide film). The sacrificial layer 54 is made of, for example, SiN (silicon nitride film). As shown in FIG. 3, the sacrificial layer 54 disposed on the uppermost layer is exposed as a whole. Each sacrificial layer 54 except the sacrificial layer 54 disposed on the uppermost layer is partially exposed at the end of the multilayer film 44 as shown in FIG. Hereinafter, a portion of each sacrificial layer 54 exposed at the end of the multilayer film 44 is referred to as an “exposed portion”. The insulating layer 52 is an example of a first insulating layer, and the sacrificial layer 54 is an example of a first sacrificial layer. The stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction within the plane of each layer, and the direction parallel to the paper surface of FIG. It is defined as the Y direction.
　続いて、図２のステップＳ１０２及び図４に示すように、多層膜４４の端部において露出するそれぞれの犠牲層５４の露出部分に犠牲層５６が積層される。ステップＳ１０２における犠牲層５６の積層では、それぞれの犠牲層５４の露出部分の上面において犠牲層５６が選択的に成膜される。すなわち、犠牲層５６は、それぞれの犠牲層５４の露出部分の上面に成膜され、それぞれの犠牲層５４の側面に成膜されない。犠牲層５６の厚さは、それぞれの犠牲層５４の上層に形成されているそれぞれの絶縁層５２の厚さよりも薄い。犠牲層５６は、例えば、ＳｉＮ（シリコン窒化膜）等で構成される。犠牲層５６は、例えばＣＶＤ（Chemical　Vapor　Deposition）やＡＬＤ（Atomic　Layer　Deposition）等により、それぞれの犠牲層５４の露出部分に積層される。なお、犠牲層５６は、それぞれの犠牲層５４の露出部分だけでなく、最上層に配置された犠牲層５４にも積層される。犠牲層５６は、第２の犠牲層の一例である。この犠牲層５６は、例えば、ＡＬＤで成膜する事ができる。ＡＬＤは、例えば、第１の吸着工程、トリートメント工程、第２の吸着工程及び窒化工程を含む。ＡＬＤの具体的な条件は、以下の通りである。
＜第１の吸着工程＞
・エッチングガス：Ｃｌ２およびＡｒの混合ガス
・エッチング温度：２００～５００℃
・エッチング時間：１０～１８０ｓｅｃ
＜トリートメント工程＞
・エッチングガス：ＮＨ３およびＡｒの混合ガス
・エッチング温度：２００～５００℃
・エッチング時間：１０～１８０ｓｅｃ
＜第２の吸着工程＞
・エッチングガス：ＳｉＨ２Ｃｌ２およびＮ２の混合ガス
・エッチング温度：２００～５００℃
・エッチング時間：１０～１８０ｓｅｃ
＜窒化工程＞
・エッチングガス：Ｎ２
・エッチング温度：２００～５００℃
・エッチング時間：１０～１８０ｓｅｃ
　上記第１の吸着工程、トリートメント工程、第２の吸着工程及び窒化工程が繰り返されることによって、それぞれの犠牲層５４の露出部分の上面において犠牲層５６が選択的に成膜される。 Subsequently, as shown in step S <b> 102 of FIG. 2 and FIG. 4, a sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44. In the lamination of the sacrificial layer 56 in step S102, the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. That is, the sacrificial layer 56 is formed on the upper surface of the exposed portion of each sacrificial layer 54 and is not formed on the side surface of each sacrificial layer 54. The thickness of the sacrificial layer 56 is smaller than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54. The sacrificial layer 56 is made of, for example, SiN (silicon nitride film). The sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The sacrificial layer 56 is laminated not only on the exposed portion of each sacrificial layer 54 but also on the sacrificial layer 54 disposed on the uppermost layer. The sacrificial layer 56 is an example of a second sacrificial layer. The sacrificial layer 56 can be formed by ALD, for example. ALD includes, for example, a first adsorption process, a treatment process, a second adsorption process, and a nitridation process. Specific conditions for ALD are as follows.
<First adsorption step>
Etching gas: mixed gas of Cl 2 and Ar Etching temperature: 200 to 500 ° C.
・ Etching time: 10 to 180 sec
<Treatment process>
Etching gas: NH 3 and Ar mixed gas Etching temperature: 200-500 ° C
・ Etching time: 10 to 180 sec
<Second adsorption process>
Etching gas: SiH 2 Cl 2 and N 2 mixed gas Etching temperature: 200 to 500 ° C.
・ Etching time: 10 to 180 sec
<Nitriding process>
Etching gas: N 2
・ Etching temperature: 200 ~ 500 ℃
・ Etching time: 10 to 180 sec
By repeating the first adsorption process, the treatment process, the second adsorption process, and the nitriding process, the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54.
　続いて、図２のステップＳ１０３及び図５に示すように、多層膜４４上に絶縁層４６が積層される。ステップＳ１０３における絶縁層４６の積層では、犠牲層５６が覆われるように、多層膜４４上に絶縁層４６が積層される。絶縁層４６は、例えばＣＶＤやＡＬＤ等により、多層膜４４上に積層される。絶縁層４６は、第２の絶縁層の一例である。ここで、絶縁層４６は、例えばＳｉＯ２（シリコン酸化膜）である。絶縁層４６の具体的な成膜条件は、以下の通りである。
・原材料：　ＴＥＯＳ（オルトケイ酸テトラエチル）、Ｏ２
・形成温度：４００～９００℃
・形成時間：５～１２ｈｏｕｒｓ Subsequently, as shown in step S <b> 103 of FIG. 2 and FIG. 5, an insulating layer 46 is laminated on the multilayer film 44. In the lamination of the insulating layer 46 in step S103, the insulating layer 46 is laminated on the multilayer film 44 so that the sacrificial layer 56 is covered. The insulating layer 46 is stacked on the multilayer film 44 by, for example, CVD or ALD. The insulating layer 46 is an example of a second insulating layer. Here, the insulating layer 46 is, for example, SiO 2 (silicon oxide film). Specific film forming conditions for the insulating layer 46 are as follows.
Raw materials: TEOS (tetraethyl orthosilicate), O 2
-Formation temperature: 400-900 ° C
・ Formation time: 5-12hours
　続いて、図２のステップＳ１０４及び図６に示すように、それぞれの犠牲層５４及び犠牲層５６が導電層７４に置換される。すなわち、ステップＳ１０４における置換では、まず、それぞれの犠牲層５４及び犠牲層５６が、例えば、ウェットエッチング等の等方性エッチングにより除去される。その後、それぞれの犠牲層５４及び犠牲層５６が配置されていた空間に金属材料が充填されることによって、導電層７４が配置される。また、それぞれの犠牲層５４及び犠牲層５６が導電層７４に置換されることにより、それぞれの犠牲層５４の露出部分及び犠牲層５６が配置されていた空間に位置し且つ他の部分よりも厚さが厚い部分（以下「厚膜部分」と呼ぶ）７４ａが導電層７４に形成される。ここで、犠牲層５４及び犠牲層５６のウェットエッチングは、例えば、下記の条件で行われる。
・エッチング液：例えばＳＣ－１（Ｈ２Ｏ:Ｈ２Ｏ２:ＮＨ４ＯＨ＝５:１:１～５:１:０．０５の混合液）またはＳＰＭ（Ｈ２ＳＯ４：Ｈ２Ｏ２＝１：１～４：１の混合液）
・エッチング温度：２００～３５０℃
・エッチング時間：３０～１８０ｍｉｎ
　また、金属材料の充填による導電層７４の形成については、たとえば金属材料はタングステンであり、ＷＦ６やＷ（ＣＯ）６などの原料を用いたＣＶＤ（Chemical　Vapor　Deposition）やＡＬＤ（Atomic　Layer　Deposition）などの周知技術を用いることが可能である。 Subsequently, as shown in step S <b> 104 of FIG. 2 and FIG. 6, the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74. That is, in the replacement in step S104, the sacrificial layer 54 and the sacrificial layer 56 are first removed by isotropic etching such as wet etching, for example. Thereafter, the conductive layer 74 is disposed by filling the space in which the sacrificial layer 54 and the sacrificial layer 56 are disposed with a metal material. Further, by replacing the sacrificial layer 54 and the sacrificial layer 56 with the conductive layer 74, the sacrificial layer 54 is located in the space where the exposed portion and the sacrificial layer 56 were disposed and is thicker than the other portions. A thick portion (hereinafter referred to as a “thick film portion”) 74 a is formed in the conductive layer 74. Here, the wet etching of the sacrificial layer 54 and the sacrificial layer 56 is performed, for example, under the following conditions.
Etching solution: SC-1 (mixed solution of H 2 O: H 2 O 2 : NH 4 OH = 5: 1: 1 to 5: 1: 0.05) or SPM (H 2 SO 4 : H 2 O) 2 = mixture of 1: 1 to 4: 1)
・ Etching temperature: 200-350 ℃
・ Etching time: 30 ~ 180min
Further, regarding the formation of the conductive layer 74 by filling with a metal material, for example, the metal material is tungsten, and CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) using raw materials such as WF 6 and W (CO) 6 is used. It is possible to use known techniques such as.
　続いて、図２のステップＳ１０５及び図７に示すように、導電層７４をエッチストップ層として、絶縁層４６がエッチングされ、絶縁層４６に、Ｚ方向に絶縁層４６を貫通するコンタクトホールＣＨ´が複数形成される。複数のコンタクトホールＣＨ´は、例えば、ＲＩＥ（Reactive　Ion　Etching）等の異方性エッチングにより一括で形成される。ステップＳ１０５のエッチングでは、導電層７４のうち、厚膜部分７４ａに向かって、絶縁層４６がエッチングされる。これにより、それぞれのコンタクトホールＣＨ´は、導電層７４の厚膜部分７４ａへ到達する。導電層７４の厚膜部分７４ａは、他の部分よりも厚さが厚いので、対応するコンタクトホールＣＨ´がエッチングにより導電層７４の厚膜部分７４ａに到達した場合でも、エッチストップマージンが大きく配線のダメージが発生し難くなる。ここで、コンタクトホールＣＨ´のエッチング方法は、例えばドライエッチングであり、エッチング装置としては、容量結合プラズマ（ＣＣＰ）型装置を採用することができる。この時のエッチングの具体的な条件は以下の通りである。
・エッチングガス：ＣＦ４、ＡｒおよびＯ２の混合ガス
・ガス流量：ＣＦ４／Ａｒ／Ｏ２＝１００～３００ｓｃｃｍ／５００～１０００ｓｃｃｍ／５０～１００ｓｃｃｍ
・エッチング温度：２０～１００℃
・エッチング時間：１～３００ｍｉｎ
・エッチングパワー：周波数１３～６０ＭＨｚで５００～３０００Ｗ Subsequently, as shown in step S105 of FIG. 2 and FIG. 7, the insulating layer 46 is etched using the conductive layer 74 as an etch stop layer, and a contact hole CH ′ penetrating the insulating layer 46 in the Z direction is formed in the insulating layer 46. A plurality of are formed. The plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching), for example. In the etching in step S105, the insulating layer 46 is etched toward the thick film portion 74a in the conductive layer 74. As a result, each contact hole CH ′ reaches the thick film portion 74 a of the conductive layer 74. Since the thick film portion 74a of the conductive layer 74 is thicker than the other portions, even when the corresponding contact hole CH ′ reaches the thick film portion 74a of the conductive layer 74 by etching, the etching stop margin is large. The damage is less likely to occur. Here, the etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as the etching apparatus. Specific conditions for etching at this time are as follows.
Etching gas: CF 4 , Ar and O 2 mixed gas Gas flow rate: CF 4 / Ar / O 2 = 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 1 to 300 min
Etching power: 500 to 3000 W at a frequency of 13 to 60 MHz
　続いて、図２のステップＳ１０６及び図８に示すように、それぞれのコンタクトホールＣＨ´内に金属材料４８が充填される。これにより、図１２に示すように、金属材料４８と、導電層７４の厚膜部分７４ａとが接触する。金属材料４８は、Ｗ（タングステン）等、コンタクトプラグ１８を形成するための金属材料であり、ＷＦ６やＷ（ＣＯ）６などの原料を用いたＣＶＤやＡＬＤなどの周知技術を用いることが可能である。このようにして、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０が製造される。なお、基板４２は、基板１２として機能し、絶縁層５２は、絶縁層２２として機能し、導電層７４は、導電層２４として機能し、絶縁層４６は、絶縁層１６として機能する。また、金属材料４８は、コンタクトプラグ１８として機能し、コンタクトホールＣＨ´は、コンタクトホールＣＨとして機能する。 Subsequently, as shown in step S106 of FIG. 2 and FIG. 8, a metal material 48 is filled in each contact hole CH ′. Thereby, as shown in FIG. 12, the metal material 48 and the thick film portion 74a of the conductive layer 74 are in contact with each other. The metal material 48 is a metal material for forming the contact plug 18 such as W (tungsten), and a well-known technique such as CVD or ALD using a raw material such as WF 6 or W (CO) 6 can be used. It is. In this way, the NAND flash memory 10 according to this embodiment is manufactured. Note that the substrate 42 functions as the substrate 12, the insulating layer 52 functions as the insulating layer 22, the conductive layer 74 functions as the conductive layer 24, and the insulating layer 46 functions as the insulating layer 16. The metal material 48 functions as the contact plug 18 and the contact hole CH ′ functions as the contact hole CH.
　以上、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法によれば、多層膜４４の端部において露出するそれぞれの犠牲層５４の露出部分に犠牲層５６を積層し、絶縁層４６を積層し、それぞれの犠牲層５４及び犠牲層５６を導電層７４に置換する。そして、導電層７４のうち、それぞれの犠牲層５４の露出部分及び犠牲層５６が配置されていた空間に位置し且つ他の部分よりも厚さが厚い部分（つまり、厚膜部分７４ａ）に向かって、絶縁層４６をエッチングする。ここで、導電層７４の厚膜部分７４ａは、他の部分よりも厚さが厚いので、対応するコンタクトホールＣＨ´がエッチングにより導電層７４の厚膜部分７４ａに到達した場合でも、エッチストップマージンが大きく配線のダメージが発生し難くなる。つまり、本実施形態によれば、エッチストップ層として用いられる導電層７４の耐久性を向上することができる。その結果、積層構造のＮＡＮＤ型フラッシュメモリ１０において、各層における導電層７４へ到達するコンタクトホールＣＨ´が正常に形成される。 As described above, according to the method for manufacturing the NAND flash memory 10 according to the present embodiment, the sacrificial layer 56 is stacked on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44, and the insulating layer 46 is stacked. Each of the sacrificial layer 54 and the sacrificial layer 56 is replaced with a conductive layer 74. Then, the conductive layer 74 is located in the space where the exposed portion of the sacrificial layer 54 and the sacrificial layer 56 are disposed, and toward the portion thicker than the other portions (that is, the thick film portion 74a). Then, the insulating layer 46 is etched. Here, since the thick film portion 74a of the conductive layer 74 is thicker than the other portions, even when the corresponding contact hole CH ′ reaches the thick film portion 74a of the conductive layer 74 by etching, an etch stop margin is obtained. Is difficult to damage the wiring. That is, according to this embodiment, the durability of the conductive layer 74 used as the etch stop layer can be improved. As a result, in the NAND flash memory 10 having the stacked structure, the contact hole CH ′ reaching the conductive layer 74 in each layer is normally formed.
　また、本実施形態によれば、犠牲層５６の厚さは、それぞれの犠牲層５４の上層に形成されているそれぞれの絶縁層５２の厚さよりも薄い。そのため、それぞれの犠牲層５４及び犠牲層５６が導電層７４に置換された場合に、多層膜４４の積層方向に隣り合う導電層７４が、それぞれの絶縁層５２によって、互いに電気的に絶縁される。その結果、積層構造のＮＡＮＤ型フラッシュメモリ１０において、各層における導電層７４間の短絡が回避される。 Further, according to the present embodiment, the thickness of the sacrificial layer 56 is thinner than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54. Therefore, when the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74, the conductive layers 74 adjacent in the stacking direction of the multilayer film 44 are electrically insulated from each other by the respective insulating layers 52. . As a result, in the NAND flash memory 10 having the stacked structure, a short circuit between the conductive layers 74 in each layer is avoided.
　また、本実施形態によれば、犠牲層５６を積層する工程では、それぞれの犠牲層５４の露出部分の上面において犠牲層５６を選択的に成膜する。これにより、犠牲層５６を高効率に積層することができる。 Further, according to the present embodiment, in the step of laminating the sacrificial layer 56, the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. Thereby, the sacrificial layer 56 can be laminated with high efficiency.
４４　多層膜
４６　絶縁層（第２の絶縁層）
４８　金属材料
５２　絶縁層（第１の絶縁層）
５４　犠牲層（第１の犠牲層）
５６　犠牲層（第２の犠牲層）
７４　導電層 44 Multilayer film 46 Insulating layer (second insulating layer)
48 Metal material 52 Insulating layer (first insulating layer)
54 Sacrificial layer (first sacrificial layer)
56 Sacrificial layer (second sacrificial layer)
74 Conductive layer

Claims (3)

  1. 　第１の絶縁層と第１の犠牲層とが交互に積層され、端部が階段状に形成された多層膜の前記端部において露出するそれぞれの前記第１の犠牲層の露出部分に第２の犠牲層を積層する工程と、
    　前記第２の犠牲層が覆われるように前記多層膜上に第２の絶縁層を積層する工程と、
    　それぞれの前記第１の犠牲層及び前記第２の犠牲層を導電層に置換する工程と、
    　前記導電層のうち、それぞれの前記第１の犠牲層の露出部分及び前記第２の犠牲層が配置されていた空間に位置し且つ他の部分よりも厚さが厚い部分に向かって、前記第２の絶縁層をエッチングする工程と
    　を含むことを特徴とする不揮発性記憶装置の製造方法。     The first insulating layer and the first sacrificial layer are alternately laminated, and the second sacrificial layer is exposed on the exposed portion of the first sacrificial layer exposed at the end portion of the multilayer film having the end portion formed in a step shape. Laminating a sacrificial layer of
    Laminating a second insulating layer on the multilayer film so as to cover the second sacrificial layer;
    Replacing each of the first sacrificial layer and the second sacrificial layer with a conductive layer;
    Of the conductive layer, the first sacrificial layer is exposed to the exposed portion of the first sacrificial layer and the second sacrificial layer is located in a space where the first sacrificial layer is located and the first sacrificial layer is thicker than the other portions. And a step of etching the insulating layer. 2. A method of manufacturing a nonvolatile memory device, comprising:
  2. 　前記第２の犠牲層の厚さは、それぞれの前記第１の犠牲層の上層に形成されているそれぞれの前記第１の絶縁層の厚さよりも薄いことを特徴とする請求項１に記載の不揮発性記憶装置の製造方法。 The thickness of the said 2nd sacrificial layer is thinner than the thickness of each said 1st insulating layer currently formed in the upper layer of each said 1st sacrificial layer, It is characterized by the above-mentioned. A method for manufacturing a nonvolatile memory device.
  3. 　前記第２の犠牲層を積層する工程では、それぞれの前記第１の犠牲層の露出部分の上面において前記第２の犠牲層を選択的に成膜することを特徴とする請求項１又は２に記載の不揮発性記憶装置の製造方法。 3. The method according to claim 1, wherein in the step of laminating the second sacrificial layer, the second sacrificial layer is selectively formed on an upper surface of an exposed portion of each of the first sacrificial layers. The manufacturing method of the non-volatile memory device of description.
PCT/JP2019/007555 2018-03-02 2019-02-27 Production method for nonvolatile storage device WO2019168027A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018037568 2018-03-02
JP2018-037568 2018-03-02

Publications (1)

Publication Number Publication Date
WO2019168027A1 true WO2019168027A1 (en) 2019-09-06

Family

ID=67805409

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/007555 WO2019168027A1 (en) 2018-03-02 2019-02-27 Production method for nonvolatile storage device

Country Status (2)

Country Link
TW (1) TW201944581A (en)
WO (1) WO2019168027A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802851A (en) * 2019-11-14 2021-05-14 爱思开海力士有限公司 Method of forming thin layer and method of manufacturing nonvolatile memory device using the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113437083A (en) * 2021-06-29 2021-09-24 长江存储科技有限责任公司 Preparation method of three-dimensional memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20180053686A1 (en) * 2016-08-16 2018-02-22 Chung-il Hyun Semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20180053686A1 (en) * 2016-08-16 2018-02-22 Chung-il Hyun Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802851A (en) * 2019-11-14 2021-05-14 爱思开海力士有限公司 Method of forming thin layer and method of manufacturing nonvolatile memory device using the same

Also Published As

Publication number Publication date
TW201944581A (en) 2019-11-16

Similar Documents

Publication Publication Date Title
CN108735756B (en) Substrate processing method and semiconductor device manufactured by the same
CN108807169B (en) Substrate processing method and semiconductor device manufactured using the same
US9419012B1 (en) Three-dimensional memory structure employing air gap isolation
EP3271944B1 (en) Honeycomb cell structure three-dimensional non-volatile memory device
KR100809330B1 (en) Semiconductor devices free stress of gate spacer and method for fabricating the same
KR102650930B1 (en) 3D memory device and manufacturing method thereof
JP2022508036A (en) 3D memory device
US20130307050A1 (en) Nonvolatile memory device and method for fabricating the same
CN107195633A (en) Semiconductor storage and its manufacture method
CN111403397B (en) 3D NAND memory and manufacturing method thereof
KR20140025054A (en) Nonvolatile memory device and method for fabricating the same
JP2008193078A (en) Wiring structure of semiconductor device, and forming method thereof
WO2019168027A1 (en) Production method for nonvolatile storage device
CN112310103A (en) Vertical semiconductor device and method for manufacturing vertical semiconductor device
TWI615949B (en) Three-dimensional memory device and method of forming the same
WO2021020084A1 (en) Semiconductor device
WO2019168036A1 (en) Production method for nonvolatile storage device
US9917097B2 (en) Method of manufacturing semiconductor device
CN113284907B (en) Three-dimensional memory and manufacturing method thereof
US20220246636A1 (en) Method of forming a stepped surface in a three-dimensional memory device and structures incorporating the same
JP2022144220A (en) Semiconductor device manufacturing method and etching method
JP2022142897A (en) Pattern formation method and semiconductor device manufacturing method
TW202323567A (en) Hard mask film including graphene layer intercalated structure and manufacturing method thereof
TW202404108A (en) Integrated chip and method for forming a trench capacitor
CN116249350A (en) Semiconductor structure, manufacturing method thereof, memory device and memory system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19759991

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19759991

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP