CN111403397B

CN111403397B - 3D NAND memory and manufacturing method thereof

Info

Publication number: CN111403397B
Application number: CN202010146798.6A
Authority: CN
Inventors: 王贝寒; 徐伟; 周文斌; 黄攀; 夏季
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-03-05
Filing date: 2020-03-05
Publication date: 2021-05-07
Anticipated expiration: 2040-03-05
Also published as: CN113178452A; CN111403397A; CN113178452B

Abstract

The invention provides a 3D NAND memory and a manufacturing method thereof, wherein a first top selection gate tangent is formed at a position where a common source contact part is to be formed before a gate line gap is formed, the width of the first top selection gate tangent is larger than that of the gate line gap, so that the stack layer is replaced by an insulating material forming the top selection gate tangent around the formed common source contact part, the formation window of the contact part forming the common source is increased, and even if the contact part is slightly deviated from the contact of a common source, the contact part cannot contact with gate layers on two sides of the bridge common source, so that the electric leakage risk of a device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent. The first top selection gate tangent line and the second top selection gate tangent line can be formed by using the same mask, so that the preparation of the mask is saved, the etching step is saved, and the manufacturing cost of the memory is reduced.

Description

3D NAND memory and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof.

Background

As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit are becoming more and more popular.

In a 3D NAND process, a gate line gap is usually formed to form a stacked gate layer, and in order to control an effective gate area, the size of the gate line gap needs to be limited, so that the size of the gate line gap is very limited, and when a common source is formed through the gate line gap and a contact portion of the common source is further formed, the position of the contact portion and the position of the common source are slightly deviated, so that the contact portion bridges the gate layer on two sides of the common source, which causes damages such as electric leakage and the like, and seriously affects the use of the device.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a 3D NAND memory and a method for manufacturing the same, in which top select gate tangents are formed on both sides or around a common source contact of a common source, and replace gate stack layers on both sides of the common source contact with insulating layers, so that a formation window of a contact portion of the common source is increased, even if the contact portion is deviated from the common source contact, the contact portion does not bridge to gate layers on both sides, a risk of leakage is reduced, and a yield of the device is improved.

To achieve the above and other related objects, the present invention provides a method of manufacturing a 3D NAND memory: the manufacturing method comprises the following steps:

providing a substrate, wherein the substrate is provided with a substrate surface in a first direction and a second direction which are mutually orthogonal, and a stacked structure formed by alternately stacking insulating layers and sacrificial layers is formed on the substrate surface along a third direction which is vertical to the substrate surface;

forming a plurality of first top select gate tangents in the stack structure;

forming a gate line slit extending in the first direction in the stacked structure, the gate line slit passing through the first top select gate tangent line, and the first top select gate tangent line forming a sidewall of the gate line slit at the first top select gate tangent line;

forming a common source in the gate line slit, at the first top select gate tangent, the first top select gate tangent covering a sidewall of the common source;

forming a contact electrically connected with the common source, wherein the contact is positioned above the common source with the side wall covered by the first top selection gate tangent.

Optionally, providing a substrate having a substrate surface in a first direction and a second direction orthogonal to each other, and forming a stacked structure on the substrate surface in which insulating layers and sacrificial layers are alternately stacked in a third direction perpendicular to the substrate surface further includes:

depositing the insulating layer and the sacrificial layer on the substrate in sequence to form a first stacked structure;

forming a lower channel hole in the first stacked structure penetrating the stacked structure in the third direction;

continuing to deposit the insulating layer and the sacrificial layer over the first stacked structure to form a second stacked structure.

Optionally, the method for manufacturing a 3D NAND memory further includes: at least one second top select gate tangent is formed in the stack structure.

Optionally, forming a plurality of the first top select gate tangents on top of the stack structure comprises:

etching the stacked structure to form a plurality of first grooves, wherein the first grooves are distributed at intervals in the first direction;

and filling an insulating material in the first groove to form the top selection gate tangent.

Optionally, forming at least one second top select gate cut in the stack structure comprises:

etching the stacked structure to form at least one second groove, wherein the second groove continuously extends in the first direction;

and filling an insulating material in the second groove to form a second top selection gate tangent.

Optionally, the depth of the first trench and the second trench in the third direction is between 1 and 10 layers of the stacked structure.

Optionally, in the second direction, a width of the first top selection gate tangent is greater than a width of the gate line slit.

Optionally, the first top selection gate tangent line includes a first portion and a second portion spaced apart from each other in the second direction, and a spacing distance between the first portion and the second portion is less than or equal to a width of the gate line slit.

Optionally, the 3D NAND memory manufacturing method further includes the steps of:

etching the second stacked structure to form an upper channel hole, wherein the upper channel hole is communicated with the lower channel hole to form a channel hole penetrating through the stacked structure;

forming a selective epitaxial structure at the bottom of the channel hole;

sequentially forming a barrier layer, a charge trapping layer, a tunneling layer and a channel layer on the side wall of the channel hole, wherein the channel layer is communicated with the selective epitaxial structure;

and filling a dielectric layer in the channel hole.

Optionally, the 3D NAND memory manufacturing method further includes:

removing the sacrificial layer in the stacked structure through the gate line gap etching to form a gate groove;

and depositing a gate conductive material in the gate trench to form a gate layer.

Optionally, the forming of the common source in the gate line slit further comprises:

forming a bottom conducting layer at the bottom of the grid line gap;

forming a gate isolation layer on the side wall of the gate line gap;

filling a source electrode conducting material in the grid line gap;

forming the common source contact over the source conductive material.

Optionally, forming a contact electrically connected to the common source at the first top select gate tangent position further comprises:

forming a contact hole at a position corresponding to a tangent line of the first top selection gate, wherein the width of the contact hole is less than or equal to the width of the gate line gap in the first direction;

and filling a conductive material in the contact hole to form a contact part electrically conducted with the common source contact.

The present invention also provides a 3D NAND memory, comprising:

a substrate having a substrate surface in a first direction and a second direction orthogonal to each other, a stacked structure formed on the substrate surface in a third direction perpendicular to the substrate surface, the stacked structure including insulating layers and gate electrode layers alternately stacked;

a first top select gate tangent line formed in a top select gate of the gate layer;

a gate line slit extending in the first direction and penetrating the stacked structure in the third direction, the gate line slit passing through the first top select gate tangent, and the first top select gate tangent forming a sidewall of the gate line slit at the first top select gate tangent;

a common source formed in the gate line slit, at the top select gate tangent, the top select gate tangent covering a sidewall of the common source;

and forming a contact part which is electrically conducted with the common source above the common source, wherein the contact part is positioned above the common source, the side wall of which is covered by the top selection gate tangent line.

Optionally, the 3D NAND memory further comprises at least one second top select gate tangent.

Optionally, the first top select gate tangents are spaced apart in the first direction, and the second top select gate tangents are continuously distributed in the first direction.

Optionally, the 3D NAND memory further includes a channel structure penetrating the stacked structure in the third direction, and includes:

a selective epitaxial structure formed at the bottom of the channel hole;

the barrier layer, the charge trapping layer, the tunneling layer and the channel layer are sequentially distributed from the side wall of the channel hole to the center, and the channel layer is communicated with the selective epitaxial structure;

a dielectric layer formed in the channel hole.

Optionally, the depths of the first top selection gate tangent line and the second top selection gate tangent line in the third direction are 1-10 layers of the stacked structure.

As described above, the 3D NAND memory and the method for manufacturing the same according to the present invention have at least the following advantageous effects:

when the 3D NAND memory is formed, a plurality of first top selection gate tangents distributed at intervals in a first direction and second top selection gate tangents continuously extending along the first direction are formed on the top of a stacked structure at the same time through the same mask, then a gate line gap continuously extending along the first direction is formed, the gap penetrates through the first top selection gate tangents, and the width of the first top selection gate tangents is larger than that of the gate line gap in a second direction perpendicular to the first direction. And then forming a common source contact in the gate line gap, and forming a common source contact part at a position corresponding to the first top selection gate tangent line, wherein the width of the contact part is smaller than that of the gate line gap in the second direction, so that a structure that the width of the contact part is less than that of the gate line gap and less than that of the first top selection gate tangent line is formed. Therefore, the insulating layer forming the first top selection gate tangent line is used for replacing the original laminated gate layer around the common source contact, so that the forming window of the contact part of the common source is increased, and even if the contact part is slightly deviated from the common source contact, the contact part cannot bridge the gate layers on two sides of the common source contact, so that the leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent.

On the other hand, the method simultaneously forms the first top selection gate tangent line and the second top selection gate tangent line through the same mask, saves the preparation of the mask and the etching step, and therefore reduces the manufacturing cost of the memory.

Drawings

FIG. 1 is a flow chart of a method for manufacturing a 3D NAND memory according to an embodiment of the invention.

Fig. 2 is a schematic diagram showing the position relationship of the common source and the common source contact portion to be formed in the manufacturing process of the 3D NAND memory, and the view is a schematic diagram of a top view of the substrate.

Fig. 3 shows a schematic view of the structure of the substrate provided, this view being a schematic cross-sectional view along the line L-L in the Y direction shown in fig. 1.

Fig. 4 is a schematic structural view illustrating the formation of a first trench in the structure shown in fig. 3.

Fig. 5 is a schematic diagram illustrating a position relationship of the first trench and the common source/drain contact formed in fig. 4, which is also a schematic diagram of a top view of the substrate.

Fig. 6 is a schematic structural view illustrating a top selection gate cut line formed by filling an insulating layer in the first trench shown in fig. 4.

Fig. 7 is a schematic structural diagram illustrating the formation of a channel structure and the formation of an insulating cap layer in the structure shown in fig. 6.

Fig. 8 is a schematic view illustrating a structure in which a gate line slit is formed in the structure shown in fig. 7.

Fig. 9 shows a schematic structure of forming a gate.

Fig. 10 is a schematic diagram illustrating a structure of forming a common source in the gate line slit shown in fig. 9.

Fig. 11 is a schematic diagram of a structure of a contact portion for forming a common source above the common source shown in fig. 9.

Fig. 12 is an enlarged schematic view of the structure in circle a of fig. 11.

Fig. 13 is a schematic structural diagram illustrating formation of the first trench and the second trench in a preferred embodiment of the first embodiment.

FIG. 14 is a schematic diagram illustrating a structure of forming a first top select gate tangent and a second top select gate tangent in the structure shown in FIG. 13.

FIG. 15 is a schematic diagram illustrating the formation of a channel structure and an insulating cap layer in the structure shown in FIG. 14.

Fig. 16 is a schematic structural diagram illustrating a first trench formed in the method for manufacturing a 3D NAND memory according to the second embodiment of the present invention.

Fig. 17 is a schematic diagram illustrating a position relationship of the first trench and the common source/drain contact shown in fig. 16, which is also a schematic diagram of a top view of the substrate.

Fig. 18 is a schematic view illustrating a structure of filling an insulating layer in the first trench shown in fig. 16 to form a top select gate tangent line.

FIG. 19 is a schematic diagram of a stack structure formed by the method for manufacturing a 3D NAND memory according to the fourth embodiment of the invention.

Fig. 20 is a schematic structural view illustrating formation of a first trench in the stacked structure shown in fig. 19.

Description of the element reference numerals

100 substrate

101 stack structure

100-1 first Stacking Structure

100-2 second Stacking Structure

1011 insulating layer

1012 sacrificial layer

102 lower channel hole

1021 epitaxial structure

1022 substitute material

103 first trench

103' second trench

104 common source

105 common source contact

106 first top select gate tangent

106' second top select gate tangent

107 upper channel hole

108 channel structure

1081 memory layer

1082 channel layer

1083 dielectric material layer

109 gap of grid line

1091 bottom conducting layer of common source

1092 Gate isolation layer

1093 Source conductive Material

1094 common source contact

110 grid layer

111 insulating cap layer

203 first trench

203' second trench

2031A first portion of the first groove

2032 second part of the first groove

206 first top select gate tangent

206' second pseudo top select gate tangent

303 first trench

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated.

Example one

In the manufacturing process of the 3D NAND, it is usually necessary to form a gate line slit, remove and replace a sacrificial layer in the stacked structure through the gate line slit, form a gate layer, form a common source of the array memory structure at the position of the gate line slit, and then form a contact of the common source above the common source. Referring to fig. 1, due to the size of the device and the area of the gate in the device, the size of the gate line gap and the common source 104 formed therein is very limited, the contact 105 of the common source is formed above the common source 104, and the limited common source size limits the formation window of the contact 105, so that if the contact 105 is formed on both sides of the active source 104 with a slight deviation in position during the formation of the contact 105, the contact easily bridges the gate layers on both sides of the common source, which may cause device leakage.

In order to solve the above problem, the present embodiment provides a method for forming a step structure of a 3D NAND memory, as shown in fig. 2, the method including the steps of:

step S101: providing a substrate, forming a stacked structure on the substrate, wherein the substrate is provided with a substrate surface in a first direction and a second direction which are mutually orthogonal, and the stacked structure formed by alternately stacking an insulating layer and a sacrificial layer is formed on the substrate surface along a third direction which is vertical to the substrate surface;

in the present embodiment, the stacked structure formed on the substrate includes the insulating layers and the sacrificial layers alternately arranged, and the number of stacked layers may be 64 layers, 128 layers, or even more. The stacked structure can be formed by sequentially stacking, and can also be formed in multiple times when the number of layers is large, wherein a part of stacked layers are formed above the substrate, and then the rest stacked layers are continuously formed above the first stacked structure to form the final stacked structure. The present embodiment is described by taking an example of sequentially forming a first stack and a second stack over a substrate.

As shown in fig. 3, a cross-sectional view along line L-L in the Y direction shown in fig. 1 is shown. The substrate 100 is provided, and the insulating layer 1011 and the sacrificial layer 1012 are alternately deposited on the substrate 100 in sequence to form the first stacked structure 100-1. Then, a sacrificial layer 1012 and an insulating layer 1011 are alternately formed in this order on the first stacked structure 100-1, and finally, the stacked structure 101 is formed. In this embodiment, the insulating layer 1011 and the sacrificial layer 1012 may be silicon oxide and silicon nitride, respectively, and the stacked structure 101 may be formed by alternately depositing silicon nitride and silicon oxide on the substrate 100 in sequence by using Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or other suitable deposition methods.

In a preferred embodiment of the present embodiment, after the first stacked structure 100-1 is formed and before the second stacked structure 100-2 is formed, the first stacked structure 100-1 is etched until a portion of the substrate to form the lower channel hole 102, and then the epitaxial structure 1021 is formed from the substrate at the bottom of the channel hole 102. More preferably, a replacement material 1022 is filled over the epitaxial structure 1021 to prevent contamination or damage to the trench hole during subsequent formation of the upper stack structure.

Then, a sacrificial layer 1012 and an insulating layer 1011 are alternately deposited over the first stacked structure 100-1 having the lower channel hole 102 formed therein to form an upper stacked structure 100-2, thereby forming the entire stacked structure 101.

Step S102: forming a plurality of first top select gate tangents at the top of the stack structure, the plurality of first top select gate tangents extending continuously in the first direction;

in the present embodiment, the stacked structure is etched by, for example, a dry etching process, as shown in fig. 4, a plurality of first trenches 103 are formed in the stacked structure, the plurality of first trenches 103 are distributed at intervals in a first direction, i.e., in the X direction shown in fig. 1, and the depth of the first trenches 103 in a third direction perpendicular to a plane formed by the X direction and the Y direction may be 1 to 10 layers or 6 to 10 layers of stacked layers, for example, the thickness of five layers of stacked layers shown in fig. 4 of the present embodiment. Still referring to fig. 1, the first trench 103 is distributed corresponding to a contact 105 of a common source to be formed later, and a width W of the first trench 103 is greater than a width of a gate line slit to be formed later in a second direction, the Y direction shown in fig. 1.

The positional relationship between the first trench 103 formed in the stacked structure and the subsequently formed common source 104 and the contact 105 thereof is shown in fig. 5. In the second direction, i.e. the Y-direction shown in fig. 5, the first trench 103 has a width W which is larger than the width of the common source and of course also larger than the width of the contact 105. The length of the first groove in the X direction is not limited, but may be longer than the length of the contact portion 105 for cost reasons.

After forming the first trench 103 and the second trench 103', the first trench 103 is filled with an insulating material as shown in fig. 6, and a first top select gate tangent 106 is formed in the first trench 103. Preferably, simultaneously in the stackingThe insulating material is formed over the structure. The insulating material may be an oxide, such as silicon oxide or the like. The thickness of the insulating material over the stacked structure may be

In a preferred embodiment of the present embodiment, after forming the first top select gate tangent, a step of forming the channel structure 108 shown in fig. 7 is further included. Specifically, the step of forming the channel structure includes:

the second stack 100-2 is etched to form an upper channel hole 107 corresponding to the lower channel hole 102 (as shown in fig. 7), and the replacement material 1022 in the lower channel hole 102 is removed to form a channel hole penetrating the entire stack 101. A memory layer 1081 and a channel layer 1082 are then sequentially formed on the sidewalls of the channel hole as shown in fig. 7, more preferably, a dielectric material layer 1083 is filled in the core portion of the channel hole, and still more preferably, an air gap 1084 is reserved in the central portion of the channel hole, as shown in fig. 7, wherein the air gap 1084 may be an elliptical or elliptical-like structure. As is well known, the memory layer 1081 is a multi-layer structure including a blocking layer, a charge trapping layer, and a tunneling layer, which are not shown in detail herein. In an embodiment of the invention, the blocking layer may be a single layer or a stacked layer or a mixed layer of materials such as aluminum oxide, silicon oxynitride, and the like. The charge trapping layer may be a single layer or a stack of layers of materials such as silicon nitride and silicon oxynitride, or a wide bandgap material such as a mixed layer. The tunneling layer can be a single layer or a lamination layer or a mixed layer of silicon oxide and silicon oxynitride. The channel layer may be polysilicon. The layer of dielectric material may be silicon oxide.

After the channel structure is formed, forming an insulating cap layer 111 over the stacked structure, for example, the insulating cap layer 111 may be formed by depositing an insulating material over the stacked structure, and the thickness of the insulating cap layer 111 may be

Step S103: forming a gate line slit extending in the first direction in the stacked structure, the gate line slit passing through the first top select gate tangent line, and the first top select gate tangent line forming a sidewall of the gate line slit at the first top select gate tangent line;

and controlling the pattern through a mask, sequentially performing hard mask deposition, photoresist spin coating and baking, exposure and dry etching, and etching the stacked structure until the stacked structure penetrates through a part of the silicon substrate to form a gate line gap 109 which penetrates through the stacked structure and extends in the X direction.

As shown in fig. 8, the width of the gate line slit is smaller than the width of the first top selection gate cut line 106, and thus, the insulating material forming the first top selection gate cut line 106 is disposed at both sides of the gate line slit at the upper portion of the stack structure, instead of the sacrificial layer and the insulating layer which are alternately arranged.

Step S104: forming a common source in the gate line slit, at the first top select gate tangent, the first top select gate tangent covering a sidewall of the common source;

in this embodiment, before forming the common source in the gate line gap, a gate layer is first formed, specifically, after forming the gate line gap 109, a gate trench is formed by removing the sacrificial layer in the stacked structure by wet etching with the gate line gap 109 as a cut-in, and a gate conductive material is deposited in the gate trench to form a gate layer, so as to form a stacked gate 110 as shown in fig. 9. Wherein the top layer of the stacked structure forms a top select gate, and the conductive material may be tungsten, diamond, nickel, titanium, or the like.

After the stacked gates are formed, as shown in fig. 10, high-concentration active ions are injected into the bottom of the gate line gap to form a bottom conductive layer 1091 of the common source; then, a gate isolation layer 1092 is formed on the sidewall of the gate line gap, and a source conductive material 1093 is filled in the gate line gap, where the source conductive material 1093 may be polysilicon or the like. The source conductive material 1093 is preferably flush with the bottom of the first trench 103 or lower than the bottom of the first trench 103. The source conductive material 1093 may preferably be flush with the bottom of said first trench 103 or lower than the bottom of the first trench 103, e.g. by controlling the filling time of the source conductive material or by etch back. More preferably, only the source conductive material at the location of the first top select gate tangent 106 may be etched back such that the source conductive material 1093 is level with or below the bottom of the first trench 103, as shown in fig. 10. A conductive material is then deposited over the source conductive material, forming common source contact 1094. Since the width of the gate line gap is smaller than the width of the first trench 103, the common source contact 1094 is flanked by the insulating material filling the first trench 103 forming the first top select gate cut line 106, rather than the alternating sacrificial and insulating layers.

Step S105: forming a contact electrically connected with the common source, wherein the contact is positioned above the common source with the side wall covered by the first top selection gate tangent.

After the common source contact is formed, a contact 105 that is electrically conductive to the common source contact is formed over the common source, as shown in fig. 11 and shown. For example, an insulating layer is first deposited over the stacked structure forming the common source, contact holes may be formed at positions corresponding to the first trenches 103 (i.e., the first top select gate tangents 106) by pattern control, and then the contact holes are filled with a conductive material to form the contact portions 105. The conductive material may be the same metal material as the conductive material of the common source contact or a different metal material.

As shown in the enlarged view of the contact 105 shown in fig. 12, the two sides of the common source contact are insulating layers, so that the formation window for forming the contact is increased, and even if the contact is slightly deviated from the common source contact, the contact does not contact the gate layer bridging the two sides of the common source contact, so that the leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent.

In a preferred embodiment of this embodiment, at least one second top select gate tangent is formed at the same time as the first top select gate tangent is formed.

As shown in fig. 13, the first trenches 103 and the second trenches 103 'are formed simultaneously, and the second trenches 103' extend continuously in the first direction (X direction). Preferably, the first trench and the second trench are formed by using the same mask layer, thereby saving the manufacturing steps. Then, as shown in fig. 14, the first trench 103 and the second trench 103 'are filled with an insulating material to form a first top select gate cut line 106 and a second top select gate cut line 106'. A channel structure is then formed. In a more preferred embodiment, the width of the second top select gate tangent 106 ' (i.e., the second trench 103 ') is larger than the aperture of the channel hole, so that the second top select gate tangent 106 ' can also form the sidewall of the channel hole when forming the channel structure, as shown in fig. 15. Therefore, when the contact part of the channel structure is formed, the forming window of the contact part of the channel structure can be increased, and the manufacturing difficulty of the contact part of the channel structure is reduced.

As shown in fig. 13 to 15, only one second top select gate tangent is formed as an example, and it is understood that a plurality of second top select gate tangents may be formed according to actual needs (e.g., needs for device control).

Example two

The present embodiment also provides a method for forming a step structure of a 3D NAND memory, which is the same as the first embodiment and is not repeated herein, except that:

as shown in fig. 16, in the present embodiment, a first trench 203 is formed in the stacked structure. The first grooves 203 formed in the present embodiment are also spaced apart in the first direction, and include first portions 2031 and second portions 2032 that extend in parallel and are spaced apart in the X direction, the width of the first grooves 203 in the Y direction is also W, and the first portions 2031 and the second portions 2032 have a spacing distance Δ d in the Y direction. As shown in fig. 16 and 17, the width W is greater than the width of the gate line gap (i.e., the common source 104 formed later), and the distance Δ d between the first portion 2031 and the second portion 2032 in the Y direction is less than or equal to the width of the gate line gap (i.e., the common source 104 formed later).

The first trench 203 is then filled with an insulating material, such as silicon oxide, forming a top select gate cut 206.

Since the width of the first trench 203 is greater than the width of the gate line gap (i.e., the common source 104 to be formed later), and the distance Δ d between the first portion 2031 and the second portion 2032 in the Y direction is less than or equal to the width of the gate line gap (i.e., the common source 104 to be formed later), when the gate line gap and the common source contact are formed later as shown in fig. 9 and 10, the two sides of the common source contact 1094 are made of the insulating material forming the first top selection gate tangent 206, rather than the sacrificial layer and the insulating layer which are arranged alternately. When the contact portion 105 shown in fig. 11 is formed, the formation window of the contact portion is also increased, and even if the contact portion is slightly deviated from the common-source contact, the contact portion does not contact the gate layers on both sides of the bridge common-source contact, so that the leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent.

In a preferred embodiment of this embodiment, a second top select gate tangent line is also formed at the same time as the first top select gate tangent line, and the second top select gate tangent line has the same characteristics as the second top select gate tangent line described in the first embodiment, which is not described herein again.

EXAMPLE III

The present embodiment provides a 3D NAND memory, also referring to fig. 3 to 12, the 3D NAND memory including:

a substrate 100 having a substrate surface in a first direction and a second direction orthogonal to each other, the substrate surface having a stacked structure formed thereon in a third direction perpendicular to the substrate surface, the stacked structure including insulating layers and gate electrode layers alternately stacked;

a first top select gate tangent line formed in a top select gate of the gate layer; in a preferred embodiment, the first top selection gate tangents 106 are spaced apart in the first direction, and have a width greater than that of a subsequently formed gate line slit.

a common source formed in the gate line slit at the first top select gate tangent line that covers a sidewall of the common source;

As shown in fig. 10, in the third direction, the depth of the common source contact is 1-10 layers of the stacked structure, and the bottom of the common source contact 1094 is flush with or lower than the bottom of the first trench 103. Thus allowing the common source contact 1094 to be flanked by insulating material forming the top select gate tangent 106, rather than alternating sacrificial and insulating layers. Therefore, when the contact 105 shown in fig. 11 is formed, the formation window of the contact is increased, and even if the contact is slightly deviated from the common-source contact, the contact does not contact the gate layer on both sides of the bridge common-source contact, so that the leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent.

As shown in fig. 9 to 11, the 3D NAND memory further includes a channel structure penetrating the stack structure in a stacking direction of the stack structure, and includes: a memory layer 1081 and a channel layer 1082 sequentially distributed along the sidewall of the channel hole toward the center. More preferably the core portion of the channel hole includes a layer of dielectric material 1083. As is well known, the memory layer 1081 is a multi-layer structure including a blocking layer, a charge trapping layer, and a tunneling layer, which are not shown in detail herein. In an embodiment of the invention, the blocking layer may be a single layer or a stacked layer or a mixed layer of materials such as aluminum oxide, silicon oxynitride, and the like. The charge trapping layer may be a single layer or a stack of layers of materials such as silicon nitride and silicon oxynitride, or a wide bandgap material such as a mixed layer. The tunneling layer can be a single layer or a lamination layer or a mixed layer of silicon oxide and silicon oxynitride. The channel layer may be polysilicon. The layer of dielectric material may be silicon oxide.

Referring to fig. 15, in a preferred embodiment of the present embodiment, the 3D NAND memory further includes a second top select gate tangent line 106' that penetrates the top select gate in a stacking direction of the stack structure and extends in the first direction to isolate the top select gate. In a more preferred embodiment, the width of the second top select gate tangent 106 ' (i.e., the second trench 103 ') is larger than the aperture of the channel hole, so that the second top select gate tangent 106 ' can also form the sidewall of the channel hole when forming the channel structure, as shown in fig. 15. Therefore, when the contact part of the channel structure is formed, the forming window of the contact part of the channel structure can be increased, and the manufacturing difficulty of the contact part of the channel structure is reduced.

Example four

The embodiment also provides a method for forming the step structure of the 3D NAND memory. The difference from the first embodiment and the second embodiment is that:

in the present embodiment, as shown in fig. 19, a stacked structure 101 is formed on a substrate 100, the stacked structure being formed as a single stacked structure, the stacked structure 101 including insulating layers 1011 and sacrificial layers 1012 alternately deposited in this order. A first trench 303 is then formed in the stacked structure, followed by filling the first trench with an insulating material to form a first top select gate cut. The first top select gate tangent line has the same characteristics as the first top select gate tangent line described in the first or second embodiment, and is not described herein again.

The 3D NAND memory formed by the method of this embodiment also has the structure and features of the memory described in the third embodiment, and is not described herein again.

when the 3D NAND memory is formed, a plurality of first top selection gate tangents distributed at intervals in a first direction are formed at the top of a stacked structure, then a gate line gap continuously extending along the first direction is formed, the gap penetrates through the first top selection gate tangents, and in a second direction perpendicular to the first direction, the width of the first top selection gate tangents is larger than that of the gate line gap. And then forming a common source contact in the gate line gap, and forming a common source contact part at a position corresponding to the first top selection gate tangent line, wherein the width of the contact part is smaller than that of the gate line gap in the second direction, so that a structure that the width of the contact part is less than that of the gate line gap and less than that of the first top selection gate tangent line is formed. Therefore, the insulating layer forming the first top selection gate tangent line is used for replacing the original laminated gate layer around the common source contact, so that the forming window of the contact part of the common source is increased, and even if the contact part is slightly deviated from the common source contact, the contact part cannot bridge the gate layers on two sides of the common source contact, so that the leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent.

In addition, in a preferred embodiment of the present invention, while the first top select gate tangent is formed, a same mask layer may be used to form a second top select gate tangent continuously extending along the first direction, where a width of the second top select gate tangent may be greater than an aperture of a subsequently formed channel structure, so that an insulating layer forming the first top select gate tangent replaces an original stacked gate layer around the channel structure at the top of the stacked structure, thereby also increasing a formation window of a contact portion of the channel structure, reducing a manufacturing difficulty of the contact portion to a certain extent, further reducing a leakage risk of the device, and improving a yield of the device. On the other hand, the method simultaneously forms the first top selection gate tangent line and the second top selection gate tangent line through the same mask, saves the preparation of the mask and the etching step, and therefore reduces the manufacturing cost of the memory.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A3D NAND memory manufacturing method is characterized by comprising the following steps:

forming a plurality of first top select gate tangents in the stack structure;

forming a contact in electrical communication with the common source, the contact located above the common source with sidewalls covered by the first top select gate tangent;

wherein, in the second direction, the width of the first top selection gate tangent line is greater than the width of the gate line gap.

2. The method of manufacturing a 3D NAND memory according to claim 1, wherein providing a substrate having a substrate surface in a first direction and a second direction orthogonal to each other, and forming a stacked structure on the substrate surface in a third direction perpendicular to the substrate surface, the stacked structure having insulating layers and sacrificial layers alternately stacked, further comprises:

3. The 3D NAND memory manufacturing method of claim 1, further comprising: at least one second top select gate tangent is formed in the stack structure.

4. The method of manufacturing a 3D NAND memory as claimed in claim 3 wherein forming a plurality of first top select gate tangents on top of the stack structure comprises the steps of:

5. The method of manufacturing a 3D NAND memory as claimed in claim 4 wherein forming at least one second top select gate tangent in the stack structure comprises the steps of:

6. The method of claim 5, wherein the first trench and the second trench have a depth in the third direction of between 1 and 10 layers of the stacked structure.

7. The method of claim 1, wherein the first top select gate tangent includes a first portion and a second portion spaced apart from each other in the second direction, and wherein a spacing distance between the first portion and the second portion is less than or equal to a width of the gate line slit.

8. The method of manufacturing a 3D NAND memory of claim 2 further comprising the steps of:

forming a selective epitaxial structure at the bottom of the channel hole;

and filling a dielectric layer in the channel hole.

9. The 3D NAND memory manufacturing method of claim 1, further comprising:

10. The method of manufacturing a 3D NAND memory of claim 1 wherein forming a common source in the gate line slit further comprises:

forming a bottom conducting layer at the bottom of the grid line gap;

forming a gate isolation layer on the side wall of the gate line gap;

filling a source electrode conducting material in the grid line gap;

forming the common source contact over the source conductive material.

11. The method of manufacturing a 3D NAND memory of claim 10 wherein forming a contact in electrical communication with the common source at the first top select gate tangent location further comprises:

12. A3D NAND memory, comprising:

a gate line slit extending along the first direction and penetrating the stacked structure in the third direction, the gate line slit penetrating the first top select gate tangent, and a width of the first top select gate tangent in the second direction being greater than a width of the gate line slit, the first top select gate tangent forming a sidewall of the gate line slit at the first top select gate tangent;

13. The 3D NAND memory of claim 12 further comprising at least one second top select gate tangent.

14. The 3D NAND memory of claim 13 wherein the first top select gate tangents are spaced apart in the first direction and the second top select gate tangents are continuous in the first direction.

15. The 3D NAND memory of claim 12 further comprising a channel structure extending through the stack structure in the third direction and comprising:

a selective epitaxial structure formed at the bottom of the channel hole;

a dielectric layer formed in the channel hole.

16. The 3D NAND memory of claim 13 wherein the first top select gate tangent and the second top select gate tangent have a depth in the third direction of 1 to 10 layers of the stacked structure.