WO2019168027A1 - Procédé de production de mémoire non volatile - Google Patents

Procédé de production de mémoire non volatile Download PDF

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Publication number
WO2019168027A1
WO2019168027A1 PCT/JP2019/007555 JP2019007555W WO2019168027A1 WO 2019168027 A1 WO2019168027 A1 WO 2019168027A1 JP 2019007555 W JP2019007555 W JP 2019007555W WO 2019168027 A1 WO2019168027 A1 WO 2019168027A1
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WIPO (PCT)
Prior art keywords
layer
sacrificial layer
sacrificial
etching
conductive layer
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PCT/JP2019/007555
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English (en)
Japanese (ja)
Inventor
和雄 吉備
大久保　和哉
俊武 津田
李　彰原
寿 加藤
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東京エレクトロン株式会社
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Publication of WO2019168027A1 publication Critical patent/WO2019168027A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • the present disclosure relates to a method for manufacturing a nonvolatile memory device.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • This disclosure provides a technique capable of improving the durability of a conductive layer used as an etch stop layer.
  • the end portions of the multilayer film in which the first insulating layers and the first sacrificial layers are alternately stacked and the end portions are formed stepwise are provided.
  • Laminating a second sacrificial layer on the exposed portion of each of the first sacrificial layers exposed in step and laminating a second insulating layer on the multilayer film so as to cover the second sacrificial layer.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 6 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment.
  • a NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged.
  • the NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating layer 16, and a plurality of contact plugs 18.
  • the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
  • the substrate 12 is a substrate formed of a semiconductor such as silicon.
  • the multilayer film 14 has a structure in which the insulating layers 22 and the conductive layers 24 are alternately stacked and the end portions are formed in a stepped shape.
  • a plurality of pairs of the insulating layer 22 and the conductive layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction.
  • Each pair of the insulating layer 22 and the conductive layer 24 at the end portion of the multilayer film 14 is not covered with another pair arranged in the upper layer.
  • Each conductive layer 24 functions as a word line of each memory cell, for example.
  • Each conductive layer 24 is made of a metal such as W (tungsten).
  • Each conductive layer 24 except the conductive layer 24 disposed at the uppermost layer is not covered with the insulating layer 22 disposed at the upper layer at the end of the multilayer film 14 and is thicker than the other portions.
  • a portion (hereinafter referred to as “thick film portion”) 24 a is included.
  • each insulating layer 22 functions as an interlayer insulating film that insulates between the conductive layers 24 adjacent in the Z direction.
  • Each insulating layer 22 is, for example, a silicon oxide film.
  • the insulating layer 16 is formed on the multilayer film 14 so as to cover the multilayer film 14.
  • the insulating layer 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating layer 16.
  • the insulating layer 16 is, for example, a silicon oxide film.
  • the insulating layer 16 has a plurality of contact holes CH penetrating the insulating layer 16 in the Z direction.
  • the plurality of contact holes CH are collectively formed by etching using each conductive layer 24 as an etch stop layer.
  • each contact hole CH reaches the thick film portion 24 a of each conductive layer 24. Since the thick film portions 24a of the respective conductive layers 24 are thicker than the other portions, even when the corresponding contact holes CH reach the thick film portions 24a of the respective conductive layers 24 by etching, an etch stop margin is obtained. Is difficult to damage the wiring.
  • Each contact plug 18 is disposed in each contact hole CH.
  • Each contact plug 18 is made of a metal such as W, for example.
  • Each contact plug 18 is in contact with the thick film portion 24 a of each conductive layer 24.
  • each conductive layer 24 has the thick film portion 24a, and the corresponding contact hole CH is formed by etching so as to reach the thick film portion 24a.
  • the etch stop margin is large and wiring damage is less likely to occur. That is, the durability of the conductive layer 24 used as an etch stop layer can be improved.
  • the contact hole CH reaching the conductive layer 24 in each layer is normally formed.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment.
  • 3 to 8 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
  • the multilayer film 44 in which the insulating layers 52 and the sacrificial layers 54 are alternately stacked and the end portions are formed stepwise is formed on the substrate 42.
  • the insulating layer 52 is made of a material for forming the insulating layer 22, such as SiO 2 (silicon oxide film).
  • the sacrificial layer 54 is made of, for example, SiN (silicon nitride film). As shown in FIG. 3, the sacrificial layer 54 disposed on the uppermost layer is exposed as a whole.
  • Each sacrificial layer 54 except the sacrificial layer 54 disposed on the uppermost layer is partially exposed at the end of the multilayer film 44 as shown in FIG.
  • a portion of each sacrificial layer 54 exposed at the end of the multilayer film 44 is referred to as an “exposed portion”.
  • the insulating layer 52 is an example of a first insulating layer
  • the sacrificial layer 54 is an example of a first sacrificial layer.
  • the stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction within the plane of each layer, and the direction parallel to the paper surface of FIG. It is defined as the Y direction.
  • a sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. That is, the sacrificial layer 56 is formed on the upper surface of the exposed portion of each sacrificial layer 54 and is not formed on the side surface of each sacrificial layer 54.
  • the thickness of the sacrificial layer 56 is smaller than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54.
  • the sacrificial layer 56 is made of, for example, SiN (silicon nitride film).
  • the sacrificial layer 56 is laminated on the exposed portion of each sacrificial layer 54 by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).
  • the sacrificial layer 56 is laminated not only on the exposed portion of each sacrificial layer 54 but also on the sacrificial layer 54 disposed on the uppermost layer.
  • the sacrificial layer 56 is an example of a second sacrificial layer.
  • the sacrificial layer 56 can be formed by ALD, for example.
  • ALD includes, for example, a first adsorption process, a treatment process, a second adsorption process, and a nitridation process. Specific conditions for ALD are as follows. ⁇ First adsorption step> Etching gas: mixed gas of Cl 2 and Ar Etching temperature: 200 to 500 ° C. ⁇ Etching time: 10 to 180 sec ⁇ Treatment process> Etching gas: NH 3 and Ar mixed gas Etching temperature: 200-500 ° C ⁇ Etching time: 10 to 180 sec ⁇ Second adsorption process> Etching gas: SiH 2 Cl 2 and N 2 mixed gas Etching temperature: 200 to 500 ° C.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54.
  • an insulating layer 46 is laminated on the multilayer film 44.
  • the insulating layer 46 is laminated on the multilayer film 44 so that the sacrificial layer 56 is covered.
  • the insulating layer 46 is stacked on the multilayer film 44 by, for example, CVD or ALD.
  • the insulating layer 46 is an example of a second insulating layer.
  • the insulating layer 46 is, for example, SiO 2 (silicon oxide film).
  • Specific film forming conditions for the insulating layer 46 are as follows. Raw materials: TEOS (tetraethyl orthosilicate), O 2 -Formation temperature: 400-900 ° C ⁇ Formation time: 5-12hours
  • step S ⁇ b> 104 of FIG. 2 and FIG. 6 the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74. That is, in the replacement in step S104, the sacrificial layer 54 and the sacrificial layer 56 are first removed by isotropic etching such as wet etching, for example. Thereafter, the conductive layer 74 is disposed by filling the space in which the sacrificial layer 54 and the sacrificial layer 56 are disposed with a metal material.
  • the sacrificial layer 54 is located in the space where the exposed portion and the sacrificial layer 56 were disposed and is thicker than the other portions.
  • a thick portion (hereinafter referred to as a “thick film portion”) 74 a is formed in the conductive layer 74.
  • the wet etching of the sacrificial layer 54 and the sacrificial layer 56 is performed, for example, under the following conditions.
  • the metal material is tungsten
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the insulating layer 46 is etched using the conductive layer 74 as an etch stop layer, and a contact hole CH ′ penetrating the insulating layer 46 in the Z direction is formed in the insulating layer 46.
  • a plurality of are formed.
  • the plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching), for example.
  • RIE Reactive Ion Etching
  • the etching stop margin is large. The damage is less likely to occur.
  • the etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as the etching apparatus. Specific conditions for etching at this time are as follows.
  • Etching gas CF 4 , Ar and O 2 mixed gas
  • Gas flow rate: CF 4 / Ar / O 2 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm ⁇
  • a metal material 48 is filled in each contact hole CH ′.
  • the metal material 48 and the thick film portion 74a of the conductive layer 74 are in contact with each other.
  • the metal material 48 is a metal material for forming the contact plug 18 such as W (tungsten), and a well-known technique such as CVD or ALD using a raw material such as WF 6 or W (CO) 6 can be used. It is. In this way, the NAND flash memory 10 according to this embodiment is manufactured.
  • the substrate 42 functions as the substrate 12
  • the insulating layer 52 functions as the insulating layer 22
  • the conductive layer 74 functions as the conductive layer 24
  • the insulating layer 46 functions as the insulating layer 16.
  • the metal material 48 functions as the contact plug 18 and the contact hole CH ′ functions as the contact hole CH.
  • the sacrificial layer 56 is stacked on the exposed portion of each sacrificial layer 54 exposed at the end of the multilayer film 44, and the insulating layer 46 is stacked.
  • Each of the sacrificial layer 54 and the sacrificial layer 56 is replaced with a conductive layer 74.
  • the conductive layer 74 is located in the space where the exposed portion of the sacrificial layer 54 and the sacrificial layer 56 are disposed, and toward the portion thicker than the other portions (that is, the thick film portion 74a).
  • the insulating layer 46 is etched.
  • the thick film portion 74a of the conductive layer 74 is thicker than the other portions, even when the corresponding contact hole CH ′ reaches the thick film portion 74a of the conductive layer 74 by etching, an etch stop margin is obtained. Is difficult to damage the wiring. That is, according to this embodiment, the durability of the conductive layer 74 used as the etch stop layer can be improved. As a result, in the NAND flash memory 10 having the stacked structure, the contact hole CH ′ reaching the conductive layer 74 in each layer is normally formed.
  • the thickness of the sacrificial layer 56 is thinner than the thickness of each insulating layer 52 formed on the upper layer of each sacrificial layer 54. Therefore, when the sacrificial layer 54 and the sacrificial layer 56 are replaced with the conductive layer 74, the conductive layers 74 adjacent in the stacking direction of the multilayer film 44 are electrically insulated from each other by the respective insulating layers 52. . As a result, in the NAND flash memory 10 having the stacked structure, a short circuit between the conductive layers 74 in each layer is avoided.
  • the sacrificial layer 56 is selectively formed on the upper surface of the exposed portion of each sacrificial layer 54. Thereby, the sacrificial layer 56 can be laminated with high efficiency.
  • Multilayer film 46 Insulating layer (second insulating layer) 48 Metal material 52 Insulating layer (first insulating layer) 54 Sacrificial layer (first sacrificial layer) 56 Sacrificial layer (second sacrificial layer) 74 Conductive layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un procédé de production d'une mémoire non volatile (10). Le procédé de production comprend : une étape consistant à stratifier des secondes couches sacrificielles (56) sur des parties apparentes de premières couches sacrificielles qui sont apparente au niveaux de parties d'extrémité en forme d'escalier d'un film multicouche (44) qui est formé par stratification alternée de premières couches d'isolation (52) et des premières couches sacrificielles (54) ; une étape de stratification d'une seconde couche d'isolation (46) sur le film multicouche de façon à recouvrir les secondes couches sacrificielles ; une étape consistant à remplacer les premières couches sacrificielles et les secondes couches sacrificielles par des couches conductrices (74) ; et une étape consistant à graver la seconde couche d'isolation vers des parties épaisses (74a) des couches conductrices, les parties épaisses étant positionnées dans les espaces au niveau desquels les secondes couches sacrificielles et les parties apparentes des premières couches sacrificielles étaient disposées et plus épaisses que d'autres parties.
PCT/JP2019/007555 2018-03-02 2019-02-27 Procédé de production de mémoire non volatile WO2019168027A1 (fr)

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JP2018-037568 2018-03-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802851A (zh) * 2019-11-14 2021-05-14 爱思开海力士有限公司 形成薄层的方法及使用其制造非易失性存储器装置的方法

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Publication number Priority date Publication date Assignee Title
CN113437083A (zh) * 2021-06-29 2021-09-24 长江存储科技有限责任公司 三维存储器的制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20180053686A1 (en) * 2016-08-16 2018-02-22 Chung-il Hyun Semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20180053686A1 (en) * 2016-08-16 2018-02-22 Chung-il Hyun Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802851A (zh) * 2019-11-14 2021-05-14 爱思开海力士有限公司 形成薄层的方法及使用其制造非易失性存储器装置的方法

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