WO2019168036A1 - Production method for nonvolatile storage device - Google Patents

Production method for nonvolatile storage device Download PDF

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Publication number
WO2019168036A1
WO2019168036A1 PCT/JP2019/007581 JP2019007581W WO2019168036A1 WO 2019168036 A1 WO2019168036 A1 WO 2019168036A1 JP 2019007581 W JP2019007581 W JP 2019007581W WO 2019168036 A1 WO2019168036 A1 WO 2019168036A1
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hole
layer
conductive layer
etching
insulating film
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PCT/JP2019/007581
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French (fr)
Japanese (ja)
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和雄 吉備
高橋　彰宏
坂本　渉
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東京エレクトロン株式会社
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Publication of WO2019168036A1 publication Critical patent/WO2019168036A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • the disclosed technology relates to a method for manufacturing a nonvolatile memory device.
  • a NAND flash memory is known as a small and large capacity non-volatile storage device.
  • a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
  • a contact with a conductive layer functioning as a word line of each memory cell In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell.
  • etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
  • the insulating layer and the sacrificial layer are alternately stacked, and the end portion is formed in a stepped shape in the stacking direction of the multilayer film.
  • a step of forming a first hole penetrating the end portion, and a part of each of the sacrificial layers on the inner side wall of the first hole is radially inward of the first hole from the insulating layer.
  • Remove the part covering the upper surface of the convex part And filling the first hole with a conductive material in a state where the upper surface of the convex portion of the conductive layer disposed in the uppermost layer in the first hole is exposed from the insulating film. Including the step of.
  • a contact with a conductive layer in each layer can be appropriately formed in a NAND flash memory having a stacked structure.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 6 is a diagram for explaining the etching of each insulating layer in more detail.
  • FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND
  • FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 9 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment.
  • FIG. 10 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 11 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 12 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
  • FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment.
  • a NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged.
  • the NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating film 16, and a plurality of contact plugs 18.
  • the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction
  • the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
  • the substrate 12 is a substrate formed of a semiconductor such as silicon.
  • the multilayer film 14 has a structure in which the conductive layers 22 and the insulating layers 24 are alternately stacked and the end portions are formed in a stepped shape.
  • a plurality of pairs of the conductive layer 22 and the insulating layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction.
  • Each conductive layer 22 functions as a word line of each memory cell, for example.
  • Each conductive layer 22 is made of a metal such as W, for example.
  • each insulating layer 24 functions as an interlayer insulating film that insulates between the conductive layers 22 adjacent in the Z direction.
  • Each insulating layer 24 is, for example, a silicon oxide film.
  • each pair of the conductive layer 22 and the insulating layer 24 is not covered with another pair disposed in the upper layer.
  • the insulating film 16 is formed on the multilayer film 14 so as to cover the multilayer film 14.
  • the insulating film 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating film 16.
  • the insulating film 16 is, for example, a silicon oxide film.
  • the multilayer film 14 and the insulating film 16 are formed with a plurality of contact holes CH penetrating the end of the multilayer film 14 in the Z direction.
  • the plurality of contact holes CH are formed at one time by etching, for example, and reach the substrate 12.
  • each contact hole CH is formed by etching, in the multilayer film 14, each conductive layer 22 is not used as an etch stop layer.
  • each conductive layer 22 protrudes inward in the radial direction of the contact hole CH from each insulating layer 24.
  • an insulating film 32 is formed along the inner wall of each contact hole CH.
  • the insulating film 32 is, for example, a silicon oxide film.
  • the insulating film 32 has an opening 32a at a position corresponding to the upper surface of the convex portion protruding in the radial direction of the contact hole CH of the conductive layer 22 disposed in the uppermost layer in each contact hole CH.
  • the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in each contact hole CH is exposed from the opening 32 a of the insulating film 32.
  • Each contact plug 18 is disposed in each contact hole CH.
  • Each contact plug 18 is made of a metal such as W, for example.
  • Each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH through the opening 32 a of the insulating film 32.
  • each contact plug 18 is electrically insulated from the other conductive layer 22 other than the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH by the insulating film 32.
  • each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH. It is electrically insulated from the conductive layer 22 by the insulating film 32.
  • each conductive layer 22 is not used as an etch stop layer in the multilayer film 14. Therefore, it is possible to electrically connect each contact plug 18 to the uppermost conductive layer 22 in the corresponding contact hole CH without using the conductive layer 22 in each layer as an etch stop layer. Become. As a result, in the NAND flash memory 10 having the stacked structure, the contact with the conductive layer 22 in each layer is appropriately formed.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment.
  • 3 to 5 and FIGS. 7 to 12 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
  • the sacrificial layers 52 and the insulating layers 54 are alternately stacked, and the multi-layer film 44 whose end portions are formed in a step shape, and the insulating film 46 that covers the multi-layer film 44, Is formed on the substrate 42.
  • the sacrificial layer 52 is made of, for example, SiN.
  • the insulating layer 54 is made of a material for forming the insulating layer 24 such as SiO 2 .
  • the stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction and the direction parallel to the paper surface of FIG. It is defined as
  • a plurality of contact holes CH ′ penetrating the end portions of the multilayer film 14 in the Z direction are formed in the multilayer film 44 and the insulating film 46.
  • the plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching) and reach the substrate 42.
  • the contact hole CH ′ is an example of a first hole.
  • An etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus. Specific conditions for etching at this time are as follows.
  • each sacrificial layer 52 is more radial in the contact hole CH ′ than the respective insulating layer 54 on the inner wall of each contact hole CH ′.
  • Each insulating layer 54 is etched so as to protrude inward.
  • each sacrificial layer 52 is formed with a convex portion 52a that protrudes radially inward of the contact hole CH ′ from the respective insulating layer 54.
  • the insulating film 46 is etched in the radial direction of the contact hole CH ′ together with the respective insulating layers 54.
  • etching gas mixed gas of CF 4 , Ar and O 2
  • Etching temperature 100-300 °C ⁇
  • Etching time 1 to 300 min
  • Etching power 500 to 3000 W at a frequency of 13 to 60 MHz
  • FIG. 6 is a diagram for explaining the etching of each insulating layer 54 in more detail.
  • FIG. 6 corresponds to a schematic plan view when each contact hole CH ′ is viewed from the Z-axis direction.
  • the cross-sectional area of the portion surrounded by each insulating layer 54 of the contact hole CH ′ is A1
  • the cross-sectional area of the portion surrounded by each sacrificial layer 52 of the contact hole CH ′ is A2.
  • each insulating layer 54 is etched until the difference (A1-A2) between the cross-sectional area A1 and the cross-sectional area A2 becomes equal to or larger than the cross-sectional area A2.
  • an insulating film 62 is deposited along the inner wall of each contact hole CH ′.
  • the insulating film 62 is deposited along the convex part 52a of each sacrificial layer 52 on the inner side wall of each contact hole CH ′.
  • the insulating film 62 is made of a material for forming the insulating film 32 such as SiO 2 .
  • the insulating film 62 is deposited along the inner wall of each contact hole CH ′ by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). Specific conditions applied to the deposition of the insulating film 62 are as follows.
  • the insulating film 62 can also be formed by using a PVD (Physical Vapor Deposition) method or spin coating.
  • the formation temperature of the CVD method can be set to 300 to 1200 ° C., and O 3 can be used instead of O 2 .
  • Perhydropolysilazane can be used as a raw material, but in that case, the insulating film 62 can be formed by a spin coating method.
  • the organic material 48 is filled in the contact hole CH ′ in which the insulating film 62 is deposited.
  • the organic material 48 is, for example, SOC (spin on carbon).
  • the organic material 48 is filled by, for example, CVD or coating.
  • each sacrificial layer 52 is replaced with a conductive layer 72 in a state where the insulating film 62 is deposited along the inner wall of each contact hole CH ′.
  • each sacrificial layer 52 is removed by isotropic etching such as wet etching, for example.
  • the conductive layer 72 is disposed by filling the space obtained by removing the respective sacrificial layers 52 with a metal material.
  • the metal material filled in the space obtained by removing each sacrificial layer 52 is a metal material for forming the conductive layer 22 such as W (tungsten).
  • each conductive layer 72 is formed with a convex portion 72a protruding in the radial direction of the contact hole CH ′ from the respective insulating layer 54.
  • the convex portions 72a of the respective conductive layers 72 are arranged at the positions where the convex portions 52a of the respective sacrifice layers 52 were arranged. Specific conditions of the wet etching at this time are as follows.
  • ⁇ Etching temperature 200-350 °C ⁇ Etching time: 30 ⁇ 180min
  • a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
  • the organic material 48 is removed.
  • the organic material 48 is removed by, for example, ashing.
  • Step S108 of FIG. 2 and FIG. 11 the protrusion protruding in the radial direction of the contact hole CH ′ of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ of the insulating film 62.
  • a portion covering the upper surface of the portion 72a is removed by etching.
  • an opening 62a is formed in the insulating film 62. From the opening 62a of the insulating film 62, the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is formed. Exposed.
  • the etching method at this time is dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus.
  • Specific conditions for etching at this time are as follows.
  • Gas flow rate: CF 4 / Ar / O 2 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm ⁇
  • Etching time 1 to 300 min
  • Etching power 500 to 3000 W at a frequency of 13 to 60 MHz
  • a metal material 78 is filled therein.
  • the metal material 78 and the upper surface of the convex part 72a of the electroconductive layer 72 arrange
  • the metal material 78 and the conductive layer 72 other than the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ are electrically insulated from each other by the insulating film 62.
  • the metal material 78 is a metal material for forming the contact plug 18 such as W (tungsten).
  • the metal material 78 is an example of a conductive material.
  • the substrate 42 functions as the substrate 12
  • the conductive layer 72 functions as the conductive layer 22
  • the insulating layer 54 functions as the insulating layer 24, and the insulating film 46 functions as the insulating film 16.
  • the metal material 78 functions as the contact plug 18, the insulating film 62 functions as the insulating film 32
  • the contact hole CH ′ functions as the contact hole CH.
  • a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
  • the upper surface of the convex portion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is exposed from the insulating film 32.
  • the metal material 78 is filled in each contact hole CH ′.
  • the metal material 78 comes into contact with the upper surface of the protrusion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′, and is electrically insulated from the other conductive layer 72 by the insulating film 62.
  • each contact hole CH ′ is formed by etching, each conductive layer 72 is not used as an etch stop layer.
  • each insulating layer 54 has a cross-sectional area A1 of a portion surrounded by each insulating layer 54 of the contact hole CH ′ and a cross-sectional area A2 of a portion surrounded by each sacrificial layer 52. Etching is performed until the difference (A1-A2) becomes equal to or larger than the cross-sectional area A2. As a result, a sufficient surface area of the upper surface of the convex portion 52a of each sacrificial layer 52 is ensured. Therefore, when each sacrificial layer 52 is replaced with the conductive layer 72, a contact for forming the contact with the conductive layer 72 is formed. A sufficient surface area is secured.
  • the surface area for forming a contact with the conductive layer 72 corresponds to, for example, the surface area of the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′. As a result, the contact resistance corresponding to the contact with the conductive layer 72 is reduced.
  • the contact hole CH ′ penetrating the end of the multilayer film 44 in the Z direction is formed in the multilayer film 44 as an example, but the disclosed technique is not limited to this.
  • the contact hole CH ′ is formed in the multilayer film 44 at the same time as another contact hole penetrating another part different from the end of the multilayer film 44 in the Z direction. You may do it.
  • the other contact hole is, for example, a memory hole for arranging a plurality of memory cells three-dimensionally.
  • the other contact hole is an example of a second hole.
  • Multilayer film 52 Sacrificial layer 54 Insulating layer 62 Insulating film 72 Conductive layer 72a Convex part 78 Metal material

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Abstract

A production method for a nonvolatile storage device (10). The production method includes: a step for forming a first hole (CH') in a multilayer film (44) that has been formed by alternatingly laminating insulation layers (54) and sacrificial layers (52) and has stair-shaped end parts; a step for etching the insulation layers at an inside wall of the first hole such that a portion of each of the sacrificial layers protrudes further toward the radial-direction inside of the first hole than the insulation layers; a step for depositing an insulating film (62) along the inside wall of the first hole; a step for replacing the sacrificial layers with conductive layers (72); a step for removing the portion of the insulating film that covers an upper surface of a protruding part (72a) of the uppermost conductive layer inside the first hole; and a step for filling the inside of the first hole with a conductive material (78).

Description

不揮発性記憶装置の製造方法Method for manufacturing nonvolatile memory device
　開示技術は、不揮発性記憶装置の製造方法に関するものである。 The disclosed technology relates to a method for manufacturing a nonvolatile memory device.
　小型で大容量な不揮発性記憶装置として、ＮＡＮＤ型フラッシュメモリが知られている。また、メモリセルの高集積化を図るために、複数のメモリセルを３次元的に配置した積層構造のＮＡＮＤ型フラッシュメモリが知られている。 A NAND flash memory is known as a small and large capacity non-volatile storage device. In addition, in order to achieve high integration of memory cells, a NAND flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known.
　積層構造のＮＡＮＤ型フラッシュメモリでは、各メモリセルのワード線として機能する導電層に対するコンタクトを形成することが求められる。コンタクトの形成では、例えば、各層における導電層をエッチストップ層として用いるエッチングを行うことによって、各層における導電層へ到達するコンタクトホールを形成する。その後、コンタクトホール内に導電性を有する材料を充填して、当該材料と、各層における導電層とを接触させる。これにより、各層における導電層に対するコンタクトが形成される。 In a NAND flash memory having a stacked structure, it is required to form a contact with a conductive layer functioning as a word line of each memory cell. In forming the contact, for example, etching using the conductive layer in each layer as an etch stop layer is performed to form a contact hole reaching the conductive layer in each layer. Thereafter, the contact hole is filled with a conductive material, and the material is brought into contact with the conductive layer in each layer. Thereby, the contact with respect to the conductive layer in each layer is formed.
米国特許出願公開第２０１７／０１１０３６５号明細書US Patent Application Publication No. 2017/0110365
　ところで、積層構造のＮＡＮＤ型フラッシュメモリでは、さらなる高集積化を図るため、メモリセルの積層数がさらに増加することが想定される。メモリセルの積層数が増加するほど、最上層に配置された導電層と最下層に配置された導電層との間の距離が増大する。そのため、各層における導電層をエッチストップ層として用いるエッチングが行われる場合、最下層に配置された導電層にコンタクトホールが到達するまでに、最上層に配置された導電層がエッチングによるダメージを受け、オーバエッチングが発生する虞がある。その結果、各層における導電層へ到達するコンタクトホールが正常に形成されず、各層における導電層に対するコンタクトを適切に形成することが困難となる。 By the way, in a NAND flash memory having a stacked structure, it is assumed that the number of stacked memory cells is further increased in order to achieve higher integration. As the number of stacked memory cells increases, the distance between the uppermost conductive layer and the lowermost conductive layer increases. Therefore, when etching using the conductive layer in each layer as an etch stop layer is performed, the conductive layer disposed in the uppermost layer is damaged by etching until the contact hole reaches the conductive layer disposed in the lowermost layer, There is a risk of over-etching. As a result, contact holes reaching the conductive layer in each layer are not normally formed, and it is difficult to appropriately form a contact to the conductive layer in each layer.
　そこで、積層構造のＮＡＮＤ型フラッシュメモリでは、各層における導電層に対するコンタクトを適切に形成することが期待されている。 Therefore, in a NAND flash memory having a stacked structure, it is expected to appropriately form a contact with a conductive layer in each layer.
　開示する不揮発性記憶装置の製造方法は、１つの実施態様において、絶縁層と犠牲層とが交互に積層され、端部が階段状に形成された多層膜に、前記多層膜の積層方向に前記端部を貫通する第１のホールを形成する工程と、前記第１のホールの内側壁において、それぞれの前記犠牲層の一部がそれぞれの前記絶縁層よりも前記第１のホールの径方向内側に突出するように、それぞれの前記絶縁層をエッチングする工程と、前記第１のホールの内側壁に沿って、絶縁膜を堆積させる工程と、それぞれの前記犠牲層を導電層に置換する工程と、前記第１のホールの内側壁に沿って堆積された前記絶縁膜のうち、前記第１のホール内で最上層に配置された前記導電層の前記第１のホールの径方向内側に突出している凸部の上面を覆う部分を除去する工程と、前記第１のホール内で最上層に配置された前記導電層の前記凸部の上面が前記絶縁膜から露出された状態で、前記第１のホール内に導電性を有する材料を充填する工程とを含む。 In one embodiment of the disclosed method for manufacturing a nonvolatile memory device, the insulating layer and the sacrificial layer are alternately stacked, and the end portion is formed in a stepped shape in the stacking direction of the multilayer film. A step of forming a first hole penetrating the end portion, and a part of each of the sacrificial layers on the inner side wall of the first hole is radially inward of the first hole from the insulating layer. Etching each of the insulating layers so as to protrude, a step of depositing an insulating film along an inner wall of the first hole, and a step of replacing each sacrificial layer with a conductive layer Of the insulating film deposited along the inner wall of the first hole, the conductive layer disposed in the uppermost layer in the first hole protrudes radially inward of the first hole. Remove the part covering the upper surface of the convex part And filling the first hole with a conductive material in a state where the upper surface of the convex portion of the conductive layer disposed in the uppermost layer in the first hole is exposed from the insulating film. Including the step of.
　開示する不揮発性記憶装置の製造方法の１つの態様によれば、積層構造のＮＡＮＤ型フラッシュメモリにおいて、各層における導電層に対するコンタクトを適切に形成することができるという効果を奏する。 According to one aspect of the disclosed method for manufacturing a nonvolatile memory device, there is an effect that a contact with a conductive layer in each layer can be appropriately formed in a NAND flash memory having a stacked structure.
図１は、本実施形態に係るＮＡＮＤ型フラッシュメモリの構造の一例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory according to the present embodiment. 図２は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を示すフローチャートである。FIG. 2 is a flowchart showing an example of a manufacturing method of the NAND flash memory according to the present embodiment. 図３は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 3 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment. 図４は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 4 is a view for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment. 図５は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 5 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment. 図６は、それぞれの絶縁層のエッチングについて更に詳細に説明するための図である。FIG. 6 is a diagram for explaining the etching of each insulating layer in more detail. 図７は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 7 is a diagram for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment. 図８は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 8 is a diagram for explaining an example of a method for manufacturing the NAND flash memory according to the present embodiment. 図９は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 9 is a view for explaining an example of the method for manufacturing the NAND flash memory according to the present embodiment. 図１０は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 10 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment. 図１１は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 11 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment. 図１２は、本実施形態に係るＮＡＮＤ型フラッシュメモリの製造方法の一例を説明するための図である。FIG. 12 is a diagram for explaining an example of the manufacturing method of the NAND flash memory according to the present embodiment.
　以下に、開示する不揮発性記憶装置の製造方法の実施形態について、図面に基づいて詳細に説明する。なお、本実施形態により開示する不揮発性記憶装置の製造方法が限定されるものではない。 Hereinafter, embodiments of a method for manufacturing a disclosed nonvolatile memory device will be described in detail with reference to the drawings. Note that the manufacturing method of the nonvolatile memory device disclosed by the present embodiment is not limited.
［ＮＡＮＤ型フラッシュメモリ１０の構造］
　図１は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の構造の一例を示す縦断面図である。図１に示すＮＡＮＤ型フラッシュメモリ１０は、図示しない複数のメモリセルを３次元的に配置した積層構造のＮＡＮＤ型フラッシュメモリである。ＮＡＮＤ型フラッシュメモリ１０は、基板１２と、多層膜１４と、絶縁膜１６と、複数のコンタクトプラグ１８とを有する。なお、以下では、図１に示した多層膜１４の積層方向をＺ方向と定義し、各層の面内において、図１の紙面に垂直な方向をＸ方向と定義し、図１の紙面に平行な方向をＹ方向と定義する。 [Structure of NAND Flash Memory 10]
FIG. 1 is a longitudinal sectional view showing an example of the structure of the NAND flash memory 10 according to the present embodiment. A NAND flash memory 10 shown in FIG. 1 is a NAND flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged. The NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating film 16, and a plurality of contact plugs 18. In the following, the stacking direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 1 is defined as the X direction in the plane of each layer, and parallel to the paper surface of FIG. Is defined as the Y direction.
　基板１２は、例えばシリコン等の半導体により形成される基板である。 The substrate 12 is a substrate formed of a semiconductor such as silicon.
　多層膜１４は、導電層２２と絶縁層２４とが交互に積層され、端部が階段状に形成された構造を有する。導電層２２と絶縁層２４との複数の対は、Ｚ方向に３次元的に配置された複数のメモリセルにそれぞれ対応する。それぞれの導電層２２は、例えば、各メモリセルのワード線として機能する。それぞれの導電層２２は、例えば、Ｗ等の金属で構成される。また、それぞれの絶縁層２４は、Ｚ方向に隣り合う導電層２２間を絶縁する層間絶縁膜として機能する。それぞれの絶縁層２４は、例えば、シリコン酸化膜等である。また、多層膜１４の端部において、導電層２２と絶縁層２４とのそれぞれの対は、上層に配置された他の対によって覆われていない。 The multilayer film 14 has a structure in which the conductive layers 22 and the insulating layers 24 are alternately stacked and the end portions are formed in a stepped shape. A plurality of pairs of the conductive layer 22 and the insulating layer 24 respectively correspond to a plurality of memory cells arranged three-dimensionally in the Z direction. Each conductive layer 22 functions as a word line of each memory cell, for example. Each conductive layer 22 is made of a metal such as W, for example. In addition, each insulating layer 24 functions as an interlayer insulating film that insulates between the conductive layers 22 adjacent in the Z direction. Each insulating layer 24 is, for example, a silicon oxide film. In addition, at the end portion of the multilayer film 14, each pair of the conductive layer 22 and the insulating layer 24 is not covered with another pair disposed in the upper layer.
　絶縁膜１６は、多層膜１４を覆うように多層膜１４上に形成される。絶縁膜１６は、多層膜１４と、絶縁膜１６上に配置される配線層との間を絶縁する層間絶縁膜として機能する。絶縁膜１６は、例えば、シリコン酸化膜等である。 The insulating film 16 is formed on the multilayer film 14 so as to cover the multilayer film 14. The insulating film 16 functions as an interlayer insulating film that insulates between the multilayer film 14 and a wiring layer disposed on the insulating film 16. The insulating film 16 is, for example, a silicon oxide film.
　本実施形態において、多層膜１４及び絶縁膜１６には、Ｚ方向に多層膜１４の端部を貫通するコンタクトホールＣＨが複数形成されている。複数のコンタクトホールＣＨは、例えば、エッチングにより一括で形成され、基板１２に到達する。ただし、それぞれのコンタクトホールＣＨがエッチングにより形成される場合、多層膜１４において、それぞれの導電層２２は、エッチストップ層として用いられない。 In this embodiment, the multilayer film 14 and the insulating film 16 are formed with a plurality of contact holes CH penetrating the end of the multilayer film 14 in the Z direction. The plurality of contact holes CH are formed at one time by etching, for example, and reach the substrate 12. However, when each contact hole CH is formed by etching, in the multilayer film 14, each conductive layer 22 is not used as an etch stop layer.
　また、それぞれのコンタクトホールＣＨの内側壁において、それぞれの導電層２２の一部がそれぞれの絶縁層２４よりもコンタクトホールＣＨの径方向内側に突出している。 Further, on the inner side wall of each contact hole CH, a part of each conductive layer 22 protrudes inward in the radial direction of the contact hole CH from each insulating layer 24.
　また、それぞれのコンタクトホールＣＨの内側壁に沿って、絶縁膜３２が形成されている。絶縁膜３２は、例えば、シリコン酸化膜等である。絶縁膜３２は、それぞれのコンタクトホールＣＨ内で最上層に配置された導電層２２のコンタクトホールＣＨの径方向に突出している凸部の上面に対応する位置に、開口３２ａを有する。それぞれのコンタクトホールＣＨ内で最上層に配置された導電層２２の凸部の上面は、絶縁膜３２の開口３２ａから露出される。 Further, an insulating film 32 is formed along the inner wall of each contact hole CH. The insulating film 32 is, for example, a silicon oxide film. The insulating film 32 has an opening 32a at a position corresponding to the upper surface of the convex portion protruding in the radial direction of the contact hole CH of the conductive layer 22 disposed in the uppermost layer in each contact hole CH. The upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in each contact hole CH is exposed from the opening 32 a of the insulating film 32.
　それぞれのコンタクトプラグ１８は、それぞれのコンタクトホールＣＨ内に配置される。それぞれのコンタクトプラグ１８は、例えば、Ｗ等の金属で構成される。それぞれのコンタクトプラグ１８は、対応するコンタクトホールＣＨ内で最上層に配置された導電層２２の凸部の上面に、絶縁膜３２の開口３２ａを介して、接触している。これに対して、それぞれのコンタクトプラグ１８は、対応するコンタクトホールＣＨ内で最上層に配置された導電層２２以外の他の導電層２２から絶縁膜３２によって電気的に絶縁されている。 Each contact plug 18 is disposed in each contact hole CH. Each contact plug 18 is made of a metal such as W, for example. Each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH through the opening 32 a of the insulating film 32. On the other hand, each contact plug 18 is electrically insulated from the other conductive layer 22 other than the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH by the insulating film 32.
　このように、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０では、それぞれのコンタクトプラグ１８は、対応するコンタクトホールＣＨ内で最上層に配置された導電層２２の凸部の上面に接触し、他の導電層２２から絶縁膜３２によって電気的に絶縁される。ここで、それぞれのコンタクトホールＣＨがエッチングにより形成される場合、多層膜１４において、それぞれの導電層２２は、エッチストップ層として用いられない。そのため、各層における導電層２２をエッチストップ層として用いることなく、それぞれのコンタクトプラグ１８と、対応するコンタクトホールＣＨ内で最上層に配置された導電層２２とを電気的に接続することが可能となる。結果として、積層構造のＮＡＮＤ型フラッシュメモリ１０において、各層における導電層２２に対するコンタクトが適切に形成される。 As described above, in the NAND flash memory 10 according to the present embodiment, each contact plug 18 is in contact with the upper surface of the convex portion of the conductive layer 22 disposed in the uppermost layer in the corresponding contact hole CH. It is electrically insulated from the conductive layer 22 by the insulating film 32. Here, when each contact hole CH is formed by etching, each conductive layer 22 is not used as an etch stop layer in the multilayer film 14. Therefore, it is possible to electrically connect each contact plug 18 to the uppermost conductive layer 22 in the corresponding contact hole CH without using the conductive layer 22 in each layer as an etch stop layer. Become. As a result, in the NAND flash memory 10 having the stacked structure, the contact with the conductive layer 22 in each layer is appropriately formed.
［ＮＡＮＤ型フラッシュメモリ１０の製造方法］
　次に、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法について説明する。図２は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法の一例を示すフローチャートである。図３～図５及び図７～図１２は、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法の一例を説明するための図である。 [Method of Manufacturing NAND Flash Memory 10]
Next, a method for manufacturing the NAND flash memory 10 according to this embodiment will be described. FIG. 2 is a flowchart showing an example of a method for manufacturing the NAND flash memory 10 according to the present embodiment. 3 to 5 and FIGS. 7 to 12 are views for explaining an example of the manufacturing method of the NAND flash memory 10 according to the present embodiment.
　図２のステップＳ１０１及び図３に示すように、犠牲層５２と絶縁層５４とが交互に積層され、端部が階段状に形成された多層膜４４と、多層膜４４を覆う絶縁膜４６とが基板４２上に作成される。図３に示した多層膜４４において、犠牲層５２は、例えば、ＳｉＮ等で構成される。また、絶縁層５４は、例えば、ＳｉＯ2等、絶縁層２４を形成するための材料によって構成される。図３に示した多層膜４４の積層方向をＺ方向と定義し、各層の面内において、図３の紙面に垂直な方向をＸ方向と定義し、図３の紙面に平行な方向をＹ方向と定義する。 As shown in step S101 of FIG. 2 and FIG. 3, the sacrificial layers 52 and the insulating layers 54 are alternately stacked, and the multi-layer film 44 whose end portions are formed in a step shape, and the insulating film 46 that covers the multi-layer film 44, Is formed on the substrate 42. In the multilayer film 44 shown in FIG. 3, the sacrificial layer 52 is made of, for example, SiN. The insulating layer 54 is made of a material for forming the insulating layer 24 such as SiO 2 . The stacking direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction, and the direction perpendicular to the paper surface of FIG. 3 is defined as the X direction and the direction parallel to the paper surface of FIG. It is defined as
　続いて、図２のステップＳ１０２及び図４に示すように、多層膜４４及び絶縁膜４６に、Ｚ方向に多層膜１４の端部を貫通するコンタクトホールＣＨ´が複数形成される。複数のコンタクトホールＣＨ´は、例えば、ＲＩＥ（Reactive　Ion　　Etching）等の異方性エッチングにより一括で形成され、基板４２に到達する。コンタクトホールＣＨ´は、第１のホールの一例である。コンタクトホールＣＨ´のエッチング方法は、例えばドライエッチングであり、エッチング装置としては、容量結合プラズマ（ＣＣＰ）型装置を採用することができる。この時のエッチングの具体的な条件は以下の通りである。
・エッチングガス：ＣＦ4、ＡｒおよびＯ2の混合ガス
・ガス流量：ＣＦ4／Ａｒ／Ｏ2＝１００～３００ｓｃｃｍ／５００～１０００ｓｃｃｍ／５０～１００ｓｃｃｍ
・エッチング温度：２０～１００℃
・エッチング時間：１～３００ｍｉｎ
・エッチングパワー：周波数１３～６０ＭＨｚで５００～３０００Ｗ Subsequently, as shown in step S102 of FIG. 2 and FIG. 4, a plurality of contact holes CH ′ penetrating the end portions of the multilayer film 14 in the Z direction are formed in the multilayer film 44 and the insulating film 46. The plurality of contact holes CH ′ are collectively formed by anisotropic etching such as RIE (Reactive Ion Etching) and reach the substrate 42. The contact hole CH ′ is an example of a first hole. An etching method of the contact hole CH ′ is, for example, dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus. Specific conditions for etching at this time are as follows.
Etching gas: mixed gas of CF 4 , Ar and O 2 Gas flow rate: CF 4 / Ar / O 2 = 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 1 to 300 min
Etching power: 500 to 3000 W at a frequency of 13 to 60 MHz
　続いて、図２のステップＳ１０３及び図５に示すように、それぞれのコンタクトホールＣＨ´の内側壁において、それぞれの犠牲層５２の一部がそれぞれの絶縁層５４よりもコンタクトホールＣＨ´の径方向内側に突出するように、それぞれの絶縁層５４がエッチングされる。これにより、それぞれの犠牲層５２には、それぞれの絶縁層５４よりもコンタクトホールＣＨ´の径方向内側に突出する凸部５２ａが形成される。また、ステップＳ１０３におけるエッチングでは、それぞれの絶縁層５４と共に、絶縁膜４６がコンタクトホールＣＨ´の径方向にエッチングされる。それぞれの絶縁層５４のエッチング及び絶縁膜４６のエッチングには、例えば、ドライエッチング等の等方性エッチングが用いられる。この時のエッチングの具体的な条件は以下の通りである。
・エッチングガス：ＣＦ４、ＡｒおよびＯ２の混合ガス
・ガス流量：ＣＦ4／Ａｒ／Ｏ2＝１００～３００ｓｃｃｍ／５００～１０００ｓｃｃｍ／５０～１００ｓｃｃｍ
・エッチング温度：１００～３００℃
・エッチング時間：１～３００ｍｉｎ
・エッチングパワー：周波数１３～６０ＭＨｚで５００～３０００Ｗ Subsequently, as shown in step S103 of FIG. 2 and FIG. 5, a part of each sacrificial layer 52 is more radial in the contact hole CH ′ than the respective insulating layer 54 on the inner wall of each contact hole CH ′. Each insulating layer 54 is etched so as to protrude inward. Thereby, each sacrificial layer 52 is formed with a convex portion 52a that protrudes radially inward of the contact hole CH ′ from the respective insulating layer 54. In the etching in step S103, the insulating film 46 is etched in the radial direction of the contact hole CH ′ together with the respective insulating layers 54. For the etching of each insulating layer 54 and the etching of the insulating film 46, for example, isotropic etching such as dry etching is used. Specific conditions for etching at this time are as follows.
Etching gas: mixed gas of CF 4 , Ar and O 2 Gas flow rate: CF 4 / Ar / O 2 = 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm
・ Etching temperature: 100-300 ℃
・ Etching time: 1 to 300 min
Etching power: 500 to 3000 W at a frequency of 13 to 60 MHz
　ここで、図６を参照して、それぞれの絶縁層５４のエッチングについて更に詳細に説明する。図６は、それぞれの絶縁層５４のエッチングについて更に詳細に説明するための図である。図６は、それぞれのコンタクトホールＣＨ´をＺ軸方向から見た場合の模式的な平面図に相当する。図６において、コンタクトホールＣＨ´のそれぞれの絶縁層５４で囲まれる部分の断面積がＡ１であり、コンタクトホールＣＨ´のそれぞれの犠牲層５２で囲まれる部分の断面積がＡ２であるものとする。この場合、それぞれの絶縁層５４は、断面積Ａ１と断面積Ａ２との差（Ａ１－Ａ２）が断面積Ａ２以上となるまで、エッチングされる。これにより、それぞれの犠牲層５２の凸部５２ａの上面の表面積が十分に確保されるので、それぞれの犠牲層５２が後述する導電層７２に置換された場合に、導電層７２に対するコンタクトを形成するための表面積が十分に確保される。その結果、導電層７２に対するコンタクトに応じた接触抵抗が低減される。 Here, the etching of each insulating layer 54 will be described in more detail with reference to FIG. FIG. 6 is a diagram for explaining the etching of each insulating layer 54 in more detail. FIG. 6 corresponds to a schematic plan view when each contact hole CH ′ is viewed from the Z-axis direction. In FIG. 6, it is assumed that the cross-sectional area of the portion surrounded by each insulating layer 54 of the contact hole CH ′ is A1, and the cross-sectional area of the portion surrounded by each sacrificial layer 52 of the contact hole CH ′ is A2. . In this case, each insulating layer 54 is etched until the difference (A1-A2) between the cross-sectional area A1 and the cross-sectional area A2 becomes equal to or larger than the cross-sectional area A2. Thereby, a sufficient surface area of the upper surface of the convex portion 52a of each sacrificial layer 52 is ensured, so that a contact to the conductive layer 72 is formed when each sacrificial layer 52 is replaced with a conductive layer 72 described later. A sufficient surface area is ensured. As a result, the contact resistance corresponding to the contact with the conductive layer 72 is reduced.
　続いて、図２のステップＳ１０４及び図７に示すように、それぞれのコンタクトホールＣＨ´の内側壁に沿って、絶縁膜６２が堆積される。これにより、それぞれのコンタクトホールＣＨ´の内側壁において、それぞれの犠牲層５２の凸部５２ａに沿って、絶縁膜６２が堆積される。絶縁膜６２は、例えば、ＳｉＯ2等、絶縁膜３２を形成するための材料により構成される。絶縁膜６２は、例えば、ＣＶＤ（Chemical　Vapor　Deposition）やＡＬＤ（Atomic　Layer　Deposition）等により、それぞれのコンタクトホールＣＨ´の内側壁に沿って、堆積される。絶縁膜６２の堆積に適用される具体的な条件は以下の通りである。
・原材料：　ＴＥＯＳ（オルトケイ酸テトラエチル）、Ｏ2
・形成温度：４００～９００℃
・形成時間：５～１２ｈｏｕｒｓ
　なお、ＰＶＤ（Physical　Vapor　Deposition）法又はスピンコートを用いても、絶縁膜６２を形成することができる。ＣＶＤ法の形成温度は、３００～１２００℃に設定することもでき、Ｏ2に代えて、Ｏ3を用いることもできる。原料としてペルヒドロポリシラザンを用いることもできるが、その場合はスピンコートによる塗布法において絶縁膜６２を成膜することができる。 Subsequently, as shown in step S104 of FIG. 2 and FIG. 7, an insulating film 62 is deposited along the inner wall of each contact hole CH ′. Thereby, the insulating film 62 is deposited along the convex part 52a of each sacrificial layer 52 on the inner side wall of each contact hole CH ′. The insulating film 62 is made of a material for forming the insulating film 32 such as SiO 2 . The insulating film 62 is deposited along the inner wall of each contact hole CH ′ by, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). Specific conditions applied to the deposition of the insulating film 62 are as follows.
Raw materials: TEOS (tetraethyl orthosilicate), O 2
-Formation temperature: 400-900 ° C
・ Formation time: 5-12hours
Note that the insulating film 62 can also be formed by using a PVD (Physical Vapor Deposition) method or spin coating. The formation temperature of the CVD method can be set to 300 to 1200 ° C., and O 3 can be used instead of O 2 . Perhydropolysilazane can be used as a raw material, but in that case, the insulating film 62 can be formed by a spin coating method.
　続いて、図２のステップＳ１０５及び図８に示すように、絶縁膜６２が堆積されたコンタクトホールＣＨ´内に、有機材料４８が充填される。有機材料４８は、例えば、ＳＯＣ（スピンオンカーボン）等である。有機材料４８は、例えば、ＣＶＤや塗布等により充填される。 Subsequently, as shown in step S105 of FIG. 2 and FIG. 8, the organic material 48 is filled in the contact hole CH ′ in which the insulating film 62 is deposited. The organic material 48 is, for example, SOC (spin on carbon). The organic material 48 is filled by, for example, CVD or coating.
　続いて、図２のステップＳ１０６及び図９に示すように、それぞれのコンタクトホールＣＨ´の内側壁に沿って絶縁膜６２が堆積された状態で、それぞれの犠牲層５２が導電層７２に置換される。すなわち、ステップＳ１０６における置換では、まず、それぞれの犠牲層５２が、例えば、ウェットエッチング等の等方性エッチングにより除去される。その後、それぞれの犠牲層５２が除去されて得られた空間に金属材料が充填されることによって、導電層７２が配置される。それぞれの犠牲層５２が除去されて得られた空間に充填される金属材料は、例えば、Ｗ（タングステン）等、導電層２２を形成するための金属材料である。それぞれの犠牲層５２が導電層７２に置換されることによって、それぞれの導電層７２には、それぞれの絶縁層５４よりもコンタクトホールＣＨ´の径方向に突出する凸部７２ａが形成される。それぞれの導電層７２の凸部７２ａは、それぞれの犠牲層５２の凸部５２ａが配置されていた位置に配置される。この時のウェットエッチングの具体的な条件は以下の通りである。
・エッチング液：例えばＳＣ－１（Ｈ2Ｏ:Ｈ2Ｏ2:ＮＨ4ＯＨ＝５:１:１～５:１:０．０５の混合液）またはＳＰＭ（Ｈ2ＳＯ4：Ｈ2Ｏ2＝１：１～４：１の混合液）
・エッチング温度：２００～３５０℃
・エッチング時間：３０～１８０ｍｉｎ
　なお、金属材料の充填については、たとえばタングステンの他、ＷＦ6やＷ（ＣＯ）6などの原料を用いた周知技術を用いることが可能である。 Subsequently, as shown in step S <b> 106 of FIG. 2 and FIG. 9, each sacrificial layer 52 is replaced with a conductive layer 72 in a state where the insulating film 62 is deposited along the inner wall of each contact hole CH ′. The That is, in the replacement in step S106, first, each sacrificial layer 52 is removed by isotropic etching such as wet etching, for example. Thereafter, the conductive layer 72 is disposed by filling the space obtained by removing the respective sacrificial layers 52 with a metal material. The metal material filled in the space obtained by removing each sacrificial layer 52 is a metal material for forming the conductive layer 22 such as W (tungsten). By replacing each sacrificial layer 52 with the conductive layer 72, each conductive layer 72 is formed with a convex portion 72a protruding in the radial direction of the contact hole CH ′ from the respective insulating layer 54. The convex portions 72a of the respective conductive layers 72 are arranged at the positions where the convex portions 52a of the respective sacrifice layers 52 were arranged. Specific conditions of the wet etching at this time are as follows.
Etching solution: for example, SC-1 (mixture of H 2 O: H 2 O 2 : NH 4 OH = 5: 1: 1 to 5: 1: 0.05) or SPM (H 2 SO 4 : H 2 O 2 = mixture of 1: 1 to 4: 1)
・ Etching temperature: 200-350 ℃
・ Etching time: 30 ~ 180min
For filling the metal material, for example, a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
　続いて、図２のステップＳ１０７及び図１０に示すように、有機材料４８が除去される。有機材料４８は、例えば、アッシングにより除去される。 Subsequently, as shown in step S107 of FIG. 2 and FIG. 10, the organic material 48 is removed. The organic material 48 is removed by, for example, ashing.
　続いて、図２のステップＳ１０８及び図１１に示すように、絶縁膜６２のうち、コンタクトホールＣＨ´内で最上層に配置された導電層７２のコンタクトホールＣＨ´の径方向に突出している凸部７２ａの上面を覆う部分がエッチング除去される。これにより、図１１に示すように、絶縁膜６２に開口６２ａが形成され、絶縁膜６２の開口６２ａから、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面が露出される。この時のエッチング方法は、ドライエッチングであり、エッチング装置としては、容量結合プラズマ（ＣＣＰ）型装置を採用することができる。この時のエッチングの具体的な条件は以下の通りである。
・エッチングガス：ＣＦ4、ＡｒおよびＯ2の混合ガス
・ガス流量：ＣＦ4／Ａｒ／Ｏ2＝１００～３００ｓｃｃｍ／５００～１０００ｓｃｃｍ／５０～１００ｓｃｃｍ
・エッチング温度：２０～１００℃
・エッチング時間：１～３００ｍｉｎ
・エッチングパワー：周波数１３～６０ＭＨｚで５００～３０００Ｗ Subsequently, as shown in Step S108 of FIG. 2 and FIG. 11, the protrusion protruding in the radial direction of the contact hole CH ′ of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ of the insulating film 62. A portion covering the upper surface of the portion 72a is removed by etching. As a result, as shown in FIG. 11, an opening 62a is formed in the insulating film 62. From the opening 62a of the insulating film 62, the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is formed. Exposed. The etching method at this time is dry etching, and a capacitively coupled plasma (CCP) type apparatus can be adopted as an etching apparatus. Specific conditions for etching at this time are as follows.
Etching gas: mixed gas of CF 4 , Ar and O 2 Gas flow rate: CF 4 / Ar / O 2 = 100 to 300 sccm / 500 to 1000 sccm / 50 to 100 sccm
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 1 to 300 min
Etching power: 500 to 3000 W at a frequency of 13 to 60 MHz
　続いて、図２のステップＳ１０９及び図１２に示すように、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面が露出された状態で、それぞれのコンタクトホールＣＨ´内に金属材料７８が充填される。これにより、図１２に示すように、金属材料７８と、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面とが接触する。これに対して、金属材料７８と、コンタクトホールＣＨ´内で最上層に配置された導電層７２以外の他の導電層７２とは、絶縁膜６２によって互いに電気的に絶縁されている。金属材料７８は、Ｗ（タングステン）等、コンタクトプラグ１８を形成するための金属材料である。金属材料７８は、導電性を有する材料の一例である。このようにして、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０が製造される。なお、基板４２は、基板１２として機能し、導電層７２は、導電層２２として機能し、絶縁層５４は、絶縁層２４として機能し、絶縁膜４６は、絶縁膜１６として機能する。また、金属材料７８は、コンタクトプラグ１８として機能し、絶縁膜６２は、絶縁膜３２として機能し、コンタクトホールＣＨ´は、コンタクトホールＣＨとして機能する。なお、金属材料の充填については、たとえばタングステンの他、ＷＦ6やＷ（ＣＯ）6などの原料を用いた周知技術を用いることが可能である。 Subsequently, as shown in step S109 of FIG. 2 and FIG. 12, each contact hole CH ′ with the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ exposed. A metal material 78 is filled therein. Thereby, as shown in FIG. 12, the metal material 78 and the upper surface of the convex part 72a of the electroconductive layer 72 arrange | positioned in the uppermost layer in contact hole CH 'contact. On the other hand, the metal material 78 and the conductive layer 72 other than the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ are electrically insulated from each other by the insulating film 62. The metal material 78 is a metal material for forming the contact plug 18 such as W (tungsten). The metal material 78 is an example of a conductive material. In this way, the NAND flash memory 10 according to this embodiment is manufactured. Note that the substrate 42 functions as the substrate 12, the conductive layer 72 functions as the conductive layer 22, the insulating layer 54 functions as the insulating layer 24, and the insulating film 46 functions as the insulating film 16. The metal material 78 functions as the contact plug 18, the insulating film 62 functions as the insulating film 32, and the contact hole CH ′ functions as the contact hole CH. For filling the metal material, for example, a well-known technique using a raw material such as WF 6 or W (CO) 6 in addition to tungsten can be used.
　以上、本実施形態に係るＮＡＮＤ型フラッシュメモリ１０の製造方法によれば、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面が絶縁膜３２から露出された状態で、それぞれのコンタクトホールＣＨ´内に金属材料７８が充填される。これにより、金属材料７８は、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面に接触し、他の導電層７２から絶縁膜６２によって電気的に絶縁される。ここで、それぞれのコンタクトホールＣＨ´がエッチングにより形成される場合、それぞれの導電層７２は、エッチストップ層として用いられない。そのため、各層における導電層７２をエッチストップ層として用いることなく、金属材料７８と、コンタクトホールＣＨ´内で最上層に配置された導電層７２とを電気的に接続することが可能となる。結果として、積層構造のＮＡＮＤ型フラッシュメモリ１０において、各層における導電層７２に対するコンタクトが適切に形成される。 As described above, according to the method for manufacturing the NAND flash memory 10 according to the present embodiment, the upper surface of the convex portion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ is exposed from the insulating film 32. The metal material 78 is filled in each contact hole CH ′. As a result, the metal material 78 comes into contact with the upper surface of the protrusion 72 a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′, and is electrically insulated from the other conductive layer 72 by the insulating film 62. Here, when each contact hole CH ′ is formed by etching, each conductive layer 72 is not used as an etch stop layer. Therefore, it is possible to electrically connect the metal material 78 and the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′ without using the conductive layer 72 in each layer as an etch stop layer. As a result, in the NAND flash memory 10 having the stacked structure, the contact with the conductive layer 72 in each layer is appropriately formed.
　また、本実施形態によれば、それぞれの絶縁層５４は、コンタクトホールＣＨ´のそれぞれの絶縁層５４で囲まれる部分の断面積Ａ１とそれぞれの犠牲層５２で囲まれる部分の断面積Ａ２との差（Ａ１－Ａ２）が断面積Ａ２以上となるまで、エッチングされる。これにより、それぞれの犠牲層５２の凸部５２ａの上面の表面積が十分に確保されるので、それぞれの犠牲層５２が導電層７２に置換された場合に、導電層７２に対するコンタクトを形成するための表面積が十分に確保される。導電層７２に対するコンタクトを形成するための表面積とは、例えば、コンタクトホールＣＨ´内で最上層に配置された導電層７２の凸部７２ａの上面の表面積に相当する。その結果、導電層７２に対するコンタクトに応じた接触抵抗が低減される。 Further, according to the present embodiment, each insulating layer 54 has a cross-sectional area A1 of a portion surrounded by each insulating layer 54 of the contact hole CH ′ and a cross-sectional area A2 of a portion surrounded by each sacrificial layer 52. Etching is performed until the difference (A1-A2) becomes equal to or larger than the cross-sectional area A2. As a result, a sufficient surface area of the upper surface of the convex portion 52a of each sacrificial layer 52 is ensured. Therefore, when each sacrificial layer 52 is replaced with the conductive layer 72, a contact for forming the contact with the conductive layer 72 is formed. A sufficient surface area is secured. The surface area for forming a contact with the conductive layer 72 corresponds to, for example, the surface area of the upper surface of the convex portion 72a of the conductive layer 72 disposed in the uppermost layer in the contact hole CH ′. As a result, the contact resistance corresponding to the contact with the conductive layer 72 is reduced.
［その他の実施形態］
　なお、開示技術は、上述した実施形態に限定されるものではなく、その要旨の範囲内で種々の変形が可能である。そこで、以下では、その他の実施形態について説明する。 [Other Embodiments]
The disclosed technology is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist. Therefore, other embodiments will be described below.
　上述の実施形態では、多層膜４４に、Ｚ方向に多層膜４４の端部を貫通するコンタクトホールＣＨ´を形成する場合を例に示したが、開示技術はこれに限定されるものではない。例えば、コンタクトホールＣＨ´を形成する工程では、多層膜４４に、コンタクトホールＣＨ´の形成と同時に、Ｚ方向に多層膜４４の端部とは異なる他の部分を貫通する他のコンタクトホールを形成しても良い。他のコンタクトホールは、例えば、複数のメモリセルを３次元的に配置するためのメモリホールである。他のコンタクトホールは、第２のホールの一例である。 In the above-described embodiment, the case where the contact hole CH ′ penetrating the end of the multilayer film 44 in the Z direction is formed in the multilayer film 44 as an example, but the disclosed technique is not limited to this. For example, in the step of forming the contact hole CH ′, the contact hole CH ′ is formed in the multilayer film 44 at the same time as another contact hole penetrating another part different from the end of the multilayer film 44 in the Z direction. You may do it. The other contact hole is, for example, a memory hole for arranging a plurality of memory cells three-dimensionally. The other contact hole is an example of a second hole.
４４　多層膜
５２　犠牲層
５４　絶縁層
６２　絶縁膜
７２　導電層
７２ａ　凸部
７８　金属材料 44 Multilayer film 52 Sacrificial layer 54 Insulating layer 62 Insulating film 72 Conductive layer 72a Convex part 78 Metal material

Claims (3)

  1. 　絶縁層と犠牲層とが交互に積層され、端部が階段状に形成された多層膜に、前記多層膜の積層方向に前記端部を貫通する第１のホールを形成する工程と、
    　前記第１のホールの内側壁において、それぞれの前記犠牲層の一部がそれぞれの前記絶縁層よりも前記第１のホールの径方向内側に突出するように、それぞれの前記絶縁層をエッチングする工程と、
    　前記第１のホールの内側壁に沿って、絶縁膜を堆積させる工程と、
    　それぞれの前記犠牲層を導電層に置換する工程と、
    　前記第１のホールの内側壁に沿って堆積された前記絶縁膜のうち、前記第１のホール内で最上層に配置された前記導電層の前記第１のホールの径方向内側に突出している凸部の上面を覆う部分を除去する工程と、
    　前記第１のホール内で最上層に配置された前記導電層の前記凸部の上面が前記絶縁膜から露出された状態で、前記第１のホール内に導電性を有する材料を充填する工程と
    　を含むことを特徴とする不揮発性記憶装置の製造方法。     Forming a first hole penetrating the end portion in the stacking direction of the multilayer film in the multilayer film in which the insulating layers and the sacrificial layers are alternately stacked and the end portions are stepped;
    Etching each of the insulating layers so that a part of each of the sacrificial layers protrudes radially inward of the first holes from the insulating layers on the inner wall of the first holes. When,
    Depositing an insulating film along the inner wall of the first hole;
    Replacing each said sacrificial layer with a conductive layer;
    Of the insulating film deposited along the inner wall of the first hole, the conductive layer disposed in the uppermost layer in the first hole protrudes radially inward of the first hole. Removing a portion covering the upper surface of the convex portion;
    Filling the first hole with a conductive material in a state where the upper surface of the convex portion of the conductive layer disposed in the uppermost layer in the first hole is exposed from the insulating film; A method for manufacturing a nonvolatile memory device, comprising:
  2. 　それぞれの前記絶縁層をエッチングする工程では、前記第１のホールのそれぞれの前記絶縁層で囲まれる部分の第１の断面積と前記第１のホールのそれぞれの前記犠牲層で囲まれる部分の第２の断面積との差が前記第２の断面積以上となるまで、それぞれの前記絶縁層をエッチングすることを特徴とする請求項１に記載の不揮発性記憶装置の製造方法。 In the step of etching each of the insulating layers, the first cross-sectional area of the portion surrounded by the insulating layer of each of the first holes and the first of the portion surrounded by the sacrificial layer of each of the first holes. 2. The method for manufacturing a nonvolatile memory device according to claim 1, wherein each of the insulating layers is etched until a difference from a cross-sectional area of 2 becomes equal to or larger than the second cross-sectional area.
  3. 　前記第１のホールを形成する工程では、前記多層膜に、前記第１のホールの形成と同時に、前記多層膜の積層方向に前記端部とは異なる他の部分を貫通する第２のホールを形成することを特徴とする請求項１又は２に記載の不揮発性記憶装置の製造方法。 In the step of forming the first hole, simultaneously with the formation of the first hole in the multilayer film, a second hole penetrating another part different from the end in the stacking direction of the multilayer film is formed. The method of manufacturing a nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is formed.
PCT/JP2019/007581 2018-03-02 2019-02-27 Production method for nonvolatile storage device WO2019168036A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098658A1 (en) * 2015-10-06 2017-04-06 Kabushiki Kaisha Toshiba Semiconductor memory device
US20180240811A1 (en) * 2017-02-21 2018-08-23 Samsung Electronics Co., Ltd. Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
JP2018163981A (en) * 2017-03-24 2018-10-18 東芝メモリ株式会社 Semiconductor device and manufacturing method of the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170098658A1 (en) * 2015-10-06 2017-04-06 Kabushiki Kaisha Toshiba Semiconductor memory device
US20180240811A1 (en) * 2017-02-21 2018-08-23 Samsung Electronics Co., Ltd. Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
JP2018163981A (en) * 2017-03-24 2018-10-18 東芝メモリ株式会社 Semiconductor device and manufacturing method of the same

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