WO2019095532A1 - 降低二维材料场效应晶体管接触电阻的方法 - Google Patents

降低二维材料场效应晶体管接触电阻的方法 Download PDF

Info

Publication number
WO2019095532A1
WO2019095532A1 PCT/CN2018/071344 CN2018071344W WO2019095532A1 WO 2019095532 A1 WO2019095532 A1 WO 2019095532A1 CN 2018071344 W CN2018071344 W CN 2018071344W WO 2019095532 A1 WO2019095532 A1 WO 2019095532A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
source
transition metal
field effect
effect transistor
Prior art date
Application number
PCT/CN2018/071344
Other languages
English (en)
French (fr)
Inventor
李绍娟
马玮良
袁建
拓明芬
Original Assignee
苏州大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州大学 filed Critical 苏州大学
Publication of WO2019095532A1 publication Critical patent/WO2019095532A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices

Definitions

  • the invention relates to the field of two-dimensional materials, and in particular to a method for reducing the contact resistance of a two-dimensional material field effect transistor.
  • a semiconducting two-dimensional material can overcome the short-channel effect of a conventional silicon-based field effect transistor.
  • the preparation of ultra-small, flexible flexible field effect transistors can be realized based on two-dimensional materials.
  • field effect transistors based on two-dimensional materials such as two-dimensional MoS 2 , WS 2 , MoSe 2 , PtS 2 , and PtSe 2 have attracted great attention.
  • the carrier mobility of the currently reported two-dimensional field effect transistor is still much lower than the theoretical two-dimensional material itself, one of the reasons is that the contact resistance between the two-dimensional material and the metal electrode greatly limits the device. Performance. Therefore, how to effectively reduce the contact resistance between the two-dimensional material channel and the metal electrode is the main challenge faced by the current two-dimensional field effect transistor application field.
  • an object of the present invention is to provide a method for reducing contact resistance of a two-dimensional material field effect transistor, which uses a source and drain electrode as a protective isolation layer to form a channel of a two-dimensional material between source and drain electrodes, thereby reducing The overlap area between the channel and the source and drain electrodes, thereby reducing the contact resistance between the two.
  • At least one transition metal region is evaporated on the surface of a portion of the substrate to form a transition metal layer; wherein the transition metal region has a thickness of 0.1 to 2 nm;
  • the photoresist layer has at least two holes for vaporizing the source and drain electrodes, and each of the holes is opposite to at least a part of the surface of the transition metal layer, each The hole is located at one side of the transition metal region, that is, a channel region is formed between the source and drain electrodes;
  • the transition metal is vulcanized using a sulfur source or the transition metal is selenized using a selenium source, and a two-dimensional material field effect transistor is formed after cooling.
  • the material of the substrate is insulated, and the base material is a glass or polymer flexible material.
  • the surface of the substrate is an insulating dielectric layer
  • the insulating dielectric layer is made of silicon dioxide, aluminum oxide, hafnium oxide or zirconium oxide, and the insulating dielectric layer has a thickness of 20 to 300 nm.
  • the transition metal is molybdenum (Mo), platinum (Pt), tungsten (W), manganese (Mn), nickel (Ni), cadmium (Cd) or palladium (Pd).
  • the transition metal is molybdenum (Mo), tungsten (W) or platinum (Pt).
  • the step (1) the step of sequentially depositing a gate and a gate dielectric between the substrate and the transition metal layer to further prepare a bottom gate structure.
  • the step (4) the step of sequentially depositing the gate dielectric and the gate on the surface of the two-dimensional material and/or the source/drain electrode before cooling to prepare the top gate structure is further included.
  • the material of the gate is aluminum, titanium/gold, chromium, chromium/gold, molybdenum or ITO (indium tin oxide).
  • the material of the gate dielectric is silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or boron nitride.
  • the shape of the hole is a rectangle, a square, a circle, or an irregular shape.
  • the underside of the hole may face a portion of the surface of the transition metal layer and a portion of the substrate; or the entire lower portion of the hole may face the transition metal layer.
  • the thickness of the photoresist layer is 50 nm to 2 ⁇ m.
  • the source/drain electrodes are one or both of a titanium (Ti) electrode, a gold (Au) electrode, an aluminum (Al) electrode, and a chromium (Cr) electrode.
  • the sulfur source is sulfur powder, sodium sulfide or hydrogen sulfide.
  • the source of sulfur is sulfur powder.
  • the selenium source is selenium powder or hydrogen selenide.
  • the source of selenium is selenium powder.
  • the substrate is heated to 550-750 ° C
  • the sulfur source is heated to 115-130 ° C to form a sulfur-containing atmosphere
  • the sulfur-containing atmosphere is vulcanized by contacting the transition metal
  • the substrate is heated to 400-500 ° C, and the selenium source is heated to 230-245 ° C to form a selenium-containing atmosphere, and the selenium-containing atmosphere is selenized by contacting the transition metal.
  • the sulfur source is used for vulcanization in the step (4); when the transition metal in the step (1) is platinum, the sulfur source is used in the step (4). It is vulcanized or selenized using a selenium source.
  • step (3) a portion of the source and drain electrodes are in direct contact with a portion of the transition metal region and another portion is in direct contact with the substrate.
  • step (4) another portion of the transition metal region that is not in contact with the source and drain electrodes is sulfided or selenized to form a two-dimensional material channel region.
  • the present invention has at least the following advantages:
  • the source and drain metal electrodes on both sides are used as a protective isolation layer, and the transition metal layer in the channel region between the source and drain metal electrodes is selectively converted to form a two-dimensional material channel region, thereby realizing a two-dimensional material channel region and source.
  • Self-alignment between the drain metal electrodes reduces the overlap area between the channel region of the two-dimensional material and the transition metal, thereby reducing parasitic resistance;
  • a part of the source-drain metal electrode on both sides of the channel region of the two-dimensional material is directly in contact with the underlying transition metal (a metal layer which is protected from source and drain metal and is not vulcanized or selenized outside the channel region), thereby effectively reducing the two-dimensional material.
  • the underlying transition metal a metal layer which is protected from source and drain metal and is not vulcanized or selenized outside the channel region
  • Embodiment 1 is a schematic structural view of a substrate in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic view showing the structure of a substrate in which a transition metal layer is modified in Embodiment 1 of the present invention
  • FIG. 3 is a schematic view showing the structure of a substrate after spin-coating a photoresist in Embodiment 1 of the present invention
  • FIG. 4 is a schematic view showing the structure of a substrate after vapor-depositing source and drain electrodes in a hole in Embodiment 1 of the present invention
  • FIG. 5 is a schematic structural view of a substrate after removing a photoresist in Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural view of a field effect transistor of a two-dimensional material prepared in Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural view of a field effect transistor array of a two-dimensional material prepared in Embodiment 5 of the present invention.
  • FIG. 8 is a schematic structural view of a sixth embodiment of the present invention after vapor-depositing a metal gate
  • FIG. 9 is a schematic structural view of depositing a gate dielectric layer in Embodiment 6 of the present invention.
  • FIG. 10 is a schematic structural view of a sixth embodiment of the present invention after vapor-depositing a transition metal region
  • FIG. 11 is a schematic structural view of a sixth embodiment of the present invention after vapor deposition of a source drain electrode
  • FIG. 12 is a schematic structural view of a field effect transistor of a two-dimensional material obtained by vulcanizing a transition metal region according to Embodiment 6 of the present invention.
  • FIG. 13 is a schematic top plan view of a field effect transistor of a two-dimensional material prepared in Embodiment 6 of the present invention.
  • Figure 14 is a schematic view showing the structure of a substrate in which a transition metal layer is modified in Embodiment 8 of the present invention.
  • FIG. 15 is a schematic view showing the structure of a substrate after vapor deposition of a source drain electrode in Embodiment 8 of the present invention.
  • Figure 16 is a schematic view showing the structure of a substrate after a partial transition metal region is vulcanized in Embodiment 8 of the present invention.
  • FIG. 17 is a schematic structural view of a gate dielectric layer deposited in Embodiment 8 of the present invention.
  • Embodiment 8 is a schematic structural view of a metal gate after vapor deposition in Embodiment 8 of the present invention.
  • FIG. 19 is a schematic top plan view of a field effect transistor of a two-dimensional material prepared in Embodiment 8 of the present invention.
  • the embodiment provides a method for reducing the contact resistance of a two-dimensional material field effect transistor, including the following steps:
  • a substrate which is a P-type highly doped silicon wafer whose surface is covered with silicon dioxide (SiO 2 ), having a SiO 2 layer 2 having a thickness of 100 nm on the surface and a Si layer 1 at the bottom, respectively using acetone, ethanol, Wash with deionized water and then blow dry the wafer with a nitrogen gun ( Figure 1).
  • SiO 2 silicon dioxide
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • a substrate which is a P-type highly doped silicon wafer whose surface is covered with silicon dioxide (SiO 2 ), having a 200 nm thick SiO 2 layer on its surface, which is respectively washed with acetone, ethanol, deionized water, and then The wafer was blown dry with a nitrogen gun.
  • SiO 2 silicon dioxide
  • the source and drain electrodes are evaporated in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate. At this time, a portion of the source-drain electrode is in direct contact with a portion of the transition metal region, and another portion is in direct contact with the substrate, and a portion of the transition metal is not in contact with the source-drain electrode.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • a substrate which is a P-type highly doped silicon wafer whose surface is covered with silicon dioxide (SiO 2 ), having a 250 nm thick SiO 2 layer on its surface, which is respectively washed with acetone, ethanol, deionized water, and then The wafer was blown dry with a nitrogen gun.
  • SiO 2 silicon dioxide
  • the source and drain electrodes are evaporated in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate. At this time, a portion of the source-drain electrode is in direct contact with a portion of the transition metal region, and another portion is in direct contact with the substrate, and a portion of the transition metal is not in contact with the source-drain electrode.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • a substrate which is a P-type highly doped silicon wafer whose surface is covered with alumina (Al 2 O 3 ), having a 50 nm thick Al 2 O 3 layer on its surface, respectively, using acetone, ethanol, deionized water. Wash and then dry the wafer with a nitrogen gun.
  • alumina Al 2 O 3
  • the source and drain electrodes are evaporated in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate. At this time, a portion of the source-drain electrode is in direct contact with a portion of the transition metal layer, and another portion is in direct contact with the substrate, and a portion of the transition metal is not in contact with the source-drain electrode.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • a substrate which is a P-type highly doped silicon wafer whose surface is covered with silicon dioxide (SiO 2 ), having a 300 nm thick SiO 2 layer 2 on the surface and a Si layer 1 at the bottom, respectively using acetone, ethanol, The ionized water was washed, and then the silicon wafer was blown dry with a nitrogen gun.
  • SiO 2 silicon dioxide
  • the photoresist layer has a plurality of holes for vapor-depositing source and drain electrodes, the holes are rectangular, and each hole is located in a transition metal The sides, and the lower portion of each of the holes face the surface of the transition metal and a portion of the substrate, thereby forming a channel region between the source and drain electrodes.
  • the source and drain electrodes 6 are vapor-deposited in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate. At this time, a portion of the source-drain electrode is in direct contact with a portion of the transition metal, and another portion is in direct contact with the substrate, and a portion of the transition metal is not in contact with the source-drain electrode.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • the metal gate 10 (Fig. 8) is vapor-deposited on the upper surface of the portion of the substrate 9, and specifically, chromium/gold is vapor-deposited on the upper surface of the substrate by electron beam evaporation or magnetron sputtering.
  • a gate dielectric layer 11 (Fig. 9) is deposited on the upper surface of the metal gate 10, specifically by depositing alumina on the upper surface of the metal gate by electron beam evaporation, magnetron sputtering or atomic layer deposition.
  • the deposited gate dielectric layer 11 covers a portion of the metal gate 10.
  • the area of layer 11 forms a transition metal layer having a thickness of 0.1 nm and a material of Mo.
  • the source-drain electrode 6 and the metal gate 10 are completely separated by the gate dielectric layer 11, but in a plan view, the source-drain electrode 6 and the metal gate 10 have an overlap of 1-2 micrometers in space coordinates, as shown in FIG.
  • the dotted line represents the covered area, and the solid line represents the visible area.
  • the substrate 9 was placed in a double temperature zone tube furnace, and the substrate 9 was placed in a high temperature zone at a controlled temperature of 680 degrees.
  • the sulfur powder in the low temperature region volatilizes at 130 degrees, so that the source is not in contact with the drain electrode 6 is formed exposing a metal Mo MoS 2 7 (FIG. 12) after being vulcanized sulfur atmosphere.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • a substrate was prepared which was a polymer flexible material which was washed with acetone, ethanol, deionized water, respectively, and then the substrate was blown dry with a nitrogen gun.
  • a metal gate is vapor-deposited on a portion of the upper surface of the substrate, and ITO (indium tin oxide) is deposited on the upper surface of the substrate by electron beam evaporation or magnetron sputtering.
  • ITO indium tin oxide
  • a gate dielectric layer on the upper surface of the metal gate, specifically using a transfer method to cover the upper surface of the metal gate with boron nitride.
  • the gate dielectric layer covers a portion of the metal gate.
  • a transition metal layer was formed having a thickness of 0.1 nm and a material of Mo.
  • the source and drain electrodes are vapor-deposited in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate.
  • a portion of the source-drain electrode is in direct contact with a portion of the transition metal region, and another portion is in direct contact with the gate dielectric layer, and a portion of the transition metal is not in contact with the source-drain electrode.
  • the source-drain electrodes and the metal gate are completely separated by the gate dielectric layer, but in a plan view, the source-drain electrodes and the metal gates overlap in space coordinates by 1-2 microns.
  • the processed sample is taken out, and a field effect transistor of a two-dimensional material is formed on the substrate after natural cooling.
  • This embodiment provides a method for reducing contact resistance of a two-dimensional material field effect transistor, comprising the following steps:
  • the source/drain electrodes 6 are vapor-deposited in the holes, and titanium and gold are respectively evaporated in the holes by electron beam evaporation or magnetron sputtering, and then the remaining photoresist is removed with an acetone solution to expose the other portions of the substrate. At this time, a part of the source-drain electrode 6 is in direct contact with a part of the transition metal region 3, and another portion is directly in contact with the substrate 9, and a part of the transition metal is not in contact with the source-drain electrode 6 (Fig. 15).
  • the substrate 9 was placed in a double temperature zone tube furnace, and the substrate 9 was placed in a high temperature zone at a controlled temperature of 680 degrees.
  • the sulfur powder in the low temperature region volatilizes at 130 degrees, so that the source is not in contact with the drain electrode 6 is formed exposing a metal Mo MoS 2 7 (FIG. 16) after being vulcanized sulfur atmosphere.
  • the metal gate 10 is vapor-deposited on the upper surface of the gate dielectric layer 11, and ITO (indium tin oxide) is deposited on the upper surface of the gate dielectric layer 11 by electron beam evaporation or magnetron sputtering.
  • the size of the metal gate 10 is smaller than the size of the lower gate dielectric layer 11.
  • the metal gate 10 and the source/drain electrode 6 are completely separated by the gate dielectric layer 11, but in a plan view, the source/drain electrode 6 and the metal gate 10 have an overlap of 1-2 ⁇ m in space coordinates.
  • the dotted line represents the covered area
  • the solid line represents the visible area of the naked eye.
  • the processed sample is taken out, and a field effect transistor of a two-dimensional material is formed on the substrate after natural cooling.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：在部分基底（9）的表面蒸镀至少一个过渡金属区（3），形成过渡金属层；其中，过渡金属区（3）的厚度为0.1-2nm；光刻、显影后形成光刻胶层（4），光刻胶层（4）上至少具有两个用于蒸镀源漏电极（6）的孔（5），每个孔（5）的下方正对部分过渡金属层和部分基底（9）的表面，每个孔（5）位于过渡金属区（3）的一侧；在孔（5）中蒸镀源漏电极（6），然后去除光刻胶层（4），露出其他部分的基底（9）；使用硫源对过渡金属进行硫化或使用硒源对过渡金属进行硒化，冷却后在基底（9）表面形成二维材料场效应晶体管。该方法采用源漏电极（6）作为保护隔离层，在源漏电极（6）之间形成二维材料的沟道，降低沟道与源漏电极（6）之间的交叠面积，从而降低二者之间的接触电阻。

Description

降低二维材料场效应晶体管接触电阻的方法 技术领域
本发明涉及二维材料领域，尤其涉及一种降低二维材料场效应晶体管接触电阻的方法。
背景技术
半导体性二维材料作为场效应晶体管的有源沟道区，可以克服传统硅基场效应晶体管的短沟效应。此外，由于二维材料超薄的厚度、优异的柔韧性，基于二维材料可以实现超小尺寸、可弯曲的柔性场效应晶体管的制备。近年来，基于二维MoS 2、WS 2、MoSe 2、PtS 2、PtSe 2等半导体性二维材料的场效应晶体管引起来了极大的关注。
然而，目前报道的二维场效应晶体管的载流子迁移率仍然远低于理论上二维材料本身的迁移率，其中一个原因是二维材料与金属电极之间的接触电阻极大地限制了器件的性能。因而，如何有效地降低二维材料沟道与金属电极之间的接触电阻是目前二维场效应晶体管应用领域所面临的主要挑战。
发明内容
为解决上述技术问题，本发明的目的是提供一种降低二维材料场效应晶体管接触电阻的方法，采用源漏电极作为保护隔离层，在源漏电极之间形成二维材料的沟道，降低沟道与源漏电极之间的交叠面积，从而降低二者之间的接触电阻。
本发明的一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)在部分基底的表面蒸镀至少一个过渡金属区，形成过渡金属层；其中，过渡金属区的厚度为0.1-2nm；
(2)光刻、显影后形成光刻胶层，光刻胶层上具有至少两个用于蒸镀源漏电极的孔，每个孔的下方正对至少一部分过渡金属层的表面，每个孔位于过渡金属区的一侧，即在源漏电极之间形成沟道区域；
(3)在孔中蒸镀源漏电极，然后去除光刻胶层，露出其他部分的基底；
(4)使用硫源对过渡金属进行硫化或使用硒源对过渡金属进行硒化，冷却后形成二维材料场效应晶体管。
进一步地，步骤(1)中，基底的材质绝缘，基底材质为玻璃或聚合物柔性材料。
进一步地，在步骤(1)中，基底的表面为绝缘介质层，绝缘介质层的材质为二氧化硅、 氧化铝、氧化铪或者氧化锆，绝缘介质层的厚度为20-300nm。
进一步地，在步骤(1)中，过渡金属为钼(Mo)、铂(Pt)、钨(W)、锰(Mn)、镍(Ni)、镉(Cd)或钯(Pd)。优选地，过渡金属为钼(Mo)、钨(W)或铂(Pt)。
进一步地，在步骤(1)中，还包括在基底与过渡金属层之间依次沉积栅极和栅介质的步骤，以制备底栅结构。
进一步地，在步骤(4)中，冷却前还包括在二维材料和/或源漏电极表面依次沉积栅介质和栅极的步骤，以制备顶栅结构。
进一步地，栅极的材质为铝、钛/金、铬、铬/金、钼或ITO(氧化铟锡)。
进一步地，栅介质的材质为氧化硅、氧化铝、氧化铪、氧化锆或氮化硼。
进一步地，在步骤(2)中，孔的形状为矩形、方形、圆形或者不规则形状。
进一步地，在步骤(2)中，孔的下方可以正对一部分过渡金属层的以及一部分基底的表面；或整个孔的下方全部正对着过渡金属层。
进一步地，在步骤(2)中，光刻胶层的厚度为50nm-2μm。
进一步地，在步骤(3)中，源漏电极为钛(Ti)电极、金(Au)电极、铝(Al)电极、铬(Cr)电极中的一种或两种。
进一步地，在步骤(4)中，硫源为硫粉、硫化钠或硫化氢。优选地，硫源为硫粉。
进一步地，在步骤(4)中，硒源为硒粉或硒化氢。优选地，硒源为硒粉。
进一步地，在步骤(4)中，将基底加热到550-750℃，将硫源加热到115-130℃后形成含硫气氛，含硫气氛接触过渡金属对其进行硫化；或者
在步骤(4)中，将基底加热到400-500℃，将硒源加热到230-245℃后形成含硒气氛，含硒气氛接触过渡金属对其进行硒化。
优选地，当步骤(1)中的过渡金属为钼时，步骤(4)中采用硫源对其进行硫化；当步骤(1)中的过渡金属为铂时，步骤(4)中采用硫源对其进行硫化或采用硒源对其硒化。
在步骤(3)之后，源漏电极的一部分直接与一部分过渡金属区接触，另外一部分直接与基底接触。在步骤(4)之后，使得未与源漏电极接触的另外一部分过渡金属区被硫化或硒化，形成二维材料沟道区。
借由上述方案，本发明至少具有以下优点：
采用两侧源漏金属电极作为保护隔离层，选择性的对源漏金属电极之间沟道区域的过渡金属层进行转化，从而形成二维材料沟道区，实现二维材料沟道区和源漏金属电极之间的自对准，降低二维材料沟道区与过渡金属之间的交叠面积，从而降低寄生电阻；
并且二维材料沟道区两侧的一部分源漏金属电极直接与下方的过渡金属(沟道区域之外受到源漏金属保护而未被硫化或硒化的金属层)接触，有效降低二维材料沟道与金属电极之间的接触电阻。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下为本发明的较佳实施例并配合附图详细说明如后。
附图说明
图1是本发明实施例1中基底的结构示意图；
图2是本发明实施例1中修饰了过渡金属层的基底结构示意图；
图3是本发明实施例1中旋涂光刻胶后的基底结构示意图；
图4是本发明实施例1中在孔中蒸镀源漏电极后的基底结构示意图；
图5是本发明实施例1中去除光刻胶后的基底结构示意图；
图6是本发明实施例1所制备的二维材料的场效应晶体管的结构示意图；
图7是本发明实施例5所制备的二维材料的场效应晶体管阵列的结构示意图；
图8是本发明实施例6蒸镀金属栅极后的结构示意图；
图9是本发明实施例6沉积蒸镀栅介质层后的结构示意图；
图10是本发明实施例6蒸镀过渡金属区后的结构示意图；
图11是本发明实施例6蒸镀源漏电极后的结构示意图；
图12是本发明实施例6过渡金属区被硫化后所得到的二维材料的场效应晶体管的结构示意图；
图13是本发明实施例6所制备的二维材料的场效应晶体管的俯视结构示意图；
图14是本发明实施例8中修饰了过渡金属层的基底结构示意图；
图15是本发明实施例8中蒸镀源漏电极后基底结构示意图；
图16是本发明实施例8中部分过渡金属区被硫化后基底的结构示意图；
图17是本发明实施例8中沉积栅介质层后的结构示意图；
图18是本发明实施例8中蒸镀金属栅极后的结构示意图；
图19是本发明实施例8所制备的二维材料的场效应晶体管的俯视结构示意图；
附图标记说明：
1-Si层；2-SiO 2层；3-过渡金属区；4-光刻胶层；5-孔；6-源漏电极；7-MoS 2；8-PtSe 2；9-基底；10-金属栅极；11-栅介质层。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例1
参见图1-6，本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为表面覆盖有二氧化硅(SiO 2)的P型高掺杂硅片，其表面具有100nm厚的SiO 2层2，底部是Si层1，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将硅片吹干(图1)。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底的上表面蒸镀一个矩形的过渡金属区3，其面积小于基底上表面的面积，形成过渡金属层，其厚度为0.1nm，材质为Mo(图2)。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层4，光刻胶层4上具有两个用于蒸镀源漏电极的孔5，孔5呈矩形，每个孔5的下方正对部分过渡金属区3和部分基底的表面，两个孔5分别位于过渡金属区的3两侧，即在源漏电极之间形成沟道区域(图3，虚线围成的区域代表被光刻胶层覆盖的过渡金属区3)。
(4)在孔5中蒸镀源漏电极6，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金(图4)，随后用丙酮溶液去除光刻胶层4，露出其他部分的基底(图5)。此时源漏电极6的一部分直接与一部分过渡金属区3接触，另外一部分直接与基底接触，且过渡金属的一部分未与源漏电极接触。
(5)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为550度。将硫粉放在低温区，在115度下进行挥发，使得未与源漏电极接触的Mo金属暴露在硫气氛中被硫化后形成MoS 27(图6)。
(6)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管(图6)。
实施例2
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为表面覆盖有二氧化硅(SiO 2)的P型高掺杂硅片，其表面具有200nm厚的SiO 2层，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将硅片吹干。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底的上表面蒸镀一个矩形的过渡金属区，其面积小于基底上表面的面积，形成过渡金属层，其厚度为0.1nm，材质为Mo。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极的孔，孔呈矩形，每个孔的下方正对部分过渡金属区和部分基底的表面，两个孔分别位于过渡金属区的两侧，即在源漏电极之间形成沟道区域。
(4)在孔中蒸镀源漏电极，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极的一部分直接与一部分过渡金属区接触，另外一部分直接与基底接触，且过渡金属的一部分未与源漏电极接触。
(5)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为680度。将硫粉放在低温区，在130度下进行挥发，使得未与源漏电极接触的Mo金属暴露在硫气氛中被硫化后形成MoS 2。
(6)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管。
实施例3
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为表面覆盖有二氧化硅(SiO 2)的P型高掺杂硅片，其表面具有250nm厚的SiO 2层，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将硅片吹干。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底的上表面蒸镀一个矩形的过渡金属区，其面积小于基底上表面的面积，形成过渡金属层，其厚度为0.5nm，材质为Pt。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极的孔，孔呈矩形，每个孔的下方正对部分过渡金属区和部分基底的表面，两个孔分别位于过渡金属区的两侧，即在源漏电极之间形成沟道区域。
(4)在孔中蒸镀源漏电极，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极的一部分直接与一部分过渡金属区接触，另外一部分直接与基底接触，且过渡金属的一部分未与源漏电极接触。
(5)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为750度。将硫粉放在低温区，在120度下进行挥发，使得未与源漏电极接触的Pt金属暴露在硫气氛中被硫化后形成PtS 2。
(6)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管。
实施例4
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为表面覆盖有氧化铝(Al 2O 3)的P型高掺杂硅片，其表面具有50nm厚的Al 2O 3层，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将硅片吹干。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底的上表面蒸镀一个矩形的过渡金属区，其面积小于基底上表面的面积，形成过渡金属层，其厚度为2nm，材质为Pt。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极的孔，孔呈矩形，每个孔的下方正对部分过渡金属区和部分基底的表面，两个孔分别位于过渡金属区的两侧，即在源漏电极之间形成沟道区域。
(4)在孔中蒸镀源漏电极，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极的一部分直接与一部分过渡金属层接触，另外一部分直接与基底接触，且过渡金属的一部分未与源漏电极接触。
(5)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为400度。将硒粉放在低温区，在230度下进行挥发，使得未与源漏电极接触的Pt金属暴露在硒气氛中被硒化后形成PtSe 2。
(6)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管。
实施例5
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为表面覆盖有二氧化硅(SiO 2)的P型高掺杂硅片，其表面具有300nm厚的SiO 2层2，底部为Si层1，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将硅片吹干。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底的上表面蒸镀多个矩形的过渡金属区，形成过渡金属层，各过渡金属区的面积小于基底上表面的面积，其厚度为0.5nm，材质为Pt。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有多个用于蒸镀源漏电极的孔，孔呈矩形，每个孔位于过渡金属的一侧，且每个孔的下方正对部分过渡金属和部分基底的表面，从而在源漏电极之间形成沟道区域。
(4)在孔中蒸镀源漏电极6，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极的一部分直接与一部分过渡金属接触，另外一部分直接与基底接触，且过渡金属的一部分未与源漏电极接触。
(5)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为500度。将硒粉放在低温区，在245度下进行挥发，使得未与源漏电极接触的Pt金属暴露在硒气氛中被硒化后形成PtSe 28。
(6)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管阵列(图 7)。
实施例6
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底9，其为玻璃，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将基底吹干。
(2)在基底9的部分上表面蒸镀金属栅极10(图8)，具体采用电子束蒸发或者磁控溅射在基底的上表面蒸镀铬/金。
(3)在金属栅极10的上表面沉积栅介质层11(图9)，具体采用电子束蒸发、磁控溅射或者原子层沉积法在金属栅极的上表面沉积氧化铝。所沉积的栅介质层11覆盖了金属栅极10的一部分。
(4)采用电子束蒸发、磁控溅射或者原子层沉积法在位于金属栅极10正上方的栅介质层11的上表面蒸镀一个矩形的过渡金属区3，其面积小于基底上栅介质层11的面积(图10)，形成过渡金属层，其厚度为0.1nm，材质为Mo。
(5)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极6的孔，孔呈矩形，每个孔的下方正对部分过渡金属区3和部分栅介质层11的表面，两个孔分别位于过渡金属区3的两侧，即在源漏电极6之间形成沟道区域。
(6)在孔中蒸镀源漏电极6，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出被光刻胶覆盖的区域。此时源漏电极6的一部分直接与一部分过渡金属区3接触，另外一部分直接与栅介质层11接触，且过渡金属的一部分未与源漏电极6接触(图11)。源漏电极6与金属栅极10完全被栅介质层11隔开，但是俯视情况下，源漏电极6与金属栅极10在空间坐标上有1-2微米的交叠，如图13所示，虚线处代表被覆盖的区域，实线处代表肉眼可见区域。
(7)将基底9放到双温区管式炉中，并将基底9放在高温区，控制温度为680度。将硫粉放在低温区，在130度下进行挥发，使得未与源漏电极6接触的Mo金属暴露在硫气氛中被硫化后形成MoS 27(图12)。
(8)将处理后的样品取出，自然降温后形成二维材料的场效应晶体管。
实施例7
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底，其为聚合物柔性材料，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将基底吹干。
(2)在基底的部分上表面蒸镀金属栅极，具体采用电子束蒸发或者磁控溅射在基底的上表面蒸镀ITO(氧化铟锡)。
(3)在金属栅极的上表面沉积栅介质层，具体采用转移的方法在金属栅极的上表面覆盖氮化硼。所述栅介质层覆盖了金属栅极的一部分。
(4)采用电子束蒸发、磁控溅射或者原子层沉积法在位于金属栅极正上方的栅介质层的上表面蒸镀一个矩形的过渡金属区，其面积小于基底上栅介质的面积，形成过渡金属层，其厚度为0.1nm，材质为Mo。
(5)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极的孔，孔呈矩形，每个孔的下方正对部分过渡金属区和部分栅介质层的表面，两个孔分别位于过渡金属区的两侧，即在源漏电极之间形成沟道区域。
(6)在孔中蒸镀源漏电极，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金，随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极的一部分直接与一部分过渡金属区接触，另外一部分直接与栅介质层接触，且过渡金属的一部分未与源漏电极接触。源漏电极与金属栅极完全被栅介质层隔开，但是俯视情况下，源漏电极与金属栅极在空间坐标上有1-2微米的交叠。
(7)将基底放到双温区管式炉中，并将基底放在高温区，控制温度为680度。将硫粉放在低温区，在130度下进行挥发，使得未与源漏电极接触的Mo金属暴露在硫气氛中被硫化后形成MoS 2。
(8)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管。
实施例8
本实施例提供了一种降低二维材料场效应晶体管接触电阻的方法，包括以下步骤：
(1)准备基底9，其为玻璃，分别用丙酮、乙醇、去离子水进行清洗，然后用氮***将基底吹干。
(2)采用电子束蒸发、磁控溅射或者原子层沉积法在基底9的上表面蒸镀一个矩形的过渡金属区3(图14)，其面积小于基底9的面积，形成过渡金属层，其厚度为0.1nm，材质为Mo。
(3)旋涂光刻胶，随后曝光、显影，形成光刻胶层，光刻胶层上具有两个用于蒸镀源漏电极6的孔，孔呈矩形，每个孔的下方正对部分过渡金属区3和部分基底9的表面，两个孔分别位于过渡金属区3的两侧，即在源漏电极6之间形成沟道区域。
(4)在孔中蒸镀源漏电极6，具体采用电子束蒸发或者磁控溅射分别在孔中蒸镀钛和金， 随后用丙酮溶液去除剩余的光刻胶，露出其他部分的基底。此时源漏电极6的一部分直接与一部分过渡金属区3接触，另外一部分直接与基底9接触，且过渡金属的一部分未与源漏电极6接触(图15)。
(5)将基底9放到双温区管式炉中，并将基底9放在高温区，控制温度为680度。将硫粉放在低温区，在130度下进行挥发，使得未与源漏电极6接触的Mo金属暴露在硫气氛中被硫化后形成MoS 27(图16)。
(6)沉积栅介质层11，具体采用电子束蒸发、磁控溅射或者原子层沉积法沉积氧化铝。所沉积的栅介质层完全覆盖MoS 27和源漏电极6(图17)。
(7)在栅介质层11的上表面蒸镀金属栅极10，具体采用电子束蒸发或者磁控溅射在栅介质层11的上表面蒸镀ITO(氧化铟锡)。金属栅极10的尺寸小于下方栅介质层11的尺寸。(图18)，金属栅极10与源漏电极6完全被栅介质层11隔开，但是俯视情况下，源漏电极6与金属栅极10在空间坐标上有1-2微米的交叠，如图19所示，虚线处代表被覆盖的区域，实线处代表肉眼可见区域。
(8)将处理后的样品取出，自然降温后在基底上形成二维材料的场效应晶体管。
以上所述仅是本发明的优选实施方式，并不用于限制本发明，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变型，这些改进和变型也应视为本发明的保护范围。

Claims (10)

  1. 一种降低二维材料场效应晶体管接触电阻的方法，其特征在于，包括以下步骤：
    (1)在部分基底的表面蒸镀至少一个过渡金属区，形成过渡金属层；其中，所述过渡金属区的厚度为0.1-2nm；
    (2)光刻、显影后形成光刻胶层，所述光刻胶层上具有至少两个用于蒸镀源漏电极的孔，每个孔的下方正对至少一部分所述过渡金属层的表面，每个孔位于所述过渡金属区的一侧；
    (3)在所述孔中蒸镀源漏电极，然后去除所述光刻胶层，露出其他部分的基底；
    (4)使用硫源对过渡金属进行硫化或使用硒源对过渡金属进行硒化，冷却后在基底表面形成所述二维材料场效应晶体管。
  2. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(1)中，所述基底的材质绝缘，所述基底的材质为玻璃或聚合物柔性材料。
  3. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(1)中，所述基底的表面为绝缘介质层，所属绝缘介质层的材质为二氧化硅、氧化铝、氧化铪或者氧化锆，所述绝缘介质层的厚度为20-300nm。
  4. 根据权利要求2或3所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(1)中，还包括在所述基底与所述过渡金属层之间依次沉积栅极和栅介质的步骤。
  5. 根据权利要求2或3所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(4)中，冷却前还包括依次沉积栅介质和栅极的步骤。
  6. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(1)中，所述过渡金属为钼、铂、钨、锰、镍、镉或钯中的一种。
  7. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(3)中，所述源漏电极为钛电极、金电极、铝电极和铬电极中的一种或两种。
  8. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(4)中，所述硫源为硫粉、硫化钠或硫化氢中的一种。
  9. 根据权利要求1所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：在步骤(4)中，所述硒源为硒粉或硒化氢。
  10. 根据权利要求1、8、9中任一项所述的降低二维材料场效应晶体管接触电阻的方法，其特征在于：
    在步骤(4)中，将基底加热到550-750℃，将所述硫源加热到115-130℃后形成含硫气 氛，所述含硫气氛接触过渡金属对其进行硫化；或者
    在步骤(4)中，将基底加热到400-500℃，将所述硒源加热到230-245℃后形成含硒气氛，所述含硒气氛接触过渡金属对其进行硒化。
PCT/CN2018/071344 2017-11-15 2018-01-04 降低二维材料场效应晶体管接触电阻的方法 WO2019095532A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711127151.3 2017-11-15
CN201711127151.3A CN107919388A (zh) 2017-11-15 2017-11-15 降低二维材料场效应晶体管接触电阻的方法

Publications (1)

Publication Number Publication Date
WO2019095532A1 true WO2019095532A1 (zh) 2019-05-23

Family

ID=61896390

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/071344 WO2019095532A1 (zh) 2017-11-15 2018-01-04 降低二维材料场效应晶体管接触电阻的方法

Country Status (2)

Country Link
CN (1) CN107919388A (zh)
WO (1) WO2019095532A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878516A (zh) * 2018-05-08 2018-11-23 广东工业大学 一种横向结构的二维材料场效应晶体管及其制备方法和应用
CN115274446A (zh) * 2021-04-30 2022-11-01 长鑫存储技术有限公司 晶体管结构、半导体结构及其制备方法
CN113725360B (zh) * 2021-09-02 2024-06-11 中国人民解放军国防科技大学 基于二硫化钽电荷密度波相变的热场晶体管及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106129112A (zh) * 2016-07-04 2016-11-16 华为技术有限公司 一种基于二维半导体的电子器件及其制造方法
CN106328708A (zh) * 2015-07-03 2017-01-11 三星电子株式会社 包括二维材料结构的装置及形成该二维材料结构的方法
CN106486531A (zh) * 2015-08-31 2017-03-08 台湾积体电路制造股份有限公司 半导体装置
US20170098717A1 (en) * 2015-10-05 2017-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture
CN107017303A (zh) * 2016-01-06 2017-08-04 台湾积体电路制造股份有限公司 半导体装置结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328708A (zh) * 2015-07-03 2017-01-11 三星电子株式会社 包括二维材料结构的装置及形成该二维材料结构的方法
CN106486531A (zh) * 2015-08-31 2017-03-08 台湾积体电路制造股份有限公司 半导体装置
US20170098717A1 (en) * 2015-10-05 2017-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture
CN107017303A (zh) * 2016-01-06 2017-08-04 台湾积体电路制造股份有限公司 半导体装置结构
CN106129112A (zh) * 2016-07-04 2016-11-16 华为技术有限公司 一种基于二维半导体的电子器件及其制造方法

Also Published As

Publication number Publication date
CN107919388A (zh) 2018-04-17

Similar Documents

Publication Publication Date Title
CN100448031C (zh) 底栅极薄膜晶体管、具有其的平板显示器及其制备方法
KR101312259B1 (ko) 박막 트랜지스터 및 그 제조방법
WO2019095532A1 (zh) 降低二维材料场效应晶体管接触电阻的方法
CN109300917A (zh) 一种阵列基板及其制备方法、显示面板
US20150084035A1 (en) Thin film transistor and method of manufacturing the same
US20170316953A1 (en) Method for fabricating metallic oxide thin film transistor
WO2005069383A1 (ja) 電界効果トランジスタ及びそれを用いた表示装置
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
JP2009010348A (ja) チャンネル層とその形成方法、及び該チャンネル層を含む薄膜トランジスタとその製造方法
US10833104B2 (en) Array substrate and its fabricating method, display device
WO2018223476A1 (zh) 铟镓锌氧化物薄膜晶体管的制作方法
TW201820423A (zh) 氧化物半導體裝置及其製造方法
JP2020520557A (ja) Ｏｌｅｄ表示パネルおよびその製造方法
WO2017219412A1 (zh) 顶栅型薄膜晶体管的制作方法
JP2010205765A (ja) 自己整合半導体トランジスタの製造方法
WO2019095556A1 (zh) 阵列基板、显示面板及阵列基板的制作方法
JP2020509615A (ja) 半導体デバイスのショットキーコンタクト構造及びそのようなショットキーコンタクト構造を形成する方法
JP2009206388A (ja) 薄膜トランジスタとその製造方法
KR101623583B1 (ko) 박막 트랜지스터의 제조방법
CN109148372B (zh) 薄膜晶体管制作方法、薄膜晶体管以及显示面板
US10818704B2 (en) Method for manufacturing thin film transistor, and thin film transistor, including forming an organic light-emitting device
TWI611587B (zh) 氧化物薄膜電晶體
JPS59136971A (ja) 薄膜電界効果トランジスタの製造方法
CN118039702A (zh) 一种顶栅肖特基氧化物薄膜晶体管及制备方法
WO2018045612A1 (zh) 氧化物薄膜晶体管的制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18878235

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18878235

Country of ref document: EP

Kind code of ref document: A1