WO2019056795A1 - 移位寄存器单元、驱动装置、显示装置以及驱动方法 - Google Patents

移位寄存器单元、驱动装置、显示装置以及驱动方法 Download PDF

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Publication number
WO2019056795A1
WO2019056795A1 PCT/CN2018/089281 CN2018089281W WO2019056795A1 WO 2019056795 A1 WO2019056795 A1 WO 2019056795A1 CN 2018089281 W CN2018089281 W CN 2018089281W WO 2019056795 A1 WO2019056795 A1 WO 2019056795A1
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WIPO (PCT)
Prior art keywords
pull
node
output
reset
terminal
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PCT/CN2018/089281
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English (en)
French (fr)
Inventor
丛乐乐
孙建
王珍
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18839590.9A priority Critical patent/EP3686876A4/en
Priority to US16/323,406 priority patent/US11315471B2/en
Publication of WO2019056795A1 publication Critical patent/WO2019056795A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a driving device, a display device, and a driving method.
  • a pixel array such as a liquid crystal display typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by an attached integrated driving circuit.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • GOA Gate driver On Array
  • a GOA composed of a plurality of cascaded shift register units may be used to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and corresponding to the pixel arrays by the data lines.
  • the pixel units of the row provide data signals to form the gray voltages required to display the gray levels of the image, thereby displaying each frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first pull-up node reset circuit, an output circuit, an output reset circuit, a pull-down node control circuit, and a power-on initialization circuit.
  • the input circuit is configured to charge a pull-up node in response to an input signal;
  • the first pull-up node reset circuit is configured to reset the pull-up node under control of a reset signal;
  • the output circuit Configuring to output a first clock signal to an output terminal under control of a level of the pull-up node;
  • the output reset circuit configured to perform the output terminal under control of a level of a pull-down node Reset;
  • the pull-down node control circuit is configured to control a potential of the pull-down node;
  • the power-on initialization circuit is configured to reset the pull-up node in response to a power-on initialization signal.
  • the input circuit is connected to an input terminal and the pull-up node; the first pull-up node reset circuit and the reset terminal, the first voltage terminal, and the The pull-up node is connected;
  • the output circuit is connected to the first clock signal end, the output end, and the pull-up node;
  • the output reset circuit is connected to the output end, the first voltage end, and the pull-down node;
  • a pull-down node control circuit is coupled to the second clock signal terminal, the first voltage terminal, the output terminal, and the pull-down node; the power-on initialization circuit and the initialization terminal, the first voltage terminal, and the upper Pull the node to connect.
  • the pull-down node control circuit includes a pull-down node charging circuit and a pull-down node reset circuit.
  • the pull-down node charging circuit is coupled to the second clock signal terminal, the first voltage terminal, and the pull-down node, and configured to respond to the pull-down node in response to a second clock signal different from the first clock signal Charging is performed;
  • the pull-down node reset circuit is connected to the output terminal, the first voltage terminal, and the pull-down node, and is configured to reset the pull-down node under the control of the level of the output terminal.
  • the pull-down node charging circuit includes: a first transistor having a gate connected to the first pole and configured to be connected to the second clock signal end Receiving the second clock signal, the second pole is configured to be connected to the pull-down node to charge the pull-down node; the first capacitor has a first pole connected to the pull-down node, and a second pole The first voltage terminal is connected.
  • the pull-down node charging circuit includes: a first transistor having a gate configured to be coupled to the second clock signal terminal to receive the second clock Signaling, the first pole is configured to be coupled to the second voltage terminal to receive the second voltage, and the second pole is configured to be coupled to the pull-down node to charge the pull-down node; the first capacitor, the first pole thereof The pull-down node is connected, and the second pole is connected to the first voltage terminal.
  • the pull-down node reset circuit includes: a second transistor whose gate is configured to be connected to the output terminal to receive control of a level of the output terminal a first pole is configured to be coupled to the pull down node to reset the pull down node, and a second pole is configured to be coupled to the first voltage terminal to receive a first voltage.
  • a shift register unit further includes a second pull-up node reset circuit, the second pull-up node reset circuit and the second clock signal terminal, the first voltage terminal, and the A pull-up node connection is configured to reset the pull-up node in response to the second clock signal.
  • the second pull-up node reset circuit includes: a third transistor having a gate configured to be connected to the second clock signal terminal to receive the And a second clock signal, the first pole is configured to be coupled to the pull up node to reset the pull up node, and the second pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the power-on initialization circuit includes: a fourth transistor having a gate configured to be connected to the initialization terminal to receive the power-on initialization signal, A pole is configured to be coupled to the pull up node to reset the pull up node, and a second pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the input circuit includes: a fifth transistor having a gate connected to the first electrode and configured to be connected to the input to receive the input
  • a second pole is configured to be coupled to the pull up node to charge the pull up node.
  • the input circuit includes: a fifth transistor whose gate is configured to be connected to the input terminal to receive the input signal, and the first pole is configured To be coupled to the second voltage terminal to receive a second voltage, the second pole is configured to be coupled to the pull up node to charge the pull up node.
  • the first pull-up node reset circuit includes: a sixth transistor having a gate configured to be connected to the reset terminal to receive the reset signal, A first pole is configured to be coupled to the pull up node to reset the pull up node, and a second pole is configured to be coupled to the first voltage terminal to receive a first voltage.
  • the output circuit includes: a seventh transistor having a gate configured to be connected to the pull-up node, the first pole being configured to be the same a clock signal terminal connected to receive the first clock signal, a second pole configured to be coupled to the output terminal to output the first clock signal; a second capacitor having a first pole and the seventh transistor The gate is connected, and the second pole is connected to the second pole of the seventh transistor.
  • the output reset circuit includes: an eighth transistor having a gate configured to be connected to the pull-down node, the first pole being configured to be the output The terminal is connected to output a first voltage to the output, and the second pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • At least one embodiment of the present disclosure also provides a driving apparatus including a plurality of cascaded shift register units according to any of the embodiments of the present disclosure. Except for the first stage shift register unit, the input terminals of the remaining shift register units are connected to the output terminals of the shift register unit of the previous stage; except for the last stage shift register unit, the remaining shift register units The reset terminal is connected to the output of the next stage shift register unit.
  • the power-on initialization circuit in the shift register units of each stage is configured to respond to the same power-on initialization signal.
  • At least one embodiment of the present disclosure also provides a display device including the driving device according to any of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, comprising: providing the power-on initialization signal to the power-on initialization circuit to reset the pull-up node; and providing the input circuit to the input circuit Inputting a signal to charge the pull-up node; the output reset circuit resetting the output terminal under control of a level of the pull-down node; the output circuit is at a level of the pull-up node Controlling the first clock signal to the output; providing the reset signal to the first pull-up node reset circuit to reset the pull-up node.
  • 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a timing chart of signals corresponding to the operation of the shift register unit shown in FIG. 1;
  • FIG. 3 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram showing a specific implementation example of the shift register unit shown in FIG. 3;
  • FIG. 5 is a circuit diagram showing another specific implementation example of the shift register unit shown in FIG. 3;
  • Figure 6 is a timing diagram of signals corresponding to the operation of the shift register unit shown in Figure 5;
  • FIG. 7 is a schematic diagram of a driving device according to an embodiment of the present disclosure.
  • Figure 8 is a timing diagram of a clock signal having a duty ratio of 50% for the driving device shown in Figure 7;
  • FIG. 9 is a schematic diagram of another driving device according to an embodiment of the present disclosure.
  • Figure 10 is a timing diagram of a clock signal having a duty ratio of 25% for the driving device shown in Figure 9;
  • FIG. 11 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display panel in order to realize low cost and narrow bezel, GOA (Gate driver On Array) technology can be adopted, that is, the gate driving circuit is integrated on the display panel through the thin film transistor process, thereby achieving narrow bezel and reducing assembly cost, etc.
  • GOA Gate driver On Array
  • the display panel may be a liquid crystal display (LCD) panel or an organic light emitting diode (OLED) display panel.
  • Figure 1 shows the circuit structure of a shift register unit which can be cascaded to form a GOA driver.
  • the shift register unit includes eight transistors (first transistor - eighth transistor) and two capacitors (first capacitor and second capacitor).
  • the first transistor T1 has a gate connected to the first electrode and is configured to be connected to the second clock signal terminal CKB, and the second electrode is connected to the pull-down node PD.
  • the second transistor T2 has a gate connected to the output terminal OUTPUT, a first pole connected to the pull-down node PD, and a second pole connected to the first voltage terminal VGL (eg, holding an input DC low level signal).
  • the third transistor T3 has a gate connected to the pull-down node PD, a first pole connected to the pull-up node PU, and a second pole connected to the first voltage terminal VGL.
  • the fourth transistor T4 has a gate connected to the pull-up node PU, a first pole connected to the pull-down node PD, and a second pole connected to the first voltage terminal VGL.
  • the fifth transistor T5 has a gate connected to the input terminal INPUT, a first pole connected to the high-level terminal CN (for example, holding an input DC high-level signal), and a second pole connected to the pull-up node PU.
  • the sixth transistor T6 has a gate connected to the reset terminal RESET, a first pole connected to the pull-up node PU, and a second pole connected to the low-level terminal CNB (eg, maintaining an input DC low-level signal).
  • the seventh transistor T7 has a gate connected to the pull-up node PU, a first pole connected to the first clock signal terminal CK, and a second pole connected to the output terminal OUTPUT.
  • the eighth transistor T8 has a gate connected to the pull-down node PD, a first pole connected to the output terminal OUTPUT, and a second pole connected to the first voltage terminal VGL.
  • the first capacitor C1 has a first pole connected to the pull-down node PD and a second pole connected to the first voltage terminal VGL.
  • the second capacitor C2 has a first pole connected to the pull-up node PU and a second pole connected to the output terminal OUTPUT.
  • the above transistors are all N-type transistors.
  • the following description is also made by taking an N-type transistor as an example, but embodiments of the present disclosure are not limited to such a case, for example, these transistors may be at least partially replaced with P-type transistors.
  • the operation principle of the shift register unit shown in FIG. 1 will be described below with reference to the signal timing shown in FIG. 2.
  • the shift register unit performs the following operations.
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level
  • the input terminal INPUT inputs a high level. Since the input terminal INTPUT inputs a high level, the fifth transistor T5 is turned on, so that the high level input by the high level terminal CN charges the second capacitor C2, and the potential of the pull-up node PU is pulled up to the first high level.
  • the first transistor T1 Since the second clock signal terminal CKB is input with a high level, the first transistor T1 is turned on, and the high level input by the second clock signal terminal CKB charges the pull-down node PD. Further, since the potential of the pull-up node PU is at the first high level, the fourth transistor T4 is turned on, thereby electrically connecting the pull-down node PD and the first voltage terminal VGL.
  • the first voltage terminal VGL may be set to hold an input DC low level signal.
  • the first transistor T1 and the fourth transistor T4 may be configured (for example, a size ratio of the two, a threshold voltage, etc.).
  • the seventh transistor T7 Since the pull-up node PU is at the first high level, the seventh transistor T7 is turned on, and at this time, the first clock signal terminal CK is input with a low level, so at this stage, the output terminal OUTPUT outputs the low level signal.
  • the first clock signal terminal CK inputs a high level
  • the second clock signal terminal CKB inputs a low level
  • the input terminal INPUT inputs a low level. Since the input terminal INPUT inputs a low level, the fifth transistor T5 is turned off, and the pull-up node PU maintains the first high level of the previous stage, so that the seventh transistor T7 remains turned on, since the first clock signal terminal CK at this stage The input is high, so the output OUTPUT outputs the high level signal.
  • the level of the pull-up node PU is further pulled high to reach the second high level, so that the conduction of the seventh transistor T7 is more sufficient. Since the potential of the pull-up node PU is at a high level, the fourth transistor T4 continues to be turned on, so that the pull-down node PD and the first voltage terminal VGL are electrically connected, and at this time, the first transistor T1 is low due to the input of the second clock signal terminal CKB. The level is off, so the potential of the pull-down node PD is pulled down to a lower level at this stage than in the first stage. Since the potential of the pull-down node PD is at a low level, the third transistor T3 and the eighth transistor T8 remain in an off state, thereby not affecting the normal output shift signal of the shift register unit.
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level
  • the input terminal INPUT continues to input a low level
  • the reset terminal RESET inputs a high level. Since the reset terminal RESET inputs a high level, the sixth transistor T6 is turned on, pulling the potential of the pull-up node PU to a low level input to the low-level terminal CNB (for example, keeping the input DC low-level signal), so that the seventh transistor T7 cutoff.
  • the first transistor T1 Since the second clock signal terminal CKB is input with a high level, the first transistor T1 is turned on, and the high level input by the second clock signal terminal CKB charges the pull-down node PD. At the same time, since the potential of the pull-up node PU is at a low level, the fourth transistor T4 is turned off, the discharge path of the pull-down node PD is turned off, and the pull-down node PD is charged to a high level, thereby causing the third transistor T3 and the eighth transistor T8 to be led.
  • the pull-up node PU and the pull-down node PD have a mutually constrained relationship. For example, when the potential of the pull-up node PU is high, the potential of the pull-down node PD is pulled down to a low level; for example, when the potential of the pull-down node PD is high, the potential of the pull-up node PU is pulled down to a low level. Level.
  • the potential of the pull-up node PU directly affects the output of the shift register unit, and the potential of the pull-up node PU should be stably maintained at a low level in the non-output stage, otherwise the shift register unit may be in a frame time. Cause multiple outputs. In the non-output phase, if the potential of the pull-down node PD is not well maintained at a high level, the potential of the pull-up node PU may drift, thereby affecting the normal output of the shift register unit.
  • the shift register unit when used in a display device, for example, the pull-up node PU is suspended before the display device is powered on, and the potential of the pull-up node PU is uncertain in the floating state, for example, the potential of the pull-up node PU reaches At the time of 2.5V, the seventh transistor T7 can be turned on, which may also cause the shift register unit to output multiple times within one frame time, causing the display device to display an abnormality.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first pull-up node reset circuit, an output circuit, an output reset circuit, and a power-on initialization circuit.
  • the input circuit is configured to charge the pull-up node in response to the input signal;
  • the first pull-up node reset circuit is configured to reset the pull-up node under control of the reset signal;
  • the output circuit is configured to be The first clock signal is output to the output terminal under the control of the level of the pull node;
  • the output reset circuit is configured to reset the output terminal under the control of the level of the pull-down node;
  • the power-on initialization circuit is configured to The pull-up node is reset in response to the power-on initialization signal.
  • At least one embodiment of the present disclosure also provides a driving device, a display device, and a driving method corresponding to the shift register unit described above.
  • the shift register unit, the driving device, the display device and the driving method provided by the embodiments of the present disclosure can pull down the potential of the pull-up node when the power is turned on, so that it is kept at a low level when the power is turned on. And at least one embodiment can also avoid drifting of the potential of the pull-up node, so that multiple output problems due to potential drift of the pull-up node in the non-output phase can be effectively avoided.
  • the shift register unit 100 includes an input circuit 110, a first pull-up node reset circuit 120, an output circuit 130, and an output reset circuit 140.
  • the pull-down node control circuit 160 and the power-on initialization circuit 150 are examples of the shift register unit 100.
  • the input circuit 110 is configured to charge the pull up node PU in response to an input signal.
  • the input circuit 110 can be connected to the input terminal INPUT and the pull-up node PU, and configured to electrically connect the input terminal INPUT and the pull-up node PU under the control of the signal input by the input terminal INPUT, so that the input terminal INPUT input is high.
  • the level signal can charge the pull-up node PU; for example, the input circuit 110 can also be connected to the second voltage terminal VGH (for example, to maintain an input DC high-level signal), configured to be under the control of the input signal.
  • the second voltage terminal VGH and the pull-up node PU are electrically connected, so that the high-level signal input by the second voltage terminal VGH can charge the pull-up node PU.
  • the first pull-up node reset circuit 120 is configured to reset the pull-up node PU under the control of the reset signal.
  • the first pull-up node reset circuit 120 can be configured to be connected to the reset terminal RESET, the first voltage terminal VGL (eg, to maintain an input DC low-level signal), and the pull-up node PU so that the input can be RESET at the reset terminal.
  • the pull-up node PU Under the control of the reset signal, the pull-up node PU is electrically connected to the low-level signal or the low-voltage terminal, and the low-voltage terminal is, for example, the first voltage terminal VGL, so that the pull-up node PU can be pulled down and reset.
  • the output circuit 130 is configured to output a first clock signal to the output terminal OUTPUT under the control of the level of the pull-up node PU.
  • the output circuit 130 can be configured to be connected to the first clock signal terminal CK, the output terminal OUTPUT, and the pull-up node PU, so that the first clock signal terminal CK can be made under the control of the level of the pull-up node PU.
  • the output terminal OUTPUT is electrically connected, thereby outputting the first clock signal input from the first clock signal terminal CK to the output terminal OUTPUT.
  • the output reset circuit 140 is configured to reset the output terminal OUTPUT under the control of the level of the pull-down node PD.
  • the output reset circuit 140 may be configured to be connected to the output terminal OUTPUT, the first voltage terminal VGL, and the pull-down node PD, so that the output terminal OUTPUT and the first voltage terminal VGL can be controlled under the control of the level of the pull-down node PD. Electrically connected to pull down the output OUTPUT.
  • the power up initialization circuit 150 is configured to reset the pull up node PU in response to the power up initialization signal.
  • the power-on initialization circuit 150 may be configured to be connected to the initialization terminal VSW, the first voltage terminal VGL, and the pull-up node PU to cause the pull-up node PU and the first voltage in response to the power-on initialization signal input by the initialization terminal VSW.
  • the terminal VGL is electrically connected, thereby performing pull-down reset on the pull-up node PU.
  • the pull-down node control circuit 160 is configured to be connected to the second clock signal terminal CKB, the first voltage terminal VGL, the output terminal OUTPUT, and the pull-down node PD, and controls the potential of the pull-down node PD to control the output reset circuit 140.
  • a plurality of cascaded shift register units 100 may be employed to constitute a driving device, and when the driving device is used to drive the display device, for example, the power-on initialization circuit 150 in each shift register unit 100 at power-on and power-on.
  • the potential of the pull-up node PU in the respective circuit is pulled down, so that the potential of the pull-up node PU is kept at a low level when the power is turned on, thereby effectively avoiding the non-output.
  • the stage has multiple output problems due to the potential drift of the pull-up node PU.
  • the pull-down node control circuit 160 can include a pull-down node charging circuit 161 and a pull-down node reset circuit 162.
  • the pull-down node charging circuit 161 is configured to charge the pull-down node PD in response to a second clock signal different from the first clock signal.
  • the pull-down node charging circuit 161 can be configured to be connected to the second clock signal terminal CKB, the first voltage terminal VGL, and the pull-down node PD, so that the second clock can be made under the control of the signal input by the second clock signal terminal CKB.
  • the signal terminal CKB and the pull-down node PD are electrically connected, so that the high-level signal input by the second clock signal terminal CKB can charge the pull-down node PD; for example, the pull-down node charging circuit 161 can also be configured to be connected to the second voltage terminal.
  • VGH is connected, so that the second voltage terminal VGH and the pull-down node PD can be electrically connected under the control of the second clock signal input by the second clock signal terminal CKB, so that the high-level signal input by the second voltage terminal VGH can be The pull-down node PD is charged.
  • the pull-down node reset circuit 162 is configured to reset the pull-down node PD under the control of the level of the output terminal OUTPUT.
  • the pull-down node reset circuit 162 can be configured to be connected to the output terminal OUTPUT, the first voltage terminal VGL, and the pull-down node PD, so that the pull-down node PD and the first voltage terminal can be controlled under the control of the level of the output terminal OUTPUT.
  • the VGL is electrically connected, thereby performing a pull-down reset on the pull-down node PD.
  • the shift register unit 100 may further include a second pull-up node reset circuit 170.
  • the second pull up node reset circuit 170 is configured to reset the pull up node PU in response to the second clock signal.
  • the second pull-up node reset circuit 170 may be configured to be connected to the second clock signal terminal CKB, the first voltage terminal VGL, and the pull-up node PU, so that the second clock signal that can be input at the second clock signal terminal CKB can be Under the control, the pull-up node PU and the first voltage terminal VGL are electrically connected, thereby performing pull-down reset on the pull-up node PU.
  • the pull-up node PU and the pull-down node PD no longer have a mutually constrained relationship.
  • the potential of the pull-up node PU is no longer affected by the potential of the pull-down node PD, so that in the non-output phase, the potential of the pull-up node PU can be effectively maintained at the normal potential, thereby effectively avoiding the drift of the potential of the pull-up node PU. And caused multiple output problems.
  • first voltage terminal VGL in the embodiment of the present disclosure maintains, for example, an input DC low level signal, and the DC low level is referred to as a first voltage; and the second voltage terminal VGH maintains an input DC high level, for example.
  • the signal which is referred to as the second voltage.
  • the second voltage terminal VGH connected to the input circuit 110 and the pull-down node charging circuit 161 in FIG. 3 is shown by a broken line, thereby indicating that the shift register unit 100 may include the second voltage terminal VGH or may not include the second.
  • the voltage terminal VGH is not limited by the embodiment of the present disclosure.
  • the shift register unit 100 shown in FIG. 3 can be implemented as the circuit structure shown in FIG. 4 in one example.
  • the shift register unit 100 includes first to eighth transistors T1-T8 and a first capacitor C1 and a second capacitor C2.
  • the pull-down node charging circuit 161 may be implemented to include the first transistor T1 and the first capacitor C1.
  • the gate of the first transistor T1 is connected to the first pole, and is configured to be connected to the second clock signal terminal CKB to receive the second clock signal, and the second pole is configured to be connected to the pull-down node PD to charge the pull-down node PD
  • the first pole of the first capacitor is connected to the pull-down node PD, and the second pole is connected to the first voltage terminal VGL.
  • the pull-down node reset circuit 162 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be coupled to the output terminal OUTPUT to accept control of the level of the output terminal OUTPUT, the first pole being configured to be connected to the pull-down node PD to reset the pull-down node PD, the second pole being configured It is connected to the first voltage terminal VGL to receive the first voltage.
  • the second pull-up node reset circuit 170 can be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be coupled to the second clock signal terminal CKB to receive the second clock signal, the first pole being configured to be coupled to the pull-up node PU to reset the pull-up node PU, the second pole being It is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the power-on initialization circuit 150 can be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be coupled to the initialization terminal VSW to receive a power-on initialization signal, the first pole being configured to be coupled to the pull-up node PU to reset the pull-up node PU, the second pole being configured to The first voltage terminal VGL is connected to receive the first voltage.
  • the input circuit 110 can be implemented as a fifth transistor T5.
  • a gate of the fifth transistor T5 is coupled to the first pole and is configured to be coupled to the input terminal INPUT to receive an input signal, and the second pole is configured to be coupled to the pull-up node PU to charge the pull-up node PU.
  • the first pull-up node reset circuit 120 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to be connected to the reset terminal RESET to receive a reset signal
  • the first pole is configured to be connected to the pull-up node PU to reset the pull-up node PU
  • the second pole is configured to be the first
  • the voltage terminal VGL is connected to receive the first voltage.
  • the output circuit 130 can be implemented to include a seventh transistor T7 and a second capacitor C2.
  • the gate of the seventh transistor T7 is configured to be connected to the pull-up node PU, the first pole is configured to be coupled to the first clock signal terminal CK to receive the first clock signal, and the second pole is configured to be coupled to the output terminal OUTPUT
  • the first clock signal is output; the first pole of the second capacitor C2 is connected to the gate of the seventh transistor T7, and the second pole is connected to the second pole of the seventh transistor T7.
  • the output reset circuit 140 can be implemented as an eighth transistor T8.
  • the gate of the eighth transistor T8 is configured to be connected to the pull-down node PD, the first pole is configured to be connected to the output terminal OUTPUT to output the first voltage to the output terminal OUTPUT, and the second pole is configured to be coupled to the first voltage terminal VGL Connect to receive the first voltage.
  • the shift register unit 100 shown in FIG. 3 can also be implemented as the circuit structure shown in FIG. 5 in another example.
  • the shift register unit 100 also includes first to eighth transistors T1-T8 and a first capacitor C1 and a second capacitor C2.
  • the circuit structure shown in FIG. 5 differs from the circuit structure shown in FIG. 4 in the manner in which the first transistor T1 and the fifth transistor T5 are connected.
  • the first pole of the first transistor T1 is no longer connected to the gate but to the second voltage terminal VGH.
  • the first pole of the fifth transistor T5 is no longer connected to the gate but to the second voltage terminal VGH.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt a P-type transistor.
  • the first pole may be a source
  • the second pole may be a drain, and only needs to be selected.
  • the polarities of the poles of the transistor of a given type may be correspondingly connected according to the polarities of the respective poles of the respective transistors in the embodiment of the present disclosure.
  • the transistors in the shift register unit 100 all adopt N-type transistors, the first voltage terminal VGL maintains the first voltage of the input DC low level, and the second voltage terminal VGH maintains the input DC high level.
  • the second voltage, the first clock signal terminal CK inputs a first clock signal, and the second clock signal terminal CKB inputs a second clock signal different from the first clock signal.
  • the shift register unit 100 performs the following operations.
  • the initialization terminal VSW inputs a high level. Since the initialization terminal VSW inputs a high level, the fourth transistor T4 is turned on, so that the pull-up node PU and the first voltage terminal VGL are electrically connected, and the potential of the pull-up node PU is pulled down to a low level. The seventh transistor T7 is turned off due to the low level of the pull-up node PU. Therefore, even if the first clock signal terminal CK is input to the high level at this stage, the output terminal OUTPUT cannot output the high level. It should be noted that the potential of the pull-down node PD is uncertain at this stage, and the potential of the pull-down node PD in the A phase is only schematically shown in FIG. 6. In addition, at this stage, other transistors are also kept off, and will not be described again.
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level
  • the input terminal INPUT inputs a high level. Since the input terminal INTPUT inputs a high level, the fifth transistor T5 is turned on, so that the high level input by the second voltage terminal VGH charges the second capacitor C2, and the potential of the pull-up node PU is pulled up to the first high level. . Since the pull-up node PU is at the first high level, the seventh transistor T7 is turned on, and at this time, the first clock signal terminal CK is input with a low level, so at this stage, the output terminal OUTPUT outputs the low level signal.
  • the third transistor T3 Since the second clock signal terminal CKB is input to the high level, the third transistor T3 is turned on, so that the pull-up node PU and the first voltage terminal VGL are electrically connected.
  • the third transistor T3 and the fifth transistor T5 can be configured (for example, the size ratio of the two, the threshold voltage, etc.). When both T3 and T5 are turned on, the level of the pull-up node PU can be Stay at the first high level without being pulled down.
  • the first transistor T1 is turned on by the high level input from the second clock signal terminal CKB, and the high level input from the second voltage terminal VGH charges the first capacitor C1, and the potential of the pull-down node PD is pulled high.
  • the second transistor T2 is kept off due to the low level of the output terminal OUTPUT, and the discharge path of the pull-down node PD is turned off, so in the second phase B, the potential of the pull-down node PD is maintained at the high level.
  • the eighth transistor T8 is turned on due to the high level of the pull-down node PD, so that the potential of the output terminal OUTPUT is further pulled down, and the effect of output noise reduction can be achieved.
  • the first clock signal terminal CK inputs a high level
  • the second clock signal terminal CKB inputs a low level
  • the input terminal INPUT still inputs a low level. Since the input terminal INPUT inputs a low level, the fifth transistor T5 is turned off, and the pull-up node PU maintains the first high level of the previous stage, so that the seventh transistor T7 remains turned on, since the first clock signal terminal CK at this stage The input is high, so the output OUTPUT outputs the high level signal. Due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node PU is further pulled high to reach the second high level, so that the conduction of the seventh transistor T7 is more sufficient.
  • the second transistor T2 Since the output terminal OUTPUT is at a high level, the second transistor T2 is turned on, and the pull-down node PD is electrically connected to the first voltage terminal VGL, and at this time, the first transistor T1 is turned off due to the low level input by the second clock signal terminal, so The first capacitor C1 is discharged through the second transistor, and the potential of the pull-down node PD is pulled down to a low level.
  • the third transistor T3 Since the second clock signal terminal CKB is input with a low level, the third transistor T3 is kept in an off state, so that the potential of the pull-up node PU is not affected. At the same time, since the potential of the pull-down node PD is at a low level, the eighth transistor T8 remains in an off state, so that the shift register signal of the shift register unit 100 is not normally affected.
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level
  • the input terminal INPUT continues to input a low level
  • the reset terminal RESET inputs a high level. Since the reset terminal RESET inputs a high level, the sixth transistor T6 is turned on, pulling down the potential of the pull-up node PU to the low level input by the first voltage terminal VGL, thereby turning off the seventh transistor T7.
  • the first transistor T1 Since the second clock signal terminal CKB is input to the high level, the first transistor T1 is turned on, the high level input by the second voltage terminal VGH charges the first capacitor C1, and the potential of the pull-down node PD is pulled up to the high level. Since the potential of the pull-down node PD is at a high level, the eighth transistor T8 is turned on, so that the output terminal OUTPUT and the first voltage terminal VGL are electrically connected, thereby performing pull-down reset on the output terminal OUTPUT. At this stage, the second transistor T2 is kept off due to the low level of the output terminal OUTPUT, so that the potential of the pull-down node PD can be kept at the high level.
  • the third transistor T3 is turned on, so that the low level input by the first voltage terminal VGL further pulls down the potential of the pull-up node PU, thereby making the potential of the pull-up node PU Stay low at this stage.
  • a plurality of cascaded shift register units 100 as shown in FIG. 4 or FIG. 5 may be employed to constitute a driving device.
  • the driving device when used to drive the display device, for example, when the power is turned on, the same power-on initialization signal can be simultaneously input through the initialization terminal VSW in each stage of the shift register unit 100, and the pull-up in the shift register unit 100 of each stage is performed.
  • the potential of the node PU is pulled down, so that the potential of the pull-up node PU is kept at a low level when the power is turned on, so that the multiple output problem caused by the potential drift of the pull-up node in the non-output stage can be effectively avoided.
  • the pull-up node PU and the pull-down node PD no longer have a mutually constrained relationship.
  • the second clock signal input by the second clock signal terminal CKB can individually control the potential of the pull-up node PU, so that it is no longer affected by the potential of the pull-down node PD, so that the potential of the pull-up node PU can be effective in the non-output phase. It is maintained at a normal potential, so that it is possible to effectively avoid multiple output problems caused by the drift of the PU potential of the pull-up node.
  • At least one embodiment of the present disclosure provides a driving apparatus 10, as shown in FIG. 7, the driving apparatus 10 includes a plurality of cascaded shift register units 100, and the shift register unit 100 may adopt any of the above-described embodiments.
  • the driving device 10 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scan driving function.
  • the input terminal INPUT of the remaining stages of the shift register unit is connected to the output terminal OUTPUT of the shift register unit of the previous stage.
  • the reset terminal RESET of the remaining stages of shift register units is connected to the output terminal OUTPUT of the next stage shift register unit.
  • the input INPUT of the first stage shift register unit can be configured to receive the trigger signal STV
  • the reset terminal RESET of the last stage shift register unit can be configured to receive the reset signal RST.
  • the driving device 10 when the driving device 10 is used to drive a display panel, the driving device 10 can be disposed on one side of the display panel in one example.
  • the display panel includes 2N row gate lines 300 (N is an integer greater than zero), and the output terminals OUTPUT of the stages of the shift register unit 100 in the driving device 10 may be configured to sequentially and the 2N row gate lines 300 ( As shown by the 1, 2, ..., 2N-1, 2N marks in Fig. 7, N is an integer greater than zero) for outputting a progressive scan signal.
  • a clock signal can be supplied to the clock signal terminals (the first clock signal terminal CK and the second clock signal terminal CKB) in each shift register unit 100 by the two system clock signals CLK1 and CLK2.
  • the first clock signal terminal CK of the first stage shift register unit 100 inputs CLK1
  • the second clock signal terminal CKB inputs CLK2
  • the first clock signal terminal CK of the second stage shift register unit 100 inputs CLK2, the second clock signal.
  • the terminal CKB inputs CLK1; and so on, the first clock signal terminal CK of the 2N-1th stage shift register unit 100 inputs CLK1, the second clock signal terminal CKB inputs CLK2; the first clock of the 2Nth stage shift register unit 100
  • the signal terminal CK is input to CLK2, and the second clock signal terminal CKB is input to CLK1.
  • the initialization terminals VSW of the shift register units 100 of the stages can be connected to the same signal line in response to the same power-on initialization signal POR.
  • CLK1 and CLK2 can adopt a 50% duty cycle timing signal. Since the shift register unit 100 of each stage is sequentially arranged row by row in the case shown in FIG. 7, CLK1 and The timing of CLK2 is staggered by a system clock time of 1H.
  • the driving device 10 when driving a display panel by using the driving device 10 as shown in FIG. 7, the driving device 10 may be symmetrically disposed on both sides of the display panel, so that the output terminals OUTPUT of the two driving devices 10 are connected. To both ends of the corresponding gate line, thereby achieving bilateral driving.
  • the bilateral driving method can be used in driving a large-sized display panel to solve the problem of large load on the gate line.
  • the driving device 10 in another example of the embodiment of the present disclosure, as shown in FIG. 9, in the case where the driving device 10 is provided on both sides of the display panel (bilateral driving), it is also possible to use the driving device 10 on one side for The odd-numbered row of gate lines 300 (shown as 1, 3, ..., 2N-3, 2N-1 in FIG. 9, N is an integer greater than zero), and the other side of the driving device 10 is used to drive even rows
  • the gate line 300 (shown as 2, 4, ..., 2N-2, 2N marks in Fig. 9, N is an integer greater than zero). It should be noted that, in FIG.
  • the clock signal in each shift register unit 100 can be passed through the two system clock signals CLK3 and CLK4 in the driving device 10 on the right side.
  • the terminal (the first clock signal terminal CK and the second clock signal terminal CKB) provides a clock signal, and the timings of CLK3 and CLK4 are staggered by two system clock times 2H.
  • the clock signal CLK1 and the clock signal CLK3 may be the same clock signal, and the clock signal CLK2 and the clock signal CLK4 may be the same clock signal.
  • CLK1 and CLK2 can adopt a timing signal of 25% duty ratio, since in the case shown in FIG. 9, the driving device 10 on each side is Interlaced, so the timing of CLK1 and CLK2 is staggered by two system clock times 2H.
  • each stage of the shift register unit 100 in the driving devices 10 on both sides can occupy a space of two pixel heights, so that the area occupied by the shift register unit 100 Under the premise of constant, the width of the border of the display panel can be reduced, which is beneficial to realize a narrow border.
  • the drive device 10 may further include a timing controller 200.
  • the timing controller 200 is configured, for example, to provide clock signals (CLK1, CLK2) to the shift register units 100 of each stage, and the timing controller 200 can also be configured to provide a trigger signal STV, a reset signal RST, and a power-on initialization signal POR.
  • timing controller 200 may also be configured to provide four different clock signals to the shift register units 100 through the four clock signal lines, the present disclosure. The embodiment does not limit this.
  • At least one embodiment of the present disclosure provides a display device 1, as shown in FIG. 11, which includes any of the drive devices 10 provided in the above embodiments.
  • the display device in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc., having any display function.
  • the display device 1 may further include other conventional components such as a display panel, and embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive any of the shift register units 100 provided in the embodiments of the present disclosure.
  • the driving method includes the following operations.
  • the up-up initialization circuit 150 provides a power-on initialization signal to reset the pull-up node PU; an input signal is provided to the input circuit 110 to charge the pull-up node PU; and the output reset circuit 140 controls the output-side under the control of the level of the pull-down node PD
  • the OUTPUT is reset; the output circuit 130 supplies a first clock signal to the output terminal OUTPUT under the control of the level of the pull-up node PU; and provides a reset signal to the first pull-up node reset circuit 120 to reset the pull-up node PU.
  • the up-light initialization circuit 150 provides a power-on initialization signal to reset the pull-up node PU.
  • an input signal is supplied to the input circuit 110 to charge the pull-up node PU; the output reset circuit 140 resets the output terminal OUTPUT under the control of the level of the pull-down node PD.
  • the output circuit 130 supplies a first clock signal to the output terminal OUTPUT under the control of the level of the pull-up node PU.
  • a reset signal is supplied to the first pull-up node reset circuit 120 to reset the pull-up node PU; and the output reset circuit 140 outputs the output under the control of the level of the pull-down node PD.
  • the terminal OUTPUT is reset.
  • the driving method provided in this embodiment can pull down the potential of the pull-up node when the power is turned on, so that it stays in a low state when the power is turned on, and can also prevent the potential of the pull-up node from drifting. Therefore, it is possible to effectively avoid the multiple output problem caused by the potential drift of the pull-up node in the non-output stage.

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Abstract

一种移位寄存器单元、驱动装置、显示装置以及驱动方法。该移位寄存器单元(100)包括输入电路(110)、第一上拉节点复位电路(120)、输出电路(130)、输出复位电路(140)、下拉节点控制电路(160)和上电初始化电路(150)。上电初始化电路(150)被配置为响应于上电初始化信号对上拉节点(PU)进行复位。该移位寄存器单元可以避免上拉节点的电位发生漂移，从而可以有效避免由于上拉节点的电位漂移而造成的多次输出问题。

Description

移位寄存器单元、驱动装置、显示装置以及驱动方法
本申请要求于2017年9月21日递交的中国专利申请第201710859100.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种移位寄存器单元、驱动装置、显示装置以及驱动方法。
背景技术
在显示技术领域，例如液晶显示器的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、第一上拉节点复位电路、输出电路、输出复位电路、下拉节点控制电路和上电初始化电路。所述输入电路被配置为响应于输入信号对上拉节点进行充电；所述第一上拉节点复位电路被配置为在复位信号的控制下，对所述上拉节点进行复位；所述输出电路被配置为在所述上拉节点的电平的控制下，将第一时钟信号输出至输出端；所述输出复位电路被配置为在下拉节点的电平的控制下，对所述输出端进行复位；所述下拉节点控制电路被配置为对所述下拉节点的电位进行控制；所述上电初始化电路被配置为响应于上电 初始化信号对所述上拉节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路与输入端和所述上拉节点连接；所述第一上拉节点复位电路与复位端、第一电压端和所述上拉节点连接；所述输出电路与第一时钟信号端、输出端和所述上拉节点连接；所述输出复位电路与输出端、所述第一电压端和所述下拉节点连接；所述下拉节点控制电路与第二时钟信号端、所述第一电压端、所述输出端和所述下拉节点连接；所述上电初始化电路与初始化端、所述第一电压端和所述上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉节点控制电路包括下拉节点充电电路和下拉节点复位电路。所述下拉节点充电电路与所述第二时钟信号端、所述第一电压端和所述下拉节点连接，被配置为响应不同于所述第一时钟信号的第二时钟信号对所述下拉节点进行充电；所述下拉节点复位电路与所述输出端、所述第一电压端和所述下拉节点连接，被配置在所述输出端的电平的控制下，对所述下拉节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉节点充电电路包括：第一晶体管，其栅极和第一极连接，且被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第二极被配置为和所述下拉节点连接以对所述下拉节点进行充电；第一电容，其第一极和所述下拉节点连接，第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉节点充电电路包括：第一晶体管，其栅极被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第一极被配置为和第二电压端连接以接收第二电压，第二极被配置为和所述下拉节点连接以对所述下拉节点进行充电；第一电容，其第一极和所述下拉节点连接，第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉节点复位电路包括：第二晶体管，其栅极被配置为和所述输出端连接以接受所述输出端的电平的控制，第一极被配置为和所述下拉节点连接以对所述下拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
例如，本公开一实施例提供的移位寄存器单元还包括第二上拉节点复位电路，所述第二上拉节点复位电路与所述第二时钟信号端、所述第一电压端和所述上拉节点连接，被配置为响应所述第二时钟信号对所述上拉节 点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二上拉节点复位电路包括：第三晶体管，其栅极被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述上电初始化电路包括：第四晶体管，其栅极被配置为和所述初始化端连接以接收所述上电初始化信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括：第五晶体管，其栅极和第一极连接，且被配置为和所述输入端连接以接收所述输入信号，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括：第五晶体管，其栅极被配置为和所述输入端连接以接收所述输入信号，第一极被配置为和所述第二电压端连接以接收第二电压，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一上拉节点复位电路包括：第六晶体管，其栅极被配置为和所述复位端连接以接收所述复位信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括：第七晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和所述第一时钟信号端连接以接收所述第一时钟信号，第二极被配置为和所述输出端连接以输出所述第一时钟信号；第二电容，其第一极和所述第七晶体管的栅极连接，第二极和所述第七晶体管的第二极连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出复位电路包括：第八晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述输出端连接以将第一电压输出至所述输出端，第二极被配置为和所述第一电压端连接以接收所述第一电压。
本公开至少一实施例还提供一种驱动装置，包括多个级联的本公开任一实施例所述的移位寄存器单元。除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的输出端连接；除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的输出端连接。
例如，在本公开一实施例提供的驱动装置中，所述各级移位寄存器单元中的所述上电初始化电路被配置为响应于同一上电初始化信号。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例所述的驱动装置。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：向所述上电初始化电路提供所述上电初始化信号以复位所述上拉节点；向所述输入电路提供所述输入信号以对所述上拉节点进行充电；所述输出复位电路在所述下拉节点的电平的控制下对所述输出端进行复位；所述输出电路在所述上拉节点的电平的控制下向所述输出端提供所述第一时钟信号；向所述第一上拉节点复位电路提供所述复位信号以对所述上拉节点进行复位。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种移位寄存器单元的电路示意图；
图2为对应于图1中所示的移位寄存器单元工作时的信号时序图；
图3为本公开一实施例提供的一种移位寄存器单元的示意框图；
图4为图3中所示的移位寄存器单元的一种具体实现示例的电路示意图；
图5为图3中所示的移位寄存器单元的另一种具体实现示例的电路示意图；
图6为对应于图5中所示的移位寄存器单元工作时的信号时序图；
图7为本公开一实施例提供的一种驱动装置的示意图；
图8为一种用于图7中所示的驱动装置的占空比为50％的时钟信号时 序图；
图9为本公开一实施例提供的另一种驱动装置的示意图；
图10为一种用于图9中所示的驱动装置的占空比为25％的时钟信号时序图；以及
图11为本公开一实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate driver On Array)技术，即将栅极驱动电路通过薄膜晶体管工艺集成在显示面板上，从而可以实现窄边框和降低装配成本等优势。该显示面板可以为液晶显示(LCD)面板或有机发光二极管(OLED)显示面板。
图1示出了一种移位寄存器单元的电路结构，该移位寄存器单元可以被级联以形成GOA驱动装置。如图1所示，该移位寄存器单元包括八个晶体管(第一晶体管-第八晶体管)和两个电容(第一电容和第二电容)。
第一晶体管T1，其栅极和第一极连接且被配置为和第二时钟信号端CKB连接，第二极和下拉节点PD连接。
第二晶体管T2，其栅极和输出端OUTPUT连接，第一极和下拉节点PD连接，第二极和第一电压端VGL(例如保持输入直流低电平信号)连接。
第三晶体管T3，其栅极和下拉节点PD连接，第一极和上拉节点PU连接，第二极和第一电压端VGL连接。
第四晶体管T4，其栅极和上拉节点PU连接，第一极和下拉节点PD连接，第二极和第一电压端VGL连接。
第五晶体管T5，其栅极和输入端INPUT连接，第一极和高电平端CN(例如保持输入直流高电平信号)连接，第二极和上拉节点PU连接。
第六晶体管T6，其栅极和复位端RESET连接，第一极和上拉节点PU连接，第二极和低电平端CNB(例如保持输入直流低电平信号)连接。
第七晶体管T7，其栅极和上拉节点PU连接，第一极和第一时钟信号端CK连接，第二极和输出端OUTPUT连接。
第八晶体管T8，其栅极和下拉节点PD连接，第一极和输出端OUTPUT连接，第二极和第一电压端VGL连接。
第一电容C1，其第一极和下拉节点PD连接，第二极和第一电压端VGL连接。
第二电容C2，其第一极和上拉节点PU连接，第二极和输出端OUTPUT连接。
例如上述晶体管均为N型晶体管。下面也以N型晶体管为例进行说明，但是本公开的实施例不限于这种情形，例如这些晶体管至少部分可以替换为P型晶体管。
下面结合图2所示的信号时序来说明图1所示的移位寄存器单元的工作原理，在图2所示的第一阶段A、第二阶段B以及第三阶段C共三个阶段中，该移位寄存器单元进行如下操作。
在第一阶段A，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平，输入端INPUT输入高电平。由于输入端INTPUT输入高电平，第五晶体管T5导通，使得高电平端CN输入的高电平对第二电容C2进行充电，上拉节点PU的电位被上拉至第一高电平。
由于第二时钟信号端CKB输入高电平，第一晶体管T1导通，第二时钟信号端CKB输入的高电平对下拉节点PD进行充电。又由于上拉节点PU的电位为第一高电平，第四晶体管T4导通，从而使得下拉节点PD和第一电压 端VGL电连接。这里，例如第一电压端VGL可以设置为保持输入直流低电平信号。在晶体管的设计上，可以将第一晶体管T1和第四晶体管T4配置为(例如对二者的尺寸比、阈值电压等配置)在T1和T4均导通时，下拉节点PD的电位被下拉到一个较低的电平，该低电平不会使第三晶体管和第八晶体管T8开启。需要说明的是，图2中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
由于上拉节点PU处于第一高电平，第七晶体管T7导通，此时第一时钟信号端CK输入低电平，所以在此阶段，输出端OUTPUT输出该低电平信号。
在第二阶段B，第一时钟信号端CK输入高电平，第二时钟信号端CKB输入低电平，输入端INPUT输入低电平。由于输入端INPUT输入低电平，第五晶体管T5截止，上拉节点PU保持上一阶段的第一高电平，从而使得第七晶体管T7保持导通，由于在此阶段第一时钟信号端CK输入高电平，所以输出端OUTPUT输出该高电平信号。
同时，由于第二电容C2的自举效应，上拉节点PU的电平被进一步拉高，达到第二高电平，使得第七晶体管T7的导通更充分。由于上拉节点PU的电位为高电平，第四晶体管T4继续导通，使得下拉节点PD和第一电压端VGL电连接，而此时第一晶体管T1由于第二时钟信号端CKB输入的低电平而截止，所以与第一阶段相比，在此阶段下拉节点PD的电位被下拉到一个更低的低电平。由于下拉节点PD的电位为低电平，第三晶体管T3和第八晶体管T8保持截止状态，从而不会影响移位寄存器单元正常输出移位信号。
在第三阶段C，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平，输入端INPUT继续输入低电平，复位端RESET输入高电平。由于复位端RESET输入高电平，第六晶体管T6导通，将上拉节点PU的电位下拉到低电平端CNB(例如保持输入直流低电平信号)输入的低电平，从而第七晶体管T7截止。
由于第二时钟信号端CKB输入高电平，第一晶体管T1导通，第二时钟信号端CKB输入的高电平对下拉节点PD进行充电。同时由于上拉节点PU的电位处于低电平，第四晶体管T4截止，下拉节点PD的放电路径被截止，下拉节点PD被充电至高电平，由此使得第三晶体管T3和第八晶体管T8导通，分别将上拉节点PU和输出端OUTPUT的电位下拉到第一电压端VGL输入的低电平，消除了移位寄存器单元在非输出阶段其输出端OUTPUT和 上拉节点PU处可能产生的噪声。
上述移位寄存器单元在工作时，上拉节点PU和下拉节点PD存在相互制约的关系。例如当上拉节点PU的电位为高电平时，下拉节点PD的电位会被下拉至低电平；又例如当下拉节点PD的电位为高电平时，上拉节点PU的电位会被下拉至低电平。上拉节点PU的电位的高低直接影响着该移位寄存器单元的输出，在非输出阶段上拉节点PU的电位应稳定的保持在低电平，否则移位寄存器单元在一帧时间内可能会造成多次输出。在非输出阶段，如果下拉节点PD的电位未能良好的保持在高电平，则可能导致上拉节点PU的电位发生漂移，从而影响该移位寄存器单元的正常输出。
另外，当上述移位寄存器单元例如用于显示装置中时，在该显示装置开机上电前上拉节点PU悬空，悬空状态下上拉节点PU的电位不确定，例如上拉节点PU的电位达到2.5V时就可以使第七晶体管T7导通，从而也可能导致该移位寄存器单元在一帧时间内多次输出，致使该显示装置显示异常。
本公开至少一实施例提供一种移位寄存器单元，其包括输入电路、第一上拉节点复位电路、输出电路、输出复位电路和上电初始化电路。该输入电路被配置为响应于输入信号对上拉节点进行充电；该第一上拉节点复位电路被配置为在复位信号的控制下，对上拉节点进行复位；该输出电路被配置为在上拉节点的电平的控制下，将第一时钟信号输出至输出端；该输出复位电路被配置为在下拉节点的电平的控制下，对输出端进行复位；该上电初始化电路被配置为响应于上电初始化信号对上拉节点进行复位。
本公开至少一实施例还提供对应于上述移位寄存器单元的驱动装置、显示装置以及驱动方法。
本公开的实施例提供的移位寄存器单元、驱动装置、显示装置以及驱动方法，可以在开机上电时对上拉节点的电位进行下拉，使其在开机上电时保持在低电平状态，并且至少一个实施例还可以避免上拉节点的电位发生漂移，从而可以有效避免在非输出阶段由于上拉节点的电位漂移而造成的多次输出问题。
下面结合附图对本公开的实施例进行详细说明。
本公开实施例的一个示例提供一种移位寄存器单元100，如图3所示，该移位寄存器单元100包括输入电路110、第一上拉节点复位电路120、输出电路130、输出复位电路140、下拉节点控制电路160和上电初始化电路 150。
该输入电路110被配置为响应于输入信号对上拉节点PU进行充电。例如，该输入电路110可以与输入端INPUT和上拉节点PU连接，被配置为在输入端INPUT输入的信号的控制下使输入端INPUT和上拉节点PU电连接，从而输入端INPUT输入的高电平信号可以对上拉节点PU进行充电；又例如，该输入电路110还可以与第二电压端VGH(例如保持输入直流高电平信号)连接，被配置为在输入信号的控制下，使第二电压端VGH和上拉节点PU电连接，从而第二电压端VGH输入的高电平信号可以对上拉节点PU进行充电。
该第一上拉节点复位电路120被配置为在复位信号的控制下，对上拉节点PU进行复位。例如，该第一上拉节点复位电路120可以被配置为与复位端RESET、第一电压端VGL(例如保持输入直流低电平信号)和上拉节点PU连接，从而可以在复位端RESET输入的复位信号的控制下，使得上拉节点PU和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL，从而可以对上拉节点PU进行下拉复位。
该输出电路130被配置为在上拉节点PU的电平的控制下，将第一时钟信号输出至输出端OUTPUT。例如，该输出电路130可以被配置为与第一时钟信号端CK、输出端OUTPUT和上拉节点PU连接，从而可以在上拉节点PU的电平的控制下，使第一时钟信号端CK和输出端OUTPUT电连接，从而将第一时钟信号端CK输入的第一时钟信号输出至输出端OUTPUT。
该输出复位电路140被配置为在下拉节点PD的电平的控制下，对输出端OUTPUT进行复位。例如，该输出复位电路140可以被配置为与输出端OUTPUT、第一电压端VGL和下拉节点PD连接，从而可以在下拉节点PD的电平的控制下，使输出端OUTPUT和第一电压端VGL电连接，从而对输出端OUTPUT进行下拉复位。
该上电初始化电路150被配置为响应于上电初始化信号对上拉节点PU进行复位。例如，该上电初始化电路150可以被配置为与初始化端VSW、第一电压端VGL和上拉节点PU连接，以响应于初始化端VSW输入的上电初始化信号使上拉节点PU和第一电压端VGL电连接，从而对上拉节点PU进行下拉复位。
该下拉节点控制电路160被配置为与第二时钟信号端CKB、第一电压端 VGL、输出端OUTPUT和下拉节点PD连接，对下拉节点PD的电位进行控制，进而对输出复位电路140进行控制。
例如，可以采用多个级联的上述移位寄存器单元100构成一驱动装置，当使用该驱动装置驱动显示装置时，例如在开机上电时各级移位寄存器单元100中的上电初始化电路150可以同时响应于同一上电初始化信号，对各自电路中的上拉节点PU的电位进行下拉，使上拉节点PU的电位在开机上电时保持在低电平状态，从而可以有效避免在非输出阶段由于上拉节点PU的电位漂移而造成的多次输出问题。
例如，在本实施例的一个示例中，下拉节点控制电路160可以包括下拉节点充电电路161和下拉节点复位电路162。
该下拉节点充电电路161被配置为响应不同于第一时钟信号的第二时钟信号对下拉节点PD进行充电。例如，该下拉节点充电电路161可以被配置为与第二时钟信号端CKB、第一电压端VGL和下拉节点PD连接，从而可以在第二时钟信号端CKB输入的信号的控制下使第二时钟信号端CKB和下拉节点PD电连接，从而第二时钟信号端CKB输入的高电平信号可以对下拉节点PD进行充电；又例如，该下拉节点充电电路161还可以被配置为与第二电压端VGH连接，从而可以在第二时钟信号端CKB输入的第二时钟信号的控制下，使第二电压端VGH和下拉节点PD电连接，从而使第二电压端VGH输入的高电平信号可以对下拉节点PD进行充电。
该下拉节点复位电路162被配置在输出端OUTPUT的电平的控制下，对下拉节点PD进行复位。例如，该下拉节点复位电路162可以被配置为与输出端OUTPUT、第一电压端VGL和下拉节点PD连接，从而可以在输出端OUTPUT的电平的控制下，使下拉节点PD和第一电压端VGL电连接，从而对下拉节点PD进行下拉复位。
又例如，在本公开实施例的另一个示例中，如图3所示，移位寄存器单元100还可以包括第二上拉节点复位电路170。
该第二上拉节点复位电路170被配置为响应于第二时钟信号对上拉节点PU进行复位。例如，该第二上拉节点复位电路170可以被配置为与第二时钟信号端CKB、第一电压端VGL和上拉节点PU连接，从而可以在第二时钟信号端CKB输入的第二时钟信号的控制下，使上拉节点PU和第一电压端VGL电连接，从而对上拉节点PU进行下拉复位。
在本示例提供的移位寄存器单元中，上拉节点PU和下拉节点PD不再存在相互制约的关系。上拉节点PU的电位不再受下拉节点PD的电位的影响，从而在非输出阶段，上拉节点PU的电位可以有效的保持在正常电位，从而可以有效避免因为上拉节点PU的电位的漂移而造成的多次输出问题。
需要说明的是，本公开的实施例中的第一电压端VGL例如保持输入直流低电平信号，将该直流低电平称为第一电压；第二电压端VGH例如保持输入直流高电平信号，将该直流高电平称为第二电压。以下各实施例与此相同，不再赘述。
另外，图3中和输入电路110以及下拉节点充电电路161连接的第二电压端VGH用虚线示出，以此表示此移位寄存器单元100可以包括第二电压端VGH，也可以不包括第二电压端VGH，本公开的实施例对此不作限定。
例如，图3中所示的移位寄存器单元100在一个示例中可以实现为图4所示的电路结构。如图4所示，该移位寄存器单元100包括：第一至第八晶体管T1-T8以及第一电容C1和第二电容C2。
例如，如图4所示，在该示例中，更详细地，下拉节点充电电路161可以实现为包括第一晶体管T1和第一电容C1。第一晶体管T1的栅极和第一极连接，且被配置为和第二时钟信号端CKB连接以接收第二时钟信号，第二极被配置为和下拉节点PD连接以对下拉节点PD进行充电；第一电容的第一极和下拉节点PD连接，第二极和第一电压端VGL连接。
下拉节点复位电路162可以实现为第二晶体管T2。第二晶体管T2的栅极被配置为和输出端OUTPUT连接以接受输出端OUTPUT的电平的控制，第一极被配置为和下拉节点PD连接以对下拉节点PD进行复位，第二极被配置为和第一电压端VGL连接以接收第一电压。
第二上拉节点复位电路170可以实现为第三晶体管T3。第三晶体管T3的栅极被配置为和第二时钟信号端CKB连接以接收第二时钟信号，第一极被配置为和上拉节点PU连接以对上拉节点PU进行复位，第二极被配置为和第一电压端VGL连接以接收第一电压。
上电初始化电路150可以实现为第四晶体管T4。第四晶体管T4的栅极被配置为和初始化端VSW连接以接收上电初始化信号，第一极被配置为和上拉节点PU连接以对上拉节点PU进行复位，第二极被配置为和第一电压端VGL连接以接收第一电压。
输入电路110可以实现为第五晶体管T5。第五晶体管T5的栅极和第一极连接，且被配置为和输入端INPUT连接以接收输入信号，第二极被配置为和上拉节点PU连接以对上拉节点PU进行充电。
所述第一上拉节点复位电路120可以实现为第六晶体管T6。第六晶体管T6的栅极被配置为和复位端RESET连接以接收复位信号，第一极被配置为和上拉节点PU连接以对上拉节点PU进行复位，第二极被配置为和第一电压端VGL连接以接收第一电压。
输出电路130可以实现为包括第七晶体管T7和第二电容C2。第七晶体管T7的栅极被配置为和上拉节点PU连接，第一极被配置为和第一时钟信号端CK连接以接收第一时钟信号，第二极被配置为和输出端OUTPUT连接以输出第一时钟信号；第二电容C2的第一极和第七晶体管T7的栅极连接，第二极和第七晶体管T7的第二极连接。
输出复位电路140可以实现为第八晶体管T8。第八晶体管T8的栅极被配置为和下拉节点PD连接，第一极被配置为和输出端OUTPUT连接以将第一电压输出至输出端OUTPUT，第二极被配置为和第一电压端VGL连接以接收第一电压。
例如，图3中所示的移位寄存器单元100在另一个示例中还可以实现为图5所示的电路结构。如图5所示，该移位寄存器单元100同样包括：第一至第八晶体管T1-T8以及第一电容C1和第二电容C2。
图5中所示的电路结构和图4中所示的电路结构的不同之处在于第一晶体管T1和第五晶体管T5的连接方式。这里，第一晶体管T1的第一极不再和栅极连接，而是和第二电压端VGH连接。类似的，第五晶体管T5的第一极不再和栅极连接，而是和第二电压端VGH连接。采用图5中所示的这种连接方式，可以提高第一晶体管T1和第五晶体管T5的响应速度和驱动能力。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此 时，第一极可以是漏极，第二极可以是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，第一极可以是源极，第二极可以是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。
例如，如图5所示，该移位寄存器单元100中的晶体管均采用N型晶体管，第一电压端VGL保持输入直流低电平的第一电压，第二电压端VGH保持输入直流高电平的第二电压，第一时钟信号端CK输入第一时钟信号，第二时钟信号端CKB输入与第一时钟信号不同的第二时钟信号。
下面结合图6所示的信号时序图，对图5所示的移位寄存器单元100的工作原理进行说明，在图6所示的第一阶段A、第二阶段B、第三阶段C以及第四阶段D共四个阶段中，该移位寄存器单元100进行如下操作。
在第一阶段A，初始化端VSW输入高电平。由于初始化端VSW输入高电平，第四晶体管T4导通，使得上拉节点PU和第一电压端VGL电连接，上拉节点PU的电位被下拉至低电平。第七晶体管T7由于上拉节点PU的低电平而截止，所以在此阶段即使第一时钟信号端CK输入高电平，输出端OUTPUT也无法将此高电平输出。需要说明的是，在此阶段下拉节点PD的电位不确定，图6中仅示意性的示出了下拉节点PD在A阶段的电位。另外在此阶段，其他晶体管也都保持截止状态，不再赘述。
在第二阶段B，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平，输入端INPUT输入高电平。由于输入端INTPUT输入高电平，第五晶体管T5导通，使得第二电压端VGH输入的高电平对第二电容C2进行充电，上拉节点PU的电位被上拉至第一高电平。由于上拉节点PU处于第一高电平，第七晶体管T7导通，此时第一时钟信号端CK输入低电平，所以在此阶段，输出端OUTPUT输出该低电平信号。
由于第二时钟信号端CKB输入高电平，第三晶体管T3导通，使得上拉节点PU和第一电压端VGL电连接。在晶体管的设计上，可以将第三晶体管T3与第五晶体管T5配置为(例如对二者的尺寸比、阈值电压等配置)在T3和T5均导通时，上拉节点PU的电平可以保持在第一高电平而不被下拉。
同样的，第一晶体管T1由于第二时钟信号端CKB输入的高电平而导通，第二电压端VGH输入的高电平对第一电容C1进行充电，下拉节点PD的电 位被拉高。同时第二晶体管T2由于输出端OUTPUT的低电平而保持截止，下拉节点PD的放电路径被截止，故在第二阶段B中，下拉节点PD的电位保持在高电平。第八晶体管T8由于下拉节点PD的高电平而导通，从而使输出端OUTPUT的电位进一步被拉低，可以达到输出降噪的效果。
在第三阶段C，第一时钟信号端CK输入高电平，第二时钟信号端CKB输入低电平，输入端INPUT依然输入低电平。由于输入端INPUT输入低电平，第五晶体管T5截止，上拉节点PU保持上一阶段的第一高电平，从而使得第七晶体管T7保持导通，由于在此阶段第一时钟信号端CK输入高电平，所以输出端OUTPUT输出该高电平信号。由于第二电容C2的自举效应，上拉节点PU的电位被进一步拉高，达到第二高电平，使得第七晶体管T7的导通更充分。
由于输出端OUTPUT为高电平，第二晶体管T2导通，下拉节点PD和第一电压端VGL电连接，而此时第一晶体管T1由于第二时钟信号端输入的低电平而截至，所以第一电容C1通过第二晶体管放电，下拉节点PD的电位被下拉至低电平。
由于第二时钟信号端CKB输入低电平，故第三晶体管T3保持截止状态，从而不会影响上拉节点PU的电位。同时由于下拉节点PD的电位为低电平，故第八晶体管T8保持截止状态，从而不会影响该移位寄存器单元100正常输出移位信号。
在第四阶段D，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平，输入端INPUT继续输入低电平，复位端RESET输入高电平。由于复位端RESET输入高电平，第六晶体管T6导通，将上拉节点PU的电位下拉到第一电压端VGL输入的低电平，从而使得第七晶体管T7截止。
由于第二时钟信号端CKB输入高电平，第一晶体管T1导通，第二电压端VGH输入的高电平对第一电容C1进行充电，下拉节点PD的电位被上拉至高电平。由于下拉节点PD的电位为高电平，第八晶体管T8导通，使得输出端OUTPUT和第一电压端VGL电连接，从而对输出端OUTPUT进行下拉复位。在此阶段，第二晶体管T2由于输出端OUTPUT的低电平而保持截止，从而可以保证下拉节点PD的电位保持在高电平。
同时由于第二时钟信号端CKB输入高电平，第三晶体管T3导通，使得第一电压端VGL输入的低电平对上拉节点PU的电位进行进一步下拉，从而 使上拉节点PU的电位在此阶段保持在低电平。
例如，可以采用多个级联的如图4或图5所示的移位寄存器单元100构成一驱动装置。当使用该驱动装置驱动显示装置时，例如在开机上电时可以通过各级移位寄存器单元100中的初始化端VSW同时输入同一上电初始化信号，对各级移位寄存器单元100中的上拉节点PU的电位进行下拉，使上拉节点PU的电位在开机上电时保持在低电平状态，从而可以有效避免在非输出阶段由于上拉节点的电位漂移而造成的多次输出问题。
同时，上拉节点PU和下拉节点PD不再存在相互制约的关系。第二时钟信号端CKB输入的第二时钟信号可以单独控制上拉节点PU的电位，而使其不再受下拉节点PD的电位的影响，从而在非输出阶段，上拉节点PU的电位可以有效的保持在正常电位，从而可以有效避免因为上拉节点PU电位的漂移而造成的多次输出问题。
需要说明的是，对于图4所示的移位寄存器单元100，其工作原理可以参考对于图5中所示的移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例提供一种驱动装置10，如图7所示，该驱动装置10包括多个级联的移位寄存器单元100，移位寄存器单元100可以采用上述实施例中提供的任一移位寄存器单元。该驱动装置10可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。
例如，如图7所示，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INPUT和上一级移位寄存器单元的输出端OUTPUT连接。除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端RESET和下一级移位寄存器单元的输出端OUTPUT连接。例如，第一级移位寄存器单元的输入端INPUT可以被配置为接收触发信号STV，最后一级移位寄存器单元的复位端RESET可以被配置为接收复位信号RST。
例如，如图7所示，当采用该驱动装置10驱动一显示面板时，在一个示例中可以将该驱动装置10设置于显示面板的一侧。例如，该显示面板包括2N行栅线300(N为大于零的整数)，驱动装置10中的各级移位寄存器单元100的输出端OUTPUT可以被配置为依序和该2N行栅线300(如图7中1，2，…，2N-1，2N标记所示，N为大于零的整数)连接，以用于输出逐行扫描信号。
例如，如图7所示，可以通过两个***时钟信号CLK1和CLK2向每个移位寄存器单元100中的时钟信号端(第一时钟信号端CK和第二时钟信号端CKB)提供时钟信号。例如第一级移位寄存器单元100的第一时钟信号端CK输入CLK1，第二时钟信号端CKB输入CLK2；第二级移位寄存器单元100的第一时钟信号端CK输入CLK2，第二时钟信号端CKB输入CLK1；以此类推，第2N-1级移位寄存器单元100的第一时钟信号端CK输入CLK1，第二时钟信号端CKB输入CLK2；第2N级移位寄存器单元100的第一时钟信号端CK输入CLK2，第二时钟信号端CKB输入CLK1。同时，各级移位寄存器单元100的初始化端VSW可以连接到同一信号线上，以响应同一上电初始化信号POR。
例如，如图8所示，CLK1和CLK2可以采用50％占空比的时序信号，由于在图7所示的情形中，各级移位寄存器单元100是依序逐行设置的，所以CLK1和CLK2的时序要错开一个***时钟时间1H。
需要说明的是，在采用如图7所示的驱动装置10驱动一显示面板时，还可以分别在显示面板的两侧对称的设置驱动装置10，使两个驱动装置10中的输出端OUTPUT连接到对应的栅线的两端，从而实现双边驱动。例如，双边驱动方式可以用在对中大尺寸的显示面板的驱动中，以解决栅线上负载较大的问题。
例如，在本公开实施例的另一个示例中，如图9所示，当在显示面板的两侧均设置驱动装置10的情形下(双边驱动)，还可以使一侧的驱动装置10用于驱动奇数行的栅线300(如图9中1，3，…，2N-3，2N-1标记所示，N为大于零的整数)，另一侧的驱动装置10用于驱动偶数行的栅线300(如图9中2，4，…，2N-2，2N标记所示，N为大于零的整数)。需要说明的是，在图9中，和左侧的驱动装置10类似地，在右侧的驱动装置10中可以通过两个***时钟信号CLK3和CLK4向每个移位寄存器单元100中的时钟信号端(第一时钟信号端CK和第二时钟信号端CKB)提供时钟信号，CLK3和CLK4的时序要错开两个***时钟时间2H。其中，时钟信号CLK1和时钟信号CLK3可以为同一个时钟信号，时钟信号CLK2和时钟信号CLK4可以为同一个时钟信号。
对应于图9所示的情形下，例如，如图10所示，CLK1和CLK2可以采用25％占空比的时序信号，由于在图9所示的情形中，每一侧的驱动装置10 是隔行驱动的，所以CLK1和CLK2的时序要错开两个***时钟时间2H。
当采用图9所示的驱动装置驱动显示面板时，可以使两侧的驱动装置10中的每一级移位寄存器单元100占据两个像素高度的空间，这样在移位寄存器单元100所占面积不变的前提下可以减少显示面板的边框宽度，有利于实现窄边框。
例如，如图7和图9所示，驱动装置10还可以包括时序控制器200。该时序控制器200例如被配置为向各级移位寄存器单元100提供时钟信号(CLK1，CLK2)，时序控制器200还可以被配置为提供触发信号STV、复位信号RST以及上电初始化信号POR。
需要说明的是，本公开的实施例包括但不限于上述情形，时序控制器200也可以被配置为通过四条时钟信号线向各级移位寄存器单元100提供四个不同的时钟信号，本公开的实施例对此不作限定。
本公开的实施例提供的驱动装置10的技术效果，可以参考上述实施例中关于移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例提供一种显示装置1，如图11所示，该显示装置1包括上述实施例中提供的任一驱动装置10。
需要说明的是，本实施例中的显示装置可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中提供的任一移位寄存器单元100。例如，该驱动方法包括如下操作。
向上电初始化电路150提供上电初始化信号以复位上拉节点PU；向输入电路110提供输入信号以对上拉节点PU进行充电；输出复位电路140在下拉节点PD的电平的控制下对输出端OUTPUT进行复位；输出电路130在上拉节点PU的电平的控制下向输出端OUTPUT提供第一时钟信号；以及向第一上拉节点复位电路120提供复位信号以对上拉节点PU进行复位。
例如，在一个示例中，在图6中所示的第一阶段A中，向上电初始化电路150提供上电初始化信号以复位上拉节点PU。
在图6中所示的第二阶段B中，向输入电路110提供输入信号以对上拉节点PU进行充电；输出复位电路140在下拉节点PD的电平的控制下对输出端OUTPUT进行复位。
在图6中所示的第三阶段C中，输出电路130在上拉节点PU的电平的控制下向输出端OUTPUT提供第一时钟信号。
在图6中所示的第四阶段D中，向第一上拉节点复位电路120提供复位信号以对上拉节点PU进行复位；输出复位电路140在下拉节点PD的电平的控制下对输出端OUTPUT进行复位。
本实施例中提供的驱动方法，可以在开机上电时对上拉节点的电位进行下拉，使其在开机上电时保持在低电平状态；并且还可以避免上拉节点的电位发生漂移，从而可以有效避免在非输出阶段由于上拉节点的电位漂移而造成的多次输出问题。
需要说明的是，关于该驱动方法的详细描述可以参考本公开实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种移位寄存器单元，包括：输入电路、第一上拉节点复位电路、输出电路、输出复位电路、下拉节点控制电路和上电初始化电路；其中，
    所述输入电路被配置为响应于输入信号对上拉节点进行充电；
    所述第一上拉节点复位电路被配置为在复位信号的控制下，对所述上拉节点进行复位；
    所述输出电路被配置为在所述上拉节点的电平的控制下，将第一时钟信号输出至输出端；
    所述输出复位电路被配置为在下拉节点的电平的控制下，对所述输出端进行复位；
    所述下拉节点控制电路被配置为对所述下拉节点的电位进行控制；
    所述上电初始化电路被配置为响应于上电初始化信号对所述上拉节点进行复位。
  2. 根据权利要求1所述的移位寄存器单元，其中，
    所述输入电路与输入端和所述上拉节点连接；
    所述第一上拉节点复位电路与复位端、第一电压端和所述上拉节点连接；
    所述输出电路与第一时钟信号端、输出端和所述上拉节点连接；
    所述输出复位电路与输出端、所述第一电压端和所述下拉节点连接；
    所述下拉节点控制电路与第二时钟信号端、所述第一电压端、所述输出端和所述下拉节点连接；
    所述上电初始化电路与初始化端、所述第一电压端和所述上拉节点连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述下拉节点控制电路包括下拉节点充电电路和下拉节点复位电路，
    所述下拉节点充电电路与所述第二时钟信号端、所述第一电压端和所述下拉节点连接，被配置为响应不同于所述第一时钟信号的第二时钟信号对所述下拉节点进行充电；
    所述下拉节点复位电路与所述输出端、所述第一电压端和所述下拉节点连接，被配置在所述输出端的电平的控制下，对所述下拉节点进行复位。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述下拉节点充电电路包括：
    第一晶体管，其栅极和第一极连接，且被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第二极被配置为和所述下拉节点连接以对所述下拉节点进行充电；以及
    第一电容，其第一极和所述下拉节点连接，第二极和所述第一电压端连接。
  5. 根据权利要求3所述的移位寄存器单元，其中，所述下拉节点充电电路包括：
    第一晶体管，其栅极被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第一极被配置为和第二电压端连接以接收第二电压，第二极被配置为和所述下拉节点连接以对所述下拉节点进行充电；以及
    第一电容，其第一极和所述下拉节点连接，第二极和所述第一电压端连接。
  6. 根据权利要求3所述的移位寄存器单元，其中，所述下拉节点复位电路包括：
    第二晶体管，其栅极被配置为和所述输出端连接以接受所述输出端的电平的控制，第一极被配置为和所述下拉节点连接以对所述下拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
  7. 根据权利要求3-6任一所述的移位寄存器单元，还包括第二上拉节点复位电路，其中，
    所述第二上拉节点复位电路与所述第二时钟信号端、所述第一电压端和所述上拉节点连接，被配置为响应所述第二时钟信号对所述上拉节点进行复位。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第二上拉节点复位电路包括：
    第三晶体管，其栅极被配置为和所述第二时钟信号端连接以接收所述第二时钟信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
  9. 根据权利要求2-8任一所述的移位寄存器单元，其中，所述上电初始化电路包括：
    第四晶体管，其栅极被配置为和所述初始化端连接以接收所述上电初始化信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
  10. 根据权利要求2-9任一所述的移位寄存器单元，其中，所述输入电路包括：
    第五晶体管，其栅极和第一极连接，且被配置为和所述输入端连接以接收所述输入信号，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
  11. 根据权利要求5所述的移位寄存器单元，其中，所述输入电路包括：
    第五晶体管，其栅极被配置为和所述输入端连接以接收所述输入信号，第一极被配置为和所述第二电压端连接以接收第二电压，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
  12. 根据权利要求2-11任一所述的移位寄存器单元，其中，所述第一上拉节点复位电路包括：
    第六晶体管，其栅极被配置为和所述复位端连接以接收所述复位信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和所述第一电压端连接以接收第一电压。
  13. 根据权利要求2-12任一所述的移位寄存器单元，其中，所述输出电路包括：
    第七晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和所述第一时钟信号端连接以接收所述第一时钟信号，第二极被配置为和所述输出端连接以输出所述第一时钟信号；以及
    第二电容，其第一极和所述第七晶体管的栅极连接，第二极和所述第七晶体管的第二极连接。
  14. 根据权利要求2-13任一所述的移位寄存器单元，其中，所述输出复位电路包括：
    第八晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述输出端连接以将第一电压输出至所述输出端，第二极被配置为和所述第一电压端连接以接收所述第一电压。
  15. 一种驱动装置，包括多个级联的如权利要求1-14任一所述的移位 寄存器单元，其中，
    除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的输出端连接；
    除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的输出端连接。
  16. 根据权利要求15所述的驱动装置，其中，
    所述各级移位寄存器单元中的所述上电初始化电路被配置为响应于同一上电初始化信号。
  17. 一种显示装置，包括如权利要求15或16所述的驱动装置。
  18. 一种驱动权利要求1所述的移位寄存器单元的驱动方法，包括：
    向所述上电初始化电路提供所述上电初始化信号以复位所述上拉节点；
    向所述输入电路提供所述输入信号以对所述上拉节点进行充电；
    所述输出复位电路在所述下拉节点的电平的控制下对所述输出端进行复位；
    所述输出电路在所述上拉节点的电平的控制下向所述输出端提供所述第一时钟信号；以及
    向所述第一上拉节点复位电路提供所述复位信号以对所述上拉节点进行复位。
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