WO2019051863A1 - 主动阵列开关的制造方法 - Google Patents

主动阵列开关的制造方法 Download PDF

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Publication number
WO2019051863A1
WO2019051863A1 PCT/CN2017/102868 CN2017102868W WO2019051863A1 WO 2019051863 A1 WO2019051863 A1 WO 2019051863A1 CN 2017102868 W CN2017102868 W CN 2017102868W WO 2019051863 A1 WO2019051863 A1 WO 2019051863A1
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layer
pattern
active array
manufacturing
photoresist layer
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PCT/CN2017/102868
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English (en)
French (fr)
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何怀亮
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惠科股份有限公司
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Priority to US15/739,312 priority Critical patent/US20200075642A1/en
Publication of WO2019051863A1 publication Critical patent/WO2019051863A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present application relates to a method of fabricating an active array switch, and more particularly to a method of fabricating an active array switch that can effectively protect a semiconductor layer from source and drain etch liquids.
  • the active array switch semiconductor layer that drives the display panel is mainly composed of amorphous silicon (a-Si), oxide (Oxide), and polysilicon (Poly-Si).
  • a-Si amorphous silicon
  • Oxide oxide
  • Poly-Si polysilicon
  • ESL etch stop
  • BCE back channel etch
  • Co-planner Self-Align Top Gate Co-planner Self-Align Top Gate
  • Dual Gate Dual Gate
  • ESL etch stop
  • BCE back channel etching
  • the source and drain electrode etching liquid may cause irreparable damage to the oxide semiconductor layer, affecting the electrical performance of the active array switch, and even directly lead to the active array.
  • the switch has no semiconductor characteristics.
  • an object of the present application is to provide a method for fabricating an active array switch, and more particularly to a method for fabricating an active array switch capable of effectively protecting a semiconductor layer from a source-drain etching liquid.
  • Active array switches are widely used in electronic products such as computer chips, mobile phone chips, or thin film transistors liquid crystal display (TFT LCD).
  • TFT LCD thin film transistors liquid crystal display
  • the active array switch acts as a switch for charging or discharging a storage capacitor.
  • the active array switch can be classified into an amorphous silicon active array switch (Amorphous Silicon Transistor) and a polycrystalline silicon active array switch (Low Temperature Polycrystalline Transistor) according to the material of the semiconductor layer.
  • amorphous silicon active array switch Amorphous Silicon Transistor
  • a polycrystalline silicon active array switch Low Temperature Polycrystalline Transistor
  • ZnO zinc oxide
  • zinc oxide is susceptible to substances such as plasma, etching solution, and photoresist removal. The damage, while changing the film properties of the semiconductor layer, thereby affecting the component characteristics of the active array switch.
  • the present application provides a method for fabricating an active array switch, comprising: forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern; forming a gate on the substrate An insulating layer covering the gate pattern; forming a semiconductor layer on the gate insulating layer; forming a first photoresist layer having a plurality of thicknesses on the semiconductor layer, wherein the gate is The thickness of the first photoresist layer above the pattern is greater than the thickness of the first photoresist layer above the two sides of the gate pattern; the portion of the semiconductor layer is removed to form a semiconductor pattern; Performing a dry etching process on the first photoresist layer, removing a thickness of the first photoresist layer above both sides of the gate pattern, and causing the first photoresist layer above the gate pattern The remaining thickness remaining after the layer dry etching still covers a portion of the semiconductor pattern; a second metal layer and a second photoresist layer are sequentially formed on the semiconductor pattern and the gate
  • the forming the first photoresist layer having a plurality of thicknesses comprises: forming a photosensitive material layer on the semiconductor layer, using the halftone mask to the photosensitive material layer An exposure process is performed, and a development process is performed.
  • the step of forming the first photoresist layer having a plurality of thicknesses comprises: forming a photosensitive material layer on the semiconductor layer, and performing the photosensitive material layer on a gray tone mask An exposure process, and a development process.
  • the semiconductor layer is a metal oxide semiconductor layer
  • the metal of the metal oxide semiconductor layer includes a group consisting of a group II-VI element and a compound thereof.
  • the metal oxide semiconductor layer is further doped with one or more elements selected from the group consisting of alkaline earth metals, Group IIIA, Group VA, Group VIA, or transition metals.
  • an insulating material layer is formed between the semiconductor layer and the first photoresist layer.
  • the insulating material layer is an inorganic insulating material layer such as silicon oxide or silicon nitride.
  • the insulating material layer is an organic insulating material layer such as polymethyl methacrylate or polyvinyl phenol.
  • the present invention provides a method for fabricating an active array switch, comprising: forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern; forming a gate on the substrate a conductive layer covering the gate pattern; forming a semiconductor layer on the gate insulating layer; forming a layer of insulating material on the semiconductor layer; forming a photosensitive material on the insulating material layer a layer is used to perform an exposure process on the photosensitive material layer; a developing process is performed to form a first photoresist layer having a plurality of thicknesses, wherein the first photoresist layer is located above the gate pattern a thickness of the layer is greater than a thickness of the first photoresist layer above the two sides of the gate pattern; a portion of the semiconductor layer is removed to form a semiconductor pattern; and the first photoresist layer is dry Etching process, Removing a thickness of the first photores
  • the first photoresist layer on the semiconductor layer above the gate pattern (at the back channel of the TFT) can be retained in the BCE process of the active array switch, and the film-etching process of the normal source and drain is performed. And dissolving the first photoresist layer above the gate pattern while removing the second photoresist layer from the source drain.
  • the method can effectively protect the semiconductor pattern of the back channel of the TFT from the source and drain etching liquid, so as to obtain stable active array switching electrical performance.
  • FIG. 1A is a schematic view showing film formation of a semiconductor according to an embodiment of the present application.
  • FIG. 1B is a schematic diagram of forming a first photoresist layer according to an embodiment of the present application.
  • FIG. 1C is a schematic diagram of forming a semiconductor pattern according to an embodiment of the present application.
  • FIG. 1D is a schematic diagram of a dry etching process according to an embodiment of the present application.
  • FIG. 1E is a schematic view showing forming a second metal layer and a second photoresist layer according to an embodiment of the present application.
  • FIG. 1F is a schematic diagram of removing all photoresist layers according to an embodiment of the present application.
  • FIG. 1G is a flowchart of a method for manufacturing an active array switch according to an embodiment of the present application.
  • FIG 2 is a schematic view of another embodiment of the present application including a layer of insulating material.
  • FIG. 3 is a flow chart of a method for manufacturing an active array switch according to another embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the present application provides a method for fabricating an active array switch in which a semiconductor layer is covered with a first photoresist layer to protect a semiconductor pattern formed by the semiconductor layer.
  • the present application proposes a method of fabricating an active array switch that includes the following steps. Referring to FIG. 1A to FIG. 1G , a method for manufacturing an active array switch 1 is firstly shown in FIG. 1A , a first metal layer is formed on a substrate 10 , and the first metal layer is patterned. A plurality of gate patterns 11 are formed, and a gate insulating layer 12 is formed on the substrate 10 to cover the gate pattern 11. Then, a semiconductor layer 13 is formed on the gate insulating layer 12.
  • the semiconductor layer 13 is a metal oxide semiconductor layer, and the metal of the metal oxide semiconductor layer includes a group of II-VI elements and compounds thereof.
  • the metal oxide semiconductor layer is further doped with one or more elements selected from the group consisting of alkaline earth metals, Group IIIA, Group VA, Group VIA, or transition metals.
  • a first photoresist layer 14 having a plurality of thicknesses is formed on the semiconductor layer 13, wherein the first photoresist layer 14 is located above the gate pattern 11.
  • the thickness is greater than the thickness of the first photoresist layer 14 located on both sides of the gate pattern 11.
  • the step of forming the first photoresist layer 14 having a plurality of thicknesses comprises: forming a layer of photosensitive material on the semiconductor layer 13, and performing the layer of the photosensitive material using a halftone mask An exposure process, and a development process.
  • the step of forming the first photoresist layer 14 having a plurality of thicknesses comprises: forming a layer of photosensitive material on the semiconductor layer 13, and performing a layer on the photosensitive material layer using a gray tone mask. Exposure process, and a development process.
  • a portion of the semiconductor layer 13 is removed to form a semiconductor pattern 13'.
  • the first photoresist layer 14 is subjected to a dry etching process (such as plasma etching) to remove the first photoresist layer 14 located on both sides of the gate pattern 11. Thickness, and leaving the remaining thickness (first photoresist layer 14') after the dry etching of the first photoresist layer 14 located above the gate pattern 11 still covers a portion of the semiconductor pattern 13' .
  • a dry etching process such as plasma etching
  • a second metal layer 15 and a second photoresist layer 16 are sequentially formed on the semiconductor pattern 13' and the gate insulating layer 12, and the second photoresist layer is formed.
  • Layer 16 is patterned into a source pattern and a drain pattern.
  • the second metal layer 15 is patterned to form a source 17 and a drain 18, and the second light above the source 17 and the drain 18 is removed. Resisting layer 16, and simultaneously removing all of the upper portion of the gate pattern 11 The first photoresist layer 14' is described.
  • the present application provides a method S1 for manufacturing an active array switch, which includes the following steps:
  • Step S101 forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern;
  • Step S102 forming a gate insulating layer on the substrate to cover the gate pattern
  • Step S103 forming a semiconductor layer on the gate insulating layer
  • Step S104 forming a first photoresist layer having a plurality of thicknesses on the semiconductor layer, wherein a thickness of the first photoresist layer above the gate pattern is greater than a width of the gate pattern a thickness of the first photoresist layer above;
  • Step S105 removing a portion of the semiconductor layer to form a semiconductor pattern
  • Step S106 performing a dry etching process on the first photoresist layer, removing the thickness of the first photoresist layer located on both sides of the gate pattern, and placing the upper portion of the gate pattern The remaining thickness remaining after the dry etching of the first photoresist layer still covers part of the semiconductor pattern;
  • Step S107 sequentially forming a second metal layer and a second photoresist layer on the semiconductor pattern and the gate insulating layer;
  • Step S108 patterning the second photoresist layer into a source pattern and a drain pattern
  • Step S109 patterning the second metal layer to form a source and a drain
  • Step S110 removing all of the second photoresist layers above the source and the drain, and simultaneously removing all of the first photoresist layers above the gate pattern.
  • the manufacturing method is substantially as shown in FIGS. 1A to 1F , except that an insulating material layer 19 is formed between the semiconductor layer 13 and the first photoresist layer 14 .
  • a first metal layer is formed on a substrate 10, and the first metal layer is patterned into a gate pattern 11, and a gate insulating layer 12 is formed on the substrate 10. To cover the gate pattern 11, and then to form a semiconductor layer 13 on the gate insulating layer 12.
  • an insulating material layer 19 (shown in FIG. 2) is formed on the semiconductor layer 13 to protect the metal material semiconductor layer used in the present application, wherein the insulating material layer is an inorganic insulating material layer such as silicon oxide or Silicon nitride; or may be a layer of organic insulating material such as polymethyl methacrylate or polyvinyl phenol.
  • a first photoresist layer 14 having a plurality of thicknesses is formed on the semiconductor layer 13, wherein the thickness of the first photoresist layer 14 in the middle of the gate pattern 11 is formed. Greater than the thickness of the first photoresist layer 14 on both sides of the gate pattern 11.
  • a portion of the semiconductor layer 13 is removed as shown in FIG. 1C to form a semiconductor pattern 13'.
  • the first photoresist layer 14 is subjected to a dry etching process (such as plasma etching) to remove the first layer on both sides of the gate pattern 11.
  • a thickness of the photoresist layer 14 and located in the middle of the gate pattern 11 The remaining thickness (first photoresist layer 14') remaining after dry etching of the first photoresist layer 14 still covers a portion of the semiconductor pattern 13'; the semiconductor pattern 13' and the gate
  • a second metal layer 15 and a second photoresist layer 16 are sequentially formed on the insulating layer 12, and the second photoresist layer 16 is patterned into a source pattern and a drain pattern.
  • the pattern is patterned.
  • a structure is formed as shown in FIG. 2, that is, a gate pattern 11 is formed on the substrate 10, and a gate insulating layer 12 is formed on the substrate 10 and the gate pattern 11 to cover the gate pattern 11.
  • a semiconductor pattern 13' is formed over the middle of the gate pattern 11 due to the mask effect of the photoresist layer, and the semiconductor pattern 13' is covered with an insulating material layer 19 formed of an organic or inorganic material.
  • the upper side of the pole pattern 11 is a source 17 and a drain 18 formed of a second metal layer.
  • the present application provides a method S2 for manufacturing an active array switch, including:
  • Step S201 forming a first metal layer on a substrate, and patterning the first metal layer into a gate pattern
  • Step S202 forming a gate insulating layer on the substrate to cover the gate pattern
  • Step S203 forming a semiconductor layer on the gate insulating layer
  • Step S204 forming a layer of insulating material on the semiconductor layer
  • Step S205 forming a photosensitive material layer on the insulating material layer
  • Step S206 performing an exposure process on the photosensitive material layer using a photomask
  • Step S207 performing a developing process to form a first photoresist layer having a plurality of thicknesses, wherein a thickness of the first photoresist layer above the gate pattern is greater than a width of both sides of the gate pattern a thickness of the first photoresist layer;
  • Step S208 removing a portion of the semiconductor layer to form a semiconductor pattern
  • Step S209 performing a dry etching process on the first photoresist layer to remove the thickness of the first photoresist layer located on both sides of the gate pattern, leaving the above the gate pattern
  • the first photoresist layer covers a portion of the semiconductor pattern
  • Step S210 sequentially forming a second metal layer and a second photoresist layer on the semiconductor pattern and the gate insulating layer;
  • Step S211 patterning the second photoresist layer into a source pattern and a drain pattern
  • Step S212 patterning the second metal layer to form a source and a drain
  • Step S213 removing all of the second photoresist layer above the source and the drain, and simultaneously removing all of the first photoresist layers above the gate pattern.
  • the first photoresist layer 14 on the semiconductor layer 13 above the gate pattern 11 (at the TFT back channel) can be retained in the BCE process of the active array switch 1, and then the normal source and drain electrodes are performed.
  • the film forming etching process dissolves the first photoresist layer 14' above the gate pattern 11 while the source drain removes the second photoresist layer 16. This method can effectively protect the semiconductor of the TFT back channel
  • the pattern 13' is unaffected by the source drain etch liquid to obtain a stable active array switch 1 electrical performance.

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Abstract

一种主动阵列开关的制造方法，该制造方法包括：于一基板（10）上形成一栅极图形（11）后，形成一栅极绝缘层（12）覆盖栅极图形；于栅极绝缘层上形成一半导体层（13），并于其上形成一具有多个厚度的第一光阻层（14），其中栅极图形中间上方的第一光阻层的厚度大于栅极图形两侧上方的第一光阻层的厚度；移除部分半导体层，以形成一半导体图形（13'）；对第一光阻层进行干式蚀刻制程，使只有栅极图形中间上方留下来的第一光阻层仍覆盖部分此半导体图形；于半导体图形和栅极绝缘层上形成一源极（17）和一漏极（18）；以及移除源极、漏极与栅极图形中间上方的全部光阻层（14'）。

Description

主动阵列开关的制造方法 技术领域
本申请涉及一种主动阵列开关的制造方法，特别是涉及一种能有效保护半导体层不受源漏极蚀刻液体影响的主动阵列开关的制造方法。
背景技术
驱动显示面板的主动阵列开关半导体层目前主要有非晶硅(a-Si)，氧化物(Oxide)和多晶硅(Poly-Si)等。相对于非晶硅，氧化物半导体具有较高的迁移率，较低的漏电；虽多晶硅主动阵列开关迁移率更高，但其成本较高且不合适于目前主流产品的生产线。
氧化物半导体主动阵列开关常用的结构有ESL(蚀刻阻挡)，BCE(背沟道蚀刻)，Co-planner Self-Align Top Gate(共平面顶栅自对准型)以及Dual Gate(双栅机)等结构。虽然ESL(蚀刻阻挡)结构制程相对容易，但其需要进行多次黄光制程，因此BCE(背沟道蚀刻)结构成为可进行大规模低成本量产的较佳选择。
然而BCE(背沟道蚀刻)结构的主动阵列开关制程中，难点之一是源漏极电极蚀刻液体会对氧化物半导体层造成不可恢复的损伤，影响主动阵列开关电性能，甚至直接导致主动阵列开关无半导体特性。
发明内容
为了解决上述技术问题，本申请的目的在于提供一种主动阵列开关的制造方法，特别是涉及一种能有效保护半导体层不受源漏极蚀刻液体影响的主动阵列开关的制造方法。
近年来，由于半导体制程技术的进步，主动阵列开关的制造越趋容易、快速。主动阵列开关广泛应用于诸如计算机芯片、手机芯片或是主动阵列开关液晶显示器(thin film transistor liquid crystal displayer，TFT LCD)等电子产品中。以主动阵列开关液晶显示器为例，主动阵列开关作为储存电容(storage capacitor)充电或放电的开关。
一般而言，主动阵列开关依照半导体层的材料可分为非晶硅主动阵列开关(Amorphous Silicon Transistor)以及多晶硅主动阵列开关(Low Temperature Polycrystalline Transistor)。同时，为了因应市场对于液晶显示器的需求遽增，新的主动阵列开关技术研发也有更多的投入。其中，已研发出一种以诸如氧化锌(ZnO)等的金属氧化物为半导体层的主动阵列开关，其电性特性已追上非晶硅主动阵列开关，且在组件的表现上也已经有相当不错的成果。然而，以氧化锌作为半导体层的主动阵列开关为例，在后续形成源极与漏极的制程中，氧化锌容易受到诸如电浆、蚀刻液以及去光阻液等物质 的损害，而改变半导体层的薄膜性质，进而影响主动阵列开关的组件特性。
因此本申请提供了一种主动阵列开关的制造方法，包括：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；于所述栅极绝缘层上形成一半导体层；于所述半导体层上形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；移除部份所述半导体层，以形成一半导体图形；对所述第一光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，并使位于所述栅极图形上方的所述第一光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形；于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；将所述第二光阻层图案化成一源极图形与一漏极图形；图案化所述第二金属层，以形成一源极和一漏极；以及移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
在本申请的一实施例中，形成所述具有多个厚度的第一光阻层的步骤包括：于所述半导体层上形成一感光材料层，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在本申请的一实施例中，形成所述具有多个厚度的第一光阻层的步骤包括：于所述半导体层上形成一感光材料层，使用灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在本申请的一实施例中，所述半导体层为金属氧化物半导体层，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在本申请的一实施例中，所述金属氧化物半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
在本申请的一实施例中，于所述半导体层与所述第一光阻层之间形成一绝缘材料层。
在本申请的上述实施例中，所述绝缘材料层为无机绝缘材料层，如氧化硅或氮化硅。
在本申请的上述实施例中，所述绝缘材料层为有机绝缘材料层，如聚甲基丙烯酸甲酯或聚乙烯酚。
本申请的目的及解决其技术问题还可采用以下技术措施进一步实现。本申请提供了一种主动阵列开关的制造方法，其中，包括：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；于所述栅极绝缘层上形成一半导体层；于所述半导体层上形成一形成一绝缘材料层；于所述绝缘材料层上形成一感光材料层；使用一光罩对所述感光材料层进行一曝光制程；进行一显影制程形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；移除部份所述半导体层，以形成一半导体图形；对所述第一光阻层进行干式蚀刻制程， 移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；将所述第二光阻层图案化成一源极图形与一漏极图形；图案化所述第二金属层，以形成一源极和一漏极；以及
移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
经过本申请的改进之后，可于主动阵列开关的BCE制程中，保留栅极图形上方(TFT背沟道处)半导体层上的第一光阻层，再进行正常源漏极的成膜蚀刻制程，在源漏极移除第二光阻层之同时溶解栅极图形上方的第一光阻层。此方法能有效保护TFT背沟道的半导体图形不受源漏极蚀刻液体的影响，以得到稳定的主动阵列开关电性能。
附图说明
图1A是本申请实施例所述半导体的成膜示意图。
图1B是本申请实施例所述之形成第一光阻层示意图。
图1C是本申请实施例所述的形成半导体图形示意图。
图1D是本申请实施例所述进行干式蚀刻制程示意图。
图1E是本申请实施例所述形成第二金属层及第二光阻层示意图。
图1F是本申请实施例所述移除全部光阻层示意图。
图1G是本申请一实施例所述主动阵列开关的制造方法流程图。
图2是本申请包括绝缘材料层的另一实施例示意图。
图3是本申请另一实施例所述主动阵列开关的制造方法流程图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种主动阵列开关的制造方法，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请是提供一种主动阵列开关的制造方法，使半导体层上覆盖有第一光阻层，以保护半导体层形成的半导体图形。本申请提出一种主动阵列开关的制造方法，其包括下列步骤。敬请参阅图1A至图1G，本申请提供的一种主动阵列开关1的制造方法首先如图1A所示，于一基板10上形成一第一金属层，并图案化所述第一金属层成多个栅极图形11，再于所述基板10上形成一栅极绝缘层12，以覆盖所述栅极图形11，然后于所述栅极绝缘层12上形成一半导体层13。
在一实施例中，所述半导体层13为金属氧化物半导体层，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
在上述实施例中，所述金属氧化物半导体层更掺杂选自碱土金属、IIIA族、VA族、VIA族或过渡金属所组成的族群的一或多个元素。
接下来如图1B所示，于所述半导体层13上形成一具有多个厚度的第一光阻层14，其中，位于所述栅极图形11中间上方的所述第一光阻层14的厚度大于位于所述栅极图形11两侧上方的所述第一光阻层14的厚度。
在一实施例中，形成所述具有多个厚度的第一光阻层14的步骤包括：于所述半导体层13上形成一感光材料层，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
在一实施例中，形成所述具有多个厚度的第一光阻层14的步骤包括：于所述半导体层13上形成一感光材料层，使用灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
接下来如图1C所示，移除部份所述半导体层13，以形成一半导体图形13'。
接下来如图1D所示，对所述第一光阻层14进行干式蚀刻制程(如电浆蚀刻)，移除位于所述栅极图形11两侧上方的所述第一光阻层14的厚度，并使位于所述栅极图形11中间上方的所述第一光阻层14干式蚀刻后留下来的剩余厚度(第一光阻层14')仍覆盖部分所述半导体图形13'。
接下来如图1E所示，于所述半导体图形13'和所述栅极绝缘层12上依序形成一第二金属层15及一第二光阻层16，并将所述第二光阻层16图案化成一源极图形与一漏极图形。
最后如图1F所示，图案化所述第二金属层15，以成一源极17和一漏极18，并移除所述源极17与所述漏极18上方全部的所述第二光阻层16，且同时移除所述栅极图形11中间上方的全部所 述第一光阻层14'。
亦即，本申请提供一种主动阵列开关的制造方法S1，其包括下列步骤：
步驟S101：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
步驟S102：于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
步驟S103：于所述栅极绝缘层上形成一半导体层；
步驟S104：于所述半导体层上形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；
步驟S105：移除部份所述半导体层，以形成一半导体图形；
步驟S106：对所述第一光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，并使位于所述栅极图形上方的所述第一光阻层干式蚀刻后留下来的剩余厚度仍覆盖部分所述半导体图形；
步驟S107：于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；
步驟S108：将所述第二光阻层图案化成一源极图形与一漏极图形；
步驟S109：图案化所述第二金属层，以形成一源极和一漏极；以及
步驟S110：移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
其制造方法大致如图1A至图1F，惟于所述半导体层13与所述第一光阻层14之间形成一绝缘材料层19。
亦即，如图1A所示，于一基板10上形成一第一金属层，并图案化所述第一金属层成一栅极图形11，再于所述基板10上形成一栅极绝缘层12，以覆盖所述栅极图形11，然后于所述栅极绝缘层12上形成一半导体层13。
然后在半导体层13上先形成一绝缘材料层19(如图2所示)，用以保护本申请所使用的金属材质半导体层，其中所述绝缘材料层为无机绝缘材料层，如氧化硅或氮化硅；或可为有机绝缘材料层，如聚甲基丙烯酸甲酯或聚乙烯酚。
接下来则如图1B所示，于所述半导体层13上形成一具有多个厚度的第一光阻层14，其中所述栅极图形11中间上方的所述第一光阻层14的厚度大于所述栅极图形11两侧上方的所述第一光阻层14的厚度。
再如图1C所示移除部份所述半导体层13，以形成一半导体图形13'。
续如图1D、图1E以及图1F所示，对所述第一光阻层14进行干式蚀刻制程(如电浆蚀刻)，移除位于所述栅极图形11两侧上方的所述第一光阻层14的厚度，并使位于所述栅极图形11中间上 方的所述第一光阻层14干式蚀刻后留下来的剩余厚度(第一光阻层14')仍覆盖部分所述半导体图形13'；于所述半导体图形13'和所述栅极绝缘层12上依序形成一第二金属层15及一第二光阻层16，并将所述第二光阻层16图案化成一源极图形与一漏极图形；最后图案化所述第二金属层15以形成一源极17和一漏极18，并移除所述源极17与所述漏极18上方全部的所述第二光阻层16，且同时移除所述栅极图形11中间上方的全部所述第一光阻层14'。
最后形成如图2的结构，亦即于基板10上形成有一栅极图形11，所述基板10与所述栅极图形11上形成有一栅极绝缘层12以覆盖所述栅极图形11，而在栅极图形11的中间上方因光阻层的罩幕效果保留形成一半导体图形13'，并于所述半导体图形13'上覆盖有一以有机或无机材料形成的绝缘材料层19，而在栅极图形11两侧上方则是为以第二金属层形成的源极17与漏极18。
同时，本申请的目的及解决其技术问题还可采用如图3的流程技术措施进一步实现。本申请提供了一种主动阵列开关的制造方法S2，其中，包括：
步驟S201：于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
步驟S202：于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
步驟S203：于所述栅极绝缘层上形成一半导体层；
步驟S204：于所述半导体层上形成一形成一绝缘材料层；
步驟S205：于所述绝缘材料层上形成一感光材料层；
步驟S206：使用一光罩对所述感光材料层进行一曝光制程；
步驟S207：进行一显影制程形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；
步驟S208：移除部份所述半导体层，以形成一半导体图形；
步驟S209：对所述第一光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
步驟S210：于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；
步驟S211：将所述第二光阻层图案化成一源极图形与一漏极图形；
步驟S212：图案化所述第二金属层，以形成一源极和一漏极；以及
步驟S213：移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
经过本申请的改进之后，可于主动阵列开关1的BCE制程中，保留栅极图形11上方(TFT背沟道处)半导体层13上的第一光阻层14，再进行正常源漏极的成膜蚀刻制程，在源漏极移除第二光阻层16的同时溶解栅极图形11上方的第一光阻层14'。此方法能有效保护TFT背沟道的半导体 图形13'不受源漏极蚀刻液体的影响，以得到稳定的主动阵列开关1电性能。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种主动阵列开关的制造方法，包括：
    于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
    于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
    于所述栅极绝缘层上形成一半导体层；
    于所述半导体层上形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形中间上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；
    移除部份所述半导体层，以形成一半导体图形；
    对所述第一光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
    于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；
    将所述第二光阻层图案化成一源极图形与一漏极图形；
    图案化所述第二金属层，以形成一源极和一漏极；以及
    移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
  2. 如权利要求1所述的主动阵列开关的制造方法，其中，形成所述具有多个厚度的第一光阻层的步骤包括：于所述半导体层上形成一感光材料层。
  3. 如权利要求2所述的主动阵列开关的制造方法，其中，使用一半色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
  4. 如权利要求2所述的主动阵列开关的制造方法，其中，使用一灰色调式光罩对所述感光材料层进行一曝光制程，以及进行一显影制程。
  5. 如权利要求1所述的主动阵列开关的制造方法，其中，所述半导体层为金属氧化物半导体层。
  6. 如权利要求5所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层的金属包括II-VI族元素及其化合物所组成的群组。
  7. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂碱土金属元素。
  8. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂IIIA族元素。
  9. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂VA族元素。
  10. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂VIA族元素。
  11. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂选自过渡金属所组成的族群的一个元素。
  12. 如权利要求6所述的主动阵列开关的制造方法，其中，所述金属氧化物半导体层更掺杂选自过渡金属所组成的族群的多个元素。
  13. 如权利要求1所述的主动阵列开关的制造方法，其中，于所述半导体层与所述第一光阻层之间形成一绝缘材料层。
  14. 如权利要求13所述的主动阵列开关的制造方法，其中，所述绝缘材料层为无机绝缘材料层。
  15. 如权利要求14所述的主动阵列开关的制造方法，其中，所述无机绝缘材料层为氧化硅。
  16. 如权利要求14所述的主动阵列开关的制造方法，其中，所述无机绝缘材料层为氮化硅。
  17. 如权利要求13所述的主动阵列开关的制造方法，其中，所述绝缘材料层为有机绝缘材料层。
  18. 如权利要求17所述的主动阵列开关的制造方法，其中，所述有机绝缘材料层为聚甲基丙烯酸甲酯。
  19. 如权利要求17所述的主动阵列开关的制造方法，其中，所述有机绝缘材料层为聚乙烯酚。
  20. 一种主动阵列开关的制造方法，包括：
    于一基板上形成一第一金属层，并图案化所述第一金属层成一栅极图形；
    于所述基板上形成一栅极绝缘层，以覆盖所述栅极图形；
    于所述栅极绝缘层上形成一半导体层；
    于所述半导体层上形成一形成一绝缘材料层；
    于所述绝缘材料层上形成一感光材料层；
    使用一光罩对所述感光材料层进行一曝光制程；
    进行一显影制程形成一具有多个厚度的第一光阻层，其中，位于所述栅极图形上方的所述第一光阻层的厚度大于位于所述栅极图形两侧上方的所述第一光阻层的厚度；
    移除部份所述半导体层，以形成一半导体图形；
    对所述第一光阻层进行干式蚀刻制程，移除位于所述栅极图形两侧上方的所述第一光阻层的厚度，留下所述栅极图形上方的所述第一光阻层覆盖部分所述半导体图形；
    于所述半导体图形和所述栅极绝缘层上依序形成一第二金属层及一第二光阻层；
    将所述第二光阻层图案化成一源极图形与一漏极图形；
    图案化所述第二金属层，以形成一源极和一漏极；以及
    移除所述源极与所述漏极上方全部的所述第二光阻层，且同时移除所述栅极图形上方的全部所述第一光阻层。
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