WO2018145465A1 - 阵列基板以及显示装置 - Google Patents

阵列基板以及显示装置 Download PDF

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Publication number
WO2018145465A1
WO2018145465A1 PCT/CN2017/102758 CN2017102758W WO2018145465A1 WO 2018145465 A1 WO2018145465 A1 WO 2018145465A1 CN 2017102758 W CN2017102758 W CN 2017102758W WO 2018145465 A1 WO2018145465 A1 WO 2018145465A1
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WIPO (PCT)
Prior art keywords
drain
source
array substrate
disposed
insulating layer
Prior art date
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PCT/CN2017/102758
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English (en)
French (fr)
Inventor
曹可
杨成绍
王文龙
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP17851942.7A priority Critical patent/EP3588562A4/en
Priority to US15/951,466 priority patent/US10651205B2/en
Publication of WO2018145465A1 publication Critical patent/WO2018145465A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device.
  • a thin film transistor liquid crystal display device generally includes an array substrate having a Thin Film Transistor (TFT) array and a liquid crystal cell formed by opposing substrates disposed thereon, and a liquid crystal molecular layer filled in the liquid crystal cell .
  • TFT Thin Film Transistor
  • TFT-LCDs thin film transistor liquid crystal display devices
  • At least one embodiment of the present disclosure provides an array substrate and a display device, which can solve the problems of slow response speed, low charging efficiency, and the like of a conventional array substrate, and can simultaneously avoid increasing the aperture ratio.
  • At least one embodiment of the present disclosure provides an array substrate including: a base substrate; a first active layer disposed on the base substrate; a first insulating layer disposed on the first active layer and On the substrate; a gate disposed on a side of the first insulating layer away from the first active layer; a second insulating layer disposed on the gate and the first insulating layer; a second active layer disposed on a side of the second insulating layer away from the gate; a first drain and a first source respectively disposed in contact with the first active layer portion; a second drain and a second source, respectively disposed in contact with the second active layer portion; and a pixel electrode, the first drain and the second drain are electrically connected, the first source and the second The source is electrically connected, and the pixel electrode is electrically connected to at least one of the first drain and the second drain.
  • an orthographic projection of the gate on the substrate substrate falls into the first active layer and the second active layer on the substrate. In the orthographic projection of the substrate.
  • an array substrate further includes: a first via disposed in the first insulating layer and the second insulating layer and partially exposing the first drain, the second drain The pole is connected to the first drain through the first via.
  • an array substrate further includes: a passivation layer disposed on a side of the second drain and the second source away from the second active layer, the pixel electrode is disposed Between the second drain and the passivation layer and in contact with the second drain portion.
  • an array substrate further includes: a second via hole disposed in the first insulating layer and the second insulating layer and partially exposing the first source, the second source The pole is connected to the first source through the second via.
  • an array substrate further includes: a passivation layer disposed on a side of the second drain and the second source away from the second active layer; and a third via hole, Provided in the first insulating layer, the second insulating layer, the second drain, and the passivation layer and partially exposing the first drain; and a first conductive structure disposed in the third pass The holes are electrically connected to the first drain and the second drain.
  • an array substrate further includes: a fourth via hole disposed in the first insulating layer, the second insulating layer, the second source, and the passivation layer and partially Exposing the first source; and a second conductive structure disposed in the fourth via to electrically connect the first source and the second source.
  • the pixel electrode is disposed between the second drain and the passivation layer and is in contact with the second drain portion.
  • an array substrate further includes: a fifth via hole disposed in the passivation layer and partially exposing a portion of the pixel electrode in contact with the second drain, the first A conductive structure is also disposed in the fifth via.
  • the pixel electrode includes the first conductive structure.
  • At least one embodiment of the present disclosure provides a display device including the array substrate of any of the above.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including: a substrate base Forming a first active layer on the substrate; forming a first drain and a first source on the base substrate and respectively contacting the first active layer portion; at the first active layer, Forming a first insulating layer on a side of the first source and the first drain away from the substrate; forming a gate on a side of the first insulating layer away from the first active layer; Forming a second insulating layer on a side of the gate away from the first insulating layer; forming a second active layer on a side of the second insulating layer away from the gate; away from the second insulating layer
  • One side of the gate forms a second drain and a second source and is respectively disposed in contact with the second active layer portion; and a pixel electrode is formed, the first source and the second source being electrically The first drain and the second drain are electrically connected, and the pixel electrode is electrically connected to at least one of the first drain and the second
  • the method includes: etching the first insulating layer And the second insulating layer to form a first via hole partially exposing the first source and a second via hole partially exposing the first drain, the second source passing through the first via Connected to the first source, the second drain is connected to the first drain through the second via.
  • forming the second active layer on a side of the second insulating layer away from the gate includes: being away from the second insulating layer One side of the gate forms a second semiconductor layer; and the second semiconductor layer is patterned to form the second active layer, the patterning the second semiconductor layer to form the second active layer And forming the first insulating layer and the second insulating layer to form the first via and the second via are formed by a mask process.
  • the manufacturing method further includes: forming a passivation layer on a side of the pixel electrode away from the substrate;
  • the passivation layer is disposed on a side of the second drain and the second source away from the second active layer.
  • the method for fabricating an array substrate according to an embodiment of the present disclosure further includes forming a common electrode on a side of the passivation layer away from the substrate.
  • the array substrate provided by the embodiment of the present disclosure, the manufacturing method thereof and the display device have at least one of the following beneficial effects:
  • 1 is a schematic plan view of an array substrate
  • FIG. 2 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4a is a schematic cross-sectional view of another array substrate according to an embodiment of the present disclosure.
  • 4b is a cross-sectional view of another array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a step-by-step schematic diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram showing a step-by-step manner of a method for fabricating another array substrate according to an embodiment of the present disclosure
  • FIG. 8a-8c illustrate a step-by-step schematic diagram of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • 9a-9c illustrate a step-by-step schematic diagram of a method of fabricating an array substrate.
  • the dual thin film transistor (Dual-TFT) structure includes a gate line 1, a gate 2 electrically connected to the gate line 1, a data line 3, a source 4 electrically connected to the data line 3, and a drain. 5 and a pixel electrode 6 electrically connected to the drain 5.
  • the source 4 includes a first source 41 and a second source 42.
  • the drain 5 includes a first drain 51 and a second drain 52. The first source 41 and the first drain 51 are oppositely disposed, and the second source is opposite.
  • the double thin film transistor structure improves the response speed and the charging efficiency, it increases the area occupied by the thin film transistor switch and reduces the aperture ratio.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes a base substrate, a first active layer disposed on the base substrate, a first insulating layer disposed on the first active layer and the base substrate, and disposed on the first insulating layer away from the first active layer a gate on one side of the layer, a second insulating layer disposed on the gate and the first insulating layer, a second active layer disposed on a side of the second insulating layer away from the gate, and the first active layer
  • the second drain and the second source and the pixel electrode which are disposed in contact with the first active layer and the second active layer, respectively, are partially contacted.
  • the first source and the second source are electrically connected, the first drain and the second drain are electrically connected, and the pixel electrode is electrically connected to at least one of the first drain and the second drain.
  • An embodiment of the present disclosure provides an array substrate.
  • 2 is a cross-sectional view showing an array substrate.
  • the array substrate includes a substrate substrate 101, a first active layer 102 disposed on the substrate substrate 101, and a first active layer.
  • the second drain 1081 and the second source 1082 and the pixel electrode 109 are disposed in contact with the second active layer 106, respectively.
  • the first source 1072 and the second source 1082 are electrically connected, the first drain 1071 and the second drain 1081 are electrically connected, and the pixel electrode 109 and the first drain 1071 and the second drain 1081 are electrically connected. Connected.
  • a region where the first active layer 102 is in contact with the first source 1072 may be a source region, and a region where the first active layer 102 is in contact with the first drain 1071 may be a drain.
  • a region between the source region and the drain region of the first active layer 102 is a channel region; a region where the second active layer 106 is in contact with the second source 1082 may be a source region, and the second active layer A region in contact with the second drain 1081 may be a drain region, and a channel region between the source region and the drain region of the second active layer 106.
  • the first source and the second source are electrically connected, the first drain and the second drain are electrically connected, and the pixel electrode passes through the first drain and the second drain.
  • An electrically connected electrical signal can simultaneously connect the first drain and the second drain, and the gate can simultaneously control the channel regions of the first active layer and the second active layer.
  • the array substrate can improve response speed and charging efficiency.
  • an electrical signal may enter from the first source, be shunted to the second source, and then transmitted to the first drain and the second drain through the channel regions of the first active layer and the second active layer, thereby utilizing a single The gate controls the dual channel so there is no delay.
  • FIG. 3 is a schematic plan view of the array substrate.
  • the orthographic projection of the second active layer, the second drain, and the second source on the substrate may be combined with the first active layer, The orthogonal projection of a drain and the first source on the base substrate overlaps, thereby not increasing the area occupied by the thin film transistor switch and not reducing the aperture ratio.
  • the first drain 1071 and the first source 1072 are respectively overlapped on the first active layer 102; the second drain 1081 and the second source 1082 are respectively overlapped. On the second active layer 106.
  • the distance between the first drain 1071 and the base substrate 101 is smaller than the distance between the second drain 1081 and the base substrate 101, and the first source 1072 and the base substrate 101
  • the distance is smaller than the distance between the second source 1082 and the base substrate 101; that is, another layer structure is disposed between the first drain 1071 and the second drain 1081, for example, the first insulating layer 103 and the second insulation.
  • the layer 105 is similarly provided with other layer structures, for example, a first insulating layer 103 and a second insulating layer 105, between the first source 1072 and the second source 1082.
  • the orthographic projection of the gate electrode 104 on the substrate substrate 101 falls into the first active layer 102 and the second active layer 106 on the substrate.
  • the gate electrode 104 is disposed corresponding to the channel region of the first active layer 102 and the channel region of the second active layer 106.
  • the array substrate is further The first via 121 is disposed in the first insulating layer 103 and the second insulating layer 105 and partially exposes the first drain 1071.
  • the second drain 1081 is electrically connected to the first drain 1071 through the first via 121. . Thereby, the first drain and the second drain can be electrically connected through the first via.
  • the array substrate further includes a second portion disposed in the first insulating layer 103 and the second insulating layer 105 and partially exposing the first source 1072.
  • the via 122 and the second source 108 are electrically connected to the first drain 1071 through the second via 122. Thereby, the first source and the second source are electrically connected through the second via.
  • the array substrate further includes a blunt side disposed on a side of the second drain 1081 and the second source 1082 away from the second active layer 106.
  • the pixel electrode 109 is disposed between the second drain electrode 1081 and the passivation layer 110 and is in partial contact with the second drain electrode 1081.
  • the pixel electrode 109 may overlap the second drain 1081.
  • the array substrate is connected to the second drain without passing through the via hole, thereby simplifying the structure of the array substrate and improving reliability.
  • the embodiments of the present disclosure include, but are not limited to, the pixel electrode may also be disposed on the passivation layer and electrically connected to the second drain through the via.
  • the array substrate further includes a common electrode line 111 disposed in the same layer as the gate electrode 104.
  • the common electrode line may be disposed in other layers, and the embodiment of the present disclosure is not limited herein.
  • the array substrate further includes a common electrode 112 disposed on the passivation layer 110 and electrically connected to the common electrode line 111 through the via 113.
  • An embodiment of the present disclosure provides an array substrate.
  • 4a is a cross-sectional view showing another array substrate.
  • the array substrate further includes a passivation layer 110.
  • the passivation layer 110 is disposed away from the second drain 1081 and the second source 1082.
  • the array substrate further includes a first insulating layer 103, a second insulating layer 105, a second drain 1081, and a passivation layer 110.
  • the third via hole 123 of the first drain electrode 1071 and the first via structure 123 disposed at the third via hole 123 to electrically connect the first drain electrode 1071 and the second drain electrode 1081 are partially and partially exposed. Thereby, the first drain 1071 and the second drain 1081 are electrically connected through the first conductive structure 114 and the third via 123.
  • the array substrate further includes a first insulating layer 103, a second insulating layer 105, a second source 1082, and a passivation layer 110. And partially exposing the fourth via hole 124 of the first source 1072 and setting it in the fourth via hole 124 A second conductive structure 115 electrically connected to the source 1072 and the second source 1082. Thereby, the first source 1072 and the second source 1082 are electrically connected through the second conductive structure 115 and the fourth via 124.
  • the array substrate includes a common electrode line 111 and a common electrode 112, and the common electrode 112 is electrically connected to the common electrode line 111 through the via 113.
  • the third via hole 123 and/or the fourth via hole 124 and the via hole 113 can be formed by one mask process, thereby saving process and saving cost.
  • the pixel electrode 109 is disposed between the second drain 1081 and the passivation layer 110 and partially in contact with the second drain 1081, thereby The two drains 1081 are electrically connected.
  • the pixel electrode 109 can be overlapped on the second drain 1081.
  • the array substrate is connected to the second drain without passing through the via hole, thereby simplifying the structure of the array substrate and improving reliability.
  • the embodiments of the present disclosure include, but are not limited to, the pixel electrode may also be disposed on the passivation layer and electrically connected to the second drain through the via.
  • the array substrate further includes a portion disposed in the passivation layer 110 and partially exposing a portion where the pixel electrode 109 is in contact with the second drain 1081.
  • the fifth via 125, the first conductive structure 114 is also disposed in the fifth via 125.
  • the pixel electrode 109 includes the first conductive structure 114, that is, the first conductive structure 114 may be a part of the pixel electrode 109.
  • the pixel electrode when the array substrate provided in this embodiment adopts a TN structure, that is, when only a pixel electrode is disposed on the array substrate, the pixel electrode includes a first conductive structure to increase the pixel electrode and the first drain, and The stability and reliability of the second drain electrical connection can also increase the aperture ratio of the array substrate.
  • An embodiment of the present disclosure provides a display device including the array substrate described in any one of the above embodiments. Therefore, the display device has the beneficial effects corresponding to the beneficial effects of the array substrate described in any one of the first embodiment and the second embodiment. For details, refer to the related description in the first embodiment and the second embodiment. Let me repeat. In addition, since the display device has a fast response speed and charging efficiency, it can be applied to a display device having a large size such as a television set, a stage screen, or the like.
  • An embodiment of the present disclosure provides a method for fabricating an array substrate. As shown in FIG. 5, the method for fabricating the array substrate includes the following steps S401-S408.
  • Step S401 As shown in FIG. 6a, a first active layer 102 is formed on the base substrate 101.
  • the base substrate may be a glass substrate, a quartz substrate, a plastic substrate, or the like; the first active layer
  • the material may be an oxide semiconductor, amorphous silicon, polycrystalline silicon or the like; of course, embodiments of the present disclosure include but are not limited thereto.
  • Step S402 As shown in FIG. 6b, a first drain electrode 1071 and a first source electrode 1072 are formed on the base substrate 101 and are respectively placed in contact with the first active layer 102.
  • the first drain electrode 1071 and the first source electrode 1072 are respectively overlapped on both sides of the first active layer 102, that is, the source region and the drain region of the first active layer 102.
  • the first drain 1071 and the first source 1072 are disposed on a side of the first active layer 102 away from the substrate 101.
  • the first drain 1071 and the first source 1072 are also The embodiment of the present disclosure is not limited herein. The embodiment may be disposed on the side of the first active layer 102 adjacent to the substrate.
  • Step S403 As shown in FIG. 6c, a first insulating layer 103 is formed on a side of the first active layer 102, the first source 1072, and the first drain 1071 away from the substrate 101.
  • the material of the first insulating layer may be an organic insulating material or an inorganic insulating material, and the embodiment of the present disclosure is not limited herein.
  • Step S404 As shown in FIG. 6d, a gate electrode 104 is formed on a side of the first insulating layer 103 away from the first active layer 102.
  • the material of the gate electrode may include one or more selected from the group consisting of aluminum, aluminum alloy, copper, copper alloy, molybdenum, and molybdenum aluminum alloy.
  • Step S405 As shown in FIG. 6e, a second insulating layer 105 is formed on a side of the gate 104 away from the first insulating layer 103.
  • the material of the second insulating layer may be an organic insulating material or an inorganic insulating material, and the embodiment of the present disclosure is not limited herein.
  • Step S406 As shown in FIG. 6f, a second active layer 106 is formed on a side of the second insulating layer 105 away from the gate 104.
  • the material of the second active layer may be an oxide semiconductor, amorphous silicon, polycrystalline silicon or the like; of course, embodiments of the present disclosure include but are not limited thereto.
  • Step S407 As shown in FIG. 6g, a second drain 1081 and a second source 1082 are formed on a side of the second insulating layer 105 away from the gate 104 and are respectively disposed in contact with the second active layer 106.
  • the second drain 1081 and the second source 1082 may be electrically connected to the first drain 1071 and the first source 1072 through via holes, respectively.
  • Step S408 As shown in FIG. 6h, a pixel electrode is formed, and the pixel electrode is electrically connected to at least one of the first drain and the second drain.
  • the first source and the second source are electrically connected, the first drain and the second drain are electrically connected, and the pixel electrode passes through the first drain and the second drain.
  • At least one of the electrically connected electrical signals may simultaneously connect the first drain and the second drain, and the gate may simultaneously control the channel regions of the first active layer and the second active layer.
  • the array substrate can improve response speed and charging efficiency.
  • an electrical signal may enter from the first source, be shunted to the second source, and then transmitted to the first drain and the second drain through the channel regions of the first active layer and the second active layer, thereby utilizing a single The gate controls the dual channel so there is no delay.
  • the second active layer, the second drain, and the second source are disposed on the first active layer, the first drain, and the first source, the area occupied by the thin film transistor switch is not increased and Reduce the aperture ratio.
  • the orthographic projection of the second active layer, the second drain, and the second source on the substrate may be orthogonal to the first active layer, the first drain, and the first source on the substrate. The overlap is such that the area occupied by the thin film transistor switch is not increased and the aperture ratio is not lowered.
  • the step S406 that is, after the second active layer is formed on the side of the second insulating layer away from the gate, as shown in FIG.
  • the first insulating layer 103 and the second insulating layer 105 form a first via 121 that partially exposes the first source 1072 and a second via 122 that partially exposes the first drain 1071.
  • the second source 1082 is connected to the first source 1072 through the first via 121, and the second drain 1081 is connected to the first drain 1071 through the second via 122.
  • the step S406, that is, forming the second active layer on the side of the second insulating layer away from the gate includes: the second insulating layer is away from the gate Forming a second semiconductor layer on one side; and patterning the second semiconductor layer to form a second active layer, the patterned second semiconductor layer to form a second active layer and etching the first insulating layer and the second
  • the insulating layer to form the first via and the second via may be formed by a mask process, for example, first etching the first via and the second via using a halftone mask, then performing an ashing process, and finally forming a Two active layers.
  • the manufacturing method further includes: forming a passivation layer on the formed substrate. 110.
  • the method for fabricating the array substrate further includes forming a common electrode line 111.
  • the common electrode line 111 may be formed in the same layer as the gate electrode 104.
  • the common electrode lines may be formed in other layers, and the embodiments of the present disclosure are not limited herein.
  • the array substrate further includes an etch via 115 in the passivation layer 110 and the second insulating layer 105.
  • the method for fabricating the array substrate further includes forming a common electrode 112 on the passivation layer 110, and the common electrode 112 passes through the via 113 and the common electrode line. 111 is electrically connected.
  • the passivation layer 110 is formed on the formed substrate, and the passivation layer 110 is disposed.
  • the second drain 1081 and the second source 1082 are away from the side of the second active layer 106.
  • the first insulating layer 103, the second insulating layer 105, the second drain 1081, and the passivation layer are formed.
  • a third via 123 partially exposing the first drain 1071 and a fourth via 124 partially exposing the first source 1072 are formed in the 110.
  • a first conductive structure 114 electrically connecting the first drain electrode 1071 and the second drain electrode 1081 is formed in the third via hole 123; and the first source electrode 1072 is formed in the fourth via hole 124.
  • the second source 1082 is electrically connected to the second conductive structure 115.
  • first drain 1071 and the second drain 1081 are electrically connected through the first conductive structure 114 and the third via 123.
  • the first conductive structure 114 and the second conductive structure 115 may be formed by patterning the same conductive layer through a single patterning process, and the first source is formed by the second conductive structure 115 and the fourth via 124. 1072 and the second source 1082 are electrically connected.
  • embodiments of the present disclosure include but are not limited thereto.
  • the method for fabricating the array substrate further includes forming a partially exposed pixel electrode 109 and a second drain 1081 in the passivation layer 110.
  • the reliability of the pole connection may be performed by the same mask process.

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Abstract

一种阵列基板以及显示装置。该阵列基板包括：衬底基板（101）、设置在衬底基板（101）上的第一有源层（102）、设置在第一有源层（102）和衬底基板（101）上的第一绝缘层（103）、设置在第一绝缘层（103）远离第一有源层（102）的一侧的栅极（104）、设置在栅极（104）和第一绝缘层（103）上的第二绝缘层（105）、设置在第二绝缘层（105）远离栅极（104）的一侧的第二有源层（106）、分别与第一有源层（102）部分接触设置第一漏极（1071）和第一源极（1072）、分别与第二有源层（106）部分接触设置的第二漏极（1081）和第二源极（1082）以及像素电极（109）。第一源极（1072）和第二源极（1082）电性相连，第一漏极（1071）和第二漏极（1081）电性相连，像素电极（109）与第一漏极（1071）和第二漏极（1081）至少之一电性相连。该阵列基板可提高响应速度以及充电效率，并且可同时避免增加开口率。

Description

阵列基板以及显示装置
本申请要求于2017年02月08日递交的中国专利申请第201710068945.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板以及显示装置。
背景技术
随着显示装置市场的不断发展，薄膜晶体管液晶显示装置(TFT-LCD)因其响应速度快、集成度高、功耗小、轻薄等优点已成为主流的显示装置。薄膜晶体管液晶显示装置(TFT-LCD)通常包括具有薄膜晶体管(Thin Film Transistor，TFT)阵列的阵列基板以及与之对盒设置的对置基板形成的液晶盒以及填充在液晶盒中的液晶分子层。
目前，随着薄膜晶体管液晶显示装置(TFT-LCD)的分辨率不断提高，尺寸不断增大，这就要求薄膜晶体管液晶显示装置(TFT-LCD)必须具有更快的响应速度和更高的充电效率。
发明内容
本公开至少一个实施例提供一种阵列基板以及显示装置，可解决通常的阵列基板响应速度较慢、充电效率较低等问题，并且可同时避免增加开口率。
本公开至少一个实施例提供一种阵列基板，其包括：衬底基板；第一有源层，设置在所述衬底基板上；第一绝缘层，设置在所述第一有源层和所述衬底基板上；栅极，设置在所述第一绝缘层远离所述第一有源层的一侧；第二绝缘层，设置在所述栅极和所述第一绝缘层上；第二有源层，设置在所述第二绝缘层远离所述栅极的一侧；第一漏极和第一源极，分别与所述第一有源层部分接触设置；第二漏极和第二源极，分别与所述第二有源层部分接触设置；以及像素电极，所述第一漏极和所述第二漏极电性相连，所述第一源极和所述第二源极电性相连，所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
例如，在本公开一实施例提供的阵列基板中，所述栅极在所述衬底基板上的正投影落入所述第一有源层和所述第二有源层在所述衬底基板的正投影之中。
例如，本公开一实施例提供的阵列基板还包括：第一过孔，设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一漏极，所述第二漏极通过所述第一过孔与所述第一漏极相连。
例如，本公开一实施例提供的阵列基板还包括：钝化层，设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧，所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
例如，本公开一实施例提供的阵列基板还包括：第二过孔，设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一源极，所述第二源极通过所述第二过孔与所述第一源极相连。
例如，本公开一实施例提供的阵列基板还包括：钝化层，设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧；第三过孔，设置在所述第一绝缘层、所述第二绝缘层、第二漏极以及所述钝化层中并部分暴露所述第一漏极；以及第一导电结构，设置在所述第三过孔中以将所述第一漏极和第二漏极电性相连。
例如，本公开一实施例提供的阵列基板还包括：第四过孔，设置在所述第一绝缘层、所述第二绝缘层、所述第二源极以及所述钝化层中并部分暴露所述第一源极；以及第二导电结构，设置在所述第四过孔中以将所述第一源极和所述第二源极电性相连。
例如，本公开一实施例提供的阵列基板中，所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
例如，本公开一实施例提供的阵列基板还包括：第五过孔，设置在所述钝化层中并部分暴露所述像素电极与所述第二漏极相接触的部分，所述第一导电结构还设置在所述第五过孔中。
例如，本公开一实施例提供的阵列基板中，所述像素电极包括所述第一导电结构。
本公开至少一个实施例提供一种显示装置，其包括上述任一项所述的阵列基板。
本公开至少一个实施例提供一种阵列基板的制作方法，其包括：在衬底基 板上形成第一有源层；在所述衬底基板上形成第一漏极和第一源极并分别与所述第一有源层部分接触设置；在所述第一有源层、所述第一源极以及所述第一漏极远离所述衬底基板的一侧形成第一绝缘层；在所述第一绝缘层远离所述第一有源层的一侧形成栅极；在所述栅极远离所述第一绝缘层的一侧形成第二绝缘层；在所述第二绝缘层远离所述栅极的一侧形成第二有源层；在所述第二绝缘层远离所述栅极的一侧形成第二漏极和第二源极并分别与所述第二有源层部分接触设置；以及形成像素电极，所述第一源极和所述第二源极电性相连，所述第一漏极和所述第二漏极电性相连，所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
例如，在本公开一实施例提供的阵列基板的制作方法中，在所述第二绝缘层远离所述栅极的一侧形成第二有源层后，包括：刻蚀所述第一绝缘层和所述第二绝缘层以形成部分暴露所述第一源极的第一过孔和部分暴露所述第一漏极的第二过孔，所述第二源极通过所述第一过孔与所述第一源极相连，所述第二漏极通过所述第二过孔与所述第一漏极相连。
例如，在本公开一实施例提供的阵列基板的制作方法中，在所述第二绝缘层远离所述栅极的一侧形成所述第二有源层包括：在所述第二绝缘层远离所述栅极的一侧形成第二半导体层；以及图案化所述第二半导体层以形成所述第二有源层，所述图案化所述第二半导体层以形成所述第二有源层与所述刻蚀所述第一绝缘层和所述第二绝缘层以形成所述第一过孔和所述第二过孔通过一次掩膜工艺形成。
例如，在本公开一实施例提供的阵列基板的制作方法中，在形成所述像素电极之后，该制作方法还包括：在所述像素电极远离所述衬底基板的一侧形成钝化层，所述钝化层设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧。
例如，本公开一实施例提供的阵列基板的制作方法还包括：在所述钝化层远离所述衬底基板的一侧形成公共电极。
本公开实施例提供的阵列基板及其制作方法以及显示装置至少具有以下有益效果之一：
(1)可提高阵列基板的响应速度以及充电效率。
(2)不增加薄膜晶体管开关所占的面积并且不降低开口率。
(3)结构简单，节省工艺步骤，节约成本。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的平面示意图；
图2为本公开一实施例提供的一种阵列基板的剖视示意图；
图3为本公开一实施例提供的一种阵列基板的平面示意图；
图4a为本公开一实施例提供的另一种阵列基板的剖视示意图；
图4b为本公开一实施例提供的另一种阵列基板的剖视示意图；
图5为本公开一实施例提供的一种阵列基板的制作方法的流程示意图；
图6a-图6h为本公开一实施例提供一种阵列基板的制作方法的分步示意图；
图7为本公开一实施例提供的另一种阵列基板的制作方法的分步示意图；
图8a-图8c本公开一实施例提供一种阵列基板的制作方法的分步示意图；以及
图9a-图9c本公开一实施例提供一种阵列基板的制作方法的分步示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
为了使薄膜晶体管液晶显示装置(TFT-LCD)具有更快的响应速度和更高的充电效率，双薄膜晶体管(Dual-TFT)结构被广泛使用。如图1所示，双薄膜晶体管(Dual-TFT)结构包括栅线1、与栅线1电性相连的栅极2、数据线3、与数据线3电性相连的源极4、漏极5以及与漏极5电性相连的像素电极6。源极4包括第一源极41和第二源极42，漏极5包括第一漏极51和第二漏极52，第一源极41和第一漏极51相对设置，第二源极42和第二漏极52相对设置，第一源极41、第二源极42、第一漏极51以及第二漏极52共用栅极2。这种双薄膜晶体管结构虽然提高了响应速度以及充电效率，但是增加了薄膜晶体管开关所占的面积并且减小了开口率。
本公开实施例提供一种阵列基板及其制作方法以及显示装置。该阵列基板包括衬底基板、设置在衬底基板上的第一有源层、设置在第一有源层和衬底基板上的第一绝缘层、设置在第一绝缘层远离第一有源层的一侧的栅极、设置在栅极和第一绝缘层上的第二绝缘层、设置在第二绝缘层远离栅极的一侧的第二有源层、分别与第一有源层部分接触设置第一漏极和第一源极、分别与第二有源层部分接触设置的第二漏极和第二源极以及像素电极。第一源极和第二源极电性相连，第一漏极和第二漏极电性相连，像素电极与第一漏极和第二漏极至少之一电性相连。由此，该阵列基板可在提高响应速度以及充电效率的同时，不增加薄膜晶体管开关所占的面积并不降低开口率。
下面结合附图对本公开实施例提供的阵列基板及其制作方法以及显示装置进行说明。
本公开一实施例提供一种阵列基板。图2示出了一种阵列基板的剖视示意图，如图2所示，该阵列基板包括衬底基板101、设置在衬底基板101上的第一有源层102、设置在第一有源层102和衬底基板101上的第一绝缘层103、设置在第一绝缘层103远离第一有源层102一侧的栅极104、设置在栅极104和第一绝缘层103上的第二绝缘层105、设置在第二绝缘层105远离栅极104的一侧的第二有源层106、分别与第一有源层102部分接触设置的第一漏极1071和第一源极1072、分别与第二有源层106部分接触设置的第二漏极1081和第二源极1082以及像素电极109。第一源极1072和第二源极1082电性相连，第一漏极1071和第二漏极1081电性相连，像素电极109与第一漏极1071和第二漏极1081至少之一电性相连。第一有源层102与第一源极1072相接触的区域可为源极区域，第一有源层102与第一漏极1071相接触的区域可为漏极 区域，第一有源层102的源极区域和漏极区域之间为沟道区域；第二有源层106与第二源极1082相接触的区域可为源极区域，第二有源层106与第二漏极1081相接触的区域可为漏极区域，第二有源层106的源极区域和漏极区域之间为沟道区域。
在本实施例提供的阵列基板中，第一源极和第二源极电性相连，第一漏极和第二漏极电性相连，像素电极通过第一漏极和第二漏极至少之一电性相连电信号可同时连接第一漏极和第二漏极，并且栅极可同时控制第一有源层和第二有源层的沟道区域。由此，该阵列基板可提高响应速度以及充电效率。例如，电信号可从第一源极进入，分流到第二源极后通过第一有源层和第二有源层的沟道区传输到第一漏极和第二漏极，从而利用单个栅极控制双沟道，因此不会产生延迟。另外，由于第二有源层、第二漏极以及第二源极等设置在第一有源层、第一漏极和第一源极上，从而不增加薄膜晶体管开关所占的面积并且不降低开口率。例如，图3为该阵列基板的俯视示意图，如图3所示，第二有源层、第二漏极以及第二源极在衬底基板上的正投影可与第一有源层、第一漏极和第一源极在衬底基板上的正投影重叠，从而不增加薄膜晶体管开关所占的面积并且不降低开口率。
例如，在一些示例中，如图2所示，第一漏极1071和第一源极1072分别搭接在第一有源层102上；第二漏极1081和第二源极1082分别搭接在第二有源层106上。
例如，在一些示例中，如图2所示，第一漏极1071与衬底基板101的距离小于第二漏极1081与衬底基板101的距离，第一源极1072与衬底基板101的距离小于第二源极1082与衬底基板101的距离；也就是说，第一漏极1071和第二漏极1081之间还设置有其他层结构，例如，第一绝缘层103和第二绝缘层105，同样地，第一源极1072和第二源极1082之间还设置有其他层结构，例如，第一绝缘层103和第二绝缘层105。
例如，在本实施例一示例提供的阵列基板中，如图2所示，栅极104在衬底基板101上的正投影落入第一有源层102和第二有源层106在衬底基板101的正投影之中。也就是说，栅极104与第一有源层102的沟道区域以及第二有源层106的沟道区域对应设置。由此，可保证栅极可同时控制第一有源层和第二有源层的沟道区域。
例如，在本实施例一示例提供的阵列基板中，如图2所示，该阵列基板还 包括设置在第一绝缘层103和第二绝缘层105中并部分暴露第一漏极1071的第一过孔121，第二漏极1081通过第一过孔121与第一漏极1071电性相连。由此，可通过第一过孔将第一漏极和第二漏极电性相连。
例如，在本实施例一示例提供的阵列基板中，如图2所示，该阵列基板还包括设置在第一绝缘层103和第二绝缘层105中并部分暴露第一源极1072的第二过孔122，第二源极1082通过第二过孔122与第一漏极1071电性相连。由此，可通过第二过孔将第一源极和第二源极电性相连。
例如，在本实施例一示例提供的阵列基板中，如图2所示，该阵列基板还包括设置在第二漏极1081和第二源极1082远离第二有源层106的一侧的钝化层110，像素电极109设置在第二漏极1081与钝化层110之间并与第二漏极1081部分接触。例如，如图2所示，像素电极109可搭接在第二漏极1081上。由此，该阵列基板不用通过过孔将像素电极和第二漏极相连，从而可简化该阵列基板的结构，提高可靠性。当然，本公开实施例包括但不限于此，像素电极也可设置在钝化层上并通过过孔与第二漏极电性相连。
例如，在本实施例一示例提供的阵列基板中，如图2所示，该阵列基板还包括公共电极线111，与栅极104同层设置。当然，公共电极线还可设置在其他层，本公开实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板中，如图2所示，该阵列基板还包括公共电极112，设置在钝化层110上并通过过孔113与公共电极线111电性相连。
本公开一实施例提供一种阵列基板。图4a示出了另一种阵列基板的剖视示意图，如图4a所示，该阵列基板还包括钝化层110，钝化层110设置在第二漏极1081和第二源极1082远离第二有源层106的一侧，与实施例一提供的阵列基板不同的是，该阵列基板还包括设置在第一绝缘层103、第二绝缘层105、第二漏极1081以及钝化层110中并部分暴露第一漏极1071的第三过孔123以及设置在第三过孔123以将第一漏极1071和第二漏极1081电性相连的第一导电结构114。由此，通过第一导电结构114和第三过孔123将第一漏极1071和第二漏极1081电性相连。
例如，在本实施例一示例提供的阵列基板中，如图4a所示，该阵列基板还包括设置在第一绝缘层103、第二绝缘层105、第二源极1082以及钝化层110中并部分暴露第一源极1072的第四过孔124以及设置在第四过孔124中将第 一源极1072和第二源极1082电性相连的第二导电结构115。由此，通过第二导电结构115和第四过孔124将第一源极1072和第二源极1082电性相连。
例如，如图4a所示，该阵列基板包括公共电极线111和公共电极112，公共电极112通过过孔113与公共电极线111电性相连。此时，第三过孔123和/或第四过孔124可与过孔113可通过一次掩膜工艺形成，从而可节省工艺，节约成本。
例如，在本实施例一示例提供的阵列基板中，如图4a所示，像素电极109设置在第二漏极1081和钝化层110之间并与第二漏极1081部分接触，从而与第二漏极1081电性相连。例如，如图4a所示，像素电极109可搭接在第二漏极1081上。由此，该阵列基板不用通过过孔将像素电极和第二漏极相连，从而可简化该阵列基板的结构，提高可靠性。当然，本公开实施例包括但不限于此，像素电极也可设置在钝化层上并通过过孔与第二漏极电性相连。
例如，在本实施例一示例提供的阵列基板中，如图4a所示，该阵列基板还包括设置在钝化层110中并部分暴露像素电极109与第二漏极1081相接触的部分的第五过孔125，第一导电结构114还设置在第五过孔125中。由此，可进一步提高像素电极与第二漏极电连接的可靠性。
例如，在本实施例一示例提供的阵列基板中，如图4a所示，像素电极109包括第一导电结构114，也就是说，第一导电结构114可为像素电极109的一部分。例如，如图4b所示，当本实施例提供的阵列基板采用TN结构时，即，阵列基板上只设置像素电极时，像素电极包括第一导电结构既可增加像素电极和第一漏极以及第二漏极电连接的稳定性和可靠性，还可增加该阵列基板的开口率。
本公开一实施例提供一种显示装置，其包括上述实施例一和二中任一项所描述的阵列基板。因此，该显示装置具有与上述实施例一和二中任一项所描述的阵列基板的有益效果相对应的有益效果，具体可参见实施例一和二中的相关描述，本实施例在此不再赘述。另外，由于该显示装置具有较快的响应速度和充电效率，可适用于尺寸较大的显示装置，例如电视机、舞台银幕等。
本公开一实施例提供一种阵列基板的制作方法，如图5所示，该阵列基板的制作方法包括以下步骤S401-S408。
步骤S401：如图6a所示，在衬底基板101上形成第一有源层102。
例如，衬底基板可选用玻璃基板、石英基板、塑料基板等；第一有源层的 材料可采用氧化物半导体、非晶硅、多晶硅等；当然，本公开实施例包括但不限于此。
步骤S402：如图6b所示，在衬底基板101上形成第一漏极1071和第一源极1072并分别与第一有源层102部分接触设置。
例如，如图6b所示，第一漏极1071和第一源极1072分别搭接在第一有源层102的两侧，即，第一有源层102的源极区域和漏极区域。另外，如图6b所示，第一漏极1071和第一源极1072设置在第一有源层102远离衬底基板101的一侧，当然，第一漏极1071和第一源极1072也可设置在第一有源层102靠近衬底基板的一侧，本公开实施例在此不作限制。
步骤S403：如图6c所示，在第一有源层102、第一源极1072以及第一漏极1071远离衬底基板101的一侧形成第一绝缘层103。
例如，第一绝缘层的材料可采用有机绝缘材料或无机绝缘材料，本公开实施例在此不作限制。
步骤S404：如图6d所示，在第一绝缘层103远离第一有源层102的一侧形成栅极104。
例如，栅极的材料可包括选自铝，铝合金，铜，铜合金，钼，以及钼铝合金中的一种或多种。
步骤S405：如图6e所示，在栅极104远离第一绝缘层103的一侧形成第二绝缘层105。
例如，第二绝缘层的材料可采用有机绝缘材料或无机绝缘材料，本公开实施例在此不作限制。
步骤S406：如图6f所示，在第二绝缘层105远离栅极104的一侧形成第二有源层106。
例如，第二有源层的材料可采用氧化物半导体、非晶硅、多晶硅等；当然，本公开实施例包括但不限于此。
步骤S407：如图6g所示，在第二绝缘层105远离栅极104的一侧形成第二漏极1081和第二源极1082并分别与第二有源层106部分接触设置。
例如，如图6g所示，第二漏极1081和第二源极1082可通过过孔分别与第一漏极1071和第一源极1072电性相连。
步骤S408：如图6h所示，形成像素电极，像素电极与第一漏极和第二漏极至少之一电性相连。
在本实施例提供的阵列基板的制作方法中，第一源极和第二源极电性相连，第一漏极和第二漏极电性相连，像素电极通过第一漏极和第二漏极至少之一电性相连电信号可同时连接第一漏极和第二漏极，并且栅极可同时控制第一有源层和第二有源层的沟道区域。由此，该阵列基板可提高响应速度以及充电效率。例如，电信号可从第一源极进入，分流到第二源极后通过第一有源层和第二有源层的沟道区传输到第一漏极和第二漏极，从而利用单个栅极控制双沟道，因此不会产生延迟。另外，由于第二有源层、第二漏极以及第二源极等设置在第一有源层、第一漏极和第一源极上，从而不增加薄膜晶体管开关所占的面积并且不降低开口率。另外，第二有源层、第二漏极以及第二源极在衬底基板上的正投影可与第一有源层、第一漏极和第一源极在衬底基板上的正投影重叠，从而不增加薄膜晶体管开关所占的面积并且不降低开口率。
例如，在本实施例一示例提供的阵列基板的制作方法中，在步骤S406之后，即在第二绝缘层远离栅极的一侧形成第二有源层之后，如图7所示，刻蚀第一绝缘层103和第二绝缘层105以形成部分暴露所述第一源极1072的第一过孔121和部分暴露第一漏极1071的第二过孔122。第二源极1082通过第一过孔121与第一源极1072相连，第二漏极1081通过第二过孔122与第一漏极1071相连。
例如，在本实施例一示例提供的阵列基板的制作方法中，步骤S406，即，在第二绝缘层远离栅极的一侧形成第二有源层包括：在第二绝缘层远离栅极的一侧形成第二半导体层；以及图案化第二半导体层以形成第二有源层，所述图案化第二半导体层以形成第二有源层与刻蚀所述第一绝缘层和第二绝缘层以形成第一过孔和第二过孔可通过一次掩膜工艺形成，例如，使用半色调掩膜首先刻蚀第一过孔和第二过孔，然后进行灰化工艺，最后形成第二有源层。由此，可节省工艺步骤，并降低制作成本。
例如，在本实施例一示例提供的制作方法中，在步骤S408之后，即，在形成像素电极109之后，如图8a所示，该制作方法还包括：在形成后的基板上形成钝化层110。
例如，在本实施例一示例提供的制作方法中，如图8b所示，该阵列基板的制作方法还包括形成公共电极线111，例如，公共电极线111可与栅极104同层形成。当然，公共电极线还可形成在其他层，本公开实施例在此不作限制。该阵列基板还包括在钝化层110和第二绝缘层105中刻蚀过孔113。
例如，在本实施例一示例提供的制作方法中，如图8c所示，该阵列基板的制作方法还包括在钝化层110上形成公共电极112，公共电极112通过过孔113与公共电极线111电性相连。
例如，在本实施例一示例提供的制作方法中，在步骤S408之后，即，在形成像素电极之后，如图9a所示，在形成后的基板上形成钝化层110，钝化层110设置在第二漏极1081和第二源极1082远离第二有源层106的一侧。
例如，在本实施例一示例提供的制作方法中，在形成钝化层110后，如图9b所示，在第一绝缘层103、第二绝缘层105、第二漏极1081以及钝化层110中形成部分暴露第一漏极1071的第三过孔123以及部分暴露第一源极1072的第四过孔124。如图9c所示，在第三过孔123形成将第一漏极1071和第二漏极1081电性相连的第一导电结构114；在第四过孔124中形成将第一源极1072和第二源极1082电性相连的第二导电结构115。由此，通过第一导电结构114和第三过孔123将第一漏极1071和第二漏极1081电性相连。需要说明的是，上述的第一导电结构114和第二导电结构115可为同一导电层经一次图案化工艺图案化而成，通过第二导电结构115和第四过孔124将第一源极1072和第二源极1082电性相连，当然，本公开实施例包括但不限于此。
例如，在本实施例一示例提供的阵列基板的制作方法中，如图9b所示，该阵列基板的制作方法还包括在钝化层110中形成部分暴露像素电极109与第二漏极1081相接触的部分的第五过孔125。由此，如图9c所示，可通过将第一导电结构114还设置在第五过孔125中以将像素电极109与第二漏极1081电连接，从而可进一步提高像素电极与第二漏极电连接的可靠性。例如，上述形成第五过孔的步骤与形成第三过孔、第四过孔的步骤可经同一掩膜工艺完成。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以 相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种阵列基板，包括：
    衬底基板；
    第一有源层，设置在所述衬底基板上；
    第一绝缘层，设置在所述第一有源层和所述衬底基板上；
    栅极，设置在所述第一绝缘层远离所述第一有源层的一侧；
    第二绝缘层，设置在所述栅极和所述第一绝缘层上；
    第二有源层，设置在所述第二绝缘层远离所述栅极的一侧；
    第一漏极和第一源极，分别与所述第一有源层部分接触设置；
    第二漏极和第二源极，分别与所述第二有源层部分接触设置；以及
    像素电极，
    其中，所述第一漏极和所述第二漏极电性相连，所述第一源极和所述第二源极电性相连，所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
  2. 根据权利要求1所述的阵列基板，其中，所述栅极在所述衬底基板上的正投影落入所述第一有源层和所述第二有源层在所述衬底基板的正投影之中。
  3. 根据权利要求1或2所述的阵列基板，还包括：
    第一过孔，设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一漏极，所述第二漏极通过所述第一过孔与所述第一漏极相连。
  4. 根据权利要求3所述的阵列基板，还包括：
    钝化层，设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧，
    其中，所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
  5. 根据权利要求3所述的阵列基板，还包括：
    第二过孔，设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一源极，所述第二源极通过所述第二过孔与所述第一源极相连。
  6. 根据权利要求1-5中任一项所述的阵列基板，还包括：
    钝化层，设置在所述第二漏极和所述第二源极远离所述第二有源层的一 侧；
    第三过孔，设置在所述第一绝缘层、所述第二绝缘层、第二漏极以及所述钝化层中并部分暴露所述第一漏极；以及
    第一导电结构，设置在所述第三过孔中以将所述第一漏极和第二漏极电性相连。
  7. 根据权利要求6所述的阵列基板，还包括：
    第四过孔，设置在所述第一绝缘层、所述第二绝缘层、所述第二源极以及所述钝化层中并部分暴露所述第一源极；以及
    第二导电结构，设置在所述第四过孔中以将所述第一源极和所述第二源极电性相连。
  8. 根据权利要求6所述的阵列基板，其中，所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
  9. 根据权利要求6所述的阵列基板，还包括：
    第五过孔，设置在所述钝化层中并部分暴露所述像素电极与所述第二漏极相接触的部分，所述第一导电结构还设置在所述第五过孔中。
  10. 根据权利要求6所述的阵列基板，其中，所述像素电极包括所述第一导电结构。
  11. 一种显示装置，包括权利要求1-10中任一项所述的阵列基板。
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