WO2019033306A1 - 一种脉冲宽度调制信号的动态调整方法和装置 - Google Patents

一种脉冲宽度调制信号的动态调整方法和装置 Download PDF

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Publication number
WO2019033306A1
WO2019033306A1 PCT/CN2017/097693 CN2017097693W WO2019033306A1 WO 2019033306 A1 WO2019033306 A1 WO 2019033306A1 CN 2017097693 W CN2017097693 W CN 2017097693W WO 2019033306 A1 WO2019033306 A1 WO 2019033306A1
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value
bit
dynamic
bits
cache
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PCT/CN2017/097693
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English (en)
French (fr)
Inventor
王青岗
胡喜
胡庚
卓越
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西门子公司
王青岗
胡喜
胡庚
卓越
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Priority to PCT/CN2017/097693 priority Critical patent/WO2019033306A1/zh
Publication of WO2019033306A1 publication Critical patent/WO2019033306A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Definitions

  • the present application relates to the field of signal processing technologies, and in particular, to a dynamic adjustment method and apparatus for a Pulse Width Modulation (PWM) signal.
  • PWM Pulse Width Modulation
  • PWM is an effective technique for controlling analog circuits by using the digital output of a microprocessor. It is widely used in many fields such as measurement, communication, power control and conversion. For example, PWM technology can be used in industrial field devices with current output control, especially for related devices that can be addressed by High Speed Addressable Remote Transit (HART).
  • HART High Speed Addressable Remote Transit
  • the output current accuracy of the PWM control is determined by factors such as the CPU clock frequency, the PWM control bit length, and the corner frequency of the low-pass filter.
  • the CPU clock frequency is especially critical.
  • CPU clock frequencies for low-power devices are typically low, such as 1 to 2 megahertz (MHz), making it difficult to provide a large number of PWM control bits.
  • the main object of embodiments of the present invention is to provide a method and apparatus for dynamically adjusting a PWM signal.
  • a method for dynamically adjusting a PWM signal comprising:
  • Determining a base value based on the target duty ratio storing the base value in a PWM control bit, storing accuracy compensation data of a base value in a buffer bit, and storing a dynamic compensation parameter in a dynamic compensation bit;
  • the determining the target duty cycle comprises:
  • the quotient is determined as the target duty cycle.
  • the embodiment of the present invention can quickly determine the target duty ratio by establishing a function relationship between the target output current value and the maximum output current value, which is convenient for implementation in an industrial field.
  • the determining the base value based on the target duty ratio comprises:
  • the maximum value of the control bit is determined based on the number of bits of the PWM control bit
  • the embodiment of the present invention can conveniently determine the basic value according to the number of bits of the PWM control bit, and is applicable to various specific control environments.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with a base value plus one, and the number of base values in the cache is increased by one The sum of the number is equal to the maximum value of the cache bit determined based on the number of bits of the cache bit; or
  • the precision compensation data is a number of base values stored in the cache, and the remaining portion of the cache is filled with a base value, and the sum of the number of base values in the cache and the base value plus one is Equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the embodiment of the present invention can determine the specific storage structure of the cache based on the number of base values, and can also determine the specific storage structure of the cache based on the number of base values plus one.
  • the cache storage structure has multiple implementation manners.
  • the generating the PWM signal using the base value and the precision compensation data comprises:
  • An actual duty cycle is determined using the third value and a PWM signal is generated based on the actual duty cycle.
  • the specific storage structure of the cache determines the actual duty ratio and generates a PWM signal, and the calculation process is simple, and the PWM signal generation speed is fast.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false
  • the base value stored in the cache is changed to the base value plus one, and the dynamic adjustment flag is set to logically true.
  • the step value is subtracted from the maximum value of the dynamic compensation bit.
  • the embodiment of the present invention adds one base value stored in the cache to the base value plus one, that is, increases the base value in the cache.
  • the number of ones is increased, and the number of additions is strictly limited to one, and the number of base values in the cache is reduced, wherein the number of reductions is strictly limited to one, thus finely compensating for loss accuracy.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • step value is less than the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically true, one of the base values stored in the buffer is incremented to a base value, and the dynamic adjustment flag is set to logical false.
  • the embodiment of the present invention adds one base value stored in the cache to the base value, that is, reduces the base value in the cache.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is increased when the step value is greater than or equal to the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically true.
  • the embodiment of the present invention re-adds the step value to constitute a new complete cycle.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is increased when the step value is less than the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically false.
  • the embodiment of the present invention can re-add the step value to form a new complete cycle.
  • a dynamic adjustment device for a PWM signal comprising:
  • a duty cycle and accuracy determination module for determining a target duty cycle and a number of control precision bits
  • a bit determining module configured to determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein a sum of the number of bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number;
  • a bit determining module configured to determine a base value based on the target duty ratio, store the base value in a PWM control bit, store accuracy compensation data of a base value in a buffer bit, and store a dynamic compensation parameter in a dynamic compensation bit;
  • a dynamic adjustment module configured to generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • a duty cycle and accuracy determination module is configured to determine a target output current value and a maximum output current value; The quotient of the output current value and the maximum output current value; the quotient is determined as the target duty cycle.
  • the embodiment of the present invention can quickly determine the target duty ratio by establishing a function relationship between the target output current value and the maximum output current value, which is convenient for implementation in an industrial field.
  • the bit determining module is configured to determine a control bit maximum value based on the number of bits of the PWM control bit; determine a product of the control bit maximum value and the target duty ratio, and take the product downward
  • the integer value is determined as the base value.
  • the embodiment of the present invention can conveniently determine the basic value according to the number of bits of the PWM control bit, and is applicable to various specific control environments.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with a base value plus one, and the number of base values in the cache is increased by one The sum of the number is equal to the maximum value of the cache bit determined based on the number of bits of the cache bit; or
  • the precision compensation data is a number of base values stored in the cache, and the remaining portion of the cache is filled with a base value, and the sum of the number of base values in the cache and the base value plus one is Equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the embodiment of the present invention can determine the specific storage structure of the cache based on the number of base values, and can also determine the specific storage structure of the cache based on the number of base values plus one.
  • the cache storage structure has multiple implementation manners.
  • the dynamic adjustment module is configured to extract all the base values from the cache and sum them as the first value, extract all the base values from the cache and sum them together as the second value; a sum of a value and a second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and based on the actual occupation The air ratio generates a PWM signal.
  • the specific storage structure of the cache determines the actual duty ratio and generates a PWM signal, and the calculation process is simple, and the PWM signal generation speed is fast.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, one of the buffers is stored. The base value becomes the base value plus one, the dynamic adjustment flag is set to logically true, and the step value is subtracted from the dynamic compensation bit maximum.
  • the embodiment of the present invention adds one base value stored in the cache to the base value plus one, that is, increases the base value in the cache.
  • the number of ones is increased, and the number of additions is strictly limited to one, and the number of base values in the cache is reduced, wherein the number of reductions is strictly limited to one, thus finely compensating for loss accuracy.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, a base stored in the buffer is stored. The value plus one becomes the base value, and the dynamic adjustment flag is set to logical false.
  • the embodiment of the present invention adds one base value stored in the cache to the base value, that is, reduces the base value in the cache.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logic true, the step value is increased.
  • the embodiment of the present invention re-adds the step value to constitute a new complete cycle.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is a logical false, the step value is increased.
  • the embodiment of the present invention can re-add the step value to form a new complete cycle.
  • a HART device that includes:
  • the embodiment of the present invention also proposes a HART device that improves the control precision of the PWM signal, and the HART device can also reduce the number of bits and the buffer space of the PMW control bit.
  • a storage medium storing a computer program for performing the method of any of the above. It can be seen that the embodiment of the present invention also proposes a storage medium that improves the control precision of the PWM signal.
  • FIG. 1 is a flow chart of a method for dynamically adjusting a PWM signal according to an embodiment of the present invention
  • FIG. 2 is an exemplary structural diagram of a bit composition when the number of control precision bits is 16 according to an embodiment of the present invention
  • FIG. 3 is an exemplary flowchart of a dynamic compensation method based on the bit structure shown in FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a structural diagram of a dynamic adjustment device for a PWM signal according to an embodiment of the present invention.
  • FIG. 5 is a structural diagram of a HART device according to an embodiment of the present invention.
  • FIG. 7 is a simulation diagram of an output current according to an embodiment of the present invention.
  • the embodiment of the present invention not only the accuracy of the precision data lost due to the number of bits of the PWM control being less than the number of control precision bits is compensated by the buffer (which may be referred to as one-time compensation), but also the dynamic compensation bit pair is used due to the number of PWM control bits.
  • the lost precision data performs dynamic compensation again (which can be called quadratic compensation).
  • the embodiment of the invention can reduce the number of bits and the buffer space of the PMW control bit, thereby reducing the requirement on the CPU clock frequency and saving cost.
  • FIG. 1 is a flow chart of a method for dynamically adjusting a PWM signal according to an embodiment of the present invention.
  • the method includes:
  • Step 101 Determine a target duty ratio (DutyRatio) and a control precision bit number.
  • the duty cycle is the ratio of the time that the active level occupies within one cycle; the target duty cycle is the duty cycle that the desired PWM signal can reach.
  • the target duty ratio may be determined based on the target output current value and the maximum output current value.
  • the method includes: first determining a target output current value and a maximum output current value, and then calculating a quotient of the target output current value and the maximum output current value; determining the quotient as the target duty ratio.
  • control precision bits can be specifically implemented as 4 bits, 8 bits, 16 bits, 32 bits, 64 bits. Bit, and so on.
  • Step 102 Determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein the sum of the bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number.
  • the number of control precision bits determined in step 101 is divided into three parts, which are the number of bits of the PWM control bit, the number of bits of the buffer bit, and the number of bits of the dynamic compensation bit.
  • the number of bits of the PWM control bit can be 6 bits, the number of bits of the buffer bit can be 5 bits, and the number of bits of the dynamic compensation bit can be 5 bits; or, the PWM control bit
  • the number of bits can be 8 bits, the number of bits of the buffer bit can be 4 bits, the number of bits of the dynamic compensation bit can be 4 bits, and so on.
  • the number of bits of the PWM control bits, buffer bits, and dynamic compensation bits can be flexibly allocated within the number of control precision bits based on the specific application requirements. As long as the sum of the number of bits of the assigned PWM control bit, buffer bit and dynamic compensation bit is still equal to the number of control precision bits, the control accuracy can still be guaranteed.
  • the number of bits of the PWM control bit can be reduced; when the CPU clock frequency is high, the number of bits of the PWM control bit can be increased.
  • the number of bits of the cache bit can be reduced; when the cache storage space is sufficient, the number of bits of the cache bit can be increased.
  • Step 103 Determine the base value based on the target duty ratio, store the base value in the PWM control bit, store the precision compensation data of the base value in the buffer bit, and store the dynamic compensation parameter in the dynamic compensation bit.
  • the PWM control bits are typically used to hold the base value determined by the target duty cycle.
  • the base value is an intermediate value determined by the number of bits of the PWM control bit and the target duty cycle, which is used to quickly calculate the actual duty cycle.
  • the target duty ratio of the remainder it is also convenient for the cache to store.
  • determining the base value based on the target duty ratio includes: determining a control bit maximum value based on the number of bits of the PWM control bit; determining a product of the control bit maximum value and the target duty ratio, and rounding down the product Determined as the base value.
  • the target output current value is 12.3456 mA
  • the PWM control bit is 5 bits, so the PWM control bit has a maximum value of 2 5 , that is, 32, and the product of the PWM control bit maximum value and the target duty ratio is 32 ⁇ 0.3858, and the product result is rounded down to obtain a value of 12 , to determine the base value is 12.
  • the number of PWM control bits is less than the number of control precision bits, which can reduce the PWM control period and thereby reduce low frequency noise.
  • the base value can usually only be close to the target duty cycle within the accuracy determined by the number of PWM control bits.
  • the precision compensation data of the underlying value is saved in the cache bit. Accuracy compensation data can be lost to the number of precision controlled by the number of PWM control bits According to the implementation of compensation.
  • the method includes: setting a cache whose storage space is equal to the maximum value of the cache bit, and storing a plurality of base values and a plurality of base values plus one in the cache. By adding the base value in the cache and adding one to the base value of the finest value of the base value, the finest adjustment of the duty cycle indirectly reflected by the base value can be achieved.
  • the cached storage space is determined by the size of the cache bits, and the precision compensation data represents the ratio between the base value in the cache and the base value plus one.
  • the precision compensation data can be implemented as the number of base values stored in the cache, or as the number of base values stored in the cache plus one.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is filled with the base value plus one, and the number of base values in the cache is increased by one. And, equal to the maximum number of cache bits determined based on the number of bits in the cache bit. At this time, the number of base values stored in the cache is equal to the precision compensation data, and the remaining portion of the cache stores the base value plus one, that is, the number of base values plus one is the maximum value of the cache bit minus the precision compensation data.
  • the precision compensation data is a number of the base value stored in the cache, and the remaining part of the buffer is filled with the base value, and the number of base values in the cache is increased by one. And, equal to the maximum number of cache bits determined based on the number of bits in the cache bit. At this time, the number of base values added in the buffer plus one is equal to the precision compensation data, and the remaining portion of the buffer stores the base value, that is, the number of base values is the maximum value of the buffer bit minus the precision compensation data.
  • the sum of the number of bits of the PWM control bit and the number of bits of the buffer bit is still less than the number of control precision bits. Therefore, even if the buffer bit is used to compensate the precision data lost by the PWM control bit limit, the accuracy data will still be lost.
  • the embodiment of the present invention performs secondary dynamic compensation on the lost precision data by using the dynamic compensation parameter stored in the dynamic compensation bit, and the secondary dynamic compensation mode will be specifically described in the subsequent step 104.
  • Step 104 Generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • generating the PWM signal using the base value and the precision compensation data comprises: extracting all the base values from the buffer and summing them as the first value, extracting all the base values from the buffer and summing them together as a a second value; calculating a sum of the first value and the second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and based on The actual duty cycle generates a PWM signal.
  • the PWM signal is a PWM signal generated after performing one compensation using the precision compensation data, and the PWM signal still loses part of the precision data after being compensated once.
  • the PWM generation circuit traverses the entire cache, wherein when a base value is encountered in the cache, a base value of a high level pulse is generated within a control period determined by a maximum value of the PWM control bit, and in the control The other time of the cycle is kept low; when the base value is increased by one in the buffer, the base value is added and a high level pulse is generated in the control period determined by the maximum value of the PWM control bit, and other ones in the control cycle Time is kept low. After the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes a PWM signal.
  • the dynamic compensation parameter stored in the dynamic compensation bit is used to add one to the base value and the base value in the buffer.
  • the scale is finely and dynamically adjusted to perform dynamic compensation on the missing precision data.
  • the dynamic adjustment flag is set in advance before performing dynamic compensation.
  • the dynamic adjustment flag is used to identify whether the cache has been dynamically adjusted. When the dynamic adjustment flag is logically false, it indicates that the cache has not been dynamically adjusted; when the dynamic adjustment flag is logically true, it indicates that the cache has been dynamically adjusted. The initial value of the dynamic adjustment flag is logically false.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes:
  • the maximum value of the dynamic compensation bit is determined based on the number of bits of the dynamic compensation bit; when the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, one of the base values stored in the buffer is incremented by one, The dynamic adjustment flag is set to logic true and the step value is subtracted from the dynamic compensation bit maximum.
  • the base value stored in the cache is changed to the base value plus one, that is, the number of the base value plus one in the cache is increased (the number of increments is strictly limited to 1), and the cache is reduced.
  • the number of base values in (the number of reductions is strictly limited to 1), which finely compensates for the loss accuracy.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes:
  • the maximum value of the dynamic compensation bit is determined based on the number of bits of the dynamic compensation bit; when the step value is smaller than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, adding a base value stored in the buffer to the base becomes Value, set the dynamic adjustment flag to logically false.
  • the base value stored in the cache is added to the base value, that is, the number of base values in the cache is increased by one (the number of reduction is strictly limited to 1), and the cache is increased.
  • the number of base values in (the number of increments is strictly limited to 1), thereby preventing errors caused by repeated compensation.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes: determining a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit; and when the step value is greater than or equal to the maximum value of the dynamic compensation bit When the preset dynamic adjustment flag is logically true, the step value is increased.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes: determining a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit; and when the step value is less than the maximum value of the dynamic compensation bit and When the preset dynamic adjustment flag is logically false, the step value is increased.
  • the method illustrated in Figure 1 can be implemented based on various hardware circuits or software flows.
  • a hardware circuit When a hardware circuit is employed, a specially designed permanent circuit, logic device, or programmable logic device can be utilized to perform the method illustrated in FIG.
  • a software flow When a software flow is employed, the method illustrated in Figure 1 can be performed in a variety of programming languages or assembly languages.
  • FIG. 2 is an exemplary structural diagram of bit composition when the number of control precision bits is 16 according to an embodiment of the present invention.
  • the number of control precision bits is 16 bits, wherein the PWM control bit is the first 6 bits, the buffer bit is the middle 5 bits, and the dynamic compensation bit is the last 5 bits.
  • the maximum output current value is 32 mA (mA); the target output current value is 12.3456 mA; the CPU clock frequency is 1.84320 MHz; The corner frequency of the filter is 18HZ.
  • the PWM control bit is 6 bits, so the PWM control bit has a maximum value of 2 6 , which is 64.
  • the product of the maximum value of the PWM control bit and the target duty ratio is 64 ⁇ 0.3858, and the product result is rounded down to obtain a value of 24 to determine the base value of 24.
  • the base value (24) is converted to a binary number and the result of the conversion is 011000, so the binary number (011000) is stored in the PWM control bit.
  • the cached bits are stored with the calculated precision compensation data such that the compensated actual duty cycle is as close as possible to the target duty cycle.
  • a binary number 10110 ie, 22
  • the step value is saved in the dynamic compensation bit.
  • the step value is used to control the cycle speed of the dynamic compensation process.
  • the step value is a preset value. When the desired cycle speed is faster, the step value can be increased; when the cycle speed is expected to be slow, the step value can be lowered.
  • a dynamic adjustment flag is set in advance to identify whether the cache has been dynamically adjusted. When the dynamic adjustment flag is logically false, it indicates that the cache has not been dynamically adjusted; when the dynamic adjustment flag is logically true, it indicates that the cache has been dynamically adjusted.
  • FIG. 3 is a flow chart of a dynamic compensation method based on the bit structure shown in FIG. 2, in accordance with an embodiment of the present invention.
  • the method includes:
  • Step 300 Set the initial value of the dynamic adjustment flag to logic false, obtain the base value from the PWM control bit, store the base value (ie, 24) in the cache according to the ratio of the number of storage determined by the precision of the PWM control bit.
  • the base value is incremented by one (ie, 25), and the step value is determined to be 4 based on the stored content of the dynamic compensation bit.
  • Step 301 Extract all base values and all base values from the cache and add one to generate a PWM signal.
  • all 22 base values plus one (ie 25) are extracted from the cache, and the 22 base values are summed to obtain a first value 550; all 10 base values are extracted from the cache ( That is, 24), then summing the 10 24 to obtain the second value 240; then dividing the sum of the first value (550) and the second value (240) by the maximum value of the buffer bit (32) to obtain the third value ( 24.6875), using the third value to determine the actual duty cycle after buffer compensation is 0.3857. Then, the PWM signal is generated by the actual duty ratio after the buffer compensation.
  • the PWM generation circuit traverses the entire cache, wherein when a base value is encountered in the buffer, a base value high level pulse is generated within a control period determined by a maximum value of the PWM control bit; When the base value is incremented by one in the buffer, a base value is added plus a high level pulse in the control period determined by the maximum value of the PWM control bit.
  • the PWM generation circuit traverses the entire buffer. When the base value (ie, 24) is encountered in the buffer, the PWM generation circuit generates 24 high-level pulses in 64 clock cycles, while the remaining 40 clock cycles remain low. When the base value is incremented by one (ie, 25), the PWM generation circuit generates 25 high-level pulses in 64 clock cycles, while the remaining 39 clock cycles remain low.
  • the PWM generation circuit will encounter 10 base values in the buffer and thus perform the following operations 10 times: 24 high-level pulses are generated in 64 clock cycles; the PWM generation circuit will encounter 22 base values in the buffer One is added, and thus 22 operations are performed as follows: 25 high-level pulses are generated in 64 clock cycles. After the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes a PWM signal.
  • Step 302 The step value is incremented.
  • Step 303 Determine whether the step value is greater than or equal to the maximum value of the dynamic compensation bit. If it is greater, step 304 is performed, otherwise step 305 is performed.
  • Step 304 Determine whether the dynamic adjustment flag is logically true. If yes, go back to step 301, otherwise go to step 307.
  • Step 305 Determine whether the dynamic adjustment flag is logically true. If yes, execute step 306, otherwise return to step 301.
  • Step 306 Set the dynamic adjustment identifier to logical false, and add one base value stored in the cache to the base value, that is, reduce the number of base values plus one in the cache (the number of reduction is strictly limited to 1), and increase The number of base values in the cache (the number of additions is strictly limited to 1), and then returns to step 301.
  • the original PWM signal can be dynamically restored based on the buffer that has been adjusted to prevent the error caused by the repeated compensation.
  • Step 307 Set the dynamic adjustment identifier to logically true, and add a base value stored in the cache to the base value plus one, that is, increase the number of base values plus one in the cache (the number of additions is strictly limited to 1), and decrease The number of base values in the cache (the number of additions is strictly limited to 1), and then returns to step 301. After adjustment, the number of base values in the cache becomes 9, and the number of base values plus one becomes 23. Then, in the subsequent step 301, the PWM signal can be dynamically adjusted based on the buffer that has been adjusted to finely compensate for the loss accuracy.
  • the PWM generating circuit will encounter 9 basic values, and thus perform the following operations 9 times: 24 high-level pulses are generated in 64 clock cycles; the PWM generating circuit will encounter 23 The base values are incremented by one, and thus 23 operations are performed as follows: 25 high-level pulses are generated in 64 clock cycles.
  • the subsequent step 301 after the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes the adjusted PWM signal.
  • the dynamic adjustment identifier may be not set to a logically true operation in step 307, but the dynamic adjustment identifier is set to a logically true operation between step 303 and step 303. . That is, the dynamic adjustment flag is set to a logically true operation, moving from step 307 to between step 303 and step 303, thereby avoiding possible loops.
  • an embodiment of the present invention further provides a dynamic adjustment device for a PWM signal.
  • FIG. 4 is a structural diagram of a dynamic adjustment device for a PWM signal according to an embodiment of the present invention.
  • the apparatus 400 includes:
  • a duty ratio and accuracy determining module 401 for determining a target duty ratio and a number of control precision bits
  • the bit number determining module 402 is configured to determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein a sum of the bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number;
  • the bit determining module 403 is configured to determine a base value based on the target duty ratio, store the base value in the PWM control bit, store the precision compensation data of the base value in the buffer bit, and store the dynamic compensation parameter in the dynamic compensation bit;
  • the dynamic adjustment module 404 is configured to generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • the duty cycle and progress determination module 401 is configured to determine a target output current value and a maximum output current value; calculate a quotient of the target output current value and the maximum output current value; determine the quotient as the target duty ratio.
  • the bit determining module 403 is configured to determine a control bit maximum value based on the number of bits of the PWM control bit; determine a product of the control bit maximum value and the target duty ratio, and round down the product The value is determined as the base value.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with the base value plus one; the number of base values in the cache is increased by one of the base values And, equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the dynamic adjustment module 404 is configured to extract all the base values from the cache and sum them as the first value, extract all the base values from the cache and sum them together as the second value; a sum of the first value and the second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and generating the actual duty ratio based on the actual duty ratio PWM signal.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, the buffer is stored in the cache. A base value becomes the base value plus one, the dynamic adjustment flag is set to logically true, and the step value is subtracted from the dynamic compensation bit maximum.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is smaller than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, one of the caches is stored. The base value plus one becomes the base value, and the dynamic adjustment flag is set to logical false.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, the step value is increased. .
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, the step value is increased.
  • HART devices are typically low-power devices, and the CPU clock frequency is typically low, making it difficult to provide a large number of PWM control bits.
  • the number of bits and the buffer space of the PMW control bit can be reduced under the premise of ensuring the control precision, thereby reducing the CPU clock frequency requirement and saving cost, especially for the HART device. .
  • FIG. 5 is a structural diagram of a HART device according to an embodiment of the present invention.
  • the device 500 includes:
  • a dynamic signal adjusting device 501 for generating a PWM signal
  • the current output module 502 is configured to output a current controlled by the PWM signal.
  • the PWM signal dynamic adjustment device 501 can have the same structure of the dynamic adjustment device 400 of the PWM signal as shown in FIG. 4.
  • FIG. 6 is a prior art output current simulation diagram using only buffer compensation
  • FIG. 7 is an output current simulation diagram in accordance with an embodiment of the present invention.
  • the number of bits in the PWM control bit is 9, and the number of bits in the buffer bit is 7.
  • the number of bits in the PWM control bit is 6, the number of bits in the buffer bit is 5, and the number of bits in the dynamic compensation bit. Is 5.
  • the vertical axis represents the output current
  • the horizontal axis represents the stored value of the buffer bit
  • the vertical axis represents the output current
  • the horizontal axis represents the stored value of the dynamic compensation bit.
  • the output current has the same limit value, which are -0.5 and +0.5, respectively.
  • the PWM control bit only needs 6 bits. Compared with the 9 bits required in the prior art, the number of PWM control bits is significantly reduced, and the requirement for the CPU clock frequency can be reduced.
  • the number of bits of the cache bit only needs 5 bits. Compared with the 7 bits required in the prior art, the number of cache bits is also significantly reduced, and the requirement for the cache space can also be reduced.
  • the hardware modules in the various embodiments may be implemented mechanically or electronically.
  • a hardware module can include specially designed permanent circuits or logic devices (such as dedicated processors such as FPGAs or ASICs) for performing specific operations.
  • the hardware modules may also include programmable logic devices or circuits (such as including general purpose processors or other programmable processors) that are temporarily configured by software for performing particular operations.
  • Hardware implementations can be made based on cost and time considerations, either by mechanical means, by dedicated permanent circuits, or by temporarily configured circuits (as configured by software).
  • the present invention also provides a machine readable storage medium storing instructions for causing a machine to perform a method as described herein.
  • a system or apparatus equipped with a storage medium on which software program code implementing the functions of any of the above-described embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be stored Reading and executing the program code stored in the storage medium.
  • some or all of the actual operations may be performed by an operating system or the like operating on a computer based on instructions of the program code. It is also possible to write the program code read out from the storage medium into a memory set in an expansion board inserted into the computer or into a memory set in an expansion unit connected to the computer, and then install the program based on the instruction of the program code.
  • the expansion board or the CPU or the like on the expansion unit performs part and all of the actual operations to implement the functions of any of the above embodiments.
  • Storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), Tape, non-volatile memory card and ROM.
  • the program code can be downloaded from the server computer by the communication network.

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Abstract

本发明公开了一种脉冲宽度调制信号的动态调整方法和装置。确定目标占空比和控制精度位数；确定脉冲宽度调制控制位、缓存位和动态补偿位的各自位数，其中所述脉冲宽度调制控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数；基于所述目标占空比确定基础值，在脉冲宽度调制控制位存储所述基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数；利用所述基础值和精度补偿数据生成脉冲宽度调制信号，基于所述动态补偿参数动态调整所述精度补偿数据以动态调整所述脉冲宽度调制信号。本发明可以改进脉冲宽度调制信号的控制精度，降低缓存空间和成本。

Description

一种脉冲宽度调制信号的动态调整方法和装置 技术领域
本申请涉及信号处理技术领域，尤其涉及一种脉冲宽度调制(Pulse Width Modulation，PWM)信号的动态调整方法和装置。
背景技术
PWM是利用微处理器的数字输出对模拟电路进行控制的有效技术，广泛应用于测量、通信、功率控制与变换等诸多领域中。举例，PWM技术可以应用在电流输出控制的工业现场设备中，尤其适用于可寻址远程传感器高速通道(HART，Highway Addressable Remote Transduce)的相关设备。
PWM控制的输出电流精度由CPU时钟频率、PWM控制位长度、低通滤波器转角(corner frequency)频率等因素共同决定，其中CPU时钟频率尤其关键。然而，低功率设备的CPU时钟频率通常较低，比如为1至2兆赫(MHz)，难以提供大量的PWM控制位。
目前，通常利用在缓存中预先设置的PMW控制数据对位数较少的PWM控制位进行精度补偿，以尝试提高输出电流精度。然而，这种补偿方式的输出电流精度依然不理想，还对缓存的存储空间提出较高要求。
发明内容
有鉴于此，本发明实施方式的主要目的在于提供一种PWM信号的动态调整方法和装置。
本发明实施方式的技术方案是这样实现的：
一种PWM信号的动态调整方法，包括：
确定目标占空比和控制精度位数；
确定PWM控制位、缓存位和动态补偿位的各自位数，其中所述PWM控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数；
基于所述目标占空比确定基础值，在PWM控制位存储所述基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数；
利用所述基础值和精度补偿数据生成PWM信号，基于所述动态补偿参数动态调整所述精度补偿数据以动态调整所述PWM信号。
可见，在本发明实施方式中，不仅利用缓存对因PWM控制位数小于控制精度位数而丢失的精度数据进行精度补偿，还利用动态补偿位对精度数据执行动态补偿，从而可以改进PWM信号的控制精度。
在一个实施方式中，所述确定目标占空比包括：
确定目标输出电流值和最大输出电流值；
计算目标输出电流值与最大输出电流值的商；
将所述商确定为所述目标占空比。
可见，本发明实施方式通过建立目标输出电流值与最大输出电流值之间的函数关系，可以快速确定目标占空比，便于在工业现场中的具体实施。
在一个实施方式中，所述基于目标占空比确定基础值包括：
基于PWM控制位的位数确定控制位最大值；
确定所述控制位最大值与所述目标占空比的乘积，将所述乘积的向下取整值确定为所述基础值。
可见，本发明实施方式根据PWM控制位的位数可以便捷地确定基础值，适用于各种具体的控制环境。
在一个实施方式中，所述精度补偿数据为缓存中所存储的基础值的个数，所述缓存的剩余部分填充基础值加一，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值；或
所述精度补偿数据为缓存中所存储的基础值加一的个数，所述缓存的剩余部分填充基础值，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值。
可见，本发明实施方式可以基于基础值的个数确定缓存的具体存储结构，还可以基于基础值加一的个数确定缓存的具体存储结构，缓存的存储结构具有多种实施方式。
在一个实施方式中，所述利用基础值和精度补偿数据生成PWM信号包括：
从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；
计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；
利用所述第三值确定实际占空比，并基于所述实际占空比生成PWM信号。
可见，本发明实施方式利用缓存的具体存储结构确定实际占空比并生成PWM信号，计算过程简单，PWM信号生成速度快。
在一个实施方式中，所述动态补偿参数包括步进值；
所述基于动态补偿参数动态调整所述精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；
当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值变为基础值加一，将所述动态调整标识设置为逻辑真，并且将步进值减去所述动态补偿位最大值。
可见，当确认缓存没有被动态调整过且步进值大于等于动态补偿位最大值时，本发明实施方式将缓存中所存储的一个基础值变为基础值加一，即增加缓存中的基础值加一的数目，其中增加数目严格限定为一，并且减少缓存中的基础值的数目，其中减少数目严格限定为一，因此细微补偿了丢失精度。
在一个实施方式中，所述动态补偿参数包括步进值；
所述基于动态补偿参数动态调整所述精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；
当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将所述动态调整标识设置为逻辑假。
可见，当确认缓存已经被动态调整过且步进值小于动态补偿位最大值时，本发明实施方式将缓存中所存储的一个基础值加一变为基础值，即降低缓存中的基础值加一的数目，其中降低数目严格限定为一，而且增加缓存中的基础值的数目，其中增加数目严格限定为一，从而防止了重复补偿所导致的错误。
在一个实施方式中，所述动态补偿参数包括步进值；
所述基于动态补偿参数动态调整所述精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；
当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加所述步进值。
可见，当确认缓存已经被动态调整过且步进值大于等于动态补偿位最大值时，本发明实施方式重新增加步进值，从而构成新的完整循环。
在一个实施方式中，所述动态补偿参数包括步进值；
所述基于动态补偿参数动态调整所述精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；
当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加所述步进值。
可见，当确认缓存没有被动态调整过且步进值小于动态补偿位最大值时，本发明实施方式可以重新增加步进值，从而构成新的完整循环。
一种PWM信号的动态调整装置，包括：
占空比和精度确定模块，用于确定目标占空比和控制精度位数；
位数确定模块，用于确定PWM控制位、缓存位和动态补偿位的各自位数，其中所述PWM控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数；
位确定模块，用于基于所述目标占空比确定基础值，在PWM控制位存储所述基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数；
动态调整模块，用于利用所述基础值和精度补偿数据生成PWM信号，基于所述动态补偿参数动态调整所述精度补偿数据，以动态调整所述PWM信号。
可见，在本发明实施方式中，不仅利用缓存对因PWM控制位数小于控制精度位数而丢失的精度数据进行精度补偿，还利用动态补偿位对精度数据执行动态补偿，从而可以改进PWM信号的控制精度。
在一个实施方式中，占空比和精度确定模块，用于确定目标输出电流值和最大输出电流值；计算目标 输出电流值与最大输出电流值的商；将所述商确定为所述目标占空比。
可见，本发明实施方式通过建立目标输出电流值与最大输出电流值之间的函数关系，可以快速确定目标占空比，便于在工业现场中的具体实施。
在一个实施方式中，位确定模块，用于基于PWM控制位的位数确定控制位最大值；确定所述控制位最大值与所述目标占空比的乘积，将所述乘积的向下取整值确定为所述基础值。
可见，本发明实施方式根据PWM控制位的位数可以便捷地确定基础值，适用于各种具体的控制环境。
在一个实施方式中，所述精度补偿数据为缓存中所存储的基础值的个数，所述缓存的剩余部分填充基础值加一，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值；或
所述精度补偿数据为缓存中所存储的基础值加一的个数，所述缓存的剩余部分填充基础值，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值。
可见，本发明实施方式可以基于基础值的个数确定缓存的具体存储结构，还可以基于基础值加一的个数确定缓存的具体存储结构，缓存的存储结构具有多种实施方式。
在一个实施方式中，动态调整模块，用于从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；利用所述第三值确定实际占空比，并基于所述实际占空比生成PWM信号。
可见，本发明实施方式利用缓存的具体存储结构确定实际占空比并生成PWM信号，计算过程简单，PWM信号生成速度快。
在一个实施方式中，所述动态补偿参数包括步进值；
动态调整模块，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值变为基础值加一，将所述动态调整标识设置为逻辑真，并且将步进值减去所述动态补偿位最大值。
可见，当确认缓存没有被动态调整过且步进值大于等于动态补偿位最大值时，本发明实施方式将缓存中所存储的一个基础值变为基础值加一，即增加缓存中的基础值加一的数目，其中增加数目严格限定为一，并且减少缓存中的基础值的数目，其中减少数目严格限定为一，因此细微补偿了丢失精度。
在一个实施方式中，所述动态补偿参数包括步进值；
动态调整模块，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将所述动态调整标识设置为逻辑假。
可见，当确认缓存已经被动态调整过且步进值小于动态补偿位最大值时，本发明实施方式将缓存中所存储的一个基础值加一变为基础值，即降低缓存中的基础值加一的数目，其中降低数目严格限定为一，而 且增加缓存中的基础值的数目，其中增加数目严格限定为一，从而防止了重复补偿所导致的错误。
在一个实施方式中，所述动态补偿参数包括步进值；
动态调整模块，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加所述步进值。
可见，当确认缓存已经被动态调整过且步进值大于等于动态补偿位最大值时，本发明实施方式重新增加步进值，从而构成新的完整循环。
在一个实施方式中，所述动态补偿参数包括步进值；
动态调整模块，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加所述步进值。
可见，当确认缓存没有被动态调整过且步进值小于动态补偿位最大值时，本发明实施方式可以重新增加步进值，从而构成新的完整循环。
一种HART设备，包括：
如上任一项所述的PWM信号的动态调整装置，用于生成PWM信号；
电流输出模块，用于输出被所述PWM信号所控制的电流。可见，本发明实施方式还提出了一种改进PWM信号的控制精度的HART设备，该HART设备还可以降低PMW控制位的位数及缓存空间。
一种存储介质，其中存储有计算机程序，该计算机程序用于执行上述任一项所述的方法。可见，本发明实施方式还提出了一种改进PWM信号的控制精度的存储介质。
附图说明
图1为根据本发明实施方式的PWM信号的动态调整方法的流程图；
图2为根据本发明实施方式控制精度位数为16时的位组成示范性结构图；
图3为根据本发明实施方式，基于图2所示的位结构的动态补偿方法的示范性流程图；
图4为根据本发明实施方式的PWM信号的动态调整装置的结构图；
图5为根据本发明实施方式的HART设备的结构图；
图6为仅采用缓存补偿的现有技术的输出电流仿真图；
图7为根据本发明实施方式的输出电流仿真图。
其中，附图标记如下：
标号 含义
101～104 步骤
301～307 步骤
400 PWM信号的动态调整装置
401 占空比和精度确定模块
402 位数确定模块
403 位确定模块
404 动态调整模块
500 HART设备
501 PWM信号的动态调整装置
502 电流输出模块
具体实施方式
为了使本发明的技术方案及优点更加清楚明白，以下结合附图及实施方式，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施方式仅仅用以阐述性说明本发明，并不用于限定本发明的保护范围。
为了描述上的简洁和直观，下文通过描述若干代表性的实施方式来对本发明的方案进行阐述。实施方式中大量的细节仅用于帮助理解本发明的方案。但是很明显，本发明的技术方案实现时可以不局限于这些细节。为了避免不必要地模糊了本发明的方案，一些实施方式没有进行细致地描述，而是仅给出了框架。下文中，“包括”是指“包括但不限于”，“根据……”是指“至少根据……，但不限于仅根据……”。由于汉语的语言习惯，下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。
在本发明实施方式中，不仅利用缓存对因PWM控制位数小于控制精度位数而丢失的精度数据进行精度补偿(可以称为一次补偿)，还进一步利用动态补偿位对因PWM控制位数而丢失的精度数据再次执行动态补偿(可以称为二次补偿)。在保证控制精度的前提下，本发明实施方式可以降低PMW控制位的位数及缓存空间，从而降低对CPU时钟频率的要求并节约成本。
图1为根据本发明实施方式的PWM信号的动态调整方法的流程图。
如图1所示，该方法包括：
步骤101：确定目标占空比(DutyRatio)和控制精度位数。
占空比是指有效电平在一个周期之内所占的时间比率；目标占空比是期望PWM信号能达到的占空比。
在一个实施方式中，当利用PWM信号控制输出电流时，可以基于目标输出电流值和最大输出电流值确定目标占空比。具体包括：首先确定目标输出电流值和最大输出电流值，再计算目标输出电流值与最大输出电流值的商；将商确定为目标占空比。
而且，基于具体控制场景的精度需求，控制精度位数可以具体实施为4位、8位、16位、32位、64 位，等等。
以上描述了确定目标占空比的典型方式和控制精度位数的典型实例，本领域技术人员可以意识到，这种描述仅是示范性的，并不用于限定本发明实施方式的保护范围。
步骤102：确定PWM控制位、缓存位和动态补偿位的各自位数，其中PWM控制位、缓存位和动态补偿位的位数之和等于控制精度位数。
在这里，将步骤101中确定的控制精度位数分为三部分，这三部分分别是PWM控制位的位数、缓存位的位数和动态补偿位的位数。
比如，当控制精度位数为16位时：PWM控制位的位数可以为6位，缓存位的位数可以为5位，动态补偿位的位数可以为5位；或者，PWM控制位的位数可以为8位，缓存位的位数可以为4位，动态补偿位的位数可以为4位，等等。
可以基于具体的应用需求，在控制精度位数之内灵活分配PWM控制位、缓存位和动态补偿位的位数。只要分配后的PWM控制位、缓存位和动态补偿位的位数之和仍然等于控制精度位数，则依然可以保证控制精度不变。
比如，当CPU时钟频率较低时，可以降低PWM控制位的位数；当CPU时钟频率较高时，可以增加PWM控制位的位数。
再比如，当缓存存储空间紧张时，可以降低缓存位的位数；当缓存存储空间充裕时，可以增加缓存位的位数。
步骤103：基于目标占空比确定基础值，在PWM控制位存储基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数。
PWM控制位通常用于保存由目标占空比确定的基础值。基础值是由PWM控制位的位数和目标占空比所共同确定的中间值，用于后续快速计算实际占空比。另外，通过将余数的目标占空比转换为整数的基础值，还便于缓存进行存储。
在一个实施方式中，基于目标占空比确定基础值包括：基于PWM控制位的位数确定控制位最大值；确定控制位最大值与目标占空比的乘积，将乘积的向下取整值确定为基础值。
举例，假定最大输出电流值为32毫安(mA)；目标输出电流值为12.3456mA，那么目标输出电流值与最大输出电流值的商为12.3456/32＝0.3858，即目标占空比为0.3858。再假定PWM控制位为5位，因此PWM控制位最大值为25，即32，PWM控制位最大值与目标占空比的乘积为32×0.3858，对该乘积结果向下取整得到值12，即可以确定基础值为12。
PWM控制位数小于控制精度位数，可以降低PWM控制周期并由此降低低频噪声。不过，受限于PWM控制位数的精度限制，基础值通常只能在PWM控制位数所确定的精度之内接近于目标占空比。
在缓存位中保存基础值的精度补偿数据。精度补偿数据可以对受PWM控制位数限制而丢失的精度数 据执行补偿。具体包括：设置存储空间等于缓存位最大值的缓存，并且在缓存中保存若干个基础值和若干个基础值加一。通过在缓存中保存基础值及对基础值最细微增值的基础值加一，可以实现对基础值所间接体现的占空比的最细微调节。
缓存的存储空间由缓存位的大小所决定，而精度补偿数据体现了缓存中基础值与基础值加一之间的数目比例。精度补偿数据既可以实施为缓存中所存储的基础值的个数，也可以实施为缓存中所存储的基础值加一的个数。
在一个实施方式中，精度补偿数据为缓存中所存储的基础值的个数，缓存的剩余部分全部填充基础值加一，而且缓存中的基础值的个数与基础值加一的个数之和，等于基于缓存位的位数确定的缓存位最大值。此时，在缓存中存储的基础值的数目等于精度补偿数据，而缓存的剩余部分则存储基础值加一，即基础值加一的数目为缓存位最大值减去精度补偿数据。
在一个实施方式中，精度补偿数据为缓存中所存储的基础值加一的个数，缓存的剩余部分全部填充基础值，而且缓存中的基础值的个数与基础值加一的个数之和，等于基于缓存位的位数确定的缓存位最大值。此时，在缓存中存储的基础值加一的数目等于精度补偿数据，而缓存的剩余部分则存储基础值，即基础值的数目为缓存位最大值减去精度补偿数据。
PWM控制位的位数与缓存位的位数之和仍然小于控制精度位数，因此即使采用缓存位对受PWM控制位数限制而丢失的精度数据执行了一次补偿，仍然会丢失精度数据。
本发明实施方式利用动态补偿位中所存储的动态补偿参数对丢失的精度数据执行二次动态补偿，后续步骤104中将具体描述该二次动态补偿方式。
步骤104：利用基础值和精度补偿数据生成PWM信号，基于动态补偿参数动态调整精度补偿数据以动态调整PWM信号。
在一个实施方式中，利用基础值和精度补偿数据生成PWM信号包括：从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；利用第三值确定实际占空比，并基于实际占空比生成PWM信号。此时，该PWM信号为采用精度补偿数据执行一次补偿后所生成的PWM信号，该PWM信号虽然经过了一次补偿，仍然丢失了部分精度数据。在具体硬件实现中，PWM生成电路遍历整个缓存，其中当在缓存中遇到基础值时，在以PWM控制位最大值所确定的控制周期内生成基础值个高电平脉冲，而在该控制周期的其它时间保持低电平；当在缓存中遇到基础值加一时，在以PWM控制位最大值所确定的控制周期内生成基础值加一个高电平脉冲，而在该控制周期的其它时间保持低电平。PWM生成电路遍历完整个缓存后，产生的全部电平脉冲组合即构成PWM信号。
下面描述利用动态补偿位中存储的动态补偿参数对丢失的精度数据执行动态补偿的示范方式。
在本发明实施方式中，利用动态补偿位中所存储的动态补偿参数对缓存中的基础值与基础值加一的数 目比例进行细微动态调整，从而实现对丢失的精度数据执行动态补偿。
在执行动态补偿之前，预先设置动态调整标识。动态调整标识用于标识缓存是否已经被动态调整过。当动态调整标识为逻辑假时，表示缓存没有被动态调整过；当动态调整标识为逻辑真时，表示缓存已经被动态调整过。动态调整标识的初始值为逻辑假。
在一个实施方式中，动态补偿参数包括步进值，基于动态补偿参数动态调整精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值加一，将动态调整标识设置为逻辑真，并且将步进值减去动态补偿位最大值。
可见，当确认缓存没有被动态调整过时，将缓存中所存储的一个基础值变为基础值加一，即增加缓存中的基础值加一的数目(增加数目严格限定为1)，而且减少缓存中的基础值的数目(减少数目严格限定为1)，从而细微补偿了丢失精度。
在一个实施方式中，动态补偿参数包括步进值，基于动态补偿参数动态调整精度补偿数据包括：
基于动态补偿位的位数确定动态补偿位最大值；当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将动态调整标识设置为逻辑假。
可见，当确认缓存已经被动态调整过时，将缓存中所存储的一个基础值加一变为基础值，即降低缓存中的基础值加一的数目(降低数目严格限定为1)，而且增加缓存中的基础值的数目(增加数目严格限定为1)，从而防止了重复补偿所导致的错误。
在一个实施方式中，动态补偿参数包括步进值，基于动态补偿参数动态调整精度补偿数据包括：基于动态补偿位的位数确定动态补偿位最大值；当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加步进值。
在一个实施方式中，动态补偿参数包括步进值，基于动态补偿参数动态调整精度补偿数据包括：基于动态补偿位的位数确定动态补偿位最大值；当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加步进值。
可以基于各种硬件电路或软件流程实施图1所示的方法。当采用硬件电路时，可以利用专门设计的永久性电路、逻辑器件或可编程逻辑器件以执行图1所示的方法。当采用软件流程时，可以利用各种编程语言或汇编语言执行图1所示的方法。
下面结合具体的位格式对本发明实施方式进行示范性说明。
图2为根据本发明实施方式控制精度位数为16时的位组成示范性结构图。
由图2可见，控制精度位数为16位，其中PWM控制位为前面6位，缓存位为中间5位，动态补偿位为后面5位。
假定：最大输出电流值为32毫安(mA)；目标输出电流值为12.3456mA；CPU时钟频率为1.84320MHZ； 滤波器的转角频率为18HZ。
首先，计算目标输出电流值与最大输出电流值的商，12.3456/32＝0.3858，即目标占空比为0.3858。
PWM控制位为6位，因此PWM控制位最大值为26，即64。PWM控制位最大值与目标占空比的乘积为64×0.3858，对该乘积结果向下取整得到值24，即可以确定基础值为24。将基础值(24)转换为二进制数，转换结果为011000，因此在PWM控制位中存储该二进制数(011000)。
如果此时直接利用基础值(24)与PWM控制位最大值(64)确定实际占空比，则实际占空比为24/64＝0.375。可见，该实际占空比与目标占空比具有显著的精度差异，需要被执行补偿。
缓存位中存储有经过计算预先确定的精度补偿数据，以使得被补偿后的实际占空比尽量接近于目标占空比。在图2中，缓存位中保存有二进制数10110(即22)，假定表明缓存中所存储的基础值加一(也就是24+1，即25)的个数为22个。缓存位最大值为25＝32，因此基础值(即24)的个数为32-22＝10个。也就是说，在存储空间为32的缓存中，存储有22个基础值加一(即25)，10个基础值(即24)。
由于PWM控制位的位数(6)与缓存位的位数(5)之和仍然小于控制精度位数(16)，因此即使采用缓存对实际占空比执行了一次补偿，仍然会丢失精度数据。
在动态补偿位中保存步进值。步进值用于控制动态补偿过程的循环速度。步进值是预设值，当期望循环速度较快时，可以增加步进值；当期望循环速度较慢时，可以降低步进值。
在图2中，动态补偿位为二进制数00100，即4，则步进值为4。而且，动态补偿位的最大值为25＝32。
预先设置动态调整标识，用于标识缓存是否已经被动态调整过。当动态调整标识为逻辑假时，表示缓存没有被动态调整过；当动态调整标识为逻辑真时，表示缓存已经被动态调整过。
图3为根据本发明实施方式，基于图2所示的位结构的动态补偿方法流程图。
如图3所示，该方法包括：
步骤300：将动态调整标识的初始值设置为逻辑假，从PWM控制位中获取基础值，按照PWM控制位的精度补偿数据所决定的存储数目比例，在缓存中存储基础值(即24)和基础值加一(即25)，而且基于动态补偿位的存储内容确定步进值为4。
步骤301：从缓存中提取全部的基础值和全部的基础值加一，以生成PWM信号。
在这里，从缓存中提取出全部的22个基础值加一(即25)，并对这22个基础值加一求和得到第一值550；从缓存中提取出全部的10个基础值(即24)，再对这10个24求和得到第二值240；然后将第一值(550)与第二值(240)的和除以缓存位最大值(32)以得到第三值(24.6875)，利用第三值确定经过缓存补偿后的实际占空比为0.3857。接着，利用该经过缓存补偿后的实际占空比生成PWM信号。
在生成PWM信号的具体硬件实施中，PWM生成电路遍历整个缓存，其中当在缓存中遇到基础值时，在以PWM控制位最大值所确定的控制周期内生成基础值个高电平脉冲；当在缓存中遇到基础值加一时，在以PWM控制位最大值所确定的控制周期内生成基础值加一个高电平脉冲。
具体在本例中，PWM控制位最大值为26＝64，因此时钟周期数为64。PWM生成电路遍历整个缓存，当在缓存中遇到基础值(即24)时，PWM生成电路在64个时钟周期中生成24个高电平脉冲，而剩余的40个时钟周期保持低电平。当遇到基础值加一(即25)时，PWM生成电路在64个时钟周期中生成25个高电平脉冲，而剩余的39个时钟周期保持低电平。PWM生成电路将在缓存中遇到10个基础值，并由此10次执行如下操作：在64个时钟周期中生成24个高电平脉冲；PWM生成电路将在缓存中遇到22个基础值加一，并由此22次执行如下操作：在64个时钟周期中生成25个高电平脉冲。PWM生成电路遍历完整个缓存后，产生的全部电平脉冲组合即构成PWM信号。
步骤302：步进值递增。
在这里，用Id表示步进值，则Id＝Id+4。
步骤303：判断步进值是否大于等于动态补偿位最大值。如果大于则执行步骤304，否则执行步骤305。
其中，动态补偿位最大值为25＝32。当递增后的步进值大于等于32时，执行步骤304；否则，当递增后的步进值小于32时，执行步骤305。
步骤304：判断动态调整标识是否为逻辑真，如果是则返回执行步骤301，否则执行步骤307。
步骤305：判断动态调整标识是否为逻辑真，如果是则执行步骤306，否则返回执行步骤301。
步骤306：将动态调整标识设置为逻辑假，并且将缓存中所存储的一个基础值加一变为基础值，即降低缓存中的基础值加一的数目(降低数目严格限定为1)，增加缓存中的基础值的数目(增加数目严格限定为1)，然后返回执行步骤301。此时，后续步骤301中可以基于已被调整的缓存动态恢复到原始的PWM信号，防止重复补偿所导致的错误。
步骤307：将动态调整标识设置为逻辑真，并且将缓存中所存储的一个基础值变为基础值加一，即增加缓存中的基础值加一的数目(增加数目严格限定为1)，降低了缓存中的基础值的数目(增加数目严格限定为1)，然后返回执行步骤301。经过调整后，缓存中的基础值的数目变为9，而基础值加一的数目变为23。然后，后续步骤301中可以基于已被调整的缓存动态调整PWM信号，细微补偿丢失精度。具体的，在后续步骤301中，PWM生成电路将遇到9个基础值，并由此9次执行如下操作：在64个时钟周期中生成24个高电平脉冲；PWM生成电路将遇到23个基础值加一，并由此23次执行如下操作：在64个时钟周期中生成25个高电平脉冲。在后续步骤301中，PWM生成电路遍历完整个缓存后，产生的全部电平脉冲组合即构成调整后的PWM信号。
可选地，在上述流程中，可以在步骤307中不执行将动态调整标识设置为逻辑真的操作，而是在步骤303与步骤303之间，执行该将动态调整标识设置为逻辑真的操作。也就是说，将动态调整标识设置为逻辑真的操作，从步骤307中移动到步骤303与步骤303之间，从而避免可能的循环瑕疵。
上述以具体数值相应描述了PWM控制位、缓存位和动态补偿位及动态补偿过程，本领域技术人员可以意识到，这些数值仅为示范性作用，并不用于限定本发明实施方式的保护范围。
基于上述描述，本发明实施方式还提出了一种PWM信号的动态调整装置。
图4为根据本发明实施方式的PWM信号的动态调整装置的结构图。
如图4所示，该装置400包括：
占空比和精度确定模块401，用于确定目标占空比和控制精度位数；
位数确定模块402，用于确定PWM控制位、缓存位和动态补偿位的各自位数，其中PWM控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数；
位确定模块403，用于基于目标占空比确定基础值，在PWM控制位存储基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数；
动态调整模块404，用于利用基础值和精度补偿数据生成PWM信号，基于动态补偿参数动态调整所述精度补偿数据，以动态调整PWM信号。
在一个实施方式中，占空比和进度确定模块401，用于确定目标输出电流值和最大输出电流值；计算目标输出电流值与最大输出电流值的商；将商确定为所述目标占空比。
在一个实施方式中，位确定模块403，用于基于PWM控制位的位数确定控制位最大值；确定控制位最大值与所述目标占空比的乘积，将所述乘积的向下取整值确定为所述基础值。
在一个实施方式中，精度补偿数据为缓存中所存储的基础值的个数，所述缓存的剩余部分填充基础值加一；缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值。
在一个实施方式中，动态调整模块404，用于从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；利用第三值确定实际占空比，并基于实际占空比生成PWM信号。
在一个实施方式中，动态补偿参数包括步进值；
动态调整模块404，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值变为基础值加一，将所述动态调整标识设置为逻辑真，并且将步进值减去所述动态补偿位最大值。
在一个实施方式中，动态补偿参数包括步进值；
动态调整模块404，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将所述动态调整标识设置为逻辑假。
在一个实施方式中，动态补偿参数包括步进值；
动态调整模块404，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加所述步进值。
在一个实施方式中，动态补偿参数包括步进值；
动态调整模块404，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加所述步进值。
HART设备通常为低功率设备，CPU时钟频率通常较低，难以提供大量的PWM控制位。本发明实施方式通过增加二次动态补偿方式，可以在保证控制精度的前提下，降低PMW控制位的位数及缓存空间，从而降低对CPU时钟频率的要求并可以节约成本，尤其适用于HART设备。
本发明实施方式还提出了一种HART设备。图5为根据本发明实施方式的HART设备的结构图。
如图5所示，该设备500包括：
PWM信号的动态调整装置501，用于生成PWM信号；
电流输出模块502，用于输出被PWM信号所控制的电流。
其中，PWM信号的动态调整装置501可以具有如图4所示的PWM信号的动态调整装置400的相同结构。
将本发明实施方式与仅采用缓存补偿的现有技术分别应用到HART设备中，基于仿真结果可以清晰看出本发明的有益效果。图6为仅采用缓存补偿的现有技术的输出电流仿真图；图7为根据本发明实施方式的输出电流仿真图。
在图6中，PWM控制位的位数为9，缓存位的位数为7；在图7中，PWM控制位的位数为6，缓存位的位数为5，动态补偿位的位数为5。在图6中，纵轴为输出电流，横轴为缓存位的存储值；在图7中，纵轴为输出电流，横轴为动态补偿位的存储值。在图6和图7中，输出电流的限制值相同，都分别是-0.5和+0.5。
由图6和图7的对比可见，在图6为实例的现有技术中，输出电流普遍超出了限制值，在极端情况下甚至能达到限制值的两倍。应用本发明实施方式后，图7中的输出电流被限制在限制值之内。
而且，应用本发明实施方式后，PWM控制位只需要6位，相比现有技术所需的9位，PWM控制位数获得显著降低，可以降低对CPU时钟频率的需求。
另外，应用本发明实施方式后，缓存位的位数只需要5位，相比现有技术所需的7位，缓存位数也获得了显著降低，还可以降低对缓存空间的需求。
需要说明的是，上述各流程和各结构图中不是所有的步骤和模块都是必须的，可以根据实际的需要忽略某些步骤或模块。各步骤的执行顺序不是固定的，可以根据需要进行调整。各模块的划分仅仅是为了便于描述采用的功能上的划分，实际实现时，一个模块可以分由多个模块实现，多个模块的功能也可以由同一个模块实现，这些模块可以位于同一个设备中，也可以位于不同的设备中。
各实施方式中的硬件模块可以以机械方式或电子方式实现。例如，一个硬件模块可以包括专门设计的永久性电路或逻辑器件(如专用处理器，如FPGA或ASIC)用于完成特定的操作。硬件模块也可以包括由软件临时配置的可编程逻辑器件或电路(如包括通用处理器或其它可编程处理器)用于执行特定操作。 至于具体采用机械方式，或是采用专用的永久性电路，或是采用临时配置的电路(如由软件进行配置)来实现硬件模块，可以根据成本和时间上的考虑来决定。
本发明还提供了一种机器可读的存储介质，存储用于使一机器执行如本文所述方法的指令。具体地，可以提供配有存储介质的***或者装置，在该存储介质上存储着实现上述实施例中任一实施方式的功能的软件程序代码，且使该***或者装置的计算机(或CPU或MPU)读出并执行存储在存储介质中的程序代码。此外，还可以通过基于程序代码的指令使计算机上操作的操作***等来完成部分或者全部的实际操作。还可以将从存储介质读出的程序代码写到***计算机内的扩展板中所设置的存储器中或者写到与计算机相连接的扩展单元中设置的存储器中，随后基于程序代码的指令使安装在扩展板或者扩展单元上的CPU等来执行部分和全部实际操作，从而实现上述实施方式中任一实施方式的功能。
用于提供程序代码的存储介质实施方式包括软盘、硬盘、磁光盘、光盘(如CD-ROM、CD-R、CD-RW、DVD-ROM、DVD-RAM、DVD-RW、DVD+RW)、磁带、非易失性存储卡和ROM。可选择地，可以由通信网络从服务器计算机上下载程序代码。
以上所述，仅为本发明的较佳实施方式而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种脉冲宽度调制信号的动态调整方法，其特征在于，包括：
    确定目标占空比和控制精度位数(101)；
    确定脉冲宽度调制控制位、缓存位和动态补偿位的各自位数，其中所述脉冲宽度调制控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数(102)；
    基于所述目标占空比确定基础值，在脉冲宽度调制控制位存储所述基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数(103)；
    利用所述基础值和精度补偿数据生成脉冲宽度调制信号，基于所述动态补偿参数动态调整所述精度补偿数据以动态调整所述脉冲宽度调制信号(104)。
  2. 根据权利要求1所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述确定目标占空比包括：
    确定目标输出电流值和最大输出电流值；
    计算目标输出电流值与最大输出电流值的商；
    将所述商确定为所述目标占空比。
  3. 根据权利要求1所述的脉冲宽度调制信号的动态调整方法，其特征在于，
    所述基于目标占空比确定基础值包括：
    基于脉冲宽度调制控制位的位数确定控制位最大值；
    确定所述控制位最大值与所述目标占空比的乘积，将所述乘积的向下取整值确定为所述基础值。
  4. 根据权利要求3所述的脉冲宽度调制信号的动态调整方法，其特征在于，
    所述精度补偿数据为缓存中所存储的基础值的个数，所述缓存的剩余部分填充基础值加一，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值；或
    所述精度补偿数据为缓存中所存储的基础值加一的个数，所述缓存的剩余部分填充基础值，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值。
  5. 根据权利要求4所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述利用基础值和精度补偿数据生成脉冲宽度调制信号包括：
    从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；
    计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；
    利用所述第三值确定实际占空比，并基于所述实际占空比生成脉冲宽度调制信号。
  6. 根据权利要求4所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述动态补偿参数包括步进值；
    所述基于动态补偿参数动态调整所述精度补偿数据包括：
    基于动态补偿位的位数确定动态补偿位最大值；
    当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值变为基础值加一，将所述动态调整标识设置为逻辑真，并且将步进值减去所述动态补偿位最大值。
  7. 根据权利要求4所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述动态补偿参数包括步进值；
    所述基于动态补偿参数动态调整所述精度补偿数据包括：
    基于动态补偿位的位数确定动态补偿位最大值；
    当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将所述动态调整标识设置为逻辑假。
  8. 根据权利要求4所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述动态补偿参数包括步进值；
    所述基于动态补偿参数动态调整所述精度补偿数据包括：
    基于动态补偿位的位数确定动态补偿位最大值；
    当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加所述步进值。
  9. 根据权利要求4所述的脉冲宽度调制信号的动态调整方法，其特征在于，所述动态补偿参数包括步进值；
    所述基于动态补偿参数动态调整所述精度补偿数据包括：
    基于动态补偿位的位数确定动态补偿位最大值；
    当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加所述步进值。
  10. 一种脉冲宽度调制信号的动态调整装置，其特征在于，包括：
    占空比和精度确定模块(401)，用于确定目标占空比和控制精度位数；
    位数确定模块(402)，用于确定脉冲宽度调制控制位、缓存位和动态补偿位的各自位数，其中所述脉冲宽度调制控制位、缓存位和动态补偿位的位数之和等于所述控制精度位数；
    位确定模块(403)，用于基于所述目标占空比确定基础值，在脉冲宽度调制控制位存储所述基础值，在缓存位存储基础值的精度补偿数据，在动态补偿位中存储动态补偿参数；
    动态调整模块(404)，用于利用所述基础值和精度补偿数据生成脉冲宽度调制信号，基于所述动态补偿参数动态调整所述精度补偿数据，以动态调整所述脉冲宽度调制信号。
  11. 根据权利要求10所述的脉冲宽度调制信号的动态调整装置，其特征在于，
    占空比和进度确定模块(401)，用于确定目标输出电流值和最大输出电流值；计算目标输出电流值与最大输出电流值的商；将所述商确定为所述目标占空比。
  12. 根据权利要求10所述的脉冲宽度调制信号的动态调整装置，其特征在于，
    位确定模块(403)，用于基于脉冲宽度调制控制位的位数确定控制位最大值；确定所述控制位最大值与所述目标占空比的乘积，将所述乘积的向下取整值确定为所述基础值。
  13. 根据权利要求12所述的脉冲宽度调制信号的动态调整装置，其特征在于，
    所述精度补偿数据为缓存中所存储的基础值的个数，所述缓存的剩余部分填充基础值加一，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值；或
    所述精度补偿数据为缓存中所存储的基础值加一的个数，所述缓存的剩余部分填充基础值，所述缓存中的基础值的个数与基础值加一的个数之和，等于基于所述缓存位的位数确定的缓存位最大值。
  14. 根据权利要求13所述的脉冲宽度调制信号的动态调整装置，其特征在于，
    动态调整模块(404)，用于从缓存中提取全部的基础值并求和以作为第一值，从缓存中提取全部的基础值加一并求和以作为第二值；计算第一值与第二值的和，再将第一值与第二值的和除以缓存位最大值以得到第三值；利用所述第三值确定实际占空比，并基于所述实际占空比生成脉冲宽度调制信号。
  15. 根据权利要求13所述的脉冲宽度调制信号的动态调整装置，其特征在于，所述动态补偿参数包括步进值；
    动态调整模块(404)，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑假时，将缓存中所存储的一个基础值变为基础值加一，将所述动态调整标识设置为逻辑真，并且将步进值减去所述动态补偿位最大值。
  16. 根据权利要求13所述的脉冲宽度调制信号的动态调整装置，其特征在于，所述动态补偿参数包括步进值；
    动态调整模块(404)，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑真时，将缓存中所存储的一个基础值加一变为基础值，将所述动态调整标识设置为逻辑假。
  17. 根据权利要求13所述的脉冲宽度调制信号的动态调整装置，其特征在于，所述动态补偿参数包括步进值；
    动态调整模块(404)，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值大于等于动态补偿位最大值且预设置的动态调整标识为逻辑真时，增加所述步进值。
  18. 根据权利要求13所述的脉冲宽度调制信号的动态调整装置，其特征在于，所述动态补偿参数包括步进值；
    动态调整模块(404)，用于基于动态补偿位的位数确定动态补偿位最大值，当步进值小于动态补偿位最大值且预设置的动态调整标识为逻辑假时，增加所述步进值。
  19. 一种可寻址远程传感器高速通道设备，其特征在于，包括：
    如权利要求10-18中任一项所述的脉冲宽度调制信号的动态调整装置(501)，用于生成脉冲宽度调制 信号；
    电流输出模块(502)，用于输出被所述脉冲宽度调制信号所控制的电流。
  20. 一种存储介质，其特征在于，其中存储有计算机程序，该计算机程序用于执行所述权利要求1至9任一项所述的方法。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419742A (zh) * 2000-03-23 2003-05-21 马科尼通讯有限公司 脉宽调制信号的产生方法和设备以及由脉宽调制信号控制的光学衰减器
US20130038360A1 (en) * 2011-08-09 2013-02-14 Renesas Electronics Corporation Timing control device and control method thereof
CN103442482A (zh) * 2013-08-12 2013-12-11 深圳市天微电子有限公司 发光二极管照明脉冲宽度调制驱动电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419742A (zh) * 2000-03-23 2003-05-21 马科尼通讯有限公司 脉宽调制信号的产生方法和设备以及由脉宽调制信号控制的光学衰减器
US20130038360A1 (en) * 2011-08-09 2013-02-14 Renesas Electronics Corporation Timing control device and control method thereof
CN103442482A (zh) * 2013-08-12 2013-12-11 深圳市天微电子有限公司 发光二极管照明脉冲宽度调制驱动电路

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