WO2019008624A1 - Dispositif d'affichage et circuit de pixel associé - Google Patents

Dispositif d'affichage et circuit de pixel associé Download PDF

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Publication number
WO2019008624A1
WO2019008624A1 PCT/JP2017/024326 JP2017024326W WO2019008624A1 WO 2019008624 A1 WO2019008624 A1 WO 2019008624A1 JP 2017024326 W JP2017024326 W JP 2017024326W WO 2019008624 A1 WO2019008624 A1 WO 2019008624A1
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terminal
electro
optical element
circuit
voltage
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PCT/JP2017/024326
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English (en)
Japanese (ja)
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将紀 小原
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シャープ株式会社
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Priority to PCT/JP2017/024326 priority Critical patent/WO2019008624A1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to a display device, and more particularly to a display device provided with a pixel circuit including an electro-optical element.
  • the pixel circuit of the organic EL display device includes a drive transistor, a write control transistor, and the like in addition to the organic EL element.
  • TFTs thin film transistors
  • the organic EL element is a type of electro-optical element, and emits light with a luminance corresponding to the amount of current flowing.
  • the driving transistor is provided in series with the organic EL element, and controls the amount of current flowing to the organic EL element.
  • FIG. 13 is a circuit diagram of a pixel circuit of a conventional organic EL display device.
  • the pixel circuit shown in FIG. 13 is described in FIG. 20 of Patent Document 1, and includes TFTs T91 and T92, an organic EL element L9, and a capacitor C9.
  • the TFT: T91 functions as a drive transistor
  • the TFT: T92 functions as a write control transistor.
  • TFT: T92 turns on when the voltage of the scanning line Si is high level. At this time, a voltage corresponding to the video signal (hereinafter, referred to as a data voltage) is applied to the data line Dj. The data voltage is written to the gate terminal of the TFT: T91. After the voltage of the scanning line Si changes to the low level, the gate voltage of the TFT: T91 is maintained at the writing level by the action of the capacitor C9. At this time, a current of an amount corresponding to the gate voltage (data voltage) of the TFT: T91 flows through the TFT: T91 and the organic EL element L9. The organic EL element L9 emits light with a brightness (brightness according to the video signal) according to the amount of current flowing.
  • the characteristics of the organic EL element L9 deteriorate with the passage of time.
  • the current flowing through the organic EL element L9 decreases, and the luminance of the organic EL element L9 decreases.
  • the characteristics of the organic EL element L9 deteriorate faster as the luminance is higher. For this reason, a luminance difference occurs between the organic EL element emitting light at high luminance and the organic EL element emitting light at low luminance. The user recognizes this difference in brightness as uneven brightness or burn-in.
  • the characteristics of the organic EL element L9 deteriorate with the passage of time, and the display quality deteriorates.
  • the above problems include, for example, a plurality of scan lines, a plurality of data lines, a plurality of pixel circuits, a scan line drive circuit for driving the scan lines, and a data line drive circuit for driving the data lines.
  • the circuit includes an electro-optical element, a bipolar transistor connected in series with the electro-optical element, a differential amplifier whose output terminal is connected to the base terminal of the bipolar transistor, and one conduction terminal connected to the data line
  • the input terminal of the differential amplifier is generated based on the thin film transistor whose conduction terminal is connected to the non-inverting input terminal of the differential amplifier and the control terminal is connected to the scanning line, and the applied voltage to the electro-optical element
  • a display device that includes a comparison voltage generation circuit and a holding capacitor that holds a voltage applied to the non-inverting input terminal of the differential amplifier.
  • the above problem can also be solved by the above pixel circuit.
  • the storage capacitor holds the voltage applied to the non-inverting input terminal of the differential amplifier, and the bipolar transistor, the differential amplifier, and the comparison voltage generation circuit drive the electro-optical element. Construct a feedback circuit that keeps the current constant. Therefore, the drive current can be automatically maintained at the level at the time of writing inside the pixel circuit. Therefore, the display quality can be prevented from being degraded without performing compensation control from the outside of the pixel circuit. In addition, it is possible to prevent deterioration in display quality even while writing to the pixel circuit is stopped.
  • FIG. 5 is a circuit diagram of a unit circuit of the scanning line drive circuit shown in FIG. 4; 5 is a timing chart of the scanning line drive circuit shown in FIG. It is a figure which shows the time change of the brightness
  • FIG. 1 It is a figure which shows a mode that the organic electroluminescence display shown in FIG. 1 was modularized. It is a figure which shows the example of the mounting form of the organic electroluminescence display shown in FIG. It is a figure which shows a mode that multipaneling was carried out to the organic electroluminescent display apparatus shown in FIG. It is a figure which shows operation
  • FIG. 1 is a block diagram showing the configuration of the organic EL display device according to the first embodiment.
  • An organic EL display device 10 shown in FIG. 1 includes a display unit 11, a display control circuit 12, a scanning line drive circuit 13, a data line drive circuit 14, and a power supply circuit 15.
  • m and n are integers of 2 or more
  • i is an integer of 1 or more and n or less
  • j is an integer of 1 or more and m or less.
  • the horizontal direction of the drawing is called the row direction
  • the vertical direction of the drawing is called the column direction.
  • the display unit 11 includes n scanning lines S 1 to Sn, m data lines D 1 to Dm, (n ⁇ m) pixel circuits 21, and a blanket electrode (not shown) 22.
  • the scan lines S1 to Sn extend in the row direction and are arranged parallel to one another.
  • the data lines D1 to Dm extend in the column direction, and are arranged parallel to one another so as to be orthogonal to the scan lines S1 to Sn.
  • the scanning lines S1 to Sn and the data lines D1 to Dm intersect at (n ⁇ m) locations.
  • the (n ⁇ m) pixel circuits 21 are arranged corresponding to the intersections of the scanning lines S1 to Sn and the data lines D1 to Dm.
  • the pixel circuit 21 includes an organic EL element emitting light of any of red, green and blue, and functions as any of a red sub pixel, a green sub pixel and a blue sub pixel.
  • the three pixel circuits 21 arranged in the row direction function as one color pixel.
  • the display control circuit 12 outputs control signals CS1 to CS3 to the scanning line drive circuit 13, the data line drive circuit 14, and the power supply circuit 15, respectively. Further, the display control circuit 12 outputs the video signal X1 supplied from the outside of the organic EL display device 10 to the data line drive circuit 14.
  • the scanning line driving circuit 13 is formed on the organic EL panel (not shown) together with the pixel circuit 21 (gate driver monolithic configuration).
  • the scanning line drive circuit 13 drives the scanning lines S1 to Sn based on the control signal CS1.
  • the data line drive circuit 14 drives the data lines D1 to Dm based on the control signal CS2 and the video signal X1.
  • the power supply circuit 15 outputs three types of voltages ELVDD, VDD, and VSS supplied to the pixel circuit 21 based on the control signal CS3 and applies the low level voltage ELVSS to the blanket electrode 22.
  • FIG. 2 is a circuit diagram of the pixel circuit 21 in the i-th row and the j-th column.
  • the pixel circuit 21 includes an operational amplifier OP1, a bipolar transistor T1, a TFT: T2, resistors R1 and R2, a capacitor Cst, and an organic EL element L1.
  • the pixel circuit 21 is connected to the scanning line Si, the data line Dj, three wirings for supplying the voltages ELVDD, VDD, and VSS, and the blanket electrode 22 to which the low level voltage is applied.
  • the bipolar transistor T1 is a PNP transistor.
  • the bipolar transistor T1 is formed using single crystal silicon.
  • TFT: T2 is an N-channel transistor.
  • the TFT: T2 is also formed using single crystal silicon.
  • the TFT: T2 may be formed using, for example, an oxide semiconductor such as indium gallium zinc oxide (IGZO), amorphous silicon, microcrystalline silicon, low temperature polysilicon, single crystal silicon, or the like.
  • IGZO indium gallium zinc oxide
  • the organic EL element L1 has an organic light emitting layer, and emits light of any of red, green and blue.
  • the high level voltage ELVDD is applied to the collector terminal of the bipolar transistor T1.
  • the emitter terminal of the bipolar transistor T1 is connected to the anode terminal of the organic EL element L1 and one end (upper end in FIG. 2) of the resistor R2.
  • the low level voltage ELVSS is applied to the cathode terminal of the organic EL element L1.
  • the other end of the resistor R2 is connected to the inverting input terminal of the operational amplifier OP1 and one end (upper end in FIG. 2) of the resistor R1.
  • One conductive terminal (the terminal on the left side in FIG. 2) of the TFT: T2 is connected to the data line Dj.
  • the other conduction terminal of the TFT: T1 is connected to the non-inversion input terminal of the operational amplifier OP1 and one electrode (upper electrode in FIG. 2) of the capacitor Cst.
  • the gate terminal of the TFT: T2 is connected to the scanning line Si.
  • the output terminal of the operational amplifier OP1 is connected to the base terminal of the bipolar transistor T1.
  • the low level voltage VSS is applied to the other end of the resistor R1 and the other electrode of the capacitor Cst.
  • the bipolar transistor T1 is connected in series with the operational amplifier OP1.
  • the operational amplifier OP1 functions as a differential amplifier whose output terminal is connected to the base terminal of the bipolar transistor.
  • One conduction terminal of the TFT: T2 is connected to the data line Dj
  • the other conduction terminal of the TFT: T2 is connected to the non-inversion input terminal of the operational amplifier OP1
  • the control terminal of the TFT: T2 is connected to the scanning line Si There is.
  • the resistors R1 and R2 function as a comparison voltage generation circuit 23 that generates an input voltage of the inverting input terminal of the operational amplifier OP1 based on the voltage applied to the organic EL element L1.
  • the comparison voltage generation circuit 23 is a resistance division circuit including two resistors R1 and R2 connected in series.
  • the comparison voltage generation circuit 23 has one end connected to the inverting input terminal of the operational amplifier OP1, the low level voltage VSS applied to the other end, the first resistor (resistor R1), and one end connected to the anode terminal of the operational amplifier OP1 And a second resistor (resistor R2) connected to the inverting input terminal of the operational amplifier OP1.
  • the capacitor Cst functions as a holding capacitance that holds the voltage applied to the non-inverting input terminal of the operational amplifier OP1.
  • the operational amplifier OP1 may be either bipolar or MOS and may have any circuit configuration.
  • the operational amplifier OP1 may have the same circuit configuration as an operational amplifier incorporated in a commercially available IC chip.
  • the bipolar transistor T1 may be an NPN transistor, and the TFT: T2 may be a P channel transistor.
  • the resistors R1 and R2 may be diode-connected transistors.
  • a current flowing through the bipolar transistor T1 and the organic EL element L1 flows according to the gate voltage of the bipolar transistor T1 (the output voltage of the operational amplifier OP1).
  • the amplification factor of the operational amplifier OP1 is A
  • the output voltage of the operational amplifier OP1 is Vadj
  • the base-emitter voltage of the bipolar transistor T1 is VBE
  • the current flowing through the organic EL element L1 is a drive current Ioled
  • the anode voltage of the organic EL element L1 is The drive voltage is called Voled.
  • FIG. 3 is a timing chart of the organic EL display device 10.
  • n line periods (hereinafter, referred to as first to nth line periods) are set in one frame period, and the voltage of the scanning line Si becomes high level in the i-th line period.
  • the voltage of the data line Dj becomes the data voltage DVij to be written to the pixel circuit 21 in the i-th row and the j-th column.
  • FIG. 4 is a block diagram showing the configuration of the scanning line drive circuit 13.
  • the scanning line drive circuit 13 has a configuration in which n unit circuits 31 are connected in multiple stages.
  • the unit circuit 31 at the i-th stage is called SRi.
  • the unit circuit 31 has a clock terminal CK, a set terminal S, a reset terminal R, and an output terminal Q.
  • the control signal CS1 output from the display control circuit 12 to the scanning line drive circuit 13 includes two-phase clock signals CK1 and CK2 and a gate start pulse GSP.
  • the scanning line drive circuit 13 outputs n output signals Q1 to Qn based on these signals.
  • the output signals Q1 to Qn of the scanning line drive circuit 13 are applied to the scanning lines S1 to Sn, respectively.
  • the clock signal CK1 is supplied to the clock terminal CK of the unit circuit 31 in the odd-numbered stage.
  • the clock signal CK2 is supplied to the clock terminal CK of the unit circuit 31 in the even-numbered stage.
  • the gate start pulse GSP is supplied to the set terminal S of the unit circuit SR1 of the first stage.
  • An output signal of the unit circuit 31 of the previous stage is supplied to the set terminal S of the unit circuit 31 of the second to nth stages.
  • a signal RN is supplied to the reset terminal R of the nth unit circuit SRn.
  • An output signal of the unit circuit 31 of the next stage is supplied to the reset terminal R of the unit circuit 31 of the 1st to (n-1) th stages.
  • the signal RN is a gate end pulse, an output signal of a dummy stage, or the like.
  • FIG. 5 is a circuit diagram of the unit circuit 31.
  • the unit circuit 31 includes four TFTs: T11 to T14.
  • TFT: T11 to T14 are N-channel type transistors.
  • the TFTs T11 to T14 are formed using, for example, an oxide semiconductor such as IGZO, amorphous silicon, microcrystalline silicon, low temperature polysilicon, single crystal silicon, or the like, similarly to the TFT T2 in the pixel circuit 21.
  • the drain terminal and the gate terminal of the TFT: T11 are connected to the set terminal S.
  • the source terminal of the TFT: T11 is connected to the gate terminal of the TFT: T12 and the drain terminal of the TFT: T13.
  • the drain terminal of the TFT: T12 is connected to the clock terminal CK.
  • the source terminal of the TFT: T12 is connected to the output terminal Q and the drain terminal of the TFT: T14.
  • the gate terminals of the TFTs T13 and T14 are connected to the reset terminal R.
  • the low level voltage VSS is applied to the source terminals of the TFTs T13 and T14.
  • a parasitic capacitance Cgd is generated between the gate terminal and the drain terminal of the TFT: T12, and a parasitic capacitance Cgs is generated between the gate terminal and the source terminal of the TFT: T12.
  • N1 the node to which the gate terminal of TFT: T12 is connected.
  • FIG. 6 is a timing chart of the scanning line drive circuit 13. As shown in FIG. 6, the clock signal CK1 goes high and low for a predetermined time.
  • the clock signal CK2 is a negative signal of the clock signal CK1.
  • the gate start pulse GSP changes to high level. Accordingly, in the unit circuit SR1 of the first stage, the TFT: T11 is turned on, the voltage of the node N1 changes to the high level, and the TFT: T12 is turned on. At this time, since the clock signal CK1 is at low level, the output signal Q1 is at low level.
  • the gate start pulse GSP changes to low level at the start of the first line period.
  • the TFT: T11 is turned off, and the node N1 is in a floating state.
  • the clock signal CK1 changes to the high level.
  • the output signal Q1 of the unit circuit SR1 of the first stage becomes high level.
  • the voltage of the node N1 becomes high level higher than normal high level (see SR1_N1 in FIG. 6). Therefore, the high level of the output signal Q1 becomes the same level as the high level of the clock signal CK1 without decreasing by the threshold voltage of the TFT: T12.
  • the clock signal CK1 changes to low level at the end of the first line period. Along with this, the output signal Q1 of the unit circuit SR1 of the first stage becomes low level. In the second line period, the output signal Q2 of the unit circuit SR2 of the second stage becomes high level.
  • the output signal Q2 of the unit circuit 31 of the second stage is input to the reset terminal R of the unit circuit 31 of the first stage. Therefore, when the output signal Q2 of the unit circuit 31 in the second stage becomes high level, the TFTs T13 and T14 are turned on in the unit circuit 31 in the first stage. When the TFT: T13 is turned on, the voltage of the node N1 changes to low level. When the TFT: T14 is turned on, the output signal Q1 quickly changes to the low level.
  • the output signal Q1 of the unit circuit SR1 of the first stage is at the high level.
  • the output signals Q2 to Qn of the unit circuits 31 of the 2nd to nth stages respectively become high level.
  • the signal RN changes to high level. Accordingly, in the n-th unit circuit SRn, the TFTs T13 and T14 are turned on, the voltage of the node N1 changes to low level, and the output signal Qn changes to low level quickly. The signal RN changes to low level after one line period. Along with this, the TFTs T13 and T14 are turned off in the nth unit circuit SRn.
  • the scanning line drive circuit 13 may have any configuration other than the configuration shown in FIGS. 4 and 5.
  • the operation of the pixel circuit 21 in the i-th row and the j-th column will be described with reference to FIGS. 2 and 3.
  • the voltage of the scanning line Si becomes high level.
  • the TFT: T2 is turned on, and the data voltage DVij applied to the data line Dj is applied to the non-inversion input terminal of the operational amplifier OP1 and one electrode of the capacitor Cst.
  • the capacitor Cst is charged by the data voltage DVij.
  • the voltage of the scanning line Si goes low.
  • the TFT: T2 is turned off.
  • the voltage of the non-inverting input terminal of the operational amplifier OP1 is maintained at the level at the time of writing (data voltage DVij) by the action of the capacitor Cst.
  • the output voltage Vadj of the operational amplifier OP1 is A times the difference between the voltage (data voltage DVij) at the non-inverting input terminal and the voltage ( ⁇ ⁇ Voled) at the inverting input terminal.
  • the bipolar transistor T1 is turned on according to the output voltage Vadj of the operational amplifier OP1. Therefore, the drive current Ioled has an amount corresponding to the data voltage DVij, and the drive voltage Voled has a level corresponding to the data voltage DVij.
  • the organic EL element L1 emits light at a luminance corresponding to the data voltage DVij.
  • the organic EL element L1 emits light at a luminance according to the data voltage DVij until a new data voltage is written (until the i-th line period of the next frame period).
  • a case is considered where drive current Ioled increases for some reason before a new data voltage is written. In this case, the drive voltage Voled rises, and the voltage at the inverting input terminal of the operational amplifier OP1 also rises, so the output voltage Vadj of the operational amplifier OP1 decreases. Therefore, the drive current Ioled decreases.
  • drive current Ioled decreases.
  • the drive voltage Voled decreases and the voltage at the inverting input terminal of the operational amplifier OP1 also decreases, so the output voltage Vadj of the operational amplifier OP1 increases. Therefore, the drive current Ioled increases.
  • the capacitor Cst holds the voltage applied to the non-inverting input terminal of the operational amplifier OP1, and the bipolar transistor T1, the operational amplifier OP1, and the resistors R1 and R2 form a feedback circuit which keeps the drive current Ioled constant. Therefore, according to the organic EL display device 10, the drive current Ioled can be automatically maintained at the writing level inside the pixel circuit 21. Therefore, without performing the compensation control from the outside of the pixel circuit 21, it is possible to prevent the deterioration of the display quality. Also, while the writing to the pixel circuit 21 is stopped, it is possible to prevent the deterioration of the display quality.
  • the output voltage Vadj of the operational amplifier OP1 is given by the following equation (1).
  • the drive voltage Voled is given by the following equation (2).
  • the following equation (3) is derived from the equations (1) and (2).
  • Vadj A (VD ij- ⁇ x Voled) (1)
  • Voled Vadj-VBE (2)
  • Voled A ⁇ VDij / (1 + A ⁇ ⁇ ) ⁇ VBE / (1 + A ⁇ ⁇ ) ...
  • the collector current Ic of the bipolar transistor is given by the following equation (4), and the following equation (5) holds between the collector current Ic and the emitter current Ie of the bipolar transistor.
  • the following equation (6) is derived from the equations (4) and (5).
  • Ic Is ⁇ exp (VBE / Vt) (4)
  • Ic ⁇ ⁇ Ie (5)
  • VBE Vt ⁇ ln ( ⁇ ⁇ Ie / Is) (6)
  • Is is a saturation current
  • Vt is a thermal voltage.
  • ⁇ is a current amplification factor.
  • the saturation current Is and the thermal voltage Vt are constants determined by the temperature. In an ideal bipolar transistor, the thermal voltage Vt is 25.85 mV at room temperature, and the current amplification factor ⁇ is about 0.99.
  • the bipolar transistor T1 has ideal characteristics and the drive current Ioled is doubled for some reason.
  • the change amount ⁇ Voled of the drive voltage is given by the following equation (7).
  • ⁇ Voled ⁇ VBE / (1 + A ⁇ ⁇ ) (7)
  • A 1000
  • ⁇ 0.5
  • the change amount ⁇ Voled of the drive voltage is 36 ⁇ V.
  • the drive voltage Voled decreases by 36 ⁇ V.
  • FIG. 7 is a view showing temporal changes in luminance of the organic EL element.
  • the horizontal axis represents the light emission time
  • the vertical axis represents the luminance of the organic EL element.
  • the luminance of the organic EL element L1 included in the organic EL display device 10 is indicated by a solid line
  • the luminance of the organic EL element included in the conventional organic EL display device is indicated by a broken line.
  • the characteristics of the organic EL element deteriorate with the light emission time.
  • the drive current Ioled fluctuates with the light emission time, and the luminance of the organic EL element fluctuates. For this reason, in the conventional organic EL display device, the display quality is degraded.
  • the organic EL display device 10 solid line
  • the drive current Ioled is always kept at the write level by the action of the feedback circuit. Therefore, according to the organic EL display device 10, it is possible to prevent the fluctuation of the luminance of the organic EL element L1 and to prevent the deterioration of the display quality.
  • the characteristics of the organic EL element deteriorate faster than the characteristics of the liquid crystal element. For this reason, conventional organic EL display devices are not often used for applications (e.g., digital signage, monitors, etc.) in which the same image is continuously displayed. According to the organic EL display device 10, it is possible to prevent deterioration in display quality even while writing to the pixel circuit 21 is stopped. Therefore, the organic EL display device 10 can be suitably used for applications in which the same image is continuously displayed.
  • FIG. 8 is a view showing a wafer on which the organic EL display device 10 is formed.
  • the wafer 41 shown in FIG. 8 is manufactured using a silicon single crystal process (CMOS / bipolar mixed process).
  • the manufacturing process is, for example, a general-purpose 0.13 ⁇ m process.
  • the size of the wafer 41 is, for example, 12 inches.
  • the display unit 11 is disposed at the center of the wafer 41. Regions 42 to 44 are set on the left side, the right side, and the lower side of the display unit 11, respectively.
  • the scanning line drive circuit 13 is disposed in the regions 42 and 43. In the area 44, the display control circuit 12, the data line drive circuit 14, the power supply circuit 15, an external terminal (not shown) and the like are arranged.
  • the diagonal size (screen size) of the display unit 11 is smaller than 12 inches.
  • the process manufacture of the wafer 41 includes the steps of forming an organic EL layer emitting white light, and forming a color filter.
  • the organic EL layer is formed by a vapor deposition process or an inkjet process.
  • the color filter is formed by a transistor substrate process (miniaturization process).
  • the wafer 41 is sealed, for example, using glass and a sealing material.
  • the wafer 41 may be sealed with an inorganic or organic single layer film or a laminated film.
  • the wafer 41 is cut at the dicing lines L1 to L4 to obtain an organic EL panel 45 (FIG. 9) having peripheral circuits.
  • FIG. 9 is a diagram showing how the organic EL display device 10 is modularized.
  • a panel module control substrate 51 is provided outside the organic EL panel 45.
  • the organic EL panel 45 and the panel module control substrate 51 are connected using an FPC (Flexible Print Circuits) 52.
  • the external terminals arranged in the area 44 of the wafer 41 are connected to the wiring on the FPC 52.
  • wire bonding may be performed.
  • a standby signal indicating whether the display state or the non-display state, an enable signal indicating the start of display, a disenable signal indicating the stop of display, voltages VCC, VSS, etc. are output from the panel module control board 51 to the organic EL panel 45 Ru.
  • a polarizing plate or an anti-reflection sheet is attached to the display surface of the organic EL panel 45, and a touch panel module is attached if necessary.
  • FIG. 10 is a view showing an example of a mounting form of the organic EL display device 10.
  • the organic EL panel 45 and the panel module control board 51 are incorporated in the housing 53.
  • various circuit boards for example, a communication module, a power supply module, and the like
  • the panel module control substrate 51 and the FPC 52 are fixed to the back surface of the housing 53.
  • the display surface is covered with tempered glass, acrylic or the like to protect from external impact.
  • FIG. 11 is a view showing how the organic EL display device 10 is formed into a multi-panel.
  • a large-sized organic EL panel 46 is formed by arranging four organic EL panels 45 in a two-dimensional manner.
  • a panel module control substrate 54 is provided outside the large-sized organic EL panel 46.
  • the large-sized organic EL panel 46 and the panel module control board 54 are connected using the FPC 52.
  • the external terminal of the organic EL panel 45 is provided on the back side of the organic EL panel 45.
  • the diagonal size of the display unit 11 in the large organic EL panel 46 is smaller than 24 inches.
  • the panel module control board 54 includes an image dividing unit 55.
  • the image dividing unit 55 divides a video signal corresponding to one image into four partial video signals corresponding to four partial images, and the four partial video signals are output to the four organic EL panels 45. Output each one.
  • the process of the organic EL display device 10 is characterized in that peripheral circuits can be formed in a smaller area (narrow frame) than a general TFT manufacturing process. For this reason, the multi-display provided with the plurality of organic EL panels 45 can be easily configured.
  • the organic EL display device according to the second embodiment has the same configuration as the organic EL display device 10 according to the first embodiment, and operates in the same manner (see FIGS. 1 to 3).
  • the organic EL display device according to the present embodiment has a frame period in which the drive circuit stops its operation.
  • FIG. 12 is a diagram showing the operation of the organic EL device according to the present embodiment.
  • the organic EL device according to the present embodiment performs writing to the pixel circuit 21 at a rate of once every K frame period.
  • the voltages VDD and VSS are always supplied to the pixel circuit 21.
  • the scanning line driving circuit 13 and the data line driving circuit 14 operate.
  • a data voltage corresponding to the video signal Xa is written to the (n ⁇ m) pixel circuits 21.
  • the organic EL display device displays an image IMa based on the video signal Xa.
  • the scanning line driving circuit 13 and the data line driving circuit 14 stop their operations.
  • the organic EL display device is based on the video signal Xa.
  • the organic EL display device continuously displays the image IMa based on the video signal Xa in the first to Kth frame periods.
  • the scanning line driving circuit 13 and the data line driving circuit 14 operate, and a data voltage corresponding to the video signal Xb is written to the (n ⁇ m) pixel circuits 21.
  • the organic EL display device displays an image IMb based on the video signal Xb.
  • the scanning line driving circuit 13 and the data line driving circuit 14 stop their operation, and the organic EL display device continues to display the image IMb based on the video signal Xb.
  • the organic EL display device continuously displays the image IMb based on the video signal Xb in the (K + 1) th to 2nd K frame periods.
  • the organic EL display device 10 As described above, according to the organic EL display device 10 according to the first embodiment, it is possible to prevent deterioration in display quality even while writing to the pixel circuit 21 is stopped. Therefore, according to the organic EL display device according to the present embodiment, even when the same screen is continuously displayed, it is possible to prevent the deterioration of the display quality.
  • organic EL display device including the pixel circuit including the organic EL device (organic light emitting diode) has been described above as an example of the display device including the pixel circuit including the electro-optical device, the inorganic light emission is performed by the same method
  • An inorganic EL display device having a pixel circuit including a diode or a QLED (Quantum-dot Light Emitting Diode) display device including a pixel circuit including a quantum dot light emitting diode may be configured.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un circuit de pixel d'un dispositif d'affichage comprenant : un élément électro-optique ; un transistor bipolaire connecté en série à l'élément électro-optique ; un amplificateur différentiel dans lequel un terminal de sortie est connecté à un terminal de base du transistor bipolaire ; un transistor à couches minces dans lequel un terminal de conduction est connecté à une ligne de données, l'autre terminal de conduction étant connecté à un terminal d'entrée non inverseur de l'amplificateur différentiel, et un terminal de commande étant connecté à une ligne de balayage ; un circuit de génération de tension de comparaison qui génère une tension d'entrée d'un terminal d'entrée inverseur de l'amplificateur différentiel d'après une tension appliquée à l'élément électro-optique ; et un condensateur de stockage qui stocke la tension appliquée au terminal d'entrée non inverseur de l'amplificateur différentiel. Par conséquent, il est possible d'éliminer une détérioration de la qualité d'affichage sans effectuer de commande de compensation à partir de l'extérieur du circuit de pixel.
PCT/JP2017/024326 2017-07-03 2017-07-03 Dispositif d'affichage et circuit de pixel associé WO2019008624A1 (fr)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2020211509A1 (fr) * 2019-04-19 2020-10-22 京东方科技集团股份有限公司 Cricuit d'attaque, panneau d'affichage et procédé de fabrication de panneau d'affichage
WO2020261398A1 (fr) * 2019-06-25 2020-12-30 シャープ株式会社 Dispositif d'affichage et procédé de traitement d'image

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JP2002507773A (ja) * 1998-03-19 2002-03-12 ホローマン・チャールズ・ジェイ． Ｌｅｄ又は類似のディスプレイ素子のためのアナログドライバ
JP2005266089A (ja) * 2004-03-17 2005-09-29 Sanyo Electric Co Ltd 表示装置
JP2005536771A (ja) * 2002-08-21 2005-12-02 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 表示装置
JP2007179041A (ja) * 2005-12-02 2007-07-12 Semiconductor Energy Lab Co Ltd 半導体装置、表示装置及びに電子機器
US20150270326A1 (en) * 2013-07-24 2015-09-24 International Business Machines Corporation Active matrix using hybrid integrated circuit and bipolar transistor

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Publication number Priority date Publication date Assignee Title
JP2002507773A (ja) * 1998-03-19 2002-03-12 ホローマン・チャールズ・ジェイ． Ｌｅｄ又は類似のディスプレイ素子のためのアナログドライバ
JP2001147665A (ja) * 1999-10-27 2001-05-29 Agilent Technol Inc アクティブ・マトリックス発光ダイオード・ディスプレイ
JP2005536771A (ja) * 2002-08-21 2005-12-02 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 表示装置
JP2005266089A (ja) * 2004-03-17 2005-09-29 Sanyo Electric Co Ltd 表示装置
JP2007179041A (ja) * 2005-12-02 2007-07-12 Semiconductor Energy Lab Co Ltd 半導体装置、表示装置及びに電子機器
US20150270326A1 (en) * 2013-07-24 2015-09-24 International Business Machines Corporation Active matrix using hybrid integrated circuit and bipolar transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020211509A1 (fr) * 2019-04-19 2020-10-22 京东方科技集团股份有限公司 Cricuit d'attaque, panneau d'affichage et procédé de fabrication de panneau d'affichage
WO2020261398A1 (fr) * 2019-06-25 2020-12-30 シャープ株式会社 Dispositif d'affichage et procédé de traitement d'image

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